CN108231560A - A kind of coordination electrode preparation method and MOSFET power devices - Google Patents
A kind of coordination electrode preparation method and MOSFET power devices Download PDFInfo
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- CN108231560A CN108231560A CN201611125725.9A CN201611125725A CN108231560A CN 108231560 A CN108231560 A CN 108231560A CN 201611125725 A CN201611125725 A CN 201611125725A CN 108231560 A CN108231560 A CN 108231560A
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
Abstract
The present invention provides a kind of coordination electrode preparation method and MOSFET power devices, and the method includes the fronts in substrate to form gate dielectric layer, and be sequentially formed graphene layer and gate electrode on the gate dielectric layer；Gate contact hole is formed on gate electrode, and is exposed on the region other than gate dielectric layer in the front of substrate and forms the first contact hole；To gate contact hole and the first contact hole filling metal, it is respectively formed gate contact electrode and the first contact electrode；Metal is deposited at the back side of substrate, forms the second contact electrode；The MOSFET power devices include coordination electrode prepared by the above method.Compared with prior art, a kind of coordination electrode preparation method and MOSFET power devices, this method provided by the invention can improve the control problem of coordination electrode, reduce the conducting resistance of device, shorten reverse recovery time, reduce switching loss, improve the current gain of device.
Description
Technical field
The present invention relates to technical field of semiconductor preparation, and in particular to a kind of coordination electrode preparation method and MOSFET power
Device.
Background technology
Mos field effect transistor (Metal-Oxide-Semiconductor Field-Effect
Transistor, MOSFET) it is a kind of widely used silicon carbide power device.MOSFET power devices can will control letter
It number is supplied to after its coordination electrode and gate electrode and electric current conduction is carried out by the transmission of majority carrier, without ambipolar
Minority carrier injection is used when transistor works.At present, although MOSFET power devices have very big safety operation area
With can multiple cellular constructions use parallel the advantages of, but also there are channel mobility it is relatively low the defects of, have so as to cause it
Larger conducting resistance and energy loss is big.
Patent application No. is CN200610126666.7 discloses one kind by being moved back in hydrogen or humid atmosphere
Fire processing improves the dangling bonds terminal at gate dielectric layer and channel region interface to improve the method for channel mobility, but this side
Method can cause gate contact to aoxidize.
Invention content
In order to meet the needs of the prior art, the present invention provides a kind of coordination electrode preparation method and MOSFET power devices
Part.
In a first aspect, a kind of technical solution of coordination electrode preparation method is in the present invention：
The method includes：
Gate dielectric layer is formed, and graphene layer and grid are sequentially formed on the gate dielectric layer in the front of substrate
Electrode；
Gate contact hole is formed on the gate electrode, and be exposed in the front of the substrate gate dielectric layer with
The first contact hole is formed on outer region；
To the gate contact hole and the first contact hole filling metal, it is respectively formed gate contact electrode and the first contact electricity
Pole；Metal is deposited at the back side of the substrate, forms the second contact electrode.
Second aspect, the present invention in a kind of technical solution of MOSFET power devices be：
The MOSFET power devices include：
Substrate, epitaxial layer and contact layer with the first conduction type；The epitaxial layer and contact layer are separately positioned on institute
State the front and back of substrate；
Graphene layer is arranged on epitaxial layer on preset gate dielectric layer；
Gate electrode is arranged on the graphene layer；
Gate contact electrode is arranged in gate contact hole preset on epitaxial layer and corresponding with gate electrode；
First contact electrode, is arranged in preset first contact hole of epitaxial layer；
Second contact electrode, is arranged on the contact layer.
Compared with the immediate prior art, the beneficial effects of the invention are as follows：
1st, a kind of coordination electrode preparation method provided by the invention, after forming graphene layer on gate dielectric layer,
Gate electrode and gate contact electrode are sequentially formed on the graphene layer, contributes to improve grid based on the excellent electric conductivity of graphene layer
The control problem of electrode reduces the conducting resistance of device, shortens reverse recovery time, reduces switching loss, improves the electricity of device
Flow enhancement；
2nd, a kind of MOSFET power devices provided by the invention, gate contact electrode are arranged on graphene layer, are based on
The excellent conduction property of graphene so that when the MOSFET power devices have relatively low conducting resistance and smaller Reverse recovery
Between.
Description of the drawings
Fig. 1：A kind of implementing procedure figure of coordination electrode preparation method in the present invention；
Fig. 2：1 epitaxial layers schematic diagram of the embodiment of the present invention；
Fig. 3：Silicon carbide schematic diagram in the embodiment of the present invention 1；
Fig. 4：First impurity range, the second impurity range and third impurity range schematic diagram in the embodiment of the present invention 1；
Fig. 5：Gate medium buffer layer schematic diagram in the embodiment of the present invention 1；
Fig. 6：Gate dielectric layer schematic diagram in the embodiment of the present invention 1；
Fig. 7：Graphene layer and gate electrode schematic diagram in the embodiment of the present invention 1；
Fig. 8：Insulating layer schematic diagram in the embodiment of the present invention 1；
Fig. 9：Gate contact electrode and the first contact electrode schematic diagram in the embodiment of the present invention 1；
Figure 10：Second contact electrode schematic diagram in the embodiment of the present invention 1；
Figure 11：2 epitaxial layers schematic diagram of the embodiment of the present invention；
Figure 12：Silicon carbide schematic diagram in the embodiment of the present invention 2；
Figure 13：First impurity range, the second impurity range and channel layer schematic diagram in the embodiment of the present invention 2；
Figure 14：Gate medium buffer layer schematic diagram in the embodiment of the present invention 2；
Figure 15：Gate dielectric layer schematic diagram in the embodiment of the present invention 2；
Figure 16：Graphene layer and gate electrode schematic diagram in the embodiment of the present invention 2；
Figure 17：Insulating layer schematic diagram in the embodiment of the present invention 2；
Figure 18：Gate contact electrode and the first contact electrode schematic diagram in the embodiment of the present invention 2；
Figure 19：Second contact electrode schematic diagram in the embodiment of the present invention 2；
Figure 20：3 epitaxial layers schematic diagram of the embodiment of the present invention；
Figure 21：Silicon carbide schematic diagram in the embodiment of the present invention 3；
Figure 22：First impurity range, the second impurity range, field limiting ring and field cut-off ring schematic diagram in the embodiment of the present invention 3；
Figure 23：Gate medium buffer layer schematic diagram in the embodiment of the present invention 3；
Figure 24：Gate dielectric layer schematic diagram in the embodiment of the present invention 3；
Figure 25：Graphene layer and gate electrode schematic diagram in the embodiment of the present invention 3；
Figure 26：Insulating layer schematic diagram in the embodiment of the present invention 3；
Figure 27：Gate contact electrode and the first contact electrode schematic diagram in the embodiment of the present invention 3；
Figure 28：Second contact electrode schematic diagram in the embodiment of the present invention 3；
Wherein, 101：N-type substrate；102：N-shaped epitaxial layer；103：Contact layer；104：Second contact electrode；111：P-type carbon
SiClx well region；112：Second impurity range；113：First contact electrode；121：First impurity range；122：First contact electrode；131：
Third impurity range；141：Gate medium buffer layer；142：Gate dielectric layer；151：Gate electrode；152：Gate contact electrode；161：
Insulating layer；171：First contact hole；172：Gate contact hole；181：Graphene layer；201：N-type substrate；202：N-shaped epitaxial layer；
203：Contact layer；204：Second contact electrode；211：P-type silicon carbide；212：Second impurity range；213：First contact electricity
Pole；221：First impurity range；222：First contact electrode；231：N-type channel layer；241：Gate medium buffer layer；242：Grid electricity
Dielectric layer；251：Gate electrode；252：Gate contact electrode；261：Insulating layer；271：First contact hole；272：Gate contact hole；
281：Graphene layer；301：N-type substrate；302：N-shaped epitaxial layer；303：Second contact electrode；311：P-type silicon carbide；
312：Second impurity range；313：First contact electrode；314：Field limiting ring；315：First cut-off ring；321：First impurity range；
322：First contact electrode；323：Second cut-off ring；341：Gate medium buffer layer；342：Gate dielectric layer；351：Grid electricity
Pole；352：Gate contact electrode；361：Insulating layer；371：First contact hole；372：Gate contact hole；381：Graphene layer.
Specific embodiment
Purpose, technical scheme and advantage to make the embodiment of the present invention are clearer, below in conjunction with the embodiment of the present invention
In attached drawing, the technical solution in the embodiment of the present invention is clearly and completely illustrated, it is clear that described embodiment is
Part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
All other embodiments obtained without making creative work shall fall within the protection scope of the present invention.
Separately below with reference to attached drawing, a kind of coordination electrode preparation method provided in an embodiment of the present invention is illustrated.
Fig. 1 is a kind of implementing procedure figure of coordination electrode preparation method in the present invention, as shown in the figure, can be in the present embodiment
Coordination electrode is prepared as steps described below, specially：
Step S101：Gate dielectric layer is formed, and stone is sequentially formed on the gate dielectric layer in the front of substrate
Black alkene layer and gate electrode.
Step S102：Gate contact hole is formed on gate electrode, and gate dielectric layer is exposed in the front of substrate
The first contact hole is formed on region in addition.
Step S103：To the gate contact hole and the first contact hole filling metal, be respectively formed gate contact electrode and
First contact electrode；Metal is deposited at the back side of substrate, forms the second contact electrode.
Connection in graphene between each carbon atom is very flexible, and stable lattice structure makes carbon atom have outstanding lead
Electrically.Electronics in graphene will not scatter when being moved in track due to lattice defect or introducing foreign atom, electronics
The interference being subject to is very small.After forming graphene layer on gate dielectric layer in the present embodiment, on the graphene layer sequentially
Gate electrode and gate contact electrode are formed, contributes to improve the control problem of gate electrode based on the excellent electric conductivity of graphene layer,
The conducting resistance of device is reduced, shortens reverse recovery time, reduces switching loss, improves the current gain of device.
Further, contact hole can be formed as steps described below in the present embodiment step S101, specially：
First, it in epitaxial layer of the front growth with the first conduction type of substrate, and is formed on the epitaxial layer and has the
The silicon carbide of two conduction types.Wherein, substrate is the silicon carbide substrates with the first conduction type.
Substrate is N-shaped or p-substrate in the present embodiment, and 4H-SiC, 6H-SiC, 3C-SiC or 15R-SiC crystalline substance may be used
The silicon carbide of type has 1 × 1018cm-3~1 × 1019cm-3Impurity concentration, thickness can be thick for 400~1000 μm of standard
It spends or by thinned 10~400 μm.The thickness and impurity concentration of epitaxial layer are needed according to semiconductor device to be produced
The voltage class of part determines, can choose 10~200 μm and 1 × 1014cm-3~1 × 1016cm-3。
The preparation method of silicon carbide is：
1st, mask material is formed on epitaxial layer, using photoetching that mask material is graphical, removal is used to form silicon carbide
The part mask material of well region forms ion implanting window.
2nd, by the ion implanting window by the upper surface of the ion implanting with the second conduction type to epitaxial layer.
3rd, it removes mask and activation annealing is carried out at a temperature of 1500~2200 DEG C, form silicon carbide.Wherein, it anneals
About 3~30 minutes time.Silicon carbide has 1 × 10 in the present embodiment13cm-3~5 × 1020cm-3Impurity concentration and
0.1~3 μm of junction depth.Meanwhile silicon carbide can be the silicon carbide of non-uniform doping, near its surface have compared with
Low impurity concentration, impurity concentration with junction depth increase first increases and then decreases, and at 0.3~0.8 μm of junction depth have it is highest
Impurity concentration, then continuously decrease.
2nd, the ion for being doped with the first conduction type in silicon carbide respectively forms the first impurity range, doping tool
The ion for having the second conduction type forms the second impurity range, wherein, the first impurity range and the second impurity range are according to spaced
Sequence is arranged in silicon carbide, and conducting channel is formed in the silicon carbide between the first impurity range and epitaxial layer upper surface
Region.
The preparation method of first impurity range and the second impurity range is：
1st, mask material is formed on silicon carbide, using photoetching that mask material is graphical, removal is used to form the
The part mask material of one impurity range and the second impurity range is respectively formed the first ion implanting window and the second ion implanting window
Mouthful.
2nd, the ion implanting with the first conduction type to silicon carbide is passed through by the first ion implanting window
Two ion implanting windows are by the ion implanting with the second conduction type to silicon carbide.
3rd, it removes mask and activation annealing is carried out at a temperature of 1500~2200 DEG C, form the first impurity range and the second impurity
Area.The first impurity range has 1 × 10 in the present embodiment17cm-3~5 × 1021cm-3Impurity concentration and 0.1 μm~0.8 μm of knot
Deep, the second impurity range has 1 × 1017cm-3~5 × 1021cm-3Impurity concentration and 0.1 μm~0.8 μm of junction depth.Meanwhile the
The impurity concentration and junction depth of one impurity range and the second impurity range differ.
Further, can also be formed on substrate during the second impurity range is prepared in the present embodiment field limiting ring,
Field cut-off ring and terminal structure.Wherein,
1st, field limiting ring
In the present embodiment the second conduction can be doped with to substrate by preset multiple field limiting ring ion implanting windows
The ion of type forms multiple limits.Wherein,
(1) field limiting ring is arranged on the marginal portion of substrate.
(2) width of field limiting ring and spacing are unequal, and the quantity of field limiting ring is 2~50.
(3) impurity concentration of field limiting ring and junction depth are identical with the second impurity range, i.e., in the present embodiment field limiting ring have 1 ×
1017cm-3~5 × 1021cm-3Impurity concentration and 0.1 μm~0.8 μm of junction depth.
(4) preparation method of field limiting ring is identical with a kind of preparation method of silicon carbide of above-mentioned steps.
2nd, field cut-off ring
In the present embodiment second can be sequentially doped with to substrate by preset one cut-off ring ion implanting window
The ion of conduction type and the ion with the first conduction type are respectively formed first cut-off ring and second cut-off ring, i.e.,
Second cut-off ring is on the top of the first cut-off ring.Wherein,
(1) cut-off ring in field is arranged on the side in the outside, i.e. adjacent substrate edge of field limiting ring.
(2) first cut-off ring of field cut-off ring is located at lower part, and second cut-off ring is located at top.
(3) first cut-off rings have 1 × 1018cm-3~5 × 1020cm-3Impurity concentration and 0.1~0.8 μm of junction depth,
Second cut-off ring has 1 × 1018cm-3~5 × 1020cm-3Impurity concentration and 0.1~0.4 μm of junction depth.
(4) preparation method of field cut-off ring is identical with a kind of preparation method of silicon carbide of above-mentioned steps.
3rd, terminal structure
Terminal structure is using groove isolation construction, inclined-plane junction structure, knot terminal expansion structure, floating field in the present embodiment
Ring, more floating plot structures or spatial modulation structure.
Further, can also be formed in the present embodiment on substrate after first the second impurity range of impurity range is prepared
Three impurity ranges or channel layer.Wherein,
1st, third impurity range
Epitaxial layer region doping in the present embodiment before gate dielectric layer is formed between two silicon carbides
Ion with the first conduction type forms third impurity range.
The preparation method of third impurity range is：Third impurity range is prepared using ion implanting or the method for epitaxial growth.Its
In, third impurity range has 5 × 1015cm-3~5 × 1016cm-3Impurity concentration and 0.01~0.3 μm of junction depth, and its impurity
Concentration is higher than the impurity concentration of epitaxial layer.
2nd, channel layer
Epitaxial layer region in the present embodiment before gate dielectric layer is formed between two silicon carbides and point
Two conduction channel regions neighbouring not with the epitaxial layer region are doped with the ion of the first conduction type, form channel layer.
The preparation method of channel layer is：Channel layer is prepared using the method for epitaxial growth.Wherein, doped region have 5 ×
1015cm-3~5 × 1016cm-3Impurity concentration and 0.01~0.5 μm of junction depth, and its impurity concentration be higher than epitaxial layer impurity
Concentration.
Third impurity range is being prepared in the present embodiment and channel layer while can also be doped with the to the back side of substrate
The ion of one conduction type forms contact layer, and the second contact electrode is formed in order to deposit metal on the contact layer.
The preparation method of contact layer is：
(1) by the back side of the ion implanting with the first conduction type to substrate.
(2) activation annealing technique is carried out at a temperature of 1200~2000 DEG C or uses laser activation annealing process, during annealing
Between 3~30 minutes, formed contact layer.Wherein, contact layer has 5 × 1019cm-3~5 × 1020cm-3Impurity concentration and 0.1~
0.3 μm of junction depth.
3rd, in the upper surface of conduction channel region and the upper table for the first impurity range for being respectively adjacent to the conduction channel region
Facial subregion and the upper surface of epitaxial layer form gate dielectric layer.Wherein, gate dielectric layer is the dielectric layer of insulation,
Mainly using silica material, the impurity elements such as N, P, B, Al, C can be contained, thickness is 20~400nm or smaller.
The preparation method of gate dielectric layer is：Atomic layer deposition, low-pressure chemical vapor deposition, plasma may be used to increase
Extensive chemical vapor deposition, sputtering or method for oxidation form gate dielectric layer.Wherein, the oxidizing temperature of method for oxidation for 600~
1700℃。
It can also be in the upper surface of conduction channel region and adjacent respectively before gate dielectric layer is prepared in the present embodiment
The upper surface part subregion of first impurity range of the nearly conduction channel region and the upper surface of epitaxial layer form gate medium buffer layer,
Then gate medium buffer layer is aoxidized to obtain gate dielectric layer.Wherein, gate medium buffer layer is doping Nitrogen ion N, phosphorus
Ion P, boron ion B, aluminium ion Al or carbon ion C silica, thickness is 1~100nm.
The preparation method of gate medium buffer layer is：May be used atomic layer deposition (atomic layer deposition,
ALD), low-pressure chemical vapor deposition (low pressure chemical vapor deposition, LPCVD), plasma increase
Extensive chemical is vapor-deposited (plasma enhanced chemical vapor deposition, PECVD) or the mode system of sputtering
Standby gate medium buffer layer.Wherein, gate medium buffer layer is patterned using the method for photoetching and corrosion/etching.Specially：
1st, using Other substrate materials and using modes such as ultraviolet light, laser or electron beams, in the gate medium buffering that need to retain
Required photoetching offset plate figure is produced on layer, exposes the region that need to be removed.
2nd, it is etched using reactive ion etching (reactive ion etching, RIE), inductively coupled plasma
The methods of (inductive coupled plasma, ICP), laser ablation, ion beam milling or wet etching, is to gate medium buffer layer
It performs etching.Wherein,
Reactive ion etching (reactive ion etching, RIE), inductively coupled plasma (inductive
Coupled plasma, ICP) etching, the material that uses of laser ablation and ion beam milling can include argon Ar, oxygen O2, nitrogen
N2, helium He, chlorine Cl2, sulfur hexafluoride SF6, carbon tetrafluoride CF4, fluoroform CHF3, octafluorocyclobutane C4F8Or Nitrogen trifluoride
NF3。
The material that wet etching uses can include phosphoric acid H3PO4, hydrofluoric acid HF, buffered hydrofluoric acid BOE, sulfuric acid H2SO4、
Nitric acid HNO3, hydrochloric acid HCl, acetic acid CH3COOH, oxydol H2O2, potassium hydroxide KOH or tetramethylammonium hydroxide TMAH, to prepare
The corrosive liquid of various concentration.
The method for oxidation of gate medium buffer layer is：
Gate medium buffer layer is aoxidized using the method for high-temperature oxydation.Wherein, oxidizing temperature is 600~1500 DEG C,
Oxygen O can be included by aoxidizing other2, hydrogen H2, vapor H2O, nitrogen N2, hydrogen chloride HCl, trichlorosilane SiHCl3, one oxidation
Nitrogen NO, laughing gas N2O, ammonia NH3With at least any one in argon Ar other.
4th, graphene layer is formed on gate dielectric layer.
Graphene layer can be formed in the present embodiment as steps described below, specially：
1st, using mechanical stripping method, chemical stripping method, solvent-thermal method, epitaxy method, organic synthesis method, diamond high temperature
Conversion method, graphite layers intercalation stripping method, chemical vapour deposition technique or SiC epitaxial growth methods prepare graphene.
It 2nd, will using matrix etching method, roll-to-roll methods, electrochemistry transfer method, dry method transfer method or mechanical stripping method
The graphene is transferred in the contact hole, forms graphene layer.Wherein, the thickness of graphene layer is 0.5~5nm.
The preparation method of graphene is illustrated by taking chemical vapour deposition technique as an example below, specially：
(1) it being passed through pure argon Ar in reative cell, discharges adsorption gas, temperature for 180~260 DEG C and keeps 15~
Then 30min is evacuated to 10-5~10-6Torr。
(2) hydrogen H is passed through into reative cell2Carry out surface preparation, 2~25sccm of gas flow, reative cell vacuum degree
0.2~1Torr, temperature are 950~1050 DEG C, 1~15min of processing time.
(3) hydrogen H is passed through into reative cell2With methane CH4Start the growth of graphene, keep hydrogen H2With methane CH4's
Flow-rate ratio is 10:1~2:1, hydrogen H2Flow is 40~250sccm, methane CH4Flow is 2~25sccm, air pressure for 0.2~
1atm, temperature are 1050~1350 DEG C, and the heating-up time is 15~60min, retention time 20-60min, and then Temperature fall, is protected
It holds flow and air pressure is constant, complete the growth of graphene.
5th, metal is deposited on graphene layer and forms gate electrode, and insulating layer is formed on the gate electrode and epitaxial layer.
Gate electrode is prepared using the preparation method of gate medium buffer layer in above-mentioned steps three in the present embodiment.Wherein, grid electricity
The thickness of pole is at least 0.1~5 μm, polysilicon may be used, Al, Ti, Ni, W or Pt material are made, while are doped with first
The ion of conduction type or the second conduction type is to enhance the conductivity type of gate electrode.
Gate electrode is completely covered insulating layer in the present embodiment, so as in gate electrode, epitaxial layer, the first impurity range and second
Electric isolation is formed between impurity range.Insulating layer has 0.5~10 μm of thickness, can be silica, silicon nitride, phosphorosilicate glass
PSG, Pyrex BSG, boron-phosphorosilicate glass BPSG, polysilicon or oxygen-containing polycrystalline silicon material and its composite construction.
The preparation method of insulating layer is：
1st, atomic layer deposition (atomic layer deposition, ALD), low-pressure chemical vapor deposition may be used
(low pressure chemical vapor deposition, LPCVD), plasma reinforced chemical vapour deposition (plasma
Enhanced chemical vapor deposition, PECVD) or sputtering mode prepare insulating layer.
2nd, reflux technique is carried out to it after forming the insulating layer, by marginal portion corners and improves the matter of insulating layer
Amount.Wherein,
(1) separation layer can be inserted between gate electrode and insulating layer, prevents reflux technique from being impacted to gate electrode.
(2) temperature of reflux technique is 500~1100 DEG C, and the gas used can include oxygen O2, hydrogen H2, vapor
H2O, nitrogen N2, hydrogen chloride HCl, trichlorosilane SiHCl3, nitric oxide NO, laughing gas N2O, ammonia NH3Or at least appoint in argon Ar
A kind of gas.
It (3) can also be by the marginal portion corners of gate electrode and oxidation in refiow process.
Further, it forms gate contact hole in the present embodiment step S102 and the first contact hole can be as steps described below
Implement.
Gate contact hole is formed on the corresponding insulating layer of gate electrode, it is miscellaneous in the corresponding insulating layer of the second impurity range and first
Respectively upper formation first contact hole is exposed on the corresponding insulating layer in region outside gate dielectric layer in matter area.Wherein,
One contact hole can be the contact hole of the shapes such as round, rectangular, strip, hexagon or octagon.
The preparation method of contact hole is：Contact hole is prepared using the method for photoetching, corrosion and/or etching.Wherein,
(1) it may be used first to corrode and etch or first etch the method corroded again again.
The side wall of (2) first contact holes can be formed including wet etching and dry etching two-stage region, by adjusting corruption
Erosion and etch process parameters and depth can obtain the contact hole at different lateral inclination angle, so as to be suitable for Miniature component
And obtuse angle is formed at sidewall edge, convenient for the manufacture of subsequent metal electrode.
(3) gate medium buffer layer is patterned in the method and step of photoetching, corrosion and/or etching and above-mentioned steps three
Method and step it is identical.
Further, gate contact electrode is formed in the present embodiment step S103 and the first contact electrode can be according to following
Step is implemented.
1st, metal layer is prepared using evaporation, sputtering or plating mode.Wherein, the metal filled to graphene layer may be used
Tungsten, chromium, platinum, titanium, silver, gold, aluminium, nickel or copper and its alloy or its composite construction, metal layer thickness are 0.01~5 μm.
2nd, annealing process is carried out to metal layer so that it forms ohm with the first impurity range, the second impurity range and gate electrode
Contact.Wherein, annealing temperature is 300~1100 DEG C, and the gas used can include hydrogen H2, nitrogen N2Or in argon Ar at least
A kind of gas.
Further, the second contact electrode is formed in the present embodiment step S103 to be implemented as steps described below.
1st, deposit metal on the contact layer, may be used tungsten, chromium, platinum, titanium, silver, gold, aluminium, nickel or copper and its alloy or its
Composite construction.
2nd, annealing process is carried out to the metal so that it forms Ohmic contact with contact layer.Wherein, annealing temperature 300
~1100 DEG C, the gas used can include hydrogen H2, nitrogen N2Or at least one of argon Ar gas.Second contact electrode
Thickness is 0.1~5 μm.
Based on above-mentioned preparation method, the present invention has further related to the embodiment of three kinds of coordination electrode preparation methods,
Each embodiment is illustrated respectively below in conjunction with the accompanying drawings.
Embodiment 1
Step S201：Prepare epitaxial layer
Fig. 2 is 1 epitaxial layers schematic diagram of the embodiment of the present invention, as shown in the figure, in the upper of n-type substrate 101 in the present embodiment
Surface growing n-type epitaxial layer 102.
Step S202：Prepare silicon carbide
Fig. 3 is silicon carbide schematic diagram in the embodiment of the present invention 1, as shown in the figure, in N-shaped epitaxial layer in the present embodiment
Two p-type silicon carbides 111 are formed in 102.
Step S203：First impurity range, the second impurity range and third impurity range
Fig. 4 is the first impurity range, the second impurity range and third impurity range schematic diagram in the embodiment of the present invention 1, as shown in the figure,
First impurity range of N-shaped 121 is respectively formed in each p-type silicon carbide 111 and a p-type second is miscellaneous in the present embodiment
Matter area 112, and the epitaxial layer 102 between two p-type silicon carbides 111 is partially formed N-shaped third impurity range 131,
In, form conduction channel region between the first impurity range 121 and third impurity range 131.Meanwhile in the back side shape of n-type substrate 101
Into n++ types contact layer 103.
Step S204：Prepare gate medium buffer layer
Fig. 5 is gate medium buffer layer schematic diagram in the embodiment of the present invention 1, as shown in the figure, gate medium buffers in the present embodiment
Layer 141 is covered on the conduction channel region of two p-type silicon carbides 111, on third impurity range and is respectively adjacent to conduction
On the subregion of the first impurity range of N-shaped 121 of channel region.
Step S205：Prepare gate dielectric layer
Fig. 6 is gate dielectric layer schematic diagram in the embodiment of the present invention 1, as shown in the figure, delaying in the present embodiment in gate medium
Rush formation gate dielectric layer 142 on layer 141.
Step S206：Prepare graphene layer and gate electrode
Fig. 7 is graphene layer and gate electrode schematic diagram in the embodiment of the present invention 1, as shown in the figure, in grid in the present embodiment
Graphene layer 181 is formed on dielectric layer 142, gate electrode 151 is then formed on the graphene layer 181.
Step S207：Prepare insulating layer
Fig. 8 is insulating layer schematic diagram in the embodiment of the present invention 1, as shown in the figure, in gate electrode 151 and extension in the present embodiment
Insulating layer 161 is formed on layer 102.
Step S208：Prepare gate contact electrode and the first contact electrode
Fig. 9 is gate contact electrode and the first contact electrode schematic diagram in the embodiment of the present invention 1, as shown in the figure, this implementation
Gate contact hole 172 is formed in example on 151 corresponding insulating layer 161 of gate electrode, in 112 corresponding insulating layer of the second impurity range
161 and first are exposed on the corresponding insulating layer 161 in region outside gate dielectric layer 142 upper shape respectively in impurity range 122
Into the first contact hole 171.Then it fills metal to the first contact hole 171 and gate contact hole 172 and is respectively formed the first contact electricity
Pole 113, first contacts electrode 122 and gate contact electrode 152.
Step S209：Prepare the second contact electrode
Figure 10 is the second contact electrode schematic diagram in the embodiment of the present invention 1, as shown in the figure, in contact layer in the present embodiment
Metal is deposited on 103 and forms the second contact electrode 104.
Embodiment 2
Step S301：Prepare epitaxial layer
Figure 11 is 2 epitaxial layers schematic diagram of the embodiment of the present invention, as shown in the figure, in the upper of n-type substrate 201 in the present embodiment
Surface growing n-type epitaxial layer 202.
Step S302：Prepare silicon carbide
Figure 12 is silicon carbide schematic diagram in the embodiment of the present invention 2, as shown in the figure, in N-shaped epitaxial layer in the present embodiment
Two p-type silicon carbides 211 are formed in 202.
Step S303：First impurity range, the second impurity range and channel layer
Figure 13 is the first impurity range, the second impurity range and channel layer schematic diagram in the embodiment of the present invention 2, as shown in the figure, this
First impurity range of N-shaped 221 and second impurity of p-type are respectively formed in embodiment in each p-type silicon carbide 211
Area 212, and the conduction channel region of two p-type silicon carbides 211 and its between substrate on form n-type channel layer 231.
Meanwhile form n++ types contact layer 203 at the back side of n-type substrate 201.
Step S304：Prepare gate medium buffer layer
Figure 14 is gate medium buffer layer schematic diagram in the embodiment of the present invention 2, as shown in the figure, gate medium buffers in the present embodiment
Layer 241 is covered in n-type channel layer 231 and is respectively adjacent to the subregion of the first impurity range of N-shaped 221 of conduction channel region
On.
Step S305：Prepare gate dielectric layer
Figure 15 is gate dielectric layer schematic diagram in the embodiment of the present invention 2, as shown in the figure, delaying in the present embodiment in gate medium
Rush formation gate dielectric layer 242 on layer 241.
Step S306：Prepare graphene layer and gate electrode
Figure 16 is graphene layer and gate electrode schematic diagram in the embodiment of the present invention 2, as shown in the figure, in grid in the present embodiment
Graphene layer 281 is formed on dielectric layer 242, gate electrode 251 is then formed on the graphene layer 281.
Step S307：Prepare insulating layer
Figure 17 is insulating layer schematic diagram in the embodiment of the present invention 2, as shown in the figure, in gate electrode 251 and outside in the present embodiment
Prolong formation insulating layer 261 on layer 102.
Step S308：Prepare gate contact electrode and the first contact electrode
Figure 18 is gate contact electrode and the first contact electrode schematic diagram in the embodiment of the present invention 1, as shown in the figure, this implementation
Gate contact hole 272 is formed in example on 251 corresponding insulating layer 261 of gate electrode, in 212 corresponding insulating layer of the second impurity range
261 and first are exposed on the corresponding insulating layer 261 in region outside gate dielectric layer 242 upper shape respectively in impurity range 222
Into the first contact hole 271.Then it fills metal to the first contact hole 271 and gate contact hole 272 and is respectively formed the first contact electricity
Pole 213, first contacts electrode 222 and gate contact electrode 252.
Step S309：Prepare the second contact electrode
Figure 19 is the second contact electrode schematic diagram in the embodiment of the present invention 2, as shown in the figure, in contact layer in the present embodiment
Metal is deposited on 203 and forms the second contact electrode 204.
Embodiment 3
Step S401：Prepare epitaxial layer
Figure 20 is 3 epitaxial layers schematic diagram of the embodiment of the present invention, as shown in the figure, in the upper of n-type substrate 301 in the present embodiment
Surface growing n-type epitaxial layer 302.
Step S402：Prepare silicon carbide
Figure 21 is silicon carbide schematic diagram in the embodiment of the present invention 3, as shown in the figure, in N-shaped epitaxial layer in the present embodiment
Two p-type silicon carbides 311 are formed in 302.
Step S403：First impurity range, the second impurity range, field limiting ring and field cut-off ring
Figure 22 is that ring schematic diagram is ended in first impurity range, the second impurity range, field limiting ring and field in the embodiment of the present invention 3, such as
Shown in figure, first impurity range of N-shaped 321 and a p are respectively formed in the present embodiment in a p-type silicon carbide 311
The second impurity range of type 312 is respectively formed two the first impurity ranges of N-shaped 321 and a p in another p-type silicon carbide 311
The second impurity range of type 312.
Two p-type field limiting rings 314 and a field cut-off ring are formed at the edge of N-shaped epitaxial layer 302, this ends under ring
Half portion is divided into first cut-off ring 315, and top half is second cut-off ring 323.Meanwhile it is formed at the back side of n-type substrate 301
N++ types contact layer 303.
Step S404：Prepare gate medium buffer layer
Figure 23 is gate medium buffer layer schematic diagram in the embodiment of the present invention 3, as shown in the figure, gate medium buffers in the present embodiment
On the subregion of the first impurity range of N-shaped 321 that layer 341 was covered on conduction channel region, was respectively adjacent to conduction channel region,
On the subregion of the field limiting ring 314 and upper surface of epitaxial layer 302.
Step S405：Prepare gate dielectric layer
Figure 24 is gate dielectric layer schematic diagram in the embodiment of the present invention 3, as shown in the figure, delaying in the present embodiment in gate medium
Rush formation gate dielectric layer 342 on layer 341.
Step S406：Prepare graphene layer and gate electrode
Figure 25 is graphene layer and gate electrode schematic diagram in the embodiment of the present invention 3, as shown in the figure, in grid in the present embodiment
Graphene layer 381 is formed on dielectric layer 342, gate electrode 351 is then formed on the graphene layer 381.
Step S407：Prepare insulating layer
Figure 26 is insulating layer schematic diagram in the embodiment of the present invention 3, as shown in the figure, in gate electrode 351 and outside in the present embodiment
Prolong formation insulating layer 361 on layer 302.
Step S408：Prepare gate contact electrode and the first contact electrode
Figure 27 is gate contact electrode and the first contact electrode schematic diagram in the embodiment of the present invention 3, as shown in the figure, this implementation
Gate contact hole 372 is formed in example on 351 corresponding insulating layer 361 of gate electrode, in 312 corresponding insulating layer of the second impurity range
361 and first are exposed on the corresponding insulating layer 361 in region outside gate dielectric layer 342 upper shape respectively in impurity range 322
Into the first contact hole 371.Then it fills metal to the first contact hole 371 and gate contact hole 372 and is respectively formed the first contact electricity
Pole 313, first contacts electrode 322 and gate contact electrode 352.
Step S409：Prepare the second contact electrode
Figure 28 is the second contact electrode schematic diagram in the embodiment of the present invention 3, as shown in the figure, in n-type substrate in the present embodiment
Metal is deposited on 301 back side and forms the second contact electrode 303.
The present invention also provides a kind of MOSFET power devices, and provide specific implementation.
In the present embodiment MOSFET power devices include with the first conduction type substrate, epitaxial layer and contact layer and
Graphene layer, gate electrode, gate contact electrode, the first contact electrode and the second contact electrode.Wherein,
Epitaxial layer and contact layer are separately positioned on the front and back of substrate, and graphene layer is arranged on preset on epitaxial layer
On gate dielectric layer, gate electrode is arranged on graphene layer, and gate contact electrode is arranged on preset on epitaxial layer and and grid
In the corresponding gate contact hole of electrode, the first contact electrode is arranged in preset first contact hole of epitaxial layer, the second contact electricity
Pole is set on the contact layer.
The impurity concentration 1 × 10 of epitaxial layer14cm-3~1 × 1016cm-3, thickness is 10~200 μm；The thickness of graphene layer
For 0.5~5nm；Gate contact electrode, first contact electrode and second contact electrode metal using tungsten, chromium, platinum, titanium, silver,
At least one of gold, aluminium, nickel and copper metal, and its thickness is 0.1~5 μm.Gate electrode is with the more of the first conduction type
Crystal silicon, Al, Ti, Ni, W or Pt；Alternatively, gate electrode is the polysilicon with the second conduction type, Al, Ti, Ni, W or Pt.Grid electricity
The thickness of pole is 0.1~5 μm.
The gate contact electrode of MOSFET power devices is arranged on graphene layer in the present embodiment, excellent based on graphene
Conduction property so that the MOSFET power devices have relatively low conducting resistance and smaller reverse recovery time.
Further, MOSFET power devices can also include following structures in the present embodiment.
MOSFET power devices further include silicon carbide and insulating layer in the present embodiment.Wherein,
Silicon carbide is arranged in epitaxial layer, and impurity concentration is 1 × 1013cm-3~5 × 1020cm-3, junction depth 0.1
~3 μm.Silicon carbide includes the first impurity range with the first conduction type and the second impurity with the second conduction type
Area, wherein：First impurity range and the second impurity range are arranged according to spaced sequence in silicon carbide, the first impurity range
And conduction channel region is formed in the silicon carbide between epitaxial layer upper surface.Insulating layer is arranged on gate electrode and epitaxial layer
On.
Further, in the present embodiment in embodiment gate dielectric layer, gate contact hole and the first contact hole position
Relationship is：
Gate dielectric layer is arranged on the upper surface of conduction channel region and is respectively adjacent to the first of the conduction channel region
The upper surface part subregion of impurity range and the upper surface of epitaxial layer.The thickness of gate dielectric layer is 10~500nm.
Gate contact hole is arranged on the corresponding insulating layer of gate electrode.
First contact hole is separately positioned on the first impurity range and the corresponding insulating layer of the second impurity range.
Further, MOSFET power devices further include following structures in the present embodiment.
MOSFET power devices further include in the present embodiment：Field limiting ring, cut-off ring, terminal structure and gate medium buffer layer.
Wherein, terminal structure is using groove isolation construction, inclined-plane junction structure, knot terminal expansion structure, floating field ring, more floating plot structures
Or spatial modulation structure.
Gate medium buffer layer is arranged on the upper surface of conduction channel region and is respectively adjacent to the first of the conduction channel region
The upper surface part subregion of impurity range and the upper surface of epitaxial layer, gate dielectric layer are arranged on the gate medium buffer layer.Its
In,
Gate dielectric layer be doping after polysilicon, non-crystalline silicon, unformed silicon, silica, silicon nitride, aluminium oxide or
High-k dielectric layer, and the impurity concentration in the region of adjacent epitaxial layer is higher than the region far from epitaxial layer in the gate dielectric layer
Impurity concentration；The impurity of doping is O ions, N ions, P ion, B ions or Al ions；Alternatively, gate dielectric layer is mixed to be non-
Polysilicon, non-crystalline silicon, unformed silicon, silica, silicon nitride, aluminium oxide or high-k dielectric layer after miscellaneous.
Further, MOSFET power devices further include following structures in the present embodiment.
MOSFET power devices further include third impurity range or channel layer in the present embodiment.Wherein,
Third impurity range is the doped region with the first conduction type, is arranged on outer between two silicon carbides
Prolong in layer region.The thickness of third impurity range is 0.01~0.5 μm, and doping concentration is 5 × 1015cm-3~5 × 1016cm-3And its
Doping concentration is higher than the doping concentration of epitaxial layer.
Channel layer is the channel layer with the first conduction type, is arranged on the epi region between two silicon carbides
In domain and respectively in two conduction channel regions neighbouring with the epitaxial layer region.The thickness of channel layer is 0.01~0.5 μm,
Doping concentration is 5 × 1015cm-3~5 × 1016cm-3And its doping concentration is higher than the doping concentration of epitaxial layer.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
God and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (17)
1. a kind of coordination electrode preparation method, which is characterized in that the method includes：
Gate dielectric layer is formed in the front of substrate, and graphene layer and grid electricity are sequentially formed on the gate dielectric layer
Pole；
Gate contact hole is formed on the gate electrode, and is exposed to other than gate dielectric layer in the front of the substrate
The first contact hole is formed on region；
To the gate contact hole and the first contact hole filling metal, it is respectively formed gate contact electrode and the first contact electrode；
Metal is deposited at the back side of the substrate, forms the second contact electrode.
2. a kind of coordination electrode preparation method as described in claim 1, which is characterized in that the substrate is with the first conduction
The silicon carbide substrates of type；The front formation gate dielectric layer in substrate includes：
In epitaxial layer of the front growth with the first conduction type of the substrate, and being formed on the epitaxial layer has second to lead
The silicon carbide of electric type；
The ion for being doped with the first conduction type in the silicon carbide respectively forms the first impurity range, is doped with the
The ion of two conduction types forms the second impurity range, wherein：First impurity range and the second impurity range are according to spaced
Sequence is arranged in silicon carbide；It is formed in silicon carbide between first impurity range and epitaxial layer upper surface conductive
Channel region；
In the upper surface of the conduction channel region and the upper surface part for the first impurity range for being respectively adjacent to the conduction channel region
Subregion and the upper surface of epitaxial layer form gate dielectric layer；
It is described to include in the front formation gate contact hole of substrate and the first contact hole：It is formed on the gate electrode and epitaxial layer
Insulating layer；Gate contact hole is formed on the corresponding insulating layer of the gate electrode, in the corresponding insulating layer of second impurity range
The first contact is respectively formed on insulating layer corresponding with the region being exposed to outside gate dielectric layer in first impurity range
Hole.
3. a kind of coordination electrode preparation method as described in claim 1, which is characterized in that described to be formed in silicon carbide
It is further included during second impurity range：Field limiting ring, field cut-off ring and terminal structure are formed over the substrate, specially:
The ion of the second conduction type, shape are doped with to the epitaxial layer by preset multiple field limiting ring ion implanting windows
Into multiple field limiting rings；
By preset one cut-off ring ion implanting window to the epitaxial layer be sequentially doped with the second conduction type from
Son and the ion with the first conduction type are respectively formed first cut-off ring and second cut-off ring；
The terminal structure is using groove isolation construction, inclined-plane junction structure, knot terminal expansion structure, floating field ring, more floating areas
Structure or spatial modulation structure.
4. a kind of coordination electrode preparation method as claimed in claim 2, which is characterized in that
Include before the formation gate dielectric layer：Epitaxial layer region between two silicon carbides is doped with
The ion of first conduction type forms third impurity range, conducting channel is formed between first impurity range and third impurity range
Region；Alternatively,
Epitaxial layer region and neighbouring with the epitaxial layer region respectively two conductive ditches between two silicon carbides
Road region doping has the ion of the first conduction type, forms channel layer.
5. a kind of coordination electrode preparation method as claimed in claim 2, which is characterized in that
Include before the formation gate dielectric layer：In the upper surface of the conduction channel region and it is respectively adjacent to the conduction
The upper surface part subregion of first impurity range of channel region and the upper surface of epitaxial layer form gate medium buffer layer.
6. a kind of coordination electrode preparation method as claimed in claim 2, which is characterized in that
The formation gate dielectric layer includes：Using atomic layer deposition, low-pressure chemical vapor deposition, plasma-reinforced chemical gas
Mutually deposition, sputtering or method for oxidation form gate dielectric layer；
The oxidizing temperature of the method for oxidation is 600~1700 DEG C.
7. a kind of coordination electrode preparation method as claimed in claim 2, which is characterized in that
It is described to include after formation insulating layer on gate electrode and epitaxial layer：The insulating layer is carried out at 500~1100 DEG C
Reflux；
The gas of the reflux uses oxygen O2, hydrogen H2, vapor H2O, nitrogen N2, hydrogen chloride HCl, trichlorosilane SiHCl3、
Nitric oxide NO, laughing gas N2O, ammonia NH3Or at least any one gas in argon Ar.
8. a kind of coordination electrode preparation method as described in claim 1, which is characterized in that
The graphene layer that formed on gate dielectric layer includes：
Using mechanical stripping method, chemical stripping method, solvent-thermal method, epitaxy method, organic synthesis method, diamond pyrolytic conversion
Method, graphite layers intercalation stripping method, chemical vapour deposition technique or SiC epitaxial growth methods prepare graphene；
Using matrix etching method, roll-to-roll methods, electrochemistry transfer method, dry method transfer method or mechanical stripping method by the stone
Black alkene is transferred on the gate dielectric layer, forms graphene layer.
9. a kind of coordination electrode preparation method as described in claim 1, which is characterized in that
It is described to include before the back side of substrate deposits metal：Be doped at the back side of the substrate the first conduction type from
Son forms contact layer.
10. a kind of MOSFET power devices, which is characterized in that the MOSFET power devices include：
Substrate, epitaxial layer and contact layer with the first conduction type；The epitaxial layer and contact layer are separately positioned on the lining
The front and back at bottom；
Graphene layer is arranged on epitaxial layer on preset gate dielectric layer；
Gate electrode is arranged on the graphene layer；
Gate contact electrode is arranged in gate contact hole preset on epitaxial layer and corresponding with gate electrode；
First contact electrode, is arranged in preset first contact hole of epitaxial layer；
Second contact electrode, is arranged on the contact layer.
11. a kind of MOSFET power devices as claimed in claim 10, which is characterized in that
The MOSFET power devices further include：
Silicon carbide is arranged in the epitaxial layer；The silicon carbide includes first with the first conduction type
Impurity range and the second impurity range with the second conduction type；Wherein：First impurity range and the second impurity range are according to mutual
The sequence at interval is arranged in silicon carbide, shape in the silicon carbide between first impurity range and epitaxial layer upper surface
Into conduction channel region；
Insulating layer is arranged on the gate electrode and epitaxial layer.
12. a kind of MOSFET power devices as claimed in claim 11, which is characterized in that
The gate dielectric layer is arranged on the upper surface of the conduction channel region and is respectively adjacent to the conduction channel region
The upper surface part subregion of first impurity range and the upper surface of epitaxial layer；
The gate contact hole is arranged on the corresponding insulating layer of the gate electrode, and first contact hole is separately positioned on described
On first impurity range and the corresponding insulating layer of the second impurity range.
13. a kind of MOSFET power devices as claimed in claim 11, which is characterized in that
The MOSFET power devices further include：Field limiting ring, field cut-off ring, terminal structure and gate medium buffer layer；
The terminal structure is using groove isolation construction, inclined-plane junction structure, knot terminal expansion structure, floating field ring, more floating areas
Structure or spatial modulation structure；
The gate medium buffer layer is arranged on the upper surface of the conduction channel region and is respectively adjacent to the conduction channel region
The upper surface part subregion of first impurity range and the upper surface of epitaxial layer, the gate dielectric layer are arranged on gate medium buffering
On layer；The gate medium buffer layer is the silica for adulterating Nitrogen ion N, phosphonium ion P, boron ion B, aluminium ion Al or carbon ion C,
Its thickness is 1~100nm.
14. a kind of MOSFET power devices as claimed in claim 11, which is characterized in that
The MOSFET power devices further include：Third impurity range or channel layer；
The third impurity range is the doped region with the first conduction type, is arranged between two silicon carbides
Epitaxial layer region in；The thickness of the third impurity range is 0.01~0.5 μm, and doping concentration is 5 × 1015cm-3~5 ×
1016cm-3And its doping concentration is higher than the doping concentration of the epitaxial layer；
The channel layer be the channel layer with the first conduction type, the extension being arranged between two silicon carbides
In layer region and respectively in two conduction channel regions neighbouring with the epitaxial layer region；The thickness of the channel layer is 0.01
~0.5 μm, doping concentration is 5 × 1015cm-3~5 × 1016cm-3And its doping concentration is higher than the doping concentration of the epitaxial layer.
15. a kind of MOSFET power devices as claimed in claim 10, which is characterized in that
The gate dielectric layer be doping after polysilicon, non-crystalline silicon, unformed silicon, silica, silicon nitride, aluminium oxide or
High-k dielectric layer, and the impurity concentration in the region of adjacent epitaxial layer is higher than the region far from epitaxial layer in the gate dielectric layer
Impurity concentration；The impurity of the doping is O ions, N ions, P ion, B ions or Al ions；
Alternatively,
The gate dielectric layer is polysilicon, non-crystalline silicon, unformed silicon, silica, silicon nitride, the aluminium oxide after undoped
Or high-k dielectric layer.
16. a kind of MOSFET power devices as claimed in claim 10, which is characterized in that
The gate electrode is the polysilicon with the first conduction type, Al, Ti, Ni, W or Pt；Alternatively,
The gate electrode is the polysilicon with the second conduction type, Al, Ti, Ni, W or Pt.
17. a kind of MOSFET power devices as claimed in claim 11, which is characterized in that
The impurity concentration 1 × 10 of the epitaxial layer14cm-3~1 × 1016cm-3, thickness is 10~200 μm；
The impurity concentration of the silicon carbide is 1 × 1013cm-3~5 × 1020cm-3, junction depth is 0.1~3 μm；
The impurity concentration of first impurity range and the second impurity range is 1 × 1017cm-3~5 × 1021cm-3, thickness is 0.1
~0.8 μm；
The thickness of the gate dielectric layer is 10~500nm；
The thickness of the gate electrode is 0.1~5 μm；
The thickness of the graphene layer is 0.5~5nm；
The gate contact electrode, first contact electrode and second contact electrode metal using tungsten, chromium, platinum, titanium, silver, gold,
At least one of aluminium, nickel and copper metal, and its thickness is 0.1~5 μm.
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