CN105552117A - Semiconductor device with metal gate electrode and manufacturing method for semiconductor device - Google Patents
Semiconductor device with metal gate electrode and manufacturing method for semiconductor device Download PDFInfo
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- CN105552117A CN105552117A CN201510953152.8A CN201510953152A CN105552117A CN 105552117 A CN105552117 A CN 105552117A CN 201510953152 A CN201510953152 A CN 201510953152A CN 105552117 A CN105552117 A CN 105552117A
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 108
- 239000002184 metal Substances 0.000 title claims abstract description 108
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 230000004888 barrier function Effects 0.000 claims abstract description 86
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 47
- 229910021389 graphene Inorganic materials 0.000 claims abstract description 47
- 238000000034 method Methods 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000009713 electroplating Methods 0.000 claims abstract description 8
- 239000000126 substance Substances 0.000 claims abstract description 8
- 238000005516 engineering process Methods 0.000 claims description 25
- 239000000463 material Substances 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 238000005498 polishing Methods 0.000 claims description 8
- 239000000243 solution Substances 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- 230000008569 process Effects 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- HZAXFHJVJLSVMW-UHFFFAOYSA-N 2-Aminoethan-1-ol Chemical compound NCCO HZAXFHJVJLSVMW-UHFFFAOYSA-N 0.000 claims description 3
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 claims description 3
- 229910001151 AlNi Inorganic materials 0.000 claims description 3
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims description 3
- 229910018565 CuAl Inorganic materials 0.000 claims description 3
- IAZDPXIOMUYVGZ-UHFFFAOYSA-N Dimethylsulphoxide Chemical compound CS(C)=O IAZDPXIOMUYVGZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 229910010038 TiAl Inorganic materials 0.000 claims description 3
- 229910010165 TiCu Inorganic materials 0.000 claims description 3
- 229910010380 TiNi Inorganic materials 0.000 claims description 3
- 239000000908 ammonium hydroxide Substances 0.000 claims description 3
- 229960001760 dimethyl sulfoxide Drugs 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- 229910000040 hydrogen fluoride Inorganic materials 0.000 claims description 3
- 239000011259 mixed solution Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 150000003512 tertiary amines Chemical class 0.000 claims description 3
- 238000007740 vapor deposition Methods 0.000 claims description 3
- 239000013078 crystal Substances 0.000 abstract description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 230000007547 defect Effects 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 229910016862 AlW Inorganic materials 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 150000001721 carbon Chemical group 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 229920006395 saturated elastomer Polymers 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229910000906 Bronze Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 1
- LDDQLRUQCUTJBB-UHFFFAOYSA-N ammonium fluoride Chemical compound [NH4+].[F-] LDDQLRUQCUTJBB-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000010974 bronze Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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Abstract
The invention belongs to the technical field of a manufacturing process for a semiconductor integrated circuit, and discloses a semiconductor device with a metal gate electrode. The semiconductor device comprises a substrate, an insulating layer with a groove, and a metal gate electrode structure formed in the groove, wherein the metal gate electrode structure comprises a high K gate dielectric layer, a work function metal layer, a graphene barrier layer, a metal seed crystal layer and gate metal. The invention also discloses a method for manufacturing the semiconductor device with the metal gate electrode. By adoption of the barrier layer made from graphene, the outline appearance of the metal gate groove can be well kept, and the filling property of subsequent gate metal electroplating is not affected; meanwhile, the semiconductor device is excellent in thermal stability and chemical stability; and in addition, the shortcoming of inconsistency of the heights of the metal gates is also avoided, and the yield and the consistency of the device are improved.
Description
Technical field
The invention belongs to semiconductor integrated circuit manufacturing process technology field, relate to a kind of semiconductor device and the manufacture method thereof with metal gate electrode.
Background technology
Since over half a century, integrated circuit (IC) manufacturing technology follows Moore's Law always, realize integration density to double for every 1.5 years, correspondingly, the scales of Metal-oxide-semicondutor field effect transistor (MOSFET) reduces, and the thickness of grid oxic horizon is also constantly thinning.But enter 45nm technology node, traditional SiO
2close to physics limit, there is serious integrity problem in the thickness of grid oxic horizon, industry starts to adopt SiON to replace SiO
2, traditional grid structure is extended to 32nm technology generation.But enter 28nn technology node, SiON grid oxic horizon cannot meet high performance device requirement, can only be applied to the low energy-consumption electronic device of some low sides.
In order to maintain Moore's Law, in 28nm and following technology generation, industry generally adopts high dielectric constant (High-k) material, and it has high dielectric constant, has the superior function of similar SiO2 simultaneously.The introducing of new material always brings certain risk, and High-k material is incompatible with conventional gate electrodes material (polysilicon), adopts metal replacement polysilicon to can further improve device performance as gate electrode.HKMG (high-k insulating barrier+metal gate electrode) technology effective supports that CMOS technology is advanced to 28nm and following technology generation.
The material that existing metal gate electrode adopts usually is generally aluminium, titanium-aluminium alloy, tungsten and aluminum bronze etc.Fig. 1 is the process chart that existing preparation has the semiconductor device of metal gate electrode, and the method comprises the following steps:
Refer to Fig. 1 a, step S01, the Semiconductor substrate 101 providing to have a dielectric layer 102, form groove 103 in described dielectric layer 102, and high-k gate dielectric layer 104 is formed on the bottom of described groove 103, and the sidewall of described groove 103 has side wall protection layer 105;
Refer to Fig. 1 b, step S02, form workfunction layers 106 and barrier layer 107 successively at the upper surface of the upper surface of described high-k gate dielectric layer 104, the sidewall of side wall protection layer 105 and dielectric layer 102;
Refer to Fig. 1 c, step S03, in described groove 103, fill up grid metal level 108, and described grid metal level 108 covers the upper surface on described barrier layer 107;
Referring to Fig. 1 d, step S04, adopting CMP (Chemical Mechanical Polishing) process (CMP) by removing the grid metal level 108 of described dielectric layer 102 upper surface, barrier layer 107 and workfunction layers 106 successively, to form metal gate electrode 109.
But, adopt above-mentioned preparation method to there will be following two problems:
First, refer to Fig. 2 a, when barrier layer filling groove, if adopt the mode of physical vapour deposition (PVD), easily can there are 200 (overhang) that overhang at groove top, groove profile pattern is changed, the opening size of groove can diminish, difficulty is caused to the filling of follow-up grid metal level, easily produces the defects such as cavity 201 in a groove, affect the reliability of device.
Secondly, when adopting common chemical vapour deposition (CVD), physical vapour deposition (PVD) or non-selective electroplating technology to fill grid metal level in a groove, consider the process window issue of follow-up CMP, need to fill excessive grid metal level.And the long period CMP remove surface grid metal level, barrier layer and workfunction layers time, due to the high selectivity polishing fluid that the polishing of grid metal level adopts, CMP is vulnerable to the impact of pattern density effect (loadingeffect) simultaneously, refer to Fig. 2 b, compared with normal metal gate electrode 203, there will be depression 204 (erosion) in graphics intensive district thus the phenomenon causing metal gate electrode height inconsistent, the yield of device and consistency are reduced.Therefore, those skilled in the art need badly provides a kind of semiconductor device and the manufacture method thereof with metal gate electrode, improves the pattern of existing metal gate electrode, improves yield and the consistency of device.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of semiconductor device and the manufacture method thereof with metal gate electrode, improves the pattern of existing metal gate electrode, improves yield and the consistency of device.
In order to solve the problems of the technologies described above, the invention provides a kind of semiconductor device with metal gate electrode, described semiconductor device comprises:
Substrate;
Insulating barrier, described insulating barrier covers the upper surface of described substrate, and described insulating barrier has a groove;
Polymetal gate electrode structure, is formed in described groove; Wherein, described polymetal gate electrode structure comprises:
High-K gate dielectric layer, covers the bottom of described groove;
Workfunction layers, covers the upper surface of described high-K gate dielectric layer and the sidewall of groove;
Graphene barrier layer, covers upper surface and the sidewall of described workfunction layers;
Metal seed layer, covers upper surface and the sidewall on described Graphene barrier layer;
Grid metal, is filled in described groove, and the upper surface of described grid metal is concordant with the upper surface of described insulating barrier.
Preferably, the material of described workfunction layers is one or more in TiN, TiAl, TaN, TiC, TaC, Ti, TiCu, TiNi, AlNi.
Preferably, the material of described grid metal is Cu, CuAl, W, Al, AlW or Au.
Preferably, the sidewall of described groove also has side wall protection layer.
The present invention also provides a kind of manufacture to have the method for the semiconductor device of metal gate electrode, comprises the following steps:
Step S01, provides the substrate that has an insulating barrier, described insulating barrier is formed a groove, forms high-K gate dielectric layer in the bottom of described groove, forms side wall protection layer at the sidewall of described groove;
Step S02, grows workfunction layers, Graphene barrier layer and metal seed layer successively in the groove with high-K gate dielectric layer;
Step S03, forms photoresist in described groove, and with it for mask removes the metal seed layer of described Graphene barrier layer upper surface;
Step S04, removes described photoresist, and cleans semiconductor device surface;
Step S05, adopt selective metal electroplating technology to fill grid metal in described groove, and the upper surface of described grid metal is concordant with the upper surface of described insulating barrier;
Step S06, removes Graphene barrier layer and the workfunction layers of described insulating barrier upper surface, to form polymetal gate electrode structure.
Preferably, in step S01, described side wall protection layer is silicon nitride, silica or both combinations.
Preferably, in step S02, adopt chemical vapor deposition method or atomic vapor deposition technique to form described Graphene barrier layer, the thickness on described Graphene barrier layer is 1nm-3nm.
Preferably, in step S03, adopt wet-etching technology to remove the metal seed layer of described Graphene barrier layer upper surface, etching solution is HF and NH
4the mixed liquor of F, HNO
3and NH
4the mixed liquor of F, H
2sO
4and H
2o
2mixed liquor, one or more in rare HF.
Preferably, in step S04, adopt wet-etching technology to remove described photoresist, etching solution is the mixed solution of methyl-sulfoxide, ammonium fluoride and hydrofluoric acid or the mixed liquor of monoethanolamine, tertiary amine, hydrogen fluoride and ammonium hydroxide.
Preferably, in step S06, CMP (Chemical Mechanical Polishing) process or photoetching and etching technics is adopted to remove Graphene barrier layer and the workfunction layers of described insulating barrier upper surface.
The invention provides a kind of semiconductor device and the manufacture method thereof with metal gate electrode, the barrier layer of Graphene material is adopted to substitute traditional barrier layer, Graphene barrier layer not only has thinner thickness, the profile pattern of metal gate groove can well be kept simultaneously, do not affect the fillibility of follow-up grid metal plating; Simultaneously, because the carbon atom of all sp2 hydridization of Graphene is all saturated to key, its structure is highly stable, thus makes Graphene barrier layer have excellent thermal stability and chemical stability, grid metal effectively can be stoped to spread in workfunction layers, thus ensure the work function stability of device.In addition, Graphene barrier layer is due to its electric conductivity, follow-up selective metal electroplating technology can be realized, make the upper surface of grid metal concordant with the upper surface of insulating barrier, decrease due to the metal filled too much needs of the grid longer surface planarisation time, avoid the defect causing metal gate height inconsistent, improve yield and the consistency of device.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, be briefly described to the accompanying drawing used required in embodiment below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 a-Fig. 1 d is the existing structural representation with the semiconductor device of metal gate electrode;
Fig. 2 a-Fig. 2 b is the existing defect schematic diagram had in the semiconductor device of metal gate electrode;
Fig. 3 is the schematic flow sheet with the manufacture method of the semiconductor device of metal gate electrode that the present invention proposes;
Fig. 4 a-Fig. 4 f is the schematic diagram that formation that the present invention proposes has the processing step of the semiconductor device of metal gate electrode.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, embodiments of the present invention are described in further detail.Those skilled in the art the content disclosed by this specification can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by embodiments different in addition, and the every details in this specification also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.
Above-mentioned and other technical characteristic and beneficial effect, by conjunction with the embodiments and the accompanying drawing semiconductor device with metal gate electrode that the present invention is proposed and manufacture method thereof be described in detail.Fig. 3 is the schematic flow sheet with the manufacture method of the semiconductor device of metal gate electrode that the present invention proposes; Fig. 4 a-Fig. 4 f is the schematic diagram that formation that the present invention proposes has the processing step of the semiconductor device of metal gate electrode.
The invention provides a kind of semiconductor device with metal gate electrode, semiconductor device comprises substrate, insulating barrier and polymetal gate electrode structure; Wherein, insulating barrier covers the upper surface of substrate, and insulating barrier has a groove, and polymetal gate electrode structure is formed in groove.
In the present embodiment; polymetal gate electrode structure specifically comprises: the high-K gate dielectric layer covering the bottom of groove; the sidewall of groove has side wall protection layer; cover the workfunction layers of the upper surface of high-K gate dielectric layer and the sidewall of groove; cover the upper surface of workfunction layers and the Graphene barrier layer of sidewall; cover the upper surface on Graphene barrier layer and the metal seed layer of sidewall, be filled in the grid metal in groove, and the upper surface of grid metal and the upper surface of insulating barrier concordant.Wherein, the material of workfunction layers be preferably in TiN, TiAl, TaN, TiC, TaC, Ti, TiCu, TiNi, AlNi one or more, the material of grid metal is preferably Cu, CuAl, W, Al, AlW or Au.
The semiconductor device with metal gate electrode disclosed in this invention can be made by many methods, the following stated be the technological process of bright the proposed manufacture of a this law embodiment as shown in Figure 3.As shown in Figure 3, the embodiment of the present invention provides a kind of manufacture to have the method for the semiconductor device of metal gate electrode, comprises the following steps:
Step S01, refers to Fig. 4 a, provides the substrate 401 that has an insulating barrier 402, insulating barrier 402 is formed a groove 403, forms high-K gate dielectric layer 404 in the bottom of groove 403, forms side wall protection layer 405 at the sidewall of groove 403.
In the present embodiment, provide the substrate 401 that has an insulating barrier 402, the material of substrate 401 is Si, and the material of insulating barrier 402 is SiO
2, form a groove 403 in the insulating barrier 402 on substrate, the degree of depth of groove 403 is preferably 45nm-75nm, and the degree of depth of the present embodiment further groove 403 is 60nm, and then in groove 403, high-K gate dielectric layer 404 is formed on bottom, and the material of high-K gate dielectric layer 404 is HfO
2, groove 403 sidewall forms side wall protection layer 405, and side wall protection layer 405 is preferably silicon nitride, silica or both combinations, and in the present embodiment, side wall protection layer 405 is Si
3n
4, thickness is 8nm.
Step S02, refers to Fig. 4 b, grows workfunction layers 406, Graphene barrier layer 407 and metal seed layer 408 in the groove 403 with high-K gate dielectric layer successively.
In this step, preferably adopt chemical vapor deposition method or atomic vapor deposition technique to form Graphene barrier layer 407, the thickness on Graphene barrier layer 407 is preferably 1nm-3nm, and the thickness in the present embodiment is preferably 1.7nm.Adopt the barrier layer of Graphene material to substitute traditional barrier layer, Graphene barrier layer not only has thinner thickness, can well keep the profile pattern of metal gate groove simultaneously, not affect the fillibility of follow-up grid metal plating.
The material of the workfunction layers 406 in the present embodiment is TiN, and thickness is 5nm; The material of metal seed layer 408 is aluminium, and thickness is 10nm.
Step S03, refers to Fig. 4 c, in groove 403, form photoresist 409, and with its metal seed layer 408 for mask removal Graphene barrier layer 407 upper surface.
In this step, preferably adopt wet-etching technology to remove the metal seed layer 408 of Graphene barrier layer 407 upper surface, etching solution is preferably HF and NH
4the mixed liquor of F, HNO
3and NH
4the mixed liquor of F, H
2sO
4and H
2o
2mixed liquor, one or more in rare HF, the material of metal seed layer 408 is preferably albronze.The etching solution that the metal seed layer 408 that after photoetching, wet etching removes surface in the present embodiment adopts is mixed liquor and the HNO of HF and NH4F
3and NH
4the mixed liquor of F.Due to the stable chemical nature on Graphene barrier layer 407, acid and alkali-resistance, therefore wet etching stops at the upper surface on Graphene barrier layer 407.
Step S04, refers to Fig. 4 d, removes photoresist 409, and cleans semiconductor device surface.
In this step, preferably adopt wet-etching technology to remove photoresist 409, etching solution is the mixed solution of methyl-sulfoxide, ammonium fluoride and hydrofluoric acid or the mixed liquor of monoethanolamine, tertiary amine, hydrogen fluoride and ammonium hydroxide.
Step S05, refers to Fig. 4 e, adopt selective metal electroplating technology to fill grid metal 410 in groove 403, and the upper surface of grid metal 410 is concordant with the upper surface of insulating barrier 402.
Because groove 403 is covered by Graphene barrier layer 407 in the present embodiment, Graphene barrier layer 407 has good electric conductivity, therefore can carry out electroplating technology.Further, owing to only having aluminum metal inculating crystal layer 408 in fluted 403, therefore electroplated aluminum has selectivity, i.e. only deposition groove 403 in, does not deposit at the upper surface on Graphene barrier layer 407.In further embodiments, grid metal 410 can be copper, tungsten, albronze etc.
Step S06, refers to Fig. 4 f, removes Graphene barrier layer 407 and the workfunction layers 406 of insulating barrier 402 upper surface, to form polymetal gate electrode structure.
In this step, preferred employing CMP (Chemical Mechanical Polishing) process or photoetching and etching technics remove fast surface thickness thinner Graphene barrier layer 407 and workfunction layers 406, form metal gate structure, insulating barrier 402 thickness lost in the present embodiment is 10nm.This step is owing to adopting low optionally polishing fluid, and polishing time is shorter, therefore can not produce depression defect in graphics intensive district.In further embodiments, remove the Graphene barrier layer 407 on surface and workfunction layers 406 also can reuse with the photoresist 409 of metal gate region be mask photoetching and etching technics.
In sum, the invention provides a kind of semiconductor device and the manufacture method thereof with metal gate electrode, the barrier layer of Graphene material is adopted to substitute traditional barrier layer, Graphene barrier layer not only has thinner thickness, the profile pattern of metal gate groove can well be kept simultaneously, do not affect the fillibility of follow-up grid metal plating; Simultaneously, because the carbon atom of all sp2 hydridization of Graphene is all saturated to key, its structure is highly stable, thus makes Graphene barrier layer have excellent thermal stability and chemical stability, grid metal effectively can be stoped to spread in workfunction layers, thus ensure the work function stability of device.In addition, Graphene barrier layer is due to its electric conductivity, follow-up selective metal electroplating technology can be realized, make the upper surface of grid metal concordant with the upper surface of insulating barrier, decrease due to the metal filled too much needs of the grid longer surface planarisation time, avoid the defect causing metal gate height inconsistent, improve yield and the consistency of device.
Above-mentioned explanation illustrate and describes some preferred embodiments of the present invention, but as previously mentioned, be to be understood that the present invention is not limited to the form disclosed by this paper, should not regard the eliminating to other embodiments as, and can be used for other combinations various, amendment and environment, and can in invention contemplated scope described herein, changed by the technology of above-mentioned instruction or association area or knowledge.And the change that those skilled in the art carry out and change do not depart from the spirit and scope of the present invention, then all should in the protection range of claims of the present invention.
Claims (10)
1. have a semiconductor device for metal gate electrode, it is characterized in that, described semiconductor device comprises:
Substrate;
Insulating barrier, described insulating barrier covers the upper surface of described substrate, and described insulating barrier has a groove;
Polymetal gate electrode structure, is formed in described groove; Wherein, described polymetal gate electrode structure comprises:
High-K gate dielectric layer, covers the bottom of described groove;
Workfunction layers, covers the upper surface of described high-K gate dielectric layer and the sidewall of groove;
Graphene barrier layer, covers upper surface and the sidewall of described workfunction layers;
Metal seed layer, covers upper surface and the sidewall on described Graphene barrier layer;
Grid metal, is filled in described groove, and the upper surface of described grid metal is concordant with the upper surface of described insulating barrier.
2. the semiconductor device with metal gate electrode according to claim 1, is characterized in that, the material of described workfunction layers is one or more in TiN, TiAl, TaN, TiC, TaC, Ti, TiCu, TiNi, AlNi.
3. the semiconductor device with metal gate electrode according to claim 1, is characterized in that, the material of described grid metal is Cu, CuAl, W, Al, AlW or Au.
4., according to the arbitrary described semiconductor device with metal gate electrode of claims 1 to 3, it is characterized in that, the sidewall of described groove also has side wall protection layer.
5. manufacture as arbitrary in Claims 1 to 4 as described in a method with the semiconductor device of metal gate electrode, it is characterized in that, comprise the following steps:
Step S01, provides the substrate that has an insulating barrier, described insulating barrier is formed a groove, forms high-K gate dielectric layer in the bottom of described groove, forms side wall protection layer at the sidewall of described groove;
Step S02, grows workfunction layers, Graphene barrier layer and metal seed layer successively in the groove with high-K gate dielectric layer;
Step S03, forms photoresist in described groove, and with it for mask removes the metal seed layer of described Graphene barrier layer upper surface;
Step S04, removes described photoresist, and cleans semiconductor device surface;
Step S05, adopt selective metal electroplating technology to fill grid metal in described groove, and the upper surface of described grid metal is concordant with the upper surface of described insulating barrier;
Step S06, removes Graphene barrier layer and the workfunction layers of described insulating barrier upper surface, to form polymetal gate electrode structure.
6. the manufacture method with the semiconductor device of metal gate electrode according to claim 5, is characterized in that, in step S01, described side wall protection layer is silicon nitride, silica or both combinations.
7. the manufacture method with the semiconductor device of metal gate electrode according to claim 5, it is characterized in that, in step S02, adopt chemical vapor deposition method or atomic vapor deposition technique to form described Graphene barrier layer, the thickness on described Graphene barrier layer is 1nm-3nm.
8. the manufacture method with the semiconductor device of metal gate electrode according to claim 5, is characterized in that, in step S03, adopt wet-etching technology to remove the metal seed layer of described Graphene barrier layer upper surface, etching solution is HF and NH
4the mixed liquor of F, HNO
3and NH
4the mixed liquor of F, H
2sO
4and H
2o
2mixed liquor, one or more in rare HF.
9. according to the arbitrary described manufacture method with the semiconductor device of metal gate electrode of claim 5 ~ 8, it is characterized in that, in step S04, adopt wet-etching technology to remove described photoresist, etching solution is the mixed solution of methyl-sulfoxide, ammonium fluoride and hydrofluoric acid or the mixed liquor of monoethanolamine, tertiary amine, hydrogen fluoride and ammonium hydroxide.
10. according to the arbitrary described manufacture method with the semiconductor device of metal gate electrode of claim 5 ~ 8, it is characterized in that, in step S06, CMP (Chemical Mechanical Polishing) process or photoetching and etching technics is adopted to remove Graphene barrier layer and the workfunction layers of described insulating barrier upper surface.
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| CN108231560A (en) * | 2016-12-09 | 2018-06-29 | 全球能源互联网研究院 | A kind of coordination electrode preparation method and MOSFET power devices |
| CN109870489A (en) * | 2019-02-28 | 2019-06-11 | 上海集成电路研发中心有限公司 | A method of preparing graphene oxide in humidity sensor |
| CN116722031A (en) * | 2023-07-20 | 2023-09-08 | 深圳优比康科技有限公司 | Power field effect transistor and preparation method thereof |
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| CN111162447B (en) * | 2019-12-31 | 2021-06-15 | 苏州辰睿光电有限公司 | Electrode window and manufacturing method of semiconductor device with electrode window |
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