CN116722031A - Power field effect transistor and preparation method thereof - Google Patents

Power field effect transistor and preparation method thereof Download PDF

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CN116722031A
CN116722031A CN202310895723.1A CN202310895723A CN116722031A CN 116722031 A CN116722031 A CN 116722031A CN 202310895723 A CN202310895723 A CN 202310895723A CN 116722031 A CN116722031 A CN 116722031A
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insulating layer
drain electrode
source electrode
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CN116722031B (en
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李捷
何艳
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Shenzhen Youbikang Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Insulated Gate Type Field-Effect Transistor (AREA)
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Abstract

A power field effect transistor and a preparation method thereof belong to the technical field of field effect transistors, and aim to solve the problems that the traditional field effect transistor is not high in utilization rate of an insulating layer due to structural arrangement, and is inconvenient to achieve the purposes of reducing leakage current, improving breakdown voltage and enhancing insulating performance when being used for isolating conductive parts between electrodes; according to the application, the first insulating layer, the gate oxide layer, the graphene layer, the second insulating layer, the silicon nitride wrapping layer and the third insulating layer are arranged, so that a means of a plurality of insulating layers is achieved, and the structural perfection and good insulating performance of the insulating layer film are further improved by controlling three factors of surface adsorption, surface diffusion and gas phase reaction.

Description

Power field effect transistor and preparation method thereof
Technical Field
The application relates to the technical field of field effect transistors, in particular to a power field effect transistor and a preparation method thereof.
Background
The field effect transistor is abbreviated as field effect transistor. There are mainly two types: the junction field effect transistor and metal-oxide semiconductor field effect transistor are composed of majority carriers to participate in conduction, also called as unipolar transistor, which belongs to voltage control type semiconductor device, and has the advantages of high input resistance (107-1015 ohm), small noise, low power consumption, large dynamic range, easy integration, no secondary breakdown phenomenon, wide safety working area, etc., the field effect transistor is a semiconductor device which controls output loop current by utilizing electric field effect of control input loop, and the traditional field effect transistor is named as such, and has low utilization rate of insulating layer, and is inconvenient to reduce leakage current when used for isolating conductive part between electrodes, improve switching efficiency and performance of the device, inconvenient to improve breakdown voltage, effectively protect against breakdown phenomenon generated when voltage is too high, protect the device from damage, inconvenient to enhance insulation performance, and make electrons unable to pass through between conductive part and insulating layer.
To solve the above problems, a power field effect transistor and a method for manufacturing the same are provided.
Disclosure of Invention
The application aims to provide a power field effect transistor and a preparation method thereof, which solve the problems that the traditional field effect transistor in the background art is not high in utilization rate of an insulating layer due to structural arrangement, and is inconvenient to achieve the purposes of reducing leakage current, improving breakdown voltage and enhancing insulating performance when being used for isolating conductive parts between electrodes.
In order to achieve the above purpose, the present application provides the following technical solutions: the power field effect transistor comprises a P-type semiconductor substrate, wherein one side of the P-type semiconductor substrate is provided with grooves, two groups of grooves are arranged, one side of the P-type semiconductor substrate provided with the grooves is provided with a first insulating layer, and N-type source electrodes and N-type drain electrodes are respectively arranged in the grooves of the two groups;
the upper end of the N-type drain electrode is provided with an integration layer, the upper end of the integration layer is provided with a drain electrode aluminum metallization layer and a source electrode aluminum metallization layer, the drain electrode aluminum metallization layer and the source electrode aluminum metallization layer are respectively positioned at the upper ends of the N-type source electrode and the N-type drain electrode, a third insulating layer is arranged between the drain electrode aluminum metallization layer and the source electrode aluminum metallization layer, the upper end of the third insulating layer is provided with a grid electrode aluminum metallization layer, and two sides of the lower end of the third insulating layer are in contact with the drain electrode aluminum metallization layer and the source electrode aluminum metallization layer.
Further, the integrated layer comprises a gate oxide layer which grows through heat treatment and has a certain thickness, and a graphene layer which is deposited on the surface of the gate oxide layer, wherein the gate oxide layer is arranged at the upper ends of the N-type source electrode and the N-type drain electrode, grooves for exposing the N-type source electrode and the N-type drain electrode are formed in the gate oxide layer in a penetrating mode, grooves for exposing the N-type source electrode and the N-type drain electrode are formed in the graphene layer in a penetrating mode, a silicon nitride wrapping layer is deposited on the outer side of the graphene layer in a back-etching mode, the silicon nitride wrapping layer wraps the inner wall of the graphene layer, a second insulating layer is deposited on the upper end of the graphene layer, the silicon nitride wrapping layer and the outer side of the gate oxide layer are wrapped by the second insulating layer, and grooves for exposing the N-type source electrode and the N-type drain electrode are formed in the second insulating layer in a penetrating mode.
Further, the first insulating layer is arranged in a chemical vapor deposition mode, the N-type source electrode and the N-type drain electrode are arranged in an ion implantation technology, the drain electrode aluminum metallization layer and the source electrode aluminum metallization layer are arranged at the upper end of the second insulating layer in a deposition mode, the drain electrode aluminum metallization layer and the source electrode aluminum metallization layer are respectively in contact with the corresponding N-type source electrode and N-type drain electrode, a third insulating layer is arranged at the upper end of the second insulating layer in a deposition mode, and the gate electrode aluminum metallization layer is arranged in a deposition mode.
The application provides another technical scheme that: the preparation method of the power field effect transistor comprises the following steps:
s010: preparing a substrate: selecting a high-purity P-type semiconductor substrate, wherein the P-type semiconductor substrate is made of silicon, cleaning, removing surface impurities and forming grooves;
s020: and (3) insulating layer growth: growing an insulating layer first insulating layer on a P-type semiconductor substrate by a Chemical Vapor Deposition (CVD) method, typically using silicon dioxide (SiO 2) as an insulating layer material;
s030: source-drain doping: doping proper type impurities into the region on the insulating layer by utilizing an ion implantation technology to form N-type regions of a source electrode and a drain electrode;
s040: and (3) generating a layer: forming an integrated layer on one layer of the P-type semiconductor substrate by means of heat treatment and deposition;
s050: preparing a gate insulating layer: a third insulating layer is grown again on the integrated layer, typically using silicon nitride (Si 3N 4) or a high dielectric constant material as the insulating layer of the gate electrode;
s060: gate metal deposition: depositing a metal thin film gate metallized aluminum layer on the third insulating layer, typically using a metal having good conductivity such as aluminum (Al) or copper (Cu);
s070: photoetching and etching: masking the area above the metal film by utilizing a photoetching technology, and etching to form a grid structure;
s080: preparing a metal electrode: depositing a metal thin film drain electrode aluminum metallization layer and a source electrode aluminum metallization layer on the source electrode and drain electrode regions, wherein a metal with good conductivity such as aluminum (Al) or copper (Cu) is generally used, and the source electrode and drain electrode structures are formed through photoetching and etching;
s090: and (3) heat treatment: through high-temperature treatment, the materials are subjected to solid-phase diffusion and lattice rearrangement, and the electrical characteristics and stability of the device are improved;
s100: packaging and testing: and packaging the prepared power field effect transistor to protect the chip, and performing performance tests such as current, voltage and power characteristics, so as to finish all implementation steps.
Further, in the step S020, the step of chemical vapor deposition:
s021: and (3) preparing a reaction gas: in the preparation of the reaction gas, disilicate (TEOS) is generally used as a precursor gas and oxygen (O2) is used as an oxidizing agent in the growth of the silicon dioxide (SiO 2) insulating layer.
S022: the deposition process comprises the following steps: the P-type semiconductor substrate is placed in a CVD reactor chamber and precursor gases and an oxidizing agent are introduced into the reactor chamber under specific temperature and pressure conditions. During the reaction, the precursor gas is decomposed to form a SiO2 film, which is deposited on the surface of the P-type semiconductor substrate.
S023: post-treatment: after deposition, some post-treatment steps, such as annealing, may be required to improve film quality or planarization.
Further, during the chemical vapor deposition in step S020, the TEOS and oxygen used will react chemically in the reaction chamber, resulting in the formation of silicon dioxide (SiO 2). The following is the reaction equation for TEOS and oxygen:
TEOS (tetraethoxysilane): si (OC 2H 5) 4, oxygen: o2.
The reaction equation:
Si(OC2H5)4 + 2O2 → SiO2 + 4CO2 + 5H2O。
in this reaction, tetraethoxysilane (TEOS) reacts with oxygen to form silica (SiO 2), carbon dioxide (CO 2) and water (H2O). This reaction is generally carried out at a high temperature and a specific pressure so that TEOS is decomposed and stable si—o bonds are formed, thereby depositing a SiO2 thin film on the surface of the P-type semiconductor substrate, and carbon dioxide and water, which are byproducts, are discharged through gas, so that a first insulating layer having a uniform structure and good insulating properties can be formed on the P-type semiconductor substrate by CVD deposition.
Further, in the step S022, siO2 is deposited on the surface of the P-type semiconductor substrate to form a thin film by pyrolysis and reaction of the reaction gas in the reaction chamber, and this process is regulated by three factors of surface adsorption, surface diffusion and gas phase reaction.
Further, by controlling the concentration of the gas phase, the temperature and the surface characteristics of the substrate, the adsorption rate of SiO2 molecules in the gas phase on the surface of the P-type semiconductor substrate reaches 10 < 13 > -10 < 15 > molecules per unit area per second.
Further, by controlling the temperature, the surface energy barrier and the surface structural factors, the rate at which SiO2 molecules adsorbed to the substrate surface move on the surface reaches 10-10 to 10-8 cm 2/s per unit area per second.
Further, by controlling the concentration of the reaction gas, the temperature and the reaction rate constant factor between the reaction substances, the rate of the reaction between the chemical substances in the reaction gas such as oxygen and TEOS and the SiO2 molecules adsorbed on the substrate surface reaches 10 to 13 molecules per second per unit area.
Compared with the prior art, the application has the following beneficial effects:
according to the power field effect transistor and the preparation method thereof, the first insulating layer, the gate oxide layer, the graphene layer, the second insulating layer, the silicon nitride wrapping layer and the third insulating layer are arranged, so that a means of multi-layer insulating layers is achieved, the structure perfection and good insulating performance of the insulating layer film are further improved by controlling three factors including surface adsorption, surface diffusion and gas phase reaction, and the problems that the conventional field effect transistor is inconvenient to achieve the purposes of reducing leakage current, improving breakdown voltage and enhancing insulating performance when being used for isolating conductive parts between electrodes due to the fact that the structure is arranged and the utilization rate of the insulating layer is low are solved.
Drawings
FIG. 1 is a schematic view of a P-type semiconductor substrate structure according to the present application;
FIG. 2 is a schematic diagram of an integrated layer structure according to the present application;
FIG. 3 is a schematic diagram of the structure of the drain, source and gate aluminum metallizations according to the present application;
FIG. 4 is a schematic diagram of the preparation method of the present application;
fig. 5 is a schematic diagram of an insulation layer growth method according to the present application.
In the figure: 1. a P-type semiconductor substrate; 11. a groove; 12. a first insulating layer; 13. an N-type source electrode; 14. an N-type drain; 2. an integration layer; 21. a gate oxide layer; 22. a graphene layer; 221. a silicon nitride encapsulation layer; 23. a second insulating layer; 3. a drain electrode metallized aluminum layer; 4. a third insulating layer; 5. a gate metalized aluminum layer; 6. a source metallization aluminum layer.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In order to solve the technical problems that the conventional field effect transistor is not high in utilization rate of an insulating layer due to structural arrangement, and is inconvenient to achieve the purposes of reducing leakage current, improving breakdown voltage and enhancing insulating performance when being used for isolating conductive parts between electrodes, as shown in fig. 1-5, the following preferred technical scheme is provided:
a power field effect transistor comprises a P-type semiconductor substrate, grooves 11 are formed in one side of the P-type semiconductor substrate 1, two groups of grooves 11 are formed in the side of the P-type semiconductor substrate 1 provided with the grooves 11, a first insulating layer 12 is arranged in the side of the P-type semiconductor substrate 1 provided with the grooves 11, an N-type source electrode 13 and an N-type drain electrode 14 are respectively arranged in the grooves 11 of the two groups, an integrated layer 2 is arranged at the upper end of the N-type drain electrode 14, a drain electrode aluminum metallization layer 3 and a source electrode aluminum metallization layer 6 are arranged at the upper end of the integrated layer 2, the drain electrode aluminum metallization layer 3 and the source electrode aluminum metallization layer 6 are respectively arranged at the upper ends of the N-type source electrode 13 and the N-type drain electrode 14, a third insulating layer 4 is arranged between the drain electrode aluminum metallization layer 3 and the source electrode aluminum metallization layer 6, a gate electrode aluminum metallization layer 5 is arranged at the upper end of the third insulating layer 4, and two sides of the lower end of the third insulating layer 4 are in contact with the drain electrode aluminum metallization layer 3 and the source electrode aluminum metallization layer 6.
The integration layer 2 comprises a gate oxide layer 21 which grows through heat treatment and has a certain thickness, and a graphene layer 22 which is deposited on the surface of the gate oxide layer 21, wherein the gate oxide layer 21 is arranged at the upper ends of the N-type source electrode 13 and the N-type drain electrode 14, grooves for exposing the N-type source electrode 13 and the N-type drain electrode 14 are formed in the gate oxide layer 21 in a penetrating manner, grooves for exposing the N-type source electrode 13 and the N-type drain electrode 14 are formed in the graphene layer 22 in a penetrating manner, a silicon nitride wrapping layer 221 is deposited on the outer side of the graphene layer 22 in a back-etching manner, the silicon nitride wrapping layer 221 wraps the inner wall of the graphene layer 22, a second insulating layer 23 is deposited on the upper end of the graphene layer 22 and wraps the outer side of the gate oxide layer 21, grooves for exposing the N-type source electrode 13 and the N-type drain electrode 14 are formed in the second insulating layer 23 in a penetrating manner, the first insulating layer 12 is formed in a penetrating manner through chemical vapor deposition, the N-type source electrode 13 and the N-type drain electrode 14 are formed in a penetrating manner, a drain electrode 3 and a drain electrode 6 are formed in a manner through ion implantation technique, an aluminum layer 3 and an aluminum layer 6 are formed on the inner wall of the graphene layer 22 in a manner, an aluminum layer is deposited on the second insulating layer 3 is formed on the drain electrode 4, and the drain electrode is formed in a corresponding manner to the aluminum layer is formed on the second insulating layer 4, and the drain electrode is formed in a metal layer, and is formed on the second insulating layer 3 insulating layer is formed.
To further better explain the above examples, the present application also provides an embodiment, a method for manufacturing a power field effect transistor, including the following steps:
s010: preparing a substrate: selecting a high-purity P-type semiconductor substrate 1, wherein the P-type semiconductor substrate 1 is made of silicon, cleaning, removing surface impurities and forming a groove 11;
s020: and (3) insulating layer growth: growing an insulating layer first insulating layer 12 on the P-type semiconductor substrate 1 by a chemical vapor deposition CVD method, typically using silicon dioxide SiO2 as an insulating layer material;
s030: source-drain doping: doping proper type impurities into the region on the insulating layer by utilizing an ion implantation technology to form N-type regions of a source electrode and a drain electrode;
s040: and (3) generating a layer: forming an integrated layer 2 on one layer of the P-type semiconductor substrate 1 by means of heat treatment and deposition;
s050: preparing a gate insulating layer: a third insulating layer 4 is grown again on the integrated layer 2, and silicon nitride Si3N4 or a material with high dielectric constant is generally used as an insulating layer of the gate;
s060: gate metal deposition: a metal film gate electrode metallized aluminum layer 5 is deposited on the third insulating layer 4, and a metal having good conductivity such as aluminum Al or copper Cu is generally used;
s070: photoetching and etching: masking the area above the metal film by utilizing a photoetching technology, and etching to form a grid structure;
s080: preparing a metal electrode: depositing a metal film drain electrode metalized aluminum layer 3 and a source electrode metalized aluminum layer 6 on the source electrode and drain electrode regions, wherein a metal with good conductivity such as aluminum Al or copper Cu is generally used, and the source electrode and drain electrode structures are formed through photoetching and etching;
s090: and (3) heat treatment: through high-temperature treatment, the materials are subjected to solid-phase diffusion and lattice rearrangement, and the electrical characteristics and stability of the device are improved;
s100: packaging and testing: and packaging the prepared power field effect transistor to protect the chip, and performing performance tests such as current, voltage and power characteristics, so as to finish all implementation steps.
Step of chemical vapor deposition in step S020:
s021: and (3) preparing a reaction gas: the reaction gas is prepared, and disilicate TEOS is generally used as a precursor gas and oxygen O2 is used as an oxidizing agent in the growth of the silicon dioxide SiO2 insulating layer.
S022: the deposition process comprises the following steps: the P-type semiconductor substrate 1 is placed in a CVD reaction chamber, and a precursor gas and an oxidizing agent are introduced into the reaction chamber under specific temperature and pressure conditions. During the reaction, the precursor gas is decomposed to form a SiO2 thin film, and is deposited on the surface of the P-type semiconductor substrate 1.
S023: post-treatment: after deposition, some post-treatment steps, such as annealing, may be required to improve film quality or planarization.
During the chemical vapor deposition in step S020, the TEOS and oxygen used will react chemically in the reaction chamber, resulting in the formation of silica SiO 2. The following is the reaction equation for TEOS and oxygen:
TEOS tetraethoxysilane: si (OC 2H 5) 4, oxygen: o2.
The reaction equation:
Si(OC2H5)4 + 2O2 → SiO2 + 4CO2 + 5H2O。
in this reaction tetraethoxysilane TEOS reacts with oxygen to form silica SiO2, carbon dioxide CO2 and water H2O. This reaction is generally carried out at a high temperature and a specific pressure so that TEOS is decomposed and stable si—o bonds are formed, thereby depositing a SiO2 thin film on the surface of the P-type semiconductor substrate 1, and by-product carbon dioxide and water are discharged through the gas, so that the first insulating layer 12 having a uniform structure and good insulating properties can be formed on the P-type semiconductor substrate 1 by CVD deposition.
In step S022, siO2 is deposited on the surface of the P-type semiconductor substrate 1 to form a thin film by pyrolysis and reaction of the reaction gas in the reaction chamber, and this process is regulated by three factors of surface adsorption, surface diffusion and gas phase reaction.
By controlling the concentration of the gas phase, the temperature and the surface characteristics of the substrate, the adsorption rate of SiO2 molecules in the gas phase on the surface of the P-type semiconductor substrate 1 reaches 10-13 to 10-15 molecules per unit area, by controlling the temperature, the surface energy barrier and the surface structural factors, the movement rate of the SiO2 molecules adsorbed on the surface of the substrate reaches 10-10 to 10-8 cm 2/s per unit area, by controlling the reaction rate constant factors among the concentration of the reaction gas, the temperature and the reaction substances, the reaction rate of the chemical substances in the reaction gases such as oxygen and TEOS and the SiO2 molecules adsorbed on the surface of the substrate reaches 10-13 molecules per unit area, by arranging the first insulating layer, the gate oxide layer, the graphene layer, the second insulating layer, the silicon nitride wrapping layer and the third insulating layer, the means of the multi-layer insulating layer is achieved, and the structure and the good insulating performance of the insulating layer film are further improved by controlling the three factors of the surface adsorption, the surface diffusion and the gas phase reaction.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Although embodiments of the present application have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the application, the scope of which is defined in the appended claims and their equivalents.

Claims (10)

1. A power field effect transistor comprising a P-type semiconductor substrate (1), characterized in that: a groove (11) is formed in one side of the P-type semiconductor substrate (1), two groups of grooves (11) are formed in the groove, a first insulating layer (12) is arranged on the side of the P-type semiconductor substrate (1) provided with the grooves (11), and an N-type source electrode (13) and an N-type drain electrode (14) are respectively arranged in the grooves (11) of the two groups;
the upper end of N type drain electrode (14) is provided with integrated layer (2), the upper end of integrated layer (2) is provided with drain electrode aluminium metallizations layer (3) and source electrode aluminium metallizations layer (6), and drain electrode aluminium metallizations layer (3) and source electrode aluminium metallizations layer (6) are in the upper end of N type source electrode (13) and N type drain electrode (14) respectively, the position between drain electrode aluminium metallizations layer (3) and source electrode aluminium metallizations layer (6) is provided with third insulating layer (4), the upper end of third insulating layer (4) is provided with grid electrode aluminium metallizations layer (5), the lower extreme both sides of third insulating layer (4) are in contact with drain electrode aluminium metallizations layer (3) and source electrode aluminium metallizations layer (6).
2. A power fet as claimed in claim 1, wherein: the integrated layer (2) comprises a gate oxide layer (21) which grows through heat treatment and has a certain thickness and a graphene layer (22) which is deposited on the surface of the gate oxide layer (21), the gate oxide layer (21) is arranged at the upper ends of the N-type source electrode (13) and the N-type drain electrode (14), grooves which are used for exposing the N-type source electrode (13) and the N-type drain electrode (14) are formed in the gate oxide layer (21) in a penetrating mode, grooves which are used for exposing the N-type source electrode (13) and the N-type drain electrode (14) are formed in the graphene layer (22) in a penetrating mode, a silicon nitride wrapping layer (221) is deposited on the outer side of the graphene layer (22) in a back-etching mode, the silicon nitride wrapping layer (221) wraps the inner wall of the graphene layer (22), a second insulating layer (23) is arranged on the upper end of the graphene layer (22) in a depositing mode, grooves which are used for exposing the N-type source electrode (13) and the N-type drain electrode (14) are formed in the second insulating layer (23) in a penetrating mode.
3. The power field effect transistor and the preparation method thereof according to claim 2, wherein: the first insulating layer (12) is arranged in a chemical vapor deposition mode, the N-type source electrode (13) and the N-type drain electrode (14) are arranged in an ion implantation technology, the drain electrode aluminum metallization layer (3) and the source electrode aluminum metallization layer (6) are arranged at the upper end of the second insulating layer (23) in a deposition mode, the drain electrode aluminum metallization layer (3) and the source electrode aluminum metallization layer (6) are respectively contacted with the corresponding N-type source electrode (13) and the corresponding N-type drain electrode (14), the third insulating layer (4) is arranged at the upper end of the second insulating layer (23) in a deposition mode, and the gate electrode aluminum metallization layer (5) is arranged in a deposition mode.
4. A method for manufacturing a power field effect transistor according to any one of claims 1 to 3, characterized in that: the method comprises the following steps:
s010: preparing a substrate: selecting a high-purity P-type semiconductor substrate (1), wherein the P-type semiconductor substrate (1) is made of silicon, cleaning, removing surface impurities and forming a groove (11);
s020: and (3) insulating layer growth: growing an insulating layer first insulating layer (12) on the P-type semiconductor substrate (1) by a Chemical Vapor Deposition (CVD) method, typically using silicon dioxide (SiO 2) as an insulating layer material;
s030: source-drain doping: doping proper type impurities into the region on the insulating layer by utilizing an ion implantation technology to form N-type regions of a source electrode and a drain electrode;
s040: and (3) generating a layer: forming an integrated layer (2) on one layer of the P-type semiconductor substrate (1) by means of heat treatment and deposition;
s050: preparing a gate insulating layer: a third insulating layer (4) is grown again on the integrated layer (2), typically using silicon nitride (Si 3N 4) or a high dielectric constant material as the insulating layer for the gate;
s060: gate metal deposition: depositing a metal thin film gate metallized aluminum layer (5) on the third insulating layer (4), and generally using a metal having good conductivity such as aluminum (Al) or copper (Cu);
s070: photoetching and etching: masking the area above the metal film by utilizing a photoetching technology, and etching to form a grid structure;
s080: preparing a metal electrode: depositing a metal thin film drain electrode metalized aluminum layer (3) and a source electrode metalized aluminum layer (6) on the source electrode and drain electrode regions, wherein a metal with good conductivity such as aluminum (Al) or copper (Cu) is generally used, and the source electrode and drain electrode structures are formed through photoetching and etching;
s090: and (3) heat treatment: through high-temperature treatment, the materials are subjected to solid-phase diffusion and lattice rearrangement, and the electrical characteristics and stability of the device are improved;
s100: packaging and testing: and packaging the prepared power field effect transistor to protect the chip, and performing performance tests such as current, voltage and power characteristics, so as to finish all implementation steps.
5. The power field effect transistor and the preparation method thereof according to claim 4, wherein: step of chemical vapor deposition in step S020:
s021: and (3) preparing a reaction gas: preparing a reaction gas, in growing a silicon dioxide (SiO 2) insulating layer, usually using disilicate (TEOS) as a precursor gas and oxygen (O2) as an oxidizing agent;
s022: the deposition process comprises the following steps: a P-type semiconductor substrate (1) is placed in a CVD reactor chamber and precursor gases and an oxidizing agent are introduced into the reactor chamber under specific temperature and pressure conditions. In the reaction process, the precursor gas is decomposed to generate a SiO2 film, and the SiO2 film is deposited on the surface of the P-type semiconductor substrate (1);
s023: post-treatment: after deposition, some post-treatment steps, such as annealing, may be required to improve film quality or planarization.
6. The power field effect transistor and the preparation method thereof according to claim 5, wherein: during the chemical vapor deposition in step S020, the TEOS and oxygen used will react chemically in the reaction chamber, resulting in the formation of silicon dioxide (SiO 2). The following is the reaction equation for TEOS and oxygen:
TEOS (tetraethoxysilane): si (OC 2H 5) 4, oxygen: o2;
the reaction equation:
Si(OC2H5)4 + 2O2 → SiO2 + 4CO2 + 5H2O。
7. the power field effect transistor and the preparation method thereof according to claim 5, wherein: in step S022, siO2 is deposited on the surface of the P-type semiconductor substrate (1) to form a thin film by pyrolysis and reaction of a reaction gas in a reaction chamber, and the process is regulated by three factors of surface adsorption, surface diffusion and gas phase reaction.
8. The power field effect transistor and the preparation method thereof according to claim 7, wherein: by controlling the concentration, temperature and substrate surface characteristics of the gas phase, the adsorption rate of SiO2 molecules in the gas phase on the surface of the P-type semiconductor substrate (1) reaches 10 < 13 > -10 < 15 > molecules per unit area per second.
9. The power field effect transistor and the preparation method thereof according to claim 7, wherein:
by controlling the temperature, the surface energy barrier and the surface structural factors, the speed of the SiO2 molecules adsorbed on the surface of the substrate on the surface is 10 < -10 > to 10 < -8 > cm < -2 >/s per unit area per second.
10. The power field effect transistor and the preparation method thereof according to claim 7, wherein: by controlling the concentration of the reaction gas, the temperature and the reaction rate constant factor between the reaction substances, the reaction rate between the chemical substances in the reaction gas such as oxygen and TEOS and SiO2 molecules adsorbed on the surface of the substrate reaches 10 to 10 < 13 > molecules per unit area per second.
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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH118379A (en) * 1997-06-16 1999-01-12 Toshiba Corp Semiconductor device and manufacture thereof
US20050037583A1 (en) * 2002-12-30 2005-02-17 Cheolsoo Park Semiconductor transistors and methods of fabricating the same
US20080258185A1 (en) * 2007-04-19 2008-10-23 Huan-Tsung Huang Semiconductor structure with dielectric-sealed doped region
US20130043515A1 (en) * 2010-06-25 2013-02-21 Ru Huang Strained Channel Field Effect Transistor and the Method for Fabricating the Same
CN105552117A (en) * 2015-12-17 2016-05-04 上海集成电路研发中心有限公司 Semiconductor device with metal gate electrode and manufacturing method for semiconductor device
US9871063B1 (en) * 2016-07-15 2018-01-16 Magnachip Semiconductor, Ltd. Display driver semiconductor device and manufacturing method thereof
WO2021037335A1 (en) * 2019-08-26 2021-03-04 National Center For Scientific Research Demokritos A negative quantum capacitance field effect transistor
US20220123134A1 (en) * 2020-10-21 2022-04-21 IceMos Technology Limited Semiconductor Device and Method of Forming Low Voltage Power Mosfets Using Graphene for Metal Layers and Graphene Nanoribbons for Channel and Drain Enhancement Regions of Power Vertical and Lateral Mosfets on substrates of Silicon, GAN, SIC, or Diamond to Integrate Narrow Band Gap Engineering with Wide Band Gap Engineering and Achieve Energy Saving Devices and Environmental Progress in the Power Semiconductor Industry

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH118379A (en) * 1997-06-16 1999-01-12 Toshiba Corp Semiconductor device and manufacture thereof
US20050037583A1 (en) * 2002-12-30 2005-02-17 Cheolsoo Park Semiconductor transistors and methods of fabricating the same
US20080258185A1 (en) * 2007-04-19 2008-10-23 Huan-Tsung Huang Semiconductor structure with dielectric-sealed doped region
US20130043515A1 (en) * 2010-06-25 2013-02-21 Ru Huang Strained Channel Field Effect Transistor and the Method for Fabricating the Same
CN105552117A (en) * 2015-12-17 2016-05-04 上海集成电路研发中心有限公司 Semiconductor device with metal gate electrode and manufacturing method for semiconductor device
US9871063B1 (en) * 2016-07-15 2018-01-16 Magnachip Semiconductor, Ltd. Display driver semiconductor device and manufacturing method thereof
WO2021037335A1 (en) * 2019-08-26 2021-03-04 National Center For Scientific Research Demokritos A negative quantum capacitance field effect transistor
US20220123134A1 (en) * 2020-10-21 2022-04-21 IceMos Technology Limited Semiconductor Device and Method of Forming Low Voltage Power Mosfets Using Graphene for Metal Layers and Graphene Nanoribbons for Channel and Drain Enhancement Regions of Power Vertical and Lateral Mosfets on substrates of Silicon, GAN, SIC, or Diamond to Integrate Narrow Band Gap Engineering with Wide Band Gap Engineering and Achieve Energy Saving Devices and Environmental Progress in the Power Semiconductor Industry

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
李炳宗等: "《硅基集成芯片制造工艺原理》", 30 November 2021, 复旦大学出版社, pages: 686 - 687 *

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