CN103681256A - A novel silicon carbide MOSFET device and a manufacturing method thereof - Google Patents

A novel silicon carbide MOSFET device and a manufacturing method thereof Download PDF

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CN103681256A
CN103681256A CN201310377625.5A CN201310377625A CN103681256A CN 103681256 A CN103681256 A CN 103681256A CN 201310377625 A CN201310377625 A CN 201310377625A CN 103681256 A CN103681256 A CN 103681256A
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silicon carbide
layer
mosfet device
photoresist
carbide mosfet
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CN103681256B (en
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黄国华
冯明宪
门洪达
张伟
王坤池
周月
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XIAMEN TIANRUI ELECTRONICS Co Ltd
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XIAMEN TIANRUI ELECTRONICS Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/048—Making electrodes
    • H01L21/049—Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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Abstract

The invention discloses a novel silicon carbide MOSFET device and a manufacturing method thereof. A silicon carbide substrate, a buffer layer and a conductive epitaxial layer positioned above the buffer layer are comprised. A gate electrode and a source electrode are arranged on the conductive epitaxial layer. The gate electrode comprise a gate medium layer. A well region and a first kind of impurity ion region are arranged inside the conductive epitaxial layer. A second kind of impurity ion region is arranged inside the well region. The gate electrode also comprises a metal level. The metal level is positioned below the gate medium layer.

Description

A kind of novel silicon carbide MOSFET device and preparation method thereof
Technical field
The present invention relates to a kind of sic semiconductor device, relate in particular to a kind of novel silicon carbide MOSFET device and preparation method thereof.
Background technology
The thickness relation in direct ratio of the withstand voltage and device drift region of high voltage power device (the N-shaped region that concentration is lower, forms with epitaxy technique conventionally), and the inversely proportional relation of the critical electric field of epitaxy layer thickness and material.Due to the large critical electric field of carborundum (SiC) (be Si 10 times), the thinner epitaxial loayer of application like this, just can realize the requirement of withstand voltage of device, can also realize lower break-over of device resistance.On the other hand, carborundum (SiC) material has the characteristics such as large band gap (be Si 3 times), high thermal conductivity (be Si 4 times) and large electronics saturation (be Si 2 times), adopt carborundum as the semiconductor device of material, to compare with adopting silicon as the material that forms semiconductor device, the possibility that when it uses under hot environment, characteristic reduces is less, and this makes carborundum become the ideal material more for the manufacture of device such as MOSFET.
It is first grow grid oxygen and polycrystalline that conventional silicon carbide power device is made flow process, photoetching etching polycrystalline, then carry out injection and the diffusion in Pwell district, the horizontal proliferation district forming is thus exactly the channel region of device, due to needs high-temperature, long diffusion technology, could form needed trench channel, such diffusion technology condition is difficult to realize at general semiconductor FAB, or need substantial contribution to drop into buy, correct new equipment, so not only bring a large amount of inputs of fixed fund, also increased greatly the unsteadiness of technique, because at so high temperature, the stability of equipment is not easy to control, the disadvantageous place of another one is the increase of manufacturing cost.
Conventional carbon SiClx power MOSFET device application polysilicon is as grid material, because the conductivity (resistivity) of polysilicon is to be decided by phosphorus doping technique, all thermal process processes after this processing step all can all it exert an influence, and structure is that the Stability of Resistivity of polysilicon is difficult to control.In the device architectures such as MOSFET and IGBT, the dynamic switch characteristic of resistance and device has great relation, for example, in break-over of device process, resistance is larger, and the opening speed of device is just slower, and corresponding ON time is just longer, thereby cause the power consumption of opening of device will be larger, not only cause reduction and the energy consumption of transfer power to increase, the increase of energy consumption can cause device heating and parameter degradation, even damages and loses efficacy.
In common silicon carbide MOSFET and IGBT structure, dielectric layer below gate electrode is one deck thermal oxide layer that one deck and grid oxygen technique are grown simultaneously, conventionally this layer of thermal oxide layer is all thinner, principle is to guarantee that enough grid sources are withstand voltage, reason is that these interface traps exert an influence to the electron transfer of channel region in every way because the interface between gate oxide and SiC substrate has a large amount of interface traps.The current SiC MOSFET manufacturing on the Si of SiC substrate face has demonstrated extremely low inversion layer mobility, this is than low two orders of magnitude of mobility value of expectation, if but to thicken this layer of oxide layer, can produce more interface trap, the problem that above-mentioned mobility is low will be more serious.
Chinese patent Granted publication number: CN102227000A, Granted publication day: on October 26th, 2011, a kind of silicon carbide MOSFET device and preparation method based on super junction disclosed, it comprises grid, silica oxides medium, source electrode, N+ source region, P+ contact zone, P trap, JFET district, N-epitaxial loayer, N+ substrate and drain electrode, the both sides of N-epitaxial loayer and to be provided with thickness under P trap be 0.5 ~ 5um, Al-doping concentration is 5 * 10 15~ 1 * 10 16cm -3p -base, so that the Electric Field Distribution at flex point place, P Jing He JFET district is more even, improve the puncture voltage of device, this patent of invention mainly solves silicon carbide MOSFET device puncture voltage when low pass resistance in prior art and is difficult to the problem improving, yet it has the following disadvantages: making flow process is first grow grid oxygen and polycrystalline, photoetching etching polycrystalline, then carry out injection and the diffusion in Pwell district, the horizontal proliferation district forming is thus exactly the channel region of device, due to needs high-temperature, long diffusion technology, could form needed trench channel, such diffusion technology condition is difficult to realize at general semiconductor FAB, or need substantial contribution to drop into buy, correct new equipment, so not only bring a large amount of inputs of fixed fund, also increased greatly the unsteadiness of technique, because at so high temperature, the stability of equipment is not easy to control, and its manufacturing cost is high.
Summary of the invention
The present invention is in order to overcome the deficiencies in the prior art part, a kind of novel silicon carbide MOSFET device and preparation method thereof is provided, it has changed the technological process of conventional carbon SiClx power MOSFET device, avoided the high-temperature technology process after grid oxygen, thereby avoided well region to advance the impact of technique on gate dielectric layer or channel region concentration, improved its impact on grid oxygen quality and device parameters, improved the dynamic characteristic of device and improved the reliability of device, and having reduced manufacturing cost.
To achieve these goals, the present invention is by the following technical solutions:
A manufacture method for novel silicon carbide MOSFET device, comprises the following steps:
(1). a carbofrax material is provided, and described carbofrax material comprises silicon carbide substrates and the resilient coating of the layer that forms at silicon carbide substrates surface deposition and be positioned at the conduction epitaxial loayer on resilient coating;
(2) upper surface at described carbofrax material applies photoresist, and photoetching, etching are injected first kind foreign ion and formed first kind impurity ion region;
(3) remove the photoresist of above-mentioned carbofrax material upper surface, more again apply photoresist, photoetching, etching, application ion implantor injects first kind foreign ion under high-temperature, and carries out High temperature diffusion, thereby forms well region;
(4) again apply photoresist, under high-temperature, inject Equations of The Second Kind foreign ion, form Equations of The Second Kind impurity ion region;
(5) adopt CVD technique, on the upper surface of carbofrax material, even growth regulation one deck oxide skin(coating), utilizes photoresist as masking layer, and this ground floor oxide skin(coating) is carried out to photoetching and etching, thereby forms interlayer dielectric layer;
(6) remove the photoresist on above-mentioned carbofrax material upper surface, and the gate oxide of growing on the upper surface of carbofrax material;
(7) on above-mentioned gate oxide and insulating medium layer, carry out photoetching and the etching of contact hole, obtain grid and source lead hole;
(8) at carbofrax material upper surface deposit first layer metal layer, by first layer metal layer being carried out to photoetching and etching obtains source electrode;
(9) at the upper surface deposit second layer metal layer of described carbofrax material, described second layer metal layer covers above-mentioned interlayer dielectric layer and gate oxide;
(10) utilize photoresist to make masking layer, the optionally above-mentioned second layer metal layer of etching and gate oxide, thus form gate electrode.
The technological process that the present invention makes silicon carbide power is from traditional different, the present invention is in making the technological process of silicon carbide MOSFET device, take first to complete the well region of device channel and the Equations of The Second Kind impurity ion region in device source region, avoid like this high-temperature technology process after grid oxygen, improved its impact on grid oxygen quality and device parameters; The part that the outmost surface of well region contacts with grid oxygen, when device is worked, form inversion regime and there is conductive capability, it is channel region, compare and in traditional handicraft, apply high temperature, horizontal proliferation forms device channel for a long time, device channel length of the present invention is decided by lithography layout, photoetching process, and do not need high-temperature, the long needed special equipment of diffusion technology diffusion technology, its low cost of manufacture, and effectively avoided the unsettled problem of ultrahigh-temperature.
As preferably, the material of described first layer metal layer adopts Ni or aluminum, and in vacuum or argon gas atmosphere, carries out rapid thermal treatment (RTP) and degenerate, with the ohmic contact of realizing ideal.
As preferably, described second layer metal layer is silicon-aluminum layer or aluminum layer, and its thickness is 2 ~ 4 microns.In this preferred version, second layer metal layer adopts silicon aluminum alloy material or pure aluminum material, thickness is between 2 ~ 4 microns, its advantage is that such gate metal layer can realize lower grid dead resistance, thereby improve the switching speed of device, reduce switching loss, and that can this carry out frequency applications for device is most important.
As preferably, described ground floor oxide skin(coating) adopts CVD technique to form, and its thickness is 0.5 ~ 1.0 micron.In this preferred version, ground floor oxide skin(coating) adopts CVD technique to form, its thickness of silica medium layer forming is like this thicker, and in traditional structure its thinner thickness of silica medium layer, adopt thicker silica medium layer, its advantage is effectively to reduce miller capacitance, thereby improves the operating frequency of device and the ability that avalanche resistance punctures.
As preferably, the thickness of described gate oxide is 10 ~ 20 nanometers.In this preferred version, the thickness of gate oxide is between 10 ~ 20 nanometers, and because its thickness is little, so the process of thermal oxidation is few, the interface trap of itself and silicon carbide substrates can be smaller.
As preferably, the doping content of described silicon carbide substrates material is at least E18/cm3.In this preferred version, the doping content of silicon carbide substrates material is more than E18/cm3, and its benefit is to reduce the series resistance that backing material forms, thereby reduces the conducting resistance of device.
A kind of novel silicon carbide MOSFET device, comprise silicon carbide substrates, resilient coating and be positioned at the conduction epitaxial loayer on resilient coating, on described conduction epitaxial loayer, be provided with gate electrode and source electrode, described gate electrode comprises gate dielectric layer, in described conduction epitaxial loayer, be provided with well region and first kind impurity ion region, in described well region, be provided with Equations of The Second Kind impurity ion region, described gate electrode also comprises metal level.
As preferably, described metal level adopts the metal materials such as Ni or aluminium.
As preferably, described silica medium layer thickness is 0.5 ~ 1.0 micron.In this preferred version, the thickness of silica medium layer is between 0.5 ~ 1.0 micron, and its Thickness Ratio is thicker, and such benefit is thicker silica medium layer, its advantage is effectively to reduce miller capacitance, thereby improves the operating frequency of device and the ability that avalanche resistance punctures.
As preferably, described silicon carbide substrates is N-shaped silicon carbide substrates or P type silicon carbide substrates.In this preferred version, silicon carbide substrates can be N-shaped silicon carbide substrates, can be also P type silicon carbide substrates, and N-shaped silicon carbide substrates can be for making MOSFET device, and p-type silicon carbide substrates can be for making IGBT device.
Compared with prior art, the present invention has following beneficial effect: (1) the present invention has changed the technological process of conventional carbon SiClx power MOSFET device, first completes and forms the Pwell region of device channel and the N in device source region +district, has avoided the high-temperature technology process after grid oxygen like this, improves its impact on grid oxygen quality and device parameters, and has reduced manufacturing cost; (2) metal material such as the present invention's application Ni replaces the polysilicon in traditional handicraft, grid material as silicon carbide power MOSFET device, can reduce significantly resistance, thereby improve the switching speed of device, reduce switching loss, this can carry out frequency applications to device and be even more important; (3) in grid and the overlapping region of drain electrode, the present invention has changed the thinner gate oxide of applied thickness in traditional structure, and replace the thicker silica medium layer forming by CVD technique, it can effectively reduce Cge electric capacity (miller capacitance), thereby has improved the operating frequency of device and the ability that avalanche resistance punctures.
Accompanying drawing explanation
Fig. 1 is a kind of structural representation of N-shaped silicon carbide power MOSFET of the present invention.
In figure, 1-drain electrode, 2-silicon carbide substrates, 3-n+ resilient coating, 4-silicon carbide epitaxial layers, 5-P+ district, 6-N+ district, 7-P well region, 8-grid, 9-inter-level dielectric, 10-JFET district, 11-medium of oxides layer, 12-source class, 13-source class contact hole.
Embodiment
Below in conjunction with the drawings and specific embodiments, the invention will be further described.
The silicon carbide substrates material proposing in the present invention can be both N-shaped silicon carbide substrates, also can adopt p-type silicon carbide substrates, take N-shaped silicon carbide substrates as example, as shown in Figure 1 in following examples.
Embodiment:
As shown in Figure 1: a kind of manufacture method of novel silicon carbide MOSFET device, is characterized in that comprising the following steps:
(1). a carbofrax material is provided, described carbofrax material comprises silicon carbide substrates 2 and the n+ resilient coating 3 of the layer that forms at silicon carbide substrates 2 surface depositions and be positioned at the silicon carbide epitaxial layers 4 on n+ resilient coating 3, wherein the doping content of n+ resilient coating 3 is set as than the high order of magnitude of the doping content of silicon carbide epitaxial layers 4, and the doping content of n+ resilient coating 3 is arranged on E14/cm 3below;
(2) upper surface at described carbofrax material applies photoresist, and photoetching, etching are injected the element that element is chosen as trivalent, as aluminium element, thereby forms P+ district 5; P+ district 5 is used to form contacting of device well region and source electrode, thereby prevents that device from latch up effect occurring;
(3) remove the photoresist of above-mentioned carbofrax material upper surface, again apply again photoresist, photoetching, etching, application high energy ion implanter carries out ion implantation technology under high-temperature, inject ion and select triad, as aluminium element, and carry out High temperature diffusion, thereby form P well region 7, between described P well region 7, be formed with JFET district 10; The part that P well region 7 its outmost surface contact with grid oxygen, when device is worked, form inversion regime and there is conductive capability, it is channel region, compare and in traditional handicraft, apply high temperature, horizontal proliferation forms device channel for a long time, device channel length of the present invention is decided by lithography layout, photoetching process, and do not need the needed special equipment of High temperature diffusion technique, and effectively avoided ultrahigh-temperature technique instability problem.
(4) again apply photoresist, under high-temperature, carry out ion implantation technology, inject ion and be chosen as pentad, as nitrogen element, form N+ district 6;
(5) adopt CVD technique, even growth regulation one deck oxide skin(coating) on the upper surface of carbofrax material, its thickness, between 0.5 ~ 1.0 micron, utilizes photoresist as masking layer, this ground floor oxide skin(coating) is carried out to photoetching and etching, thereby form interlayer dielectric layer; This region part is positioned at grid metal and n-epitaxial loayer crossover region, owing to having applied thicker dielectric material, has reduced the grid source electric capacity of device, this region another part is positioned at source electrode, gate metal, and SiC epitaxial loayer (comprises n+, p+, PW etc.), between, play reasonable buffer action;
(6) remove the photoresist on above-mentioned semiconductor first type surface, and the gate oxide of growing on semi-conductive first type surface; The thickness of gate oxide is between 40 ~ 60nm, its implementation is one deck thermal oxide layer that utilizes thermal oxidation technology to regrow, and growth temperature is controlled between 1150 ~ 1200 degrees Celsius, and carries out the high temperature anneal in nitrogen atmosphere, to reduce oxygenation level defect, improve device stability; Annealing temperature can be identical with oxidizing temperature, and nitrogen atmosphere can be the gas with various such as N2, NO;
(7) on above-mentioned gate oxide and insulating medium layer, carry out photoetching and the etching of source class contact hole 13, obtain grid 8 and source electrode 12; In the bottom of described silicon carbide substrates 2, be formed with drain electrode 1;
(8) at carbofrax material upper surface deposit first layer metal layer, by first layer metal layer being carried out to photoetching and etching obtains source electrode 12, described first layer metal layer can be the one decks such as Al, Ti, Ni, tungsten or or multiple layer metal, or its alloy, the condition of its realization is in vacuum or argon gas atmosphere, 850C-1050C temperature, carries out rapid thermal treatment (RTP) annealing, to realize the ohmic contact that is less than 5E-6 ohm.cm2;
(9) at the upper surface deposit second layer metal layer of described carbofrax material, described second layer metal layer covers above-mentioned interlayer dielectric layer 9 and medium of oxides layer 11; Second layer metal layer can be the metal materials such as Al or Ni;
(10) utilize photoresist to make masking layer, the optionally above-mentioned second layer metal layer of etching and gate oxide, thus form gate electrode, on described second layer metal layer, there is oxide dielectric layer 11.

Claims (10)

1. a manufacture method for novel silicon carbide MOSFET device, is characterized in that comprising the following steps:
(1) provide a carbofrax material, described carbofrax material comprises silicon carbide substrates and the resilient coating of the layer that forms at silicon carbide substrates surface deposition and be positioned at the conduction epitaxial loayer on resilient coating;
(2) upper surface at described carbofrax material applies photoresist, and photoetching, etching are injected first kind foreign ion and formed first kind impurity ion region;
(3) remove the photoresist of above-mentioned carbofrax material upper surface, more again apply photoresist, photoetching, etching, application ion implantor injects first kind foreign ion under high-temperature, and carries out High temperature diffusion, thereby forms well region;
(4) again apply photoresist, under high-temperature, inject Equations of The Second Kind foreign ion, form Equations of The Second Kind impurity ion region;
(5) adopt CVD technique, on the upper surface of carbofrax material, even growth regulation one deck oxide skin(coating), utilizes photoresist as masking layer, and this ground floor oxide skin(coating) is carried out to photoetching and etching, thereby forms interlayer dielectric layer;
(6) remove the photoresist on above-mentioned carbofrax material upper surface, and the gate oxide of growing on the upper surface of carbofrax material;
(7) on above-mentioned gate oxide and insulating medium layer, carry out photoetching and the etching of contact hole, obtain grid and source lead hole;
(8) at carbofrax material upper surface deposit first layer metal layer, by first layer metal layer being carried out to photoetching and etching obtains source electrode;
(9) at the upper surface deposit second layer metal layer of described carbofrax material, described second layer metal layer covers above-mentioned interlayer dielectric layer and gate oxide;
(10) utilize photoresist to make masking layer, the optionally above-mentioned second layer metal layer of etching and gate oxide, thus form gate electrode.
2. the manufacture method of a kind of novel silicon carbide MOSFET device according to claim 1, is characterized in that: the material of described first layer metal layer adopts Ni or aluminum.
3. the manufacture method of a kind of novel silicon carbide MOSFET device according to claim 1, is characterized in that: described second layer metal layer is silicon-aluminum layer or aluminum layer, and its thickness is 2 ~ 4 microns.
4. the manufacture method of a kind of novel silicon carbide MOSFET device according to claim 1, is characterized in that: described ground floor oxide skin(coating) adopts CVD technique to form, and its thickness is 0.5 ~ 1.0 micron.
5. the manufacture method of a kind of novel silicon carbide MOSFET device according to claim 1, is characterized in that: the thickness of described gate oxide is 10 ~ 20 nanometers.
6. the manufacture method of a kind of novel silicon carbide MOSFET device according to claim 1, is characterized in that: the doping content of described silicon carbide substrates material is at least E18/cm3.
7. a novel silicon carbide MOSFET device, comprise silicon carbide substrates, resilient coating and be positioned at the conduction epitaxial loayer on resilient coating, on described conduction epitaxial loayer, be provided with gate electrode and source electrode, described gate electrode comprises gate dielectric layer, in described conduction epitaxial loayer, be provided with well region and first kind impurity ion region, in described well region, be provided with Equations of The Second Kind impurity ion region, it is characterized in that: described gate electrode also comprises metal level.
8. a kind of novel silicon carbide MOSFET device according to claim 7, is characterized in that: described source class metal level adopts the metal materials such as Ni or aluminium.
9. a kind of novel silicon carbide MOSFET device according to claim 7, is characterized in that: the silica medium layer thickness of described zone isolation is 0.5 ~ 1.0 micron.
10. a kind of novel silicon carbide MOSFET device according to claim 7, is characterized in that: described silicon carbide substrates is N-shaped silicon carbide substrates or P type silicon carbide substrates.
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Cited By (5)

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CN104966735A (en) * 2015-05-26 2015-10-07 株洲南车时代电气股份有限公司 Silicon carbide MOSFET device and preparation method thereof
CN107068762A (en) * 2017-03-20 2017-08-18 西安电子科技大学 The preparation method of 4H SiC metal semiconductor field effect transis with many depression cushions
CN112750912A (en) * 2021-02-18 2021-05-04 厦门芯一代集成电路有限公司 High-voltage silicon carbide MOS device and preparation method thereof
CN113066867A (en) * 2021-03-15 2021-07-02 无锡新洁能股份有限公司 High-reliability silicon carbide MOSFET device and process method thereof
CN116994956A (en) * 2023-09-26 2023-11-03 深圳市万微半导体有限公司 Silicon carbide power device, preparation method thereof and chip

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Publication number Priority date Publication date Assignee Title
CN104966735A (en) * 2015-05-26 2015-10-07 株洲南车时代电气股份有限公司 Silicon carbide MOSFET device and preparation method thereof
CN107068762A (en) * 2017-03-20 2017-08-18 西安电子科技大学 The preparation method of 4H SiC metal semiconductor field effect transis with many depression cushions
CN112750912A (en) * 2021-02-18 2021-05-04 厦门芯一代集成电路有限公司 High-voltage silicon carbide MOS device and preparation method thereof
CN113066867A (en) * 2021-03-15 2021-07-02 无锡新洁能股份有限公司 High-reliability silicon carbide MOSFET device and process method thereof
CN113066867B (en) * 2021-03-15 2022-09-09 无锡新洁能股份有限公司 High-reliability silicon carbide MOSFET device and process method thereof
CN116994956A (en) * 2023-09-26 2023-11-03 深圳市万微半导体有限公司 Silicon carbide power device, preparation method thereof and chip
CN116994956B (en) * 2023-09-26 2023-12-05 深圳市万微半导体有限公司 Silicon carbide power device, preparation method thereof and chip

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