CN107068762A - The preparation method of 4H SiC metal semiconductor field effect transis with many depression cushions - Google Patents
The preparation method of 4H SiC metal semiconductor field effect transis with many depression cushions Download PDFInfo
- Publication number
- CN107068762A CN107068762A CN201710165905.8A CN201710165905A CN107068762A CN 107068762 A CN107068762 A CN 107068762A CN 201710165905 A CN201710165905 A CN 201710165905A CN 107068762 A CN107068762 A CN 107068762A
- Authority
- CN
- China
- Prior art keywords
- sic
- glue
- minutes
- seconds
- cap layers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 34
- 230000005669 field effect Effects 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 229910052751 metal Inorganic materials 0.000 title claims description 39
- 239000002184 metal Substances 0.000 title claims description 39
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 238000001259 photo etching Methods 0.000 claims abstract description 27
- 102000004129 N-Type Calcium Channels Human genes 0.000 claims abstract description 20
- 108090000699 N-Type Calcium Channels Proteins 0.000 claims abstract description 20
- 238000001755 magnetron sputter deposition Methods 0.000 claims abstract description 6
- 239000003292 glue Substances 0.000 claims description 68
- 238000005530 etching Methods 0.000 claims description 37
- 239000000243 solution Substances 0.000 claims description 35
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 claims description 34
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 33
- 229920002120 photoresistant polymer Polymers 0.000 claims description 31
- -1 boron ion Chemical class 0.000 claims description 28
- 238000002347 injection Methods 0.000 claims description 28
- 239000007924 injection Substances 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 28
- 229910001868 water Inorganic materials 0.000 claims description 27
- ATUOYWHBWRKTHZ-UHFFFAOYSA-N Propane Chemical compound CCC ATUOYWHBWRKTHZ-UHFFFAOYSA-N 0.000 claims description 26
- 230000000994 depressogenic effect Effects 0.000 claims description 26
- 238000000206 photolithography Methods 0.000 claims description 23
- 238000004544 sputter deposition Methods 0.000 claims description 19
- 235000011114 ammonium hydroxide Nutrition 0.000 claims description 18
- 229920003229 poly(methyl methacrylate) Polymers 0.000 claims description 18
- 239000004926 polymethyl methacrylate Substances 0.000 claims description 18
- 238000002955 isolation Methods 0.000 claims description 17
- 210000002381 plasma Anatomy 0.000 claims description 16
- 235000012431 wafers Nutrition 0.000 claims description 16
- YXFVVABEGXRONW-UHFFFAOYSA-N Toluene Chemical compound CC1=CC=CC=C1 YXFVVABEGXRONW-UHFFFAOYSA-N 0.000 claims description 15
- 238000004026 adhesive bonding Methods 0.000 claims description 14
- 239000001257 hydrogen Substances 0.000 claims description 14
- 229910052739 hydrogen Inorganic materials 0.000 claims description 14
- 108091006146 Channels Proteins 0.000 claims description 13
- 238000004140 cleaning Methods 0.000 claims description 13
- 239000001294 propane Substances 0.000 claims description 13
- 239000012530 fluid Substances 0.000 claims description 11
- 150000002500 ions Chemical class 0.000 claims description 11
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 10
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 10
- 229910000077 silane Inorganic materials 0.000 claims description 10
- OKKJLVBELUTLKV-UHFFFAOYSA-N Methanol Chemical compound OC OKKJLVBELUTLKV-UHFFFAOYSA-N 0.000 claims description 9
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 claims description 9
- 230000000694 effects Effects 0.000 claims description 9
- 238000010438 heat treatment Methods 0.000 claims description 9
- 239000012190 activator Substances 0.000 claims description 8
- 239000000956 alloy Substances 0.000 claims description 8
- 229910045601 alloy Inorganic materials 0.000 claims description 8
- 238000000137 annealing Methods 0.000 claims description 8
- 230000004888 barrier function Effects 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 8
- 230000000873 masking effect Effects 0.000 claims description 8
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 7
- 239000008367 deionised water Substances 0.000 claims description 6
- 229910021641 deionized water Inorganic materials 0.000 claims description 6
- 239000007789 gas Substances 0.000 claims description 6
- 150000002431 hydrogen Chemical class 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 230000008569 process Effects 0.000 claims description 6
- 238000002604 ultrasonography Methods 0.000 claims description 6
- 238000002513 implantation Methods 0.000 claims description 5
- 125000001967 indiganyl group Chemical group [H][In]([H])[*] 0.000 claims description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 4
- 238000001035 drying Methods 0.000 claims description 4
- 239000007788 liquid Substances 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- 238000002161 passivation Methods 0.000 claims description 4
- 235000009161 Espostoa lanata Nutrition 0.000 claims description 3
- 240000001624 Espostoa lanata Species 0.000 claims description 3
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 238000005275 alloying Methods 0.000 claims description 3
- XKMRRTOUMJRJIA-UHFFFAOYSA-N ammonia nh3 Chemical compound N.N XKMRRTOUMJRJIA-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 230000008878 coupling Effects 0.000 claims description 3
- 238000010168 coupling process Methods 0.000 claims description 3
- 238000005859 coupling reaction Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 238000001465 metallisation Methods 0.000 claims description 3
- 229910017604 nitric acid Inorganic materials 0.000 claims description 3
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 3
- 229910000069 nitrogen hydride Inorganic materials 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- 229910000679 solder Inorganic materials 0.000 claims description 3
- 238000003466 welding Methods 0.000 claims description 3
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 2
- 229910021529 ammonia Inorganic materials 0.000 claims description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims 1
- 230000001934 delay Effects 0.000 claims 1
- 239000000203 mixture Substances 0.000 claims 1
- 125000003698 tetramethyl group Chemical group [H]C([H])([H])* 0.000 claims 1
- 238000011065 in-situ storage Methods 0.000 abstract description 7
- 230000015556 catabolic process Effects 0.000 abstract description 6
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 70
- 230000009977 dual effect Effects 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 150000002739 metals Chemical class 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- UHOVQNZJYSORNB-UHFFFAOYSA-N Benzene Chemical compound C1=CC=CC=C1 UHOVQNZJYSORNB-UHFFFAOYSA-N 0.000 description 3
- 241001465805 Nymphalidae Species 0.000 description 3
- 150000001335 aliphatic alkanes Chemical class 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 229910001873 dinitrogen Inorganic materials 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a kind of preparation method of the 4H SiC metal-semiconductor field effect transistors with many depression cushions, it is therefore intended that improves the breakdown voltage and transconductance parameters of field-effect transistor, improves DC characteristic.The technical scheme used for：4H SiC SI-substrates are cleaned；Epitaxial growth SiC layer and doping diborane formation p-type cushion in situ；Simultaneously doping in situ forms N-type channel layer to p-type cushion Epitaxial growth SiC layer；Simultaneously doping in situ forms N+ cap layers to N-type channel layer epitaxially grown SiC layer；Isolated area and active area are made in N+ cap layers；Make source electrode and drain electrode；Photoetching and ion implanting are carried out to p-type cushion, many depression cushions are formed；Raceway groove above raceway groove and close to source electrode cap layers side carries out photoetching, magnetron sputtering and metal-stripping, forms gate electrode；The 4H SiC metal-semiconductor field effect transistors surface formed is passivated, anti-carved, electrode pad is formed, the making of device is completed.
Description
Technical field
The invention belongs to field-effect transistor technical field, and in particular to a kind of 4H-SiC with many depression cushions is golden
Belong to the preparation method of semiconductor field effect transistor.
Background technology
Broad stopband width, high critical electric field, high saturation drift velocity and high heat conductance that carborundum (SiC) has due to it
Etc. the attention that excellent electric property has attracted people, as third generation semi-conducting material.These good characteristics make carborundum
(SiC) usually it is applied under the condition of work such as high pressure, high temperature, high frequency, high-power.SiC is in microwave power device, especially metal
Occupy main status in the application of semiconductor field effect transistor (MESFET), it has also become in recent years in microwave power device field
The focus of research.
In the power device of microwave frequency band, 4H-SiC MESFET have great saturation drain electrode output current and punctured
Voltage.At present, the improvement carried out for 4H-SiC MESFET devices is mainly the geometry in traditional 4H-SiC MESFET
On, structure improvement is carried out to grid, channel region, drift region etc..But due to the limitation of conventional device structure, device is leaked by saturation
Electric current and breakdown voltage are limited in a balanced way, under conditions of ensureing that device current is larger, then must sacrifice puncturing for device correlation
Characteristic exchanges bigger saturated drain current for.
Most of documents are directed to the research of dual recess 4H-SiC MESFET structures and changed on the basis of this structure
Enter.The structure is stacked and formed by 4H-SiC SI-substrates, p-type cushion, N-type channel layer and N+ cap layers from bottom to up, with this
Based on stack layer, the N-type channel layer of depression is formed after etching N+ cap layers, the source half length of grid is to N-type channel layer indent
Fall into and form recessed grid structure, the N-type channel layer of depression can be completed by reactive ion etching RIE technologies.
Chinese Patent Application No. 201410181931.6 discloses 4H-SiC metal-semiconductor field effect transistors, to p-type
Cushion has carried out photoetching and ion implanting, forms three cushion depressed areas.
Chinese Patent Application No. 201510001340.0 discloses a kind of 4H-SiC metals with dual recess cushion half
Conductor field-effect transistor carries out uv-exposure, development and ion implanting using many depression cushion photolithography plates, forms three
Cushion depressed area.
The content of the invention
The invention aims to provide a kind of to make what breakdown voltage and gate transconductance be improved to have many depression bufferings
The preparation method of the 4H-SiC metal-semiconductor field effect transistors of layer.
To achieve the above object, the invention discloses following technical scheme：
The preparation method of 4H-SiC metal semiconductor field effect transis with many depression cushions, preparation process is as follows：
Step 1) 4H-SiC SI-substrates (1) are cleaned, to remove substrate surface dirt；
Step 2) in the SiC layer of the μ m-thick of 4H-SiC SI-substrates Epitaxial growth 0.65, while through diborane B2H6It is in situ
Doping, it is 1.4 × 10 to form concentration15cm-3P-type cushion (2)；
Step 3) in the SiC layer of the μ m-thick of p-type cushion (2) Epitaxial growth 0.1, while through N2Original position doping, is formed dense
Spend for 3 × 1017cm-3N-type channel layer (3)；
Step 4) in the SiC layer of the N-type channel layer μ m-thick of (3) Epitaxial growth 0.2, while through N2Original position doping, is formed dense
Spend for 1.0 × 1020cm-3N+Type cap layers；
Step 5) in N+Photoetching is carried out in type cap layers successively and isolation is injected, isolated area and active area is formed；
Step 6) carry out source and drain photoetching, magnetron sputtering, metal-stripping and high temperature alloy successively to active area, form 0.5 μm
Long source electrode (6) and drain electrode (7)；
Step 7) to the N between source electrode (6) and drain electrode (7)+Type cap layers carry out photoetching, etching, form etching depth
It is respectively 0.2 μm and 2.2 μm of chase road with length；
Step 8) photoetching and ion implanting are carried out to p-type cushion, being formed, there is depth to be 0.15 μm, respectively with source
Polar cap layer is inboard, away from source electrode cap layers it is inboard 1.4 μm at and away from the inboard 1.7 μm of places of source electrode cap layers be that starting point, length are respectively 1.2 μ
M, 0.1 μm and 0.5 μm cushion depressed area (9), (10), (11)；
Step 9) above raceway groove and close to the raceway groove progress photoetching, magnetron sputtering and metal stripping of source electrode cap layers (4) side
From 0.7 μm of long gate electrode (8) of formation；
Step 10) the 4H-SiC metal-semiconductor field effect transistors surface formed is passivated, anti-carved, form electricity
Extreme pressure solder joint, completes the making of device.
Further, the step 1) in specific cleaning process be：
(1) substrate carefully cleans to two with the cotton balls for being moistened with methanol, three times, to remove the SiC particulate of surface various sizes；
(2) it is H in mol ratio by 4H-SiC SI-substrates (1)2SO4:HNO3=1:Ultrasound 5 minutes in 1 solution；
(3) 4H-SiC SI-substrates (1) are boiled 5 minutes in 1# cleaning fluids, then deionized water rinsing is after 5 minutes
Place into and boiled in 2# cleaning fluids 5 minutes, finally rinsed well with deionized water and use N2Drying is standby；
Wherein, 1# cleaning fluids are mol ratio NaOH:H2O2:H2O=1:2:5 solution, 2# cleaning fluids mol ratio is HCl:
H2O2:H2O=1:2:7 solution.
Further, the step 2) in the specific preparation process of p-type cushion (2) be：By 4H-SiC SI-substrates
(1) it is put into growth room, silane, 10ml/min propane and 80l/ that flow is 20ml/min is then passed through into growth room
Min high-purity hydrogen, while being passed through 2ml/min B2H6, B2H6In H2In be diluted to 5%, growth temperature is 1550 DEG C, and pressure is
105Pa, continues 6min, and it is respectively 1.4 × 10 to complete doping concentration and thickness15cm-3With the system of 0.65 μm of p-type cushion (2)
Make.
Further, the step 3) in N-type channel layer (3) specific preparation process be：4H-SiC epitaxial wafers are put into
Growth room, the high-purity hydrogen of silane, 10ml/min propane and 80l/min that flow is 20ml/min is passed through into growth room,
2ml/min N is passed through simultaneously2, growth temperature is 1550 DEG C, and pressure is 105Pa, continues 5min, completes doping concentration and thickness point
Wei 3 × 1017cm-3With the making of 0.1 μm of N-type channel layer (3).
Further, the step 4) in the specific preparation process of N+ cap layers be：4H-SiC epitaxial wafers are put into growth room,
The high-purity hydrogen of silane, 10ml/min propane and 80l/min that flow is 20ml/min is passed through into growth room, is passed through simultaneously
20ml/min N2, growth temperature is 1550 DEG C, and pressure is 105Pa, continues 2min, and it is respectively 1.0 to make doping concentration and thickness
×1020cm-3With 0.2 μm of N+ cap layers.
Further, the step 5) in the specific preparation process of active area and isolated area be：
(1) positive photoresist, application rate are used：3000R/min, 2 μm of glue thickness ＞ ensure the energy in follow-up isolation injection
Enough play good barrier effect；
(2) after the completion of gluing in 90 DEG C of baking ovens front baking 90 seconds, using isolation injection photolithography plate carry out 35 seconds uv-exposures
Develop 60 seconds in special developer solution afterwards, expose 4H-SiC, it is then rear in 100 DEG C of baking ovens to dry 3 minutes；Wherein, in developer solution
The mol ratio of tetramethyl aqua ammonia and water is 1:3；
(3) carry out boron ion twice to inject, injection condition is 130keV/6 × 1012cm-2, 50keV/2 × 1012cm-2, note
Acetone+ultrasonic depolymerization is used after the completion of entering, then with the removing of photoresist by plasma 3 minutes, completes the isolation injection beyond active area；
(4) above-mentioned 4H-SiC epitaxial wafers are placed in 1600 DEG C of sensing heating furnace annealings, 10 minutes activator impurities, Ar throughputs
For 20ml/min.
Further, the step 6) in source electrode (6) and the specific preparation process of drain electrode (7) be：
(1) masking glue is using the double-deck glue of PMMA+AZ1400, it is desirable to 1.2 μm of glue thickness ＞, is first applied after piece subprocessing is clean
PMMA glue, speed is 4000R/min, and glue is thick 0.5 μm, and then front baking 120 seconds in 200 DEG C of baking ovens, apply AZ1400 again after taking-up
0.8 μm of glue；
(2) front baking 90 seconds in 90 DEG C of baking ovens, carry out using special developer solution after uv-exposure in 15 seconds using source and drain photolithography plate
Development removes AZ1400 glue in 50 seconds, then carries out pan-exposure to PMMA glue, again with toluene is developed 3 minutes, then in 100 DEG C of baking ovens
In after dry 3 minutes, complete source-drain area metallization window；Wherein, the mol ratio of tetramethyl aqua ammonia and water is 1 in developer solution:
4；
(3) multi-target magnetic control sputtering platform, room temperature sputtering 150nm Ni, 150nm Ti and 300nm Au multiple layer metals are used
It is used as source and drain metal ohmic contact, wherein working vacuum 2.5 × 10-3Pa, Ar flow 40sccm；
(4) slice, thin piece is put into 150 DEG C of special strippers of Buty after the completion of sputtering, 130 DEG C are moved into again after metal comes off
In Buty strippers, when equitemperature drops to less than 80 DEG C, then by slice, thin piece immigration acetone, take out slice, thin piece and simultaneously dried up with nitrogen, most
Post plasma removes photoresist 2 minutes；
(5) slice, thin piece is put into rapid alloying stove, under the protection of nitrogen nitrogen atmosphere, N2:H2=9:1, it is quick with 970 DEG C/min
Heating, to alloy temperature alloy 10 minutes, forms source electrode (6) and drain electrode (7).
Further, the step 7) in the N+ cap layers photoetching between source electrode (6) and drain electrode (7), etching, specifically
Process is：
(1) positive photoresist, application rate are used：3000R/min, glue thickness ＞ 2nm ensure the quarter of the glue in subsequent etching
Lose masking action；
(2) after the completion of gluing in 90 DEG C of baking ovens front baking 90 seconds, using recess channel photolithography plate carry out 35 seconds uv-exposures
Afterwards in special developer solution develop 60 seconds, then in 100 DEG C of baking ovens after dry 3 minutes, in developer solution tetramethyl aqua ammonia and
The mol ratio of water is 1:3；
(3) N is carried out using ICP sense couplings system+Etching, etching condition is etching power 375W,
Bias power 60W, operating pressure 9Pa, etching gas selection flow is 32sccm CF4It is 8sccm Ar, etch thicknesses with flow
Etching is removed with acetone+ultrasound shelter glue for 0.2 μm, after etching.
Further, the step 8) in cushion depressed area (9), (10), the specific manufacturing process of (11) be：
(1) positive photoresist, application rate are used：3000R/min, 2 μm of glue thickness ＞ ensure the energy in follow-up isolation injection
Enough play good barrier effect；
(2) after the completion of gluing in 90 DEG C of baking ovens front baking 90 seconds, using many depression cushion photolithography plates carry out 35 seconds it is ultraviolet
Develop 60 seconds in special developer solution after exposure, it is then rear in 100 DEG C of baking ovens to dry 3 minutes；Wherein, tetramethyl hydrogen in developer solution
The mol ratio for aoxidizing ammonia and water is 1:3；
(3) N~+ implantation is carried out, injection condition is 300keV/2 × 1012cm-2, temperature is 400 DEG C.After the completion of injection
With acetone+ultrasonic depolymerization, then with the removing of photoresist by plasma 3 minutes；Being formed, there is depth to be 0.15 μm, respectively with source electrode cap layers it is inboard,
It is that starting point, length are respectively 1.2 μm, 0.1 μm and 0.5 at inboard 1.4 μm away from source electrode cap layers and away from the inboard 1.7 μm of places of source electrode cap layers
μm cushion depressed area (9), (10), (11)；
(4) above-mentioned 4H-SiC epitaxial wafers are placed in 1600 DEG C of sensing heating furnace annealings, 10 minutes activator impurities, Ar throughputs
For 20ml/min, the making of many depression p-type cushions is completed.
Further, the step 9) in the specific manufacturing process of gate electrode (8) be：
(1) masking glue is using the double-deck glue of PMMA+AZ1400, it is desirable to glue thickness ＞ 1.2nm.First applied after piece subprocessing is clean
PMMA glue, speed is 4000R/min, glue thickness 0.5nm, and then front baking 120 seconds in 200 DEG C of baking ovens, apply AZ1400 again after taking-up
Glue thickness 0.8nm；
(2) front baking 90 seconds in 90 DEG C of baking ovens, are carried out aobvious with special developer solution after 15 seconds uv-exposures using grid photolithography plate
Shadow removes AZ1400 glue in 50 seconds, then carries out pan-exposure to PMMA glue, again with toluene is developed 3 minutes, then in 100 DEG C of baking ovens
Dry 3 minutes afterwards；Wherein, the mol ratio of tetramethyl aqua ammonia and water is 1 in developer solution:4；
(3) multi-target magnetic control sputtering platform is used, room temperature sputtering thickness is 150nm Ni, 150nm Ti and 300nm successively
Au multiple layer metals are used as source and drain metal ohmic contact, wherein working vacuum 2.5 × 10-3In Pa, Ar flow 40sccm, sputter procedure
Slice, thin piece is heated to 150 DEG C；
(4) slice, thin piece is put into 150 DEG C of special strippers of Buty after the completion of sputtering, 130 DEG C are moved into again after metal comes off
In Buty strippers, when equitemperature drops to less than 80 DEG C, then by slice, thin piece immigration acetone, finally take out slice, thin piece and use low discharge nitrogen
Gas is slowly dried up, finally with the removing of photoresist by plasma 3 minutes, completes the making of gate electrode (8).
Further, the step 10) in electrode pad, complete element manufacturing detailed process be：
(1) at 300 DEG C, it is passed through the SiH that flow is 300sccm simultaneously into reative cell4, 323sccm NH3With
330sccm N2, by plasma enhanced CVD technique, in the Si of the μ m-thick of surface deposition 0.53N4Layer is as blunt
Change dielectric layer；
(2) passivation photoetching uses positive photoresist, application rate 3000R/mins, it is desirable to 2 μm of glue thickness ＞, after the completion of gluing
Front baking 90 seconds in 90 DEG C of baking ovens, then carried out 35 seconds uv-exposures using anti-carving photolithography plate, with special developing liquid developing 60 seconds,
It is finally rear in 100 DEG C of baking ovens to dry 3 minutes；Wherein, the mol ratio of tetramethyl aqua ammonia and water is 1 in developer solution:3；
(3)Si3N4Etching uses RIE techniques, and etching gas selection flow is 50sccm CHF3It is 5sccm Ar with flow,
After the completion of carry out 3 minutes removing of photoresist by plasmas again, expose metal, form source, leakage and gate electrode pressure welding point, complete whole device
Make.
The preparation method of 4H-SiC metal semiconductor field effect transis disclosed by the invention with many depression cushions, has
Following beneficial effect：
The present invention departs from traditional extensive preparation technology flow, only with photoetching, in combination with traditional evaporation, splashes control
The method of sputtering, obtains device, and whole technical process is simple.The present invention makes breakdown potential by introducing many depression cushions in addition
Pressure increase, gate transconductance is improved, and the performance of device is improved.
Brief description of the drawings
The present invention will be further described in detail below in conjunction with the accompanying drawings.
Fig. 1 has the structural representation of the 4H-SiC metal-semiconductor field effect transistors of many depression cushions for the present invention
Figure.
As shown in the figure：1 is 4H-SiC SI-substrates, and 2 be p-type cushion, and 3 be N-type channel layer, and 4 be source electrode cap layers, 5
It is source electrode for drain electrode cap layers, 6,7 be drain electrode, and 8 be gate electrode, and 9,10,11 be cushion depressed area.
Embodiment
The technical scheme in the embodiment of the present invention will be clearly and completely described below, it is clear that described implementation
Example only a part of embodiment of the invention, rather than whole embodiments.Based on the embodiment in the present invention, this area is common
The every other embodiment that technical staff is obtained under the premise of creative work is not made, belongs to the model that the present invention is protected
Enclose.
As shown in figure 1, a kind of 4H-SiC metal-semiconductor field effect transistors with many depression cushions, from bottom to top
Including 4H-SiC SI-substrates (1), p-type cushion (2), N-type channel layer (3), the both sides of N-type channel layer (3) are respectively source
Polar cap layer (4) and drain electrode cap layers (5), source electrode cap layers (4) and drain electrode cap layers (5) surface are source electrode (6) and drain electrode respectively
(7), above N-type channel layer (3) and close to the side formation gate electrode (8) of source electrode cap layers, the upper surface of the cushion is in grid
Cushion depressed area (9) are provided with below electrode and grid source, length is 1.2 μm, close to the side of grid provided with slow below grid leak
Layer depressed area (10) is rushed, length is 0.1 μm, the side close to drain electrode cap layers below grid leak is provided with cushion depressed area (11),
Length is 0.5 μm.The thickness of the cushion (2) is 0.65 μm, and cushion depressed area (9), (10), the depth of (11) are
0.15μm。
The preparation method of 4H-SiC metal-semiconductor field effect transistors of the present invention, provides following three kinds of embodiments.
Embodiment 1：
It is 0.05 μm to make channel thickness, and is 0.2 μm with depth, and length is respectively 1.2 μm, 0.1 μm, 0.5 μm
The 4H-SiC metal-semiconductor field effect transistors of cushion depressed area.
The making step of the present embodiment is as follows：
Step 1) 4H-SiC SI-substrates 1 are cleaned, to remove substrate surface dirt；
(1) substrate carefully cleans to two with the cotton balls for being moistened with methanol, three times, to remove the SiC particulate of surface various sizes；
(2) by 4H-SiC SI-substrates 1 in H2SO4:HNO3=1:Ultrasound 5 minutes in 1；
(3) by 4H-SiC SI-substrates 1 in 1# cleaning fluids (mol ratio NaOH:H2O2:H2O=1:2:5) 5 points are boiled in
Clock, then deionized water rinsing 2# cleaning fluids (mol ratio HCl is placed into after 5 minutes:H2O2:H2O=1:2:7) 5 points are boiled in
Clock, 2# cleaning fluids (mol ratio HCl:H2O2:H2O=1:2:7), finally rinsed well with deionized water and use N2Drying is standby.
Step 2) in the SiC layer of the μ m-thick of 4H-SiC SI-substrates Epitaxial growth 0.7, while through diborane B2H6It is in situ
Doping, it is 1.4 × 10 to form concentration15cm-3P-type cushion 2；
4H-SiC SI-substrates 1 are put into growth room, the silicon that flow is 20ml/min is then passed through into growth room
The high-purity hydrogen of alkane, 10ml/min propane and 80l/min, while being passed through 2ml/min B2H6(H2In be diluted to 5%), growth
Temperature is 1550 DEG C, and pressure is 105Pa, continues 6min, and it is respectively 1.4 × 10 to complete doping concentration and thickness15cm-3With 0.7 μm
P-type cushion 2 making.
Step 3) in the SiC layer of the μ m-thick of 2 Epitaxial growth of P cushions 0.05, through N2Original position doping, is formed concentration be 3 ×
1017cm-3N-type channel layer 3；
4H-SiC epitaxial wafers are put into growth room, silane, 10ml/min that flow is 20ml/min are passed through into growth room
Propane and 80l/min high-purity hydrogen, while being passed through 2ml/min N2, growth temperature is 1550 DEG C, and pressure is 105Pa, holds
Continuous 5min, it is respectively 3 × 10 to complete doping concentration and thickness17cm-3With the making of 0.05 μm of N-type channel layer 3.
Step 4) in N-type channel 3 Epitaxial growth SiC layer of layer, while through N2Original position doping forms N+Cap layers.
4H-SiC epitaxial wafers are put into growth room, silane, 10ml/min that flow is 20ml/min are passed through into growth room
Propane and 80l/min high-purity hydrogen, while being passed through 20ml/min N2, growth temperature is 1550 DEG C, and pressure is 105Pa, holds
Continuous 2min, it is respectively 1.0 × 10 to make doping concentration and thickness20cm-3With 0.2 μm of N+Cap layers.
Step 5) in N+Photoetching is carried out in cap layers successively and isolation is injected, isolated area and active area is formed.
(1) positive photoresist, application rate are used：3000R/min, 2 μm of glue thickness ＞ ensure the energy in follow-up isolation injection
Enough play good barrier effect；
(2) after the completion of gluing in 90 DEG C of baking ovens front baking 90 seconds, using isolation injection photolithography plate carry out about 35 seconds it is ultraviolet expose
In special developer solution (mol ratio tetramethyl aqua ammonia after light:Water=1:3) development 60 seconds, expose 4H-SiC, then 100 in
Dried 3 minutes after in DEG C baking oven；
(3) carry out boron ion twice to inject, injection condition is 130keV/6 × 1012cm-2, 50keV/2 × 1012cm-2.Note
Acetone+ultrasonic depolymerization is used after the completion of entering, then with the removing of photoresist by plasma 3 minutes, completes the isolation injection beyond active area；
(4) above-mentioned 4H-SiC epitaxial wafers are placed in 1600 DEG C of sensing heating furnace annealings, 10 minutes activator impurities, Ar throughputs
For 20ml/min.
Step 6) in N+Source electrode 6 and drain electrode 7 are formed in type cap layers.
(1) masking glue is using the double-deck glue of PMMA+AZ1400, it is desirable to 1.2 μm of glue thickness ＞.First applied after piece subprocessing is clean
PMMA glue, speed is 4000R/min, and glue is thick about 0.5 μm, and then front baking 120 seconds in 200 DEG C of baking ovens, are applied again after taking-up
About 0.8 μm of AZ1400 glue；
(2) front baking 90 seconds in 90 DEG C of baking ovens, carry out using special developer solution after uv-exposure in 15 seconds using source and drain photolithography plate
(mol ratio tetramethyl aqua ammonia:Water=1:4) development removes AZ1400 glue in 50 seconds, then carries out pan-exposure to PMMA glue, then
Developed 3 minutes with toluene, it is then rear in 100 DEG C of baking ovens to dry 3 minutes, complete source-drain area metallization window；
(3) multi-target magnetic control sputtering platform, room temperature sputtering 150nm Ni, 150nm Ti and 300nm Au multiple layer metals are used
It is used as source and drain metal ohmic contact, wherein working vacuum 2.5 × 10-3Pa, Ar flow 40sccm；
(4) slice, thin piece is put into 150 DEG C of special strippers of Buty after the completion of sputtering, 130 DEG C are moved into again after metal comes off
In Buty strippers, when equitemperature drops to less than 80 DEG C, then by slice, thin piece immigration acetone, take out slice, thin piece and simultaneously dried up with nitrogen, most
Post plasma removes photoresist 2 minutes；
(5) slice, thin piece is put into rapid alloying stove, in nitrogen nitrogen atmosphere (mol ratio N2:H2=9:1) it is rapidly heated under protecting
(970 DEG C/min) are arrived alloy temperature alloy 10 minutes, form source electrode 6 and drain electrode 7.
Step 7) to the N between source electrode 6 and drain electrode 7+Type cap layers carry out photoetching, etching, and etch thicknesses are 0.2 μm.
(1) positive photoresist, application rate are used：3000R/min, glue thickness ＞ 2nm ensure the quarter of the glue in subsequent etching
Lose masking action；
(2) after the completion of gluing in 90 DEG C of baking ovens front baking 90 seconds, using recess channel photolithography plate carry out about 35 seconds it is ultraviolet expose
Develop 60 seconds in special developer solution after light, then rear in 100 DEG C of baking ovens to dry 3 minutes, the mol ratio of special developer solution is four
Methyl aqua ammonia:Water=1:3；
(3) N is carried out using ICP sense couplings system+Etching, etching condition is etching power 375W,
Bias power 60W, operating pressure 9Pa, etching gas selection flow is 32sccm CF4It is 8sccm Ar, etch thicknesses with flow
Etching is removed with acetone+ultrasound shelter glue for 0.2 μm, after etching.
Step 8) photoetching and ion implanting are carried out to p-type cushion, being formed, there is depth to be 0.2 μm, respectively with source
Polar cap layer is inboard, away from source electrode cap layers it is inboard 1.4 μm at and away from the inboard 1.7 μm of places of source electrode cap layers be that starting point, length are respectively 1.2 μ
M, 0.1 μm and 0.5 μm cushion depressed area.
(1) positive photoresist, application rate are used：3000R/min, 2 μm of glue thickness ＞ ensure the energy in follow-up isolation injection
Enough play good barrier effect；
(2) after the completion of gluing in 90 DEG C of baking ovens front baking 90 seconds, carry out about 35 seconds purples using many depression cushion photolithography plates
In special developer solution (mol ratio tetramethyl aqua ammonia after outer exposure:Water=1:3) development 60 seconds in, then in 100 DEG C of baking ovens
In after dry 3 minutes；
(3) N~+ implantation is carried out, injection condition is 300keV/2 × 1012cm-2, temperature is 400 DEG C.After the completion of injection
With acetone+ultrasonic depolymerization, then with the removing of photoresist by plasma 3 minutes；Being formed, there is depth to be 0.2 μm, respectively with source electrode cap layers it is inboard, away from
It is that starting point, length are respectively 1.2 μm, 0.1 μm and 0.5 μm at inboard 1.4 μm of source electrode cap layers and away from the inboard 1.7 μm of places of source electrode cap layers
Cushion depressed area；
(4) above-mentioned 4H-SiC epitaxial wafers are placed in 1600 DEG C of sensing heating furnace annealings, 10 minutes activator impurities, Ar throughputs
For 20ml/min, the making of many depression p-type cushions is completed.
Step 9) above raceway groove and close to raceway groove progress photoetching, magnetron sputtering and the metal-stripping of the side of source electrode cap layers 4,
Form gate electrode 8 0.7 μm long.
(1) masking glue is using the double-deck glue of PMMA+AZ1400, it is desirable to glue thickness ＞ 1.2nm.First applied after piece subprocessing is clean
PMMA glue, speed is 4000R/min, glue thickness about 0.5nm, and then front baking 120 seconds in 200 DEG C of baking ovens, are applied again after taking-up
AZ1400 glue thickness about 0.8nm；
(2) front baking 90 seconds in 90 DEG C of baking ovens, (are rubbed after carrying out 15 seconds uv-exposures using grid photolithography plate with special developer solution
You are than tetramethyl aqua ammonia:Water=1:4) development removes AZ1400 glue in 50 seconds, then carries out pan-exposure to PMMA glue, then use first
Benzene develops 3 minutes, then rear in 100 DEG C of baking ovens to dry 3 minutes；
(3) multi-target magnetic control sputtering platform is used, room temperature sputtering thickness is 150nm Ni, 150nm Ti and 300nm successively
Au multiple layer metals are used as source and drain metal ohmic contact, wherein working vacuum 2.5 × 10-3In Pa, Ar flow 40sccm, sputter procedure
Slice, thin piece is heated to 150 DEG C；
(4) slice, thin piece is put into 150 DEG C of special strippers of Buty after the completion of sputtering, 130 DEG C are moved into again after metal comes off
In Buty strippers, when equitemperature drops to less than 80 DEG C, then by slice, thin piece immigration acetone, finally take out slice, thin piece and use low discharge nitrogen
Gas is slowly dried up, finally with the removing of photoresist by plasma 3 minutes, completes the making of gate electrode.
Step 10) the 4H-SiC metal-semiconductor field effect transistors surface formed is passivated, anti-carved, form electricity
Extreme pressure solder joint, completes the making of device.
(1) at 300 DEG C, it is passed through the SiH that flow is 300sccm simultaneously into reative cell4, 323sccm NH3With
330sccm N2, by plasma enhanced CVD technique, in the Si of the μ m-thick of surface deposition 0.53N4Layer is as blunt
Change dielectric layer；
(2) passivation photoetching uses positive photoresist, application rate 3000R/mins, it is desirable to 2 μm of glue thickness ＞, after the completion of gluing
Front baking 90 seconds in 90 DEG C of baking ovens, then using photolithography plate 35 seconds uv-exposures of progress are anti-carved, with special developer solution (mol ratio four
Methyl aqua ammonia:Water=1:3) develop 60 seconds, it is finally rear in 100 DEG C of baking ovens to dry 3 minutes；
(3)Si3N4Etching uses RIE techniques, and etching gas selection flow is 50sccm CHF3It is 5sccm Ar with flow,
After the completion of carry out 3 minutes removing of photoresist by plasmas again, expose metal, form source, leakage and gate electrode pressure welding point, complete whole device
Make.
Embodiment 2：
It is 0.1 μm to make channel thickness, and is 0.15 μm with depth, and length is respectively 1.2 μm, 0.1 μm, 0.5 μm
The 4H-SiC metal-semiconductor field effect transistors of cushion depressed area.
The making step of the present embodiment is as follows：
Step 2) in the SiC layer of the μ m-thick of 4H-SiC SI-substrates Epitaxial growth 0.65, while through diborane B2H6It is in situ
Doping, it is 1.4 × 10 to form concentration15cm-3P-type cushion 2；
4H-SiC SI-substrates 1 are put into growth room, the silicon that flow is 20ml/min is then passed through into growth room
The high-purity hydrogen of alkane, 10ml/min propane and 80l/min, while being passed through 2ml/min B2H6(H2In be diluted to 5%), growth
Temperature is 1550 DEG C, and pressure is 105Pa, continues 6min, and it is respectively 1.4 × 10 to complete doping concentration and thickness15cm-3With 0.65 μm
P-type cushion 2 making.
Step 3) in the SiC layer of the μ m-thick of 2 Epitaxial growth of P cushions 0.1, through N2Original position doping, is formed concentration be 3 ×
1017cm-3N-type channel layer 3；
4H-SiC epitaxial wafers are put into growth room, silane, 10ml/min that flow is 20ml/min are passed through into growth room
Propane and 80l/min high-purity hydrogen, while being passed through 2ml/min N2, growth temperature is 1550 DEG C, and pressure is 105Pa, holds
Continuous 5min, it is respectively 3 × 10 to complete doping concentration and thickness17cm-3With the making of 0.1 μm of N-type channel layer 3.
Step 8) photoetching and ion implanting are carried out to p-type cushion, being formed, there is depth to be 0.15 μm, respectively with source
Polar cap layer is inboard, away from source electrode cap layers it is inboard 1.4 μm at and away from the inboard 1.7 μm of places of source electrode cap layers be that starting point, length are respectively 1.2 μ
M, 0.1 μm and 0.5 μm cushion depressed area.
(1) positive photoresist, application rate are used：3000R/min, 2 μm of glue thickness ＞ ensure the energy in follow-up isolation injection
Enough play good barrier effect；
(2) after the completion of gluing in 90 DEG C of baking ovens front baking 90 seconds, carry out about 35 seconds purples using many depression cushion photolithography plates
In special developer solution (mol ratio tetramethyl aqua ammonia after outer exposure:Water=1:3) development 60 seconds in, then in 100 DEG C of baking ovens
In after dry 3 minutes；
(3) N~+ implantation is carried out, injection condition is 300keV/2 × 1012cm-2, temperature is 400 DEG C.After the completion of injection
With acetone+ultrasonic depolymerization, then with the removing of photoresist by plasma 3 minutes；Being formed, there is depth to be 0.15 μm, respectively with source electrode cap layers it is inboard,
It is that starting point, length are respectively 1.2 μm, 0.1 μm and 0.5 at inboard 1.4 μm away from source electrode cap layers and away from the inboard 1.7 μm of places of source electrode cap layers
μm cushion depressed area；
(4) above-mentioned 4H-SiC epitaxial wafers are placed in 1600 DEG C of sensing heating furnace annealings, 10 minutes activator impurities, Ar throughputs
For 20ml/min, the making of many depression p-type cushions is completed.
Remaining step is same as Example 1.
Embodiment 3：
It is 0.15 μm to make channel thickness, and is 0.1 μm with depth, and length is respectively 1.2 μm, 0.1 μm, 0.5 μm
The 4H-SiC metal-semiconductor field effect transistors of cushion depressed area.
The making step of the present embodiment is as follows：
Step 2) in the SiC layer of the μ m-thick of 4H-SiC SI-substrates Epitaxial growth 0.60, while through diborane B2H6It is in situ
Doping, it is 1.4 × 10 to form concentration15cm-3P-type cushion 2；
4H-SiC SI-substrates 1 are put into growth room, the silicon that flow is 20ml/min is then passed through into growth room
The high-purity hydrogen of alkane, 10ml/min propane and 80l/min, while being passed through 2ml/min B2H6(H2In be diluted to 5%), growth
Temperature is 1550 DEG C, and pressure is 105Pa, continues 6min, and it is respectively 1.4 × 10 to complete doping concentration and thickness15cm-3With 0.60 μm
P-type cushion 2 making.
Step 3) in the SiC layer of the μ m-thick of 2 Epitaxial growth of P cushions 0.15, through N2Original position doping, is formed concentration be 3 ×
1017cm-3N-type channel layer 3；
4H-SiC epitaxial wafers are put into growth room, silane, 10ml/min that flow is 20ml/min are passed through into growth room
Propane and 80l/min high-purity hydrogen, while being passed through 2ml/min N2, growth temperature is 1550 DEG C, and pressure is 105Pa, holds
Continuous 5min, it is respectively 3 × 10 to complete doping concentration and thickness17cm-3With the making of 0.15 μm of N-type channel layer 3.
Step 8) photoetching and ion implanting are carried out to p-type cushion, being formed, there is depth to be 0.1 μm, respectively with source
Polar cap layer is inboard, away from source electrode cap layers it is inboard 1.4 μm at and away from the inboard 1.7 μm of places of source electrode cap layers be that starting point, length are respectively 1.2 μ
M, 0.1 μm and 0.5 μm cushion depressed area.
(1) positive photoresist, application rate are used：3000R/min, 2 μm of glue thickness ＞ ensure the energy in follow-up isolation injection
Enough play good barrier effect；
(2) after the completion of gluing in 90 DEG C of baking ovens front baking 90 seconds, carry out about 35 seconds purples using many depression cushion photolithography plates
In special developer solution (mol ratio tetramethyl aqua ammonia after outer exposure:Water=1:3) development 60 seconds in, then in 100 DEG C of baking ovens
In after dry 3 minutes；
(3) N~+ implantation is carried out, injection condition is 300keV/2 × 1012cm-2, temperature is 400 DEG C.After the completion of injection
With acetone+ultrasonic depolymerization, then with the removing of photoresist by plasma 3 minutes；Being formed, there is depth to be 0.1 μm, respectively with source electrode cap layers it is inboard, away from
It is that starting point, length are respectively 1.2 μm, 0.1 μm and 0.5 μm at inboard 1.4 μm of source electrode cap layers and away from the inboard 1.7 μm of places of source electrode cap layers
Cushion depressed area；
(4) above-mentioned 4H-SiC epitaxial wafers are placed in 1600 DEG C of sensing heating furnace annealings, 10 minutes activator impurities, Ar throughputs
For 20ml/min, the making of many depression p-type cushions is completed.
Remaining step is same as Example 1.
Compared to the content introduced in background technology, the preparation method of this structure and the 4H-SiC with transverse p/n junction
MESFET (application numbers：201410181931.6) difference is：The former has carried out photoetching and ion implanting to p-type cushion,
Form three cushion depressed areas.The latter has carried out photoetching to channel surface, etching, forms recessed gate drain drift region, and
The surface epitaxial growth SiC layer in grid leak depressed area, doped injection forms transverse p/n junction.Both are adjusted by distinct methods respectively
Raceway groove electric field has been made, and then has improved breakdown characteristic of device.
The preparation method of this structure is with having dual recess cushion 4H-SiC MESFET (application numbers：
201510001340.0) preparation method compare, difference is：The former is carried out ultraviolet using many depression cushion photolithography plates
Exposure, development and ion implanting, form three cushion depressed areas.The latter is carried out ultraviolet using dual recess cushion photolithography plate
Exposure, development and ion implanting, form two cushion depressed areas.This method is further adjusted by the electric field peak additionally introduced
Raceway groove electric field has been made, breakdown characteristic of device is further increased.
Described above is only the preferred embodiment of the present invention, rather than its limitations；Although it should be pointed out that with reference to above-mentioned each
The present invention is described in detail embodiment, it will be understood by those within the art that, it still can be to above-mentioned each
Technical scheme described in embodiment is modified, or carries out equivalent substitution to which part or all technical characteristic；And this
A little modifications and replacement, do not make the essence of corresponding technical scheme depart from the scope of various embodiments of the present invention technical scheme.
Claims (11)
1. the preparation method of the 4H-SiC metal semiconductor field effect transis with many depression cushions, it is characterised in that prepare step
It is rapid as follows：
Step 1) 4H-SiC SI-substrates (1) are cleaned, to remove substrate surface dirt；
Step 2) in the SiC layer of the μ m-thick of 4H-SiC SI-substrates Epitaxial growth 0.65, while through diborane B2H6Mix original position
Miscellaneous, it is 1.4 × 10 to form concentration15cm-3P-type cushion (2)；
Step 3) in the SiC layer of the μ m-thick of p-type cushion (2) Epitaxial growth 0.1, while through N2Original position doping, it is 3 to form concentration
×1017cm-3N-type channel layer (3)；
Step 4) in the SiC layer of the N-type channel layer μ m-thick of (3) Epitaxial growth 0.2, while through N2Original position doping, forming concentration is
1.0×1020cm-3N+Type cap layers；
Step 5) in N+Photoetching is carried out in type cap layers successively and isolation is injected, isolated area and active area is formed；
Step 6) carry out source and drain photoetching, magnetron sputtering, metal-stripping and high temperature alloy successively to active area, form 0.5 μm long
Source electrode (6) and drain electrode (7)；
Step 7) to the N between source electrode (6) and drain electrode (7)+Type cap layers carry out photoetching, etching, form etching depth and length
Respectively 0.2 μm and 2.2 μm of chase road；
Step 8) photoetching and ion implanting are carried out to p-type cushion, being formed, there is depth to be 0.15 μm, respectively with source electrode cap
Layer is inboard, away from source electrode cap layers it is inboard 1.4 μm at and away from the inboard 1.7 μm of places of source electrode cap layers be starting point, length be respectively 1.2 μm, 0.1
μm and 0.5 μm of cushion depressed area (9), (10), (11)；
Step 9) above raceway groove and close to the raceway groove progress photoetching, magnetron sputtering and metal-stripping of source electrode cap layers (4) side, shape
Into 0.7 μm of long gate electrode (8)；
Step 10) the 4H-SiC metal-semiconductor field effect transistors surface formed is passivated, anti-carved, form electrode pressure
Solder joint, completes the making of device.
2. the preparation side of the 4H-SiC metal semiconductor field effect transis according to claim 1 with many depression cushions
Method, it is characterised in that the step 1) in specific cleaning process be：
(1) substrate carefully cleans to two with the cotton balls for being moistened with methanol, three times, to remove the SiC particulate of surface various sizes；
(2) by 4H-SiC SI-substrates (1) in mol ratio H2SO4:HNO3=1:Ultrasound 5 minutes in 1 solution；
(3) 4H-SiC SI-substrates (1) are boiled 5 minutes in 1# cleaning fluids, then deionized water rinsing is put again after 5 minutes
Enter to boil in 2# cleaning fluids 5 minutes, finally rinsed well with deionized water and use N2Drying is standby；
Wherein, 1# cleaning fluids are mol ratio NaOH:H2O2:H2O=1:2:5 solution, 2# cleaning fluids are mol ratio HCl:H2O2:H2O
=1:2:7 solution.
3. the preparation side of the 4H-SiC metal semiconductor field effect transis according to claim 1 with many depression cushions
Method, it is characterised in that the step 2) in the specific preparation process of p-type cushion (2) be：By 4H-SiC SI-substrates (1)
It is put into growth room, silane, 10ml/min propane and 80l/min that flow is 20ml/min is then passed through into growth room
High-purity hydrogen, while being passed through 2ml/min B2H6, B2H6In H2In be diluted to 5%, growth temperature is 1550 DEG C, and pressure is
105Pa, continues 6min, and it is respectively 1.4 × 10 to complete doping concentration and thickness15cm-3With the system of 0.65 μm of p-type cushion (2)
Make.
4. the preparation side of the 4H-SiC metal semiconductor field effect transis according to claim 1 with many depression cushions
Method, it is characterised in that the step 3) in N-type channel layer (3) specific preparation process be：4H-SiC epitaxial wafers are put into growth
Room, the high-purity hydrogen of silane, 10ml/min propane and 80l/min that flow is 20ml/min is passed through into growth room, simultaneously
It is passed through 2ml/min N2, growth temperature is 1550 DEG C, and pressure is 105Pa, continues 5min, completes doping concentration and thickness is respectively
3×1017cm-3With the making of 0.1 μm of N-type channel layer (3).
5. the preparation side of the 4H-SiC metal semiconductor field effect transis according to claim 1 with many depression cushions
Method, it is characterised in that the step 4) in the specific preparation process of N+ cap layers be：4H-SiC epitaxial wafers are put into growth room, to
The high-purity hydrogen of silane, 10ml/min propane and 80l/min that flow is 20ml/min is passed through in growth room, is passed through simultaneously
20ml/min N2, growth temperature is 1550 DEG C, and pressure is 105Pa, continues 2min, and it is respectively 1.0 to make doping concentration and thickness
×1020cm-3With 0.2 μm of N+ cap layers.
6. the preparation side of the 4H-SiC metal semiconductor field effect transis according to claim 1 with many depression cushions
Method, it is characterised in that the step 5) in the specific preparation process of active area and isolated area be：
(1) positive photoresist, application rate are used：3000R/min, 2 μm of glue thickness ＞ ensure to rise in follow-up isolation injection
To good barrier effect；
(2) after the completion of gluing in 90 DEG C of baking ovens front baking 90 seconds, using isolation injection photolithography plate carry out 35 seconds uv-exposures after
Develop 60 seconds in special developer solution, expose 4H-SiC, it is then rear in 100 DEG C of baking ovens to dry 3 minutes；Wherein, tetramethyl in developer solution
The mol ratio of base aqua ammonia and water is 1:3；
(3) carry out boron ion twice to inject, injection condition is 130keV/6 × 1012cm-2, 50keV/2 × 1012cm-2, injected
Cheng Houyong acetone+ultrasonic depolymerization, then with the removing of photoresist by plasma 3 minutes, complete the isolation injection beyond active area；
(4) above-mentioned 4H-SiC epitaxial wafers are placed in 1600 DEG C of sensing heating furnace annealings, 10 minutes activator impurities, Ar throughputs are
20ml/min。
7. the preparation side of the 4H-SiC metal semiconductor field effect transis according to claim 1 with many depression cushions
Method, it is characterised in that the step 6) in source electrode (6) and the specific preparation process of drain electrode (7) be：
(1) masking glue is using the double-deck glue of PMMA+AZ1400, it is desirable to 1.2 μm of glue thickness ＞, and PMMA is first applied after piece subprocessing is clean
Glue, speed is 4000R/min, and glue is thick 0.5 μm, and then front baking 120 seconds in 200 DEG C of baking ovens, apply AZ1400 glue 0.8 again after taking-up
μm；
(2) front baking 90 seconds in 90 DEG C of baking ovens, carry out using special developing liquid developing after uv-exposure in 15 seconds using source and drain photolithography plate
Remove AZ1400 glue within 50 seconds, then to PMMA glue carry out pan-exposure, again with toluene develop 3 minutes, then in 100 DEG C of baking ovens after
Dry 3 minutes, complete source-drain area metallization window；Wherein, the mol ratio of tetramethyl aqua ammonia and water is 1 in developer solution:4；
(3) multi-target magnetic control sputtering platform, room temperature sputtering 150nm Ni, 150nm Ti and 300nm Au multiple layer metal conducts are used
Source and drain metal ohmic contact, wherein working vacuum 2.5 × 10-3Pa, Ar flow 40sccm；
(4) slice, thin piece is put into 150 DEG C of special strippers of Buty after the completion of sputtering, 130 DEG C of Buty are moved into again after metal comes off
In stripper, when equitemperature drops to less than 80 DEG C, then by slice, thin piece immigration acetone, take out slice, thin piece and simultaneously dried up with nitrogen, finally etc.
Ion removes photoresist 2 minutes；
(5) slice, thin piece is put into rapid alloying stove, under the protection of nitrogen nitrogen atmosphere, N2:H2=9:1, it is rapidly heated with 970 DEG C/min,
To alloy temperature alloy 10 minutes, source electrode (6) and drain electrode (7) are formed.
8. the preparation side of the 4H-SiC metal semiconductor field effect transis according to claim 1 with many depression cushions
Method, it is characterised in that the step 7) in the N+ cap layers photoetching between source electrode (6) and drain electrode (7), etching, specific mistake
Cheng Wei：
(1) positive photoresist, application rate are used：3000R/min, glue thickness ＞ 2nm ensure that the etching of the glue in subsequent etching is covered
The effect of covering；
(2) after the completion of gluing in 90 DEG C of baking ovens front baking 90 seconds, using recess channel photolithography plate carry out 35 seconds uv-exposures after
Develop 60 seconds in special developer solution, then in 100 DEG C of baking ovens after dry 3 minutes, tetramethyl aqua ammonia and water in developer solution
Mol ratio is 1:3；
(3) N is carried out using ICP sense couplings system+Etching, etching condition is etching power 375W, biasing work(
Rate 60W, operating pressure 9Pa, etching gas selection flow is 32sccm CF4It is 8sccm Ar with flow, etch thicknesses are 0.2 μ
Etching is removed with acetone+ultrasound shelter glue after m, etching.
9. the preparation side of the 4H-SiC metal semiconductor field effect transis according to claim 1 with many depression cushions
Method, it is characterised in that the step 8) in cushion depressed area (9), (10), the specific manufacturing process of (11) be：
(1) positive photoresist, application rate are used：3000R/min, 2 μm of glue thickness ＞ ensure to rise in follow-up isolation injection
To good barrier effect；
(2) after the completion of gluing in 90 DEG C of baking ovens front baking 90 seconds, carry out 35 seconds uv-exposures using many depression cushion photolithography plates
Develop 60 seconds in special developer solution afterwards, it is then rear in 100 DEG C of baking ovens to dry 3 minutes；Wherein, tetramethyl hydroxide in developer solution
The mol ratio of ammonia and water is 1:3；
(3) N~+ implantation is carried out, injection condition is 300keV/2 × 1012cm-2, temperature is 400 DEG C, and acetone is used after the completion of injection
+ ultrasonic depolymerization, then with the removing of photoresist by plasma 3 minutes；Being formed, there is depth to be 0.15 μm, respectively with source electrode cap layers inboard, away from source electrode
At inboard 1.4 μm of cap layers and away from the inboard 1.7 μm of places of source electrode cap layers it is starting point, length is respectively 1.2 μm, 0.1 μm and 0.5 μm and delays
Rush layer depressed area (9), (10), (11)；
(4) above-mentioned 4H-SiC epitaxial wafers are placed in 1600 DEG C of sensing heating furnace annealings, 10 minutes activator impurities, Ar throughputs are
20ml/min, completes the making of many depression p-type cushions.
10. the preparation side of the 4H-SiC metal semiconductor field effect transis according to claim 1 with many depression cushions
Method, it is characterised in that the step 9) in the specific manufacturing process of gate electrode (8) be：
(1) masking glue is using the double-deck glue of PMMA+AZ1400, it is desirable to glue thickness ＞ 1.2nm, and PMMA is first applied after piece subprocessing is clean
Glue, speed is 4000R/min, glue thickness 0.5nm, and then front baking 120 seconds in 200 DEG C of baking ovens, apply AZ1400 glue thick again after taking-up
0.8nm；
(2) front baking 90 seconds in 90 DEG C of baking ovens, are carried out after 15 seconds uv-exposures with special developing liquid developing 50 using grid photolithography plate
Second removes AZ1400 glue, and pan-exposure is then carried out to PMMA glue, and again with toluene is developed 3 minutes, then rear in 100 DEG C of baking ovens to dry
3 minutes；Wherein, the mol ratio of tetramethyl aqua ammonia and water is 1 in developer solution:4；
(3) multi-target magnetic control sputtering platform is used, room temperature sputtering thickness is more for 150nm Ni, 150nm Ti and 300nm Au successively
Layer metal is used as source and drain metal ohmic contact, wherein working vacuum 2.5 × 10-3By piece in Pa, Ar flow 40sccm, sputter procedure
Son is heated to 150 DEG C；
(4) slice, thin piece is put into 150 DEG C of special strippers of Buty after the completion of sputtering, 130 DEG C of Buty are moved into again after metal comes off
In stripper, when equitemperature drops to less than 80 DEG C, then by slice, thin piece immigration acetone, slice, thin piece is finally taken out and slow with low discharge nitrogen
Slow drying, finally with the removing of photoresist by plasma 3 minutes, completes the making of gate electrode (8).
11. the preparation side of the 4H-SiC metal semiconductor field effect transis according to claim 1 with many depression cushions
Method, it is characterised in that the step 10) in electrode pad, complete element manufacturing detailed process be：
(1) at 300 DEG C, it is passed through the SiH that flow is 300sccm simultaneously into reative cell4, 323sccm NH3With 330sccm's
N2, by plasma enhanced CVD technique, in the Si of the μ m-thick of surface deposition 0.53N4Layer is used as passivation dielectric layer；
(2) passivation photoetching uses positive photoresist, application rate 3000R/mins, it is desirable to 2 μm of glue thickness ＞, 90 after the completion of gluing
Front baking 90 seconds in DEG C baking oven, then carried out 35 seconds uv-exposures using anti-carving photolithography plate, with special developing liquid developing 60 seconds, finally
Dried 3 minutes after in 100 DEG C of baking ovens；Wherein, the mol ratio of tetramethyl aqua ammonia and water is 1 in developer solution:3；
(3)Si3N4Etching uses RIE techniques, and etching gas selection flow is 50sccm CHF3It is 5sccm Ar with flow, completes
Carry out 3 minutes removing of photoresist by plasmas again afterwards, expose metal, form source, leakage and gate electrode pressure welding point, complete the system of whole device
Make.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710165905.8A CN107068762A (en) | 2017-03-20 | 2017-03-20 | The preparation method of 4H SiC metal semiconductor field effect transis with many depression cushions |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710165905.8A CN107068762A (en) | 2017-03-20 | 2017-03-20 | The preparation method of 4H SiC metal semiconductor field effect transis with many depression cushions |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107068762A true CN107068762A (en) | 2017-08-18 |
Family
ID=59620740
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710165905.8A Pending CN107068762A (en) | 2017-03-20 | 2017-03-20 | The preparation method of 4H SiC metal semiconductor field effect transis with many depression cushions |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107068762A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| RU2691772C1 (en) * | 2018-03-06 | 2019-06-18 | Публичное Акционерное Общество "Электровыпрямитель" | Method for growth of epitaxial structure of monocrystalline silicon carbide with low density of epitaxial defects |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101022129A (en) * | 2007-03-26 | 2007-08-22 | 电子科技大学 | Metal-semiconductor field effect transistor with source-drain double-concave structure |
| CN101964363A (en) * | 2010-08-06 | 2011-02-02 | 电子科技大学 | Metal-semiconductor field effect transistor with stepped buffer layer structure |
| CN103681256A (en) * | 2013-08-27 | 2014-03-26 | 厦门天睿电子有限公司 | A novel silicon carbide MOSFET device and a manufacturing method thereof |
| CN104681618A (en) * | 2015-01-04 | 2015-06-03 | 西安电子科技大学 | 4H-SiC metal-semiconductor field effect transistor with double-sunken buffer layer |
-
2017
- 2017-03-20 CN CN201710165905.8A patent/CN107068762A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101022129A (en) * | 2007-03-26 | 2007-08-22 | 电子科技大学 | Metal-semiconductor field effect transistor with source-drain double-concave structure |
| CN101964363A (en) * | 2010-08-06 | 2011-02-02 | 电子科技大学 | Metal-semiconductor field effect transistor with stepped buffer layer structure |
| CN103681256A (en) * | 2013-08-27 | 2014-03-26 | 厦门天睿电子有限公司 | A novel silicon carbide MOSFET device and a manufacturing method thereof |
| CN104681618A (en) * | 2015-01-04 | 2015-06-03 | 西安电子科技大学 | 4H-SiC metal-semiconductor field effect transistor with double-sunken buffer layer |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| RU2691772C1 (en) * | 2018-03-06 | 2019-06-18 | Публичное Акционерное Общество "Электровыпрямитель" | Method for growth of epitaxial structure of monocrystalline silicon carbide with low density of epitaxial defects |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102629624B (en) | Metal-insulator-semiconductor (MIS) grid enhanced high electron mobility transistor (HEMT) device based on gallium nitride (GaN) and manufacture method of MIS grid enhanced HEMT device | |
| CN107369704B (en) | Laminated gate enhanced GaN high electron mobility transistor containing ferroelectric gate dielectric and preparation method | |
| CN104393047B (en) | 4H SiC metal-semiconductor field effect transistors with ladder disign Rotating fields | |
| CN107248528B (en) | GaN base microwave power device and preparation method thereof is lost in low frequency | |
| CN105810722A (en) | SiC metal-oxide-semiconductor field-effect transistor (MOSFET) device and fabrication method thereof | |
| CN112968059B (en) | Novel enhancement mode gaN HEMT device structure | |
| CN106229345A (en) | Laminated gate medium GaN base insulated gate HEMT and manufacture method | |
| CN106373884A (en) | Fabrication method for transistor with composite gate dielectric GaN-based insulating gate and high electron mobility | |
| CN110120425B (en) | Vertical high-voltage MOSFET device and manufacturing method | |
| CN107170822B (en) | GaN-based groove insulated gate enhanced high electron mobility transistor based on negative capacitance medium | |
| CN107393959A (en) | GaN hyperfrequencies device and preparation method based on sag | |
| CN104282764B (en) | 4H SiC metal-semiconductor field effect transistors and preparation method with domatic grid | |
| CN104037218B (en) | A kind of high-performance AlGaN/GaN HEMT high-voltage device structure based on polarity effect and manufacture method | |
| CN104681618B (en) | A kind of 4H SiC metal-semiconductor field effect transistors with dual recess cushion | |
| CN112993030A (en) | Method for improving reliability of groove grid GaN MIS FET device | |
| CN104064595B (en) | A kind of enhanced AlGaN based on slot grid structure/GaN MISHEMT device architecture and preparation method thereof | |
| CN106449737B (en) | Low contact resistance type GaN base device and preparation method thereof | |
| CN105789056A (en) | Method of preparing 4H-SiC metal semiconductor field effect transistor with part highly-doped channel | |
| CN107068762A (en) | The preparation method of 4H SiC metal semiconductor field effect transis with many depression cushions | |
| CN104867835A (en) | Preparation method for metal semiconductor field effect transistor with wide channel and deep recesses | |
| CN111785776A (en) | Vertical structure Ga2O3Preparation method of metal oxide semiconductor field effect transistor | |
| CN104916698B (en) | It is a kind of that there is field-effect transistor of three sunk structures and preparation method thereof | |
| CN104882483B (en) | Field-effect transistor with Γ grid and recess buffer layer and preparation method thereof | |
| CN113809154B (en) | Nitride barrier stress modulation device and preparation method thereof | |
| CN112993029B (en) | Method for improving GaN HEMT interface quality |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170818 |
|
| RJ01 | Rejection of invention patent application after publication |