CN113871468A - Silicon carbide MIS device with stacked gate structure and preparation method thereof - Google Patents

Silicon carbide MIS device with stacked gate structure and preparation method thereof Download PDF

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CN113871468A
CN113871468A CN202110817730.0A CN202110817730A CN113871468A CN 113871468 A CN113871468 A CN 113871468A CN 202110817730 A CN202110817730 A CN 202110817730A CN 113871468 A CN113871468 A CN 113871468A
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gate dielectric
layer
silicon carbide
thickness
substrate
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康俊勇
李光容
王伟平
吴志明
孔丽晶
吴雅苹
李煦
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Jiujiang Research Institute Of Xiamen University
Xiamen University
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Xiamen University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
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    • H01L21/049—Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
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Abstract

The invention discloses a silicon carbide MIS device with a stacked gate structure and a preparation method thereof, wherein the device structure comprises a back electrode, an N + type 4H-SiC epitaxial material substrate layer, a gate dielectric layer and a gate electrode, wherein the back electrode, the N + type 4H-SiC epitaxial material substrate layer, the AlN and the gate dielectric layer are stacked with Al2O 3. According to the invention, AlN with a high dielectric constant and Al2O3 materials are combined to form a stacked gate structure dielectric layer, and nitrogen plasma is used for carrying out surface passivation on the bottom gate dielectric AlN, so that the surface is smooth and has no reconstruction, the interface connection between the bottom gate dielectric and the upper gate dielectric is optimized, the interface characteristics of the substrate and the gate dielectric of the silicon carbide MIS device are improved, the carrier mobility and the critical breakdown field strength are improved, and the device performance is finally improved.

Description

Silicon carbide MIS device with stacked gate structure and preparation method thereof
Technical Field
The invention relates to the technical field of microelectronics, in particular to a stacked gate dielectric silicon carbide MIS device with a high dielectric constant and a preparation method thereof.
Background
The silicon carbide (SiC) material is a wide bandgap semiconductor with excellent performance, has high thermal conductivity, high critical breakdown field strength and high saturated electron drift rate, and has the advantages of stable physicochemical characteristics, extremely high irradiation resistance, mechanical strength and the like. In recent years, the technology has rapidly developed into a research hotspot in the fields of high-temperature, high-frequency and high-power electronic devices and the like.
Nevertheless, SiC-based metal-insulator-semiconductor (SiC-MIS) devices have met with significant challenges with respect to reliability and electron mobility of the gate dielectric layer. The gate dielectric of the common insulating layer is SiO2But SiC and SiO2The interface connection is not ideal, a large number of interface dangling bond carbon clusters cause a high interface state near the conduction band bottom, channel scattering and carrier capture are aggravated, the channel mobility is reduced, and the reliability of the device is influenced. At the same time, SiO2Dielectric constant lower than SiC, so that SiO2The internal electric field is stronger and will be broken down earlier, SiC and SiO2The combination of (2) does not sufficiently exert the superiority of the SiC material. With the development of semiconductor process, the device volume is continuously reduced when SiO is used2The gate dielectric reaches the ideal physical limit thickness (less than 5nm), and quantum tunneling effect even causes device failure.
Therefore, there is a need to find a dielectric layer with high dielectric constant and good interface matching to replace SiO2So as to improve the reliability of the SiC-MIS device.
Disclosure of Invention
Aiming at the problems in the related art, the invention provides a SiC-MIS device with a stacked gate structure and a preparation method thereof. Mixing AlN and Al2O3The materials are stacked to form a gate dielectric layer, and by utilizing the advantage that the lattice mismatch between AlN and 4H-SiC is smaller,the interface quality is improved, and the leakage current density is reduced. The surface of the AlN thin film is passivated by using nitrogen plasma, the surface of AlN formed by the plasma with strong reaction activity is smooth and has no reconstruction, and the interface connection between the bottom layer gate dielectric and the upper layer gate dielectric is optimized. Al with wider bonding forbidden band2O3The material pushes the interface state which can appear near the bottom of the 4H-SiC conduction band to the center of the forbidden band. The invention provides a stacked gate structure dielectric layer with high dielectric constant, high critical electric field and low interface state density and a preparation method thereof, which are used for solving the problems in the background technology.
In order to achieve the technical purpose, the technical scheme of the invention is as follows:
the SiC-MIS device is designed, and sequentially comprises a back electrode, an N + substrate layer, an N type homoepitaxial layer, a bottom gate dielectric, a dielectric interface passivation layer, an upper gate dielectric and a gate electrode from bottom to top, wherein the bottom gate dielectric and the upper gate dielectric are stacked to form a gate dielectric layer.
Further, the N + substrate layer is doped with a dopant with a concentration of 5 × 1018cm-3The N-type 4H-SiC of phosphorus ions, and the thickness of the N + substrate layer is 500 mu m.
Further, the N-type epitaxial layer is doped with a dopant with a concentration of 8 × 1015cm-3The thickness of the N type epitaxial layer is 1-100 mu m.
Further, the first grid dielectric layer is made of AlN materials, the thickness of the bottom grid dielectric layer is about 2nm, and the surface is passivated by nitrogen plasma.
Further, the upper gate dielectric layer is Al2O3The thickness of the upper layer gate dielectric is 20 nm.
Further, the back electrode is an Al thin film with the thickness of about 200 μm.
Further, the gate electrode is a cylindrical Al material with the diameter of 500 μm and the thickness of 200 nm.
A preparation method of a silicon carbide MIS device with a stacked gate structure comprises the following steps:
step S1, taking the thickness of 350 μm and the nitrogen ion doping concentration of 5 × 1018cm-3The N + silicon carbide substrate slice is prepared at 1600 ℃ and 150mbar pressure by using silane and propane as reaction gases and PH as doping source gas3The carrier gas is PH3RCA cleaning is performed under the condition of (1);
step S2, growing an N-type epitaxial layer on the cleaned N + substrate layer, and carrying out process treatment, wherein the doped ions are phosphorus ions, and the doping concentration is 8 multiplied by 1015cm-3The thickness of the N-type 4H-SiC is 1-100 mu m;
step S3, cleaning a 4H-SiC epitaxial substrate, sequentially carrying out organic solution ultrasonic cleaning, alkali cleaning and acid cleaning on a sample, carrying out 5% HF solution soaking after each cleaning step, then washing in deionized water, and drying by nitrogen;
step S4, preparing a bottom gate medium AlN film above the N-type epitaxial layer by utilizing a magnetron sputtering process;
step S5, passivating the surface by using nitrogen plasma to form an ultrathin medium interface passivation layer;
step S6, preparing an upper layer gate dielectric Al above a bottom layer gate dielectric by utilizing a magnetron sputtering process2O3Film, and carry on the high-temperature annealing treatment to the sample forming gate dielectric;
step S7, depositing Al metal on the back to prepare a back electrode;
and step S8, depositing Al metal on the front surface, preparing a gate electrode and finishing the manufacture of the MIS device.
Further, in the step S2, the process conditions are as follows: the temperature is 1600 ℃, the pressure is 150mbar, the reaction gases are silane and propane, and the doping source gas is PH3。
The invention has the beneficial effects that:
1. compared with the traditional preparation process, the method for preparing the SiC-MIS device by using the magnetron sputtering process can avoid the problems of carbon cluster aggregation and the like at the interface of the 4H-SiC and the gate dielectric, and simultaneously reduces the thermal budget.
2. The invention adopts stacked gate dielectric, and two selected materials of AlN and Al2O3Has the advantages of large forbidden band width and high dielectric constant,compared with the conventional SiO2As the dielectric layer, on the premise of ensuring the same capacitance, the physical thickness of the gate dielectric layer can be increased, the influence of quantum tunneling effect on the device is avoided, and the stability of the device is improved.
3. The bottom layer gate dielectric is made of AlN material, the lattice constant of the bottom layer gate dielectric is close to that of 4H-SiC, the lattice mismatch is small, the interface characteristic can be improved, and the problem of overhigh interface state is effectively solved.
4. According to the invention, nitrogen plasma is utilized to carry out surface passivation on the bottom layer gate dielectric AlN, the AlN surface formed by plasma treatment with strong reaction activity is smooth and has no reconstruction, and the interface connection between the bottom layer gate dielectric and the upper layer gate dielectric is optimized. Meanwhile, partial ions passivate SiC substrate dangling bonds, and high-energy particles are prevented from directly damaging the surface of the silicon carbide.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a silicon carbide MIS device having a stacked gate structure in accordance with an embodiment of the present invention;
fig. 2 is a first schematic view of a process flow of a silicon carbide MIS device having a stacked gate structure according to an embodiment of the invention at step S2;
fig. 3 is a second schematic view of a process flow step S4 of a silicon carbide MIS device having a stacked gate structure in accordance with an embodiment of the invention;
fig. 4 is a schematic diagram of a process flow step S5 of a silicon carbide MIS device having a stacked gate structure in accordance with an embodiment of the invention;
fig. 5 is a fourth schematic process flow step S6 of a silicon carbide MIS device having a stacked gate structure in accordance with an embodiment of the invention;
fig. 6 is a process flow step S7 of a silicon carbide MIS device having a stacked gate structure in accordance with an embodiment of the present invention;
in the figure: 1. an N + substrate layer; 2. an N-type epitaxial layer; 3. a bottom layer gate dielectric; 4. a dielectric interface passivation layer; 5. an upper gate dielectric layer; 6. a back electrode; 7. and a gate electrode.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments that can be derived by one of ordinary skill in the art from the embodiments given herein are intended to be within the scope of the present invention.
The first embodiment is as follows:
as shown in fig. 1, the silicon carbide MIS device with a stacked gate structure according to the embodiment of the present invention sequentially includes, from bottom to top, a back electrode 6, an N + substrate layer 1, an N-type epitaxial layer 2, a bottom gate dielectric 3, a dielectric interface passivation layer 4, an upper gate dielectric 5, and a gate electrode 7, where the bottom gate dielectric 3, the dielectric interface passivation layer 4, and the upper gate dielectric 5 are stacked to form a gate dielectric layer.
In this embodiment, the N + substrate layer 1 is doped with a dopant concentration of 5 × 1018cm-3The N-type 4H-SiC of phosphorus ions, and the thickness of the N + substrate layer is 350 mu m.
In this embodiment, the N-type epitaxial layer is doped with a dopant concentration of 8 × 1015cm-3The thickness of the N type epitaxial layer is 1-100 mu m.
In this embodiment, the first gate dielectric layer is an AlN material, the bottom gate dielectric layer has a thickness of 2nm, and the surface is passivated with nitrogen plasma.
In this embodiment, the upper gate dielectric layer is Al2O3The thickness of the upper layer gate dielectric is 20 nm.
In this embodiment, the back electrode is an Al thin film with a thickness of about 200 nm.
In this embodiment, the gate electrode is a cylindrical Al material with a diameter of 500 μm and a thickness of 200 nm.
As shown in fig. 2-6, a method for fabricating a silicon carbide MIS device having a stacked gate structure includes the steps of:
step S1, taking the thickness of 350 μm and the nitrogen ion doping concentration of 5 × 1018cm-3The N + silicon carbide substrate layer 1 is prepared at 1600 ℃ and 150mbar of pressure, the reaction gases are silane and propane, and the doping source gas is PH3The carrier gas is PH3RCA cleaning is performed under the condition of (1);
step S2, growing an N-type epitaxial layer 2 on the cleaned N + substrate layer 1, and carrying out process treatment, wherein the doping ions are phosphorus ions, and the doping concentration is 8 multiplied by 1015cm-3The thickness of the N-type 4H-SiC is 1-100 mu m;
step S3, cleaning the 4H-SiC epitaxial substrate by a wet process to remove organic matters and natural oxides, sequentially carrying out ultrasonic cleaning, alkali cleaning and acid cleaning on the sample by using an organic solution, soaking by using a 5% HF solution after each cleaning step, washing in deionized water, and drying by using nitrogen; finally, soaking the substrate for 5 minutes at 80 ℃ by using an HF solution with the concentration of 5%, ultrasonically cleaning the substrate for 20 minutes by using deionized water, washing the substrate for several times by using the deionized water, and finally drying the substrate by using nitrogen;
step S4, preparing a bottom gate dielectric 3 above the N-type epitaxial layer 2, in this embodiment, using a magnetron sputtering process, where the bottom gate substrate 3 is an AlN material. Obtaining a bottom layer gate dielectric 3 with the thickness of about 2 nm;
step S5, placing the obtained sample into a plasma degumming machine, and passivating the surface of the bottom layer gate dielectric by using nitrogen plasma to obtain an ultrathin interface passivation layer 4;
step S6, preparing an upper gate dielectric 5 above the interface passivation layer 4, in this embodiment, using a magnetron sputtering process, wherein the bottom gate dielectric 5 is Al2O3Adjusting the distance between the target material and the substrate, vacuumizing and heating the substrate, introducing high-purity oxygen as reaction gas, and naturally cooling to obtain the upper-layer gate dielectric 5 with the thickness of about 20 nm. Then putting the sample for forming the gate dielectric into an annealing furnace, introducing high-purity oxygen into the annealing furnaceCarrying out high-temperature annealing by using nitrogen;
step S7, preparing a back electrode 6, and depositing a metal electrode on the back of the sample by utilizing a magnetron sputtering process, wherein the material of the back electrode 6 is Al, and the thickness of the back electrode 6 is 200 nm;
and step S8, preparing a gate electrode 7, depositing a metal electrode on the front surface of the sample by utilizing a magnetron sputtering process, wherein the gate electrode 7 is made of Al, is cylindrical, has the diameter of 500 mu m and the thickness of 200nm, and the SiC-MIS device is manufactured.
In this embodiment, in the step S2, the process conditions are as follows: the temperature is 1600 ℃, the pressure is 150mbar, the reaction gases are silane and propane, and the doping source gas is PH3。
In this embodiment, in step S4, the magnetron sputtering process parameters are: argon flow of 30sccm, starting power of 30W, background vacuum degree of 5 × 10-5Pa, sputtering gas pressure of 0.65Pa, and sputtering time of 60-120 s.
In this embodiment, in step S5, the surface passivation parameters are: the power is 50W, the nitrogen flow is 1.5L/min, and the treatment time is 60-200 s.
In this embodiment, in step S6, the magnetron sputtering process parameters include argon flow of 30sccm, oxygen flow of 5sccm to 15sccm, starting power of 30W, and background vacuum degree of 5 × 10-4Pa, sputtering gas pressure of 0.65Pa, substrate temperature of 400 ℃ and sputtering time of 40 min; the annealing process comprises in-situ low-temperature annealing and slow high-temperature annealing, wherein the parameters of the in-situ low-temperature annealing process are that the oxygen flow is 30sccm, the temperature is 400 ℃, and the air pressure is 7 Pa. The slow high-temperature annealing process has the parameters that the flow ratio of oxygen to nitrogen is controlled to be 1:2, the high-temperature annealing comprises a heating process, a heat preservation process and a natural cooling process, and the heating process needs to be heated to 1100 ℃ through two gradient stages.
Example two:
as shown in fig. 1, the silicon carbide MIS device with a stacked gate structure according to the embodiment of the present invention sequentially includes, from bottom to top, a back electrode 6, an N + substrate layer 1, an N-type epitaxial layer 2, a bottom gate dielectric 3, a dielectric interface passivation layer 4, an upper gate dielectric 5, and a gate electrode 7, where the bottom gate dielectric 3, the dielectric interface passivation layer 4, and the upper gate dielectric 5 are stacked to form a gate dielectric layer.
In this embodiment, the N + substrate layer 1 is doped with a dopant concentration of 5 × 1018cm-3The N-type 4H-SiC of phosphorus ions, and the thickness of the N + substrate layer is 350 mu m.
In this embodiment, the N-type epitaxial layer is doped with a dopant concentration of 8 × 1015cm-3The thickness of the N type epitaxial layer is 1-100 mu m.
In this embodiment, the first gate dielectric layer is an AlN material, the bottom gate dielectric layer has a thickness of 7nm, and the surface is passivated with nitrogen plasma.
In this embodiment, the upper gate dielectric layer is Al2O3The thickness of the upper layer gate dielectric is 15 nm.
In this embodiment, the back electrode is an Al thin film with a thickness of about 200 nm.
In this embodiment, the gate electrode is a cylindrical Al material with a diameter of 500 μm and a thickness of 200 nm.
As shown in fig. 2-6, a method for fabricating a silicon carbide MIS device having a stacked gate structure includes the steps of:
step S1, taking the thickness of 300 μm and the nitrogen ion doping concentration of 5 × 1018cm-3The N + silicon carbide substrate layer 1 is prepared at 1600 ℃ and 150mbar of pressure, the reaction gases are silane and propane, and the doping source gas is PH3The carrier gas is PH3RCA cleaning is performed under the condition of (1);
step S2, growing an N-type epitaxial layer 2 on the cleaned N + substrate layer 1, and carrying out process treatment, wherein the doping ions are phosphorus ions, and the doping concentration is 8 multiplied by 1015cm-3The thickness of the N-type 4H-SiC is 1-100 mu m;
step S3, cleaning the 4H-SiC epitaxial substrate by a wet process to remove organic matters and natural oxides, sequentially carrying out ultrasonic cleaning, alkali cleaning and acid cleaning on the sample by using an organic solution, soaking by using a 5% HF solution after each cleaning step, washing in deionized water, and drying by using nitrogen; finally, soaking the substrate for 5 minutes at 80 ℃ by using an HF solution with the concentration of 5%, ultrasonically cleaning the substrate for 20 minutes by using deionized water, washing the substrate for several times by using the deionized water, and finally drying the substrate by using nitrogen;
step S4, preparing a bottom gate dielectric 3 above the N-type epitaxial layer 2, in this embodiment, using a magnetron sputtering process, where the bottom gate substrate 3 is an AlN material. Obtaining a bottom layer gate dielectric 3 with the thickness of about 7 nm;
step S5, placing the obtained sample into a plasma degumming machine, and passivating the surface of the bottom layer gate dielectric by using nitrogen plasma to obtain an ultrathin interface passivation layer 4;
step S6, preparing an upper gate dielectric 5 above the interface passivation layer 4, in this embodiment, using a magnetron sputtering process, wherein the bottom gate dielectric 5 is Al2O3Adjusting the distance between the target material and the substrate, vacuumizing, heating the substrate, introducing high-purity oxygen as reaction gas, and naturally cooling to obtain an upper-layer gate dielectric 5 with the thickness of about 15 nm. Then, putting the sample for forming the gate dielectric into an annealing furnace, and introducing high-purity oxygen and nitrogen for high-temperature annealing;
step S7, preparing a back electrode 6, and depositing a metal electrode on the back of the sample by utilizing a magnetron sputtering process, wherein the material of the back electrode 6 is Al, and the thickness of the back electrode 6 is 200 nm;
and step S8, preparing a gate electrode 7, depositing a metal electrode on the front surface of the sample by utilizing a magnetron sputtering process, wherein the gate electrode 7 is made of Al, is cylindrical, has the diameter of 500 mu m and the thickness of 200nm, and the SiC-MIS device is manufactured.
In this embodiment, in the step S2, the process conditions are as follows: the temperature is 1600 ℃, the pressure is 150mbar, the reaction gases are silane and propane, and the doping source gas is PH3。
In this embodiment, in step S4, the magnetron sputtering process parameters are: argon flow of 30sccm, starting power of 30W, background vacuum degree of 9 × 10-5Pa, sputtering gas pressure of 0.65Pa, and sputtering time of 210-420 s.
In this embodiment, in step S5, the surface passivation parameters are: the power is 50W, the nitrogen flow is 1.5L/min, and the treatment time is 60-200 s.
In this embodiment, in step S6, the magnetron sputtering process parameters include argon flow of 30sccm, oxygen flow of 5sccm to 15sccm, starting power of 30W, and background vacuum degree of 5 × 10-4Pa, sputtering gas pressure of 0.65Pa, substrate temperature of 400 ℃ and sputtering time of 40 min; the annealing process comprises in-situ low-temperature annealing and slow high-temperature annealing, wherein the parameters of the in-situ low-temperature annealing process are that the oxygen flow is 30sccm, the temperature is 400 ℃, and the air pressure is 7 Pa. The slow high-temperature annealing process has the parameters that the flow ratio of oxygen to nitrogen is controlled to be 1:2, the high-temperature annealing comprises a heating process, a heat preservation process and a natural cooling process, and the heating process needs to be heated to 1100 ℃ through two gradient stages.
Example three:
as shown in fig. 1, the silicon carbide MIS device with a stacked gate structure according to the embodiment of the present invention sequentially includes, from bottom to top, a back electrode 6, an N + substrate layer 1, an N-type epitaxial layer 2, a bottom gate dielectric 3, a dielectric interface passivation layer 4, an upper gate dielectric 5, and a gate electrode 7, where the bottom gate dielectric 3, the dielectric interface passivation layer 4, and the upper gate dielectric 5 are stacked to form a gate dielectric layer.
In this embodiment, the N + substrate layer 1 is doped with a dopant concentration of 5 × 1018cm-3The N-type 4H-SiC of phosphorus ions, and the thickness of the N + substrate layer is 350 mu m.
In this embodiment, the N-type epitaxial layer is doped with a dopant concentration of 8 × 1015cm-3The thickness of the N type epitaxial layer is 1-100 mu m.
In this embodiment, the first gate dielectric layer is an AlN material, the bottom gate dielectric layer has a thickness of 2nm, and the surface is passivated with nitrogen plasma.
In this embodiment, the upper gate dielectric layer is Al2O3The thickness of the upper layer gate dielectric is 20 nm.
In this embodiment, the back electrode is an Al thin film with a thickness of about 200 nm.
In this embodiment, the gate electrode is a cylindrical Al material with a diameter of 500 μm and a thickness of 200 nm.
As shown in fig. 2-6, a method for fabricating a silicon carbide MIS device having a stacked gate structure includes the steps of:
step S1, taking the thickness of 350 μm and the nitrogen ion doping concentration of 5 × 1018cm-3The N + silicon carbide substrate layer 1 is prepared at 1600 ℃ and 150mbar of pressure, the reaction gases are silane and propane, and the doping source gas is PH3The carrier gas is PH3RCA cleaning is performed under the condition of (1);
step S2, growing an N-type epitaxial layer 2 on the cleaned N + substrate layer 1, and carrying out process treatment, wherein the doping ions are phosphorus ions, and the doping concentration is 8 multiplied by 1015cm-3The thickness of the N-type 4H-SiC is 1-100 mu m;
step S3, cleaning the 4H-SiC epitaxial substrate by a wet process to remove organic matters and natural oxides, sequentially carrying out ultrasonic cleaning, alkali cleaning and acid cleaning on the sample by using an organic solution, soaking by using a 5% HF solution after each cleaning step, washing in deionized water, and drying by using nitrogen; finally, soaking the substrate for 5 minutes at 80 ℃ by using an HF solution with the concentration of 5%, ultrasonically cleaning the substrate for 20 minutes by using deionized water, washing the substrate for several times by using the deionized water, and finally drying the substrate by using nitrogen;
step S4, preparing a bottom gate dielectric 3 above the N-type epitaxial layer 2, in this embodiment, using a magnetron sputtering process, where the bottom gate substrate 3 is an AlN material. Obtaining a bottom layer gate dielectric 3 with the thickness of about 2 nm;
step S5, placing the obtained sample into a plasma degumming machine, and passivating the surface of the bottom layer gate dielectric by using nitrogen plasma to obtain an ultrathin interface passivation layer 4;
step S6, preparing an upper gate dielectric 5 above the interface passivation layer 4, in this embodiment, using a magnetron sputtering process, wherein the bottom gate dielectric 5 is Al2O3Adjusting the distance between the target material and the substrate, vacuumizing and heating the substrate, introducing high-purity oxygen as reaction gas, and naturally cooling to obtain the upper-layer gate dielectric 5 with the thickness of about 20 nm. Then putting the sample for forming the gate dielectric into an annealing furnace, introducing high-purity oxygen into the annealing furnaceCarrying out high-temperature annealing by using nitrogen;
step S7, preparing a back electrode 6, and depositing a metal electrode on the back of the sample by utilizing a magnetron sputtering process, wherein the material of the back electrode 6 is Al, and the thickness of the back electrode 6 is 200 nm;
and step S8, preparing a gate electrode 7, depositing a metal electrode on the front surface of the sample by utilizing a magnetron sputtering process, wherein the gate electrode 7 is made of Al, is cylindrical, has the diameter of 500 mu m and the thickness of 200nm, and the SiC-MIS device is manufactured.
In this embodiment, in the step S2, the process conditions are as follows: the temperature is 1600 ℃, the pressure is 150mbar, the reaction gases are silane and propane, and the doping source gas is PH3。
In this embodiment, in step S4, the magnetron sputtering process parameters are: argon flow of 30sccm, starting power of 30W, background vacuum degree of 9 × 10-5Pa, sputtering gas pressure of 0.65Pa, and sputtering time of 60-120 s.
In this embodiment, in step S5, the surface passivation parameters are: the power is 10-50W, the nitrogen flow is 1.5L/min, and the treatment time is 60-200 s.
In this embodiment, in step S6, the magnetron sputtering process parameters include argon flow of 30sccm, oxygen flow of 5sccm to 15sccm, starting power of 30W, and background vacuum degree of 5 × 10-4Pa, sputtering gas pressure of 0.65Pa, substrate temperature of 400 ℃ and sputtering time of 40 min; the annealing process comprises in-situ low-temperature annealing and slow high-temperature annealing, wherein the parameters of the in-situ low-temperature annealing process are that the oxygen flow is 30sccm, the temperature is 400 ℃, and the air pressure is 7 Pa. The slow high-temperature annealing process has the parameters that the flow ratio of oxygen to nitrogen is controlled to be 1:2, the high-temperature annealing comprises a heating process, a heat preservation process and a natural cooling process, and the heating process needs to be heated to 1100 ℃ through two gradient stages.
The foregoing detailed description illustrates the efficacy and principles of the present invention, but is not intended to limit the invention. Any modification or modification made by the teachings of the present invention without departing from the spirit and principle of the present invention shall be considered as equivalent replacement of the present invention, and shall be covered by the claims of the present invention and protected thereby.
In the description of the present invention, it is to be understood that the indicated orientations or positional relationships are based on the orientations or positional relationships shown in the drawings and are only for convenience in describing the present invention and simplifying the description, but are not intended to indicate or imply that the indicated devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are not to be construed as limiting the present invention.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims (8)

1. The silicon carbide MIS device with the stacked gate structure is characterized by sequentially comprising a back electrode (6), an N + substrate layer (1), an N-type epitaxial layer (2), a bottom gate dielectric (3), a dielectric interface passivation layer (4), an upper gate dielectric (5) and a gate electrode (7) from bottom to top; the bottom layer gate dielectric and the upper layer gate dielectric are stacked to form a gate dielectric layer.
2. The silicon carbide MIS device of claim 1 wherein the underlying gate dielectric (3) is an AlN material, the underlying gate dielectric having a thickness of about 2 nm.
3. Silicon carbide according to claim 1MIS device, characterized in that the upper gate dielectric (5) is Al2O3The thickness of the upper layer gate dielectric is 20 nm.
4. The silicon carbide MIS device as claimed in claim 1 wherein the N + substrate layer (1) is 350 μm thick and the material of the N + substrate layer (1) is doped to a concentration of 5 x 1018 cm-3Phosphorus ion N-type 4H-SiC.
5. The silicon carbide MIS device as claimed in claim 1, wherein the N-type epitaxial layer (2) has a thickness of 1 μm to 100 μm, and the N-type epitaxial layer (2) is doped with a dopant having a concentration of 8 x 1015 cm-3Phosphorus ion N-type 4H-SiC.
6. The silicon carbide MIS device of claim 1 wherein the back electrode (6) has a thickness of 200nm and the gate electrode (7) has a cylindrical shape with a diameter of 500 μm and a thickness of 200 nm.
7. The method of fabricating a silicon carbide MIS device of claim 1, comprising the steps of:
step S1, taking the thickness of 350 μm and the nitrogen ion doping concentration of 5 × 1018 cm-3The N + silicon carbide substrate slice is prepared at 1600 ℃ and 150mbar pressure by using silane and propane as reaction gases and PH as doping source gas3The carrier gas is PH3RCA cleaning is performed under the condition of (1);
step S2, growing an N-type epitaxial layer (2) on the cleaned N + substrate layer (1), and carrying out process treatment, wherein the doped ions are phosphorus ions, and the doping concentration is 8 multiplied by 1015 cm-3The thickness of the N-type 4H-SiC is 1-100 mu m;
step S3, cleaning a 4H-SiC epitaxial substrate, sequentially carrying out organic solution ultrasonic cleaning, alkali cleaning and acid cleaning on a sample, carrying out 5% HF solution soaking after each cleaning step, then washing in deionized water, and drying by nitrogen;
step S4, preparing an AlN film of the bottom gate dielectric (3) above the N-type epitaxial layer (2) by utilizing a magnetron sputtering process;
step S5, passivating the surface by using nitrogen plasma to form a medium interface passivation layer (4);
step S6, preparing an upper gate dielectric (5) Al above the interface passivation layer (4) by utilizing a magnetron sputtering process2O3Film, and carry on the high-temperature annealing treatment to the sample forming gate dielectric;
step S7, evaporating Al metal on the back surface to prepare a back electrode (6);
and step S8, evaporating Al metal on the front surface, preparing a gate electrode (7) and finishing the manufacture of the MIS device.
8. The method of claim 7, wherein in step S2, the conditions of the process are as follows: the temperature is 1600 ℃, the pressure is 150mbar, the reaction gases are silane and propane, and the doping source gas is PH3。
CN202110817730.0A 2021-07-20 2021-07-20 Silicon carbide MIS device with stacked gate structure and preparation method thereof Pending CN113871468A (en)

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