WO2023015611A1

WO2023015611A1 - Composite structure of semiconductor wafer, and semiconductor wafer and preparation method therefor and application thereof

Info

Publication number: WO2023015611A1
Application number: PCT/CN2021/114429
Authority: WO
Inventors: 张耀辉; 黄安东
Original assignee: 苏州龙驰半导体科技有限公司
Priority date: 2021-08-10
Filing date: 2021-08-25
Publication date: 2023-02-16
Also published as: CN115706046A

Abstract

Disclosed in the present application are a composite structure of a semiconductor wafer, and a semiconductor wafer and a preparation method therefor and an application thereof. The preparation method for a semiconductor wafer comprises: performing thermal oxidation on SiC on a surface layer of a first wafer to form a first oxide layer; forming a second oxide layer on a surface of a second wafer, and forming a peeling layer at a selected depth in the second wafer, so as to separate a first semiconductor layer and a second semiconductor layer from the second wafer, wherein the second semiconductor layer is arranged between the peeling layer and the second oxide layer; and combining the first oxide layer with the second oxide layer, and removing the first semiconductor layer by using the peeling layer. By means of the preparation method for a semiconductor wafer provided in the embodiments of the present application, the problem of C pollution caused by SiC thermal oxidation is avoided, the quality of an SiC thermal oxide layer is improved, the number of interface defects of SiO₂/SiC are reduced, and the mobility of channel carriers is improved.

Description

Composite structure of semiconductor wafer, semiconductor wafer and its manufacturing method and application

This application is based on and claims the priority of the Chinese patent application with the application number 202110911403.1 and the invention title "Composite structure of semiconductor wafer, semiconductor wafer and its manufacturing method and application" submitted on August 10, 2021.

technical field

The present application relates to a silicon carbide wafer, in particular to a composite structure of a semiconductor wafer, a semiconductor wafer and its manufacturing method and application, and belongs to the field of third-generation semiconductor technology.

Background technique

The traditional SiC gate dielectric layer uses thermally oxidized SiO ₂ , due to the presence of C, the chemical reaction process in the thermal oxidation process of SiC is complicated, and by-products such as C, CO, and SiO will be produced during the thermal oxidation process, which seriously affects the SiO ₂ layer and SiO ₂ /SiC interface quality, which in turn makes the channel mobility of the prepared SiC MOSFET extremely low, it is difficult to exceed 20cm ² /Vs (while the bulk mobility of SiC can reach 900cm ² /Vs), so Due to the impurity defects generated in the thermal oxidation process, the channel performance of SiC MOSFET will be poor. Although its impact on devices with BV exceeding 1000 volts is small, it has a great impact on devices with lower voltages, and far exceeds its limit.

Some existing research uses a thin layer of thermal gate oxide to improve interface state defects, and then deposits other dielectrics such as aluminum oxide (Al ₂ O ₃ ) to form an Al ₂ O ₃ /SiO ₂ /SiC structure, but the Al ₂ O ₃ /SiC Leakage is significantly greater than SiO ₂ /SiC, and even a 1nm-thin SiO ₂ interlayer cannot significantly improve the gate leakage problem. Therefore, thermal oxidation impurities in SiC have a great impact on performance and long-term gate reliability.

For example, high-voltage MOSFETs require thick gate oxide to meet application requirements. As shown in Figure 1, the existing SiO ₂ dielectric is thermally oxidized on the basis of SiC epitaxy to form SiO ₂ . The by-products such as C element are less likely to combine with O ² to escape, so that C element remains in the SiO ₂ /SiC interface in the form of defects, and these defects significantly reduce the carrier mobility of the SiC channel, thereby causing High frequency performance degrades.

Contents of the invention

The main purpose of this application is to provide a compound structure of semiconductor wafer, semiconductor wafer and its manufacturing method and application, so as to overcome the deficiencies in the prior art.

In order to realize the aforementioned object of the invention, the technical solutions adopted in this application include:

The embodiment of the present application provides a method for preparing a semiconductor wafer, which includes:

thermally oxidizing SiC on the surface layer of the first wafer to form a first oxide layer;

A second oxide layer is formed on the surface of the second wafer, and a lift-off layer is formed at a selected depth in the second wafer, thereby separating the first semiconductor layer and the second semiconductor layer in the second wafer, the second semiconductor layer a layer disposed between the release layer and the second oxide layer;

The first oxide layer is combined with the second oxide layer, and the first semiconductor layer is removed using the lift-off layer.

Further, both the first oxide layer and the second oxide layer are silicon oxide layers.

Further, the preparation method specifically includes: contacting the oxygen source gas with the silicon carbide material at a temperature of 1200-1400°C to perform a thermal oxidation reaction, thereby forming a first oxide layer with a predetermined thickness on the surface of the silicon carbide material. The oxygen source gas includes oxygen, oxygen-containing gas or water vapor;

After the thermal oxidation reaction is finished, the temperature of the silicon carbide material is rapidly lowered to below 300°C.

Further, the thickness of the first oxide layer is greater than 0 and less than 20 angstroms.

Further, the thickness of the second oxide layer is more than 20 angstroms, preferably 20-2000 angstroms.

Further, the thickness of the second semiconductor layer is more than 200 angstroms, preferably 200-3000 angstroms.

Further, the first wafer includes a SiC substrate and a SiC epitaxial layer formed on the SiC substrate, and the first oxide layer is formed on the surface of the SiC epitaxial layer.

Further, the second wafer includes a silicon wafer.

Further, the second oxide layer is formed by thermal oxidation of the surface layer of the second wafer.

Further, the preparation method specifically includes: forming the peeling layer at a selected depth in the second wafer by means of hydrogen ion implantation.

Further, the preparation method specifically includes: integrating the first oxide layer and the second oxide layer by means of bonding.

Further, the preparation method further includes: after removing the first semiconductor layer, removing the peeling layer remaining on the second semiconductor layer; and/or, combining the removed first semiconductor layer The peeling layer above is removed, and then the first semiconductor layer is used as a donor wafer.

Further, the wafer preparation method further includes: after removing the first semiconductor layer, performing annealing treatment on the obtained semiconductor wafer, and the annealing treatment is carried out in any one of N ₂ , NO, N ₂ O It is carried out under the condition of gas atmosphere or mixed gas atmosphere formed by two or more gases, and the temperature of the annealing treatment is 900-1700° C. and the time is 5-15 hours.

The embodiment of the present application also provides a semiconductor wafer, which includes:

first wafer,

a first silicon oxide layer formed by SiC thermal oxidation of the surface layer of the first wafer,

second semiconductor layer,

forming a second silicon oxide layer on the second semiconductor layer,

Wherein, the first silicon oxide layer is combined with the second silicon oxide layer.

Further, the first silicon oxide layer is bonded together with the second silicon oxide layer.

Further, the thickness of the first silicon oxide layer is greater than 0 and less than 20 angstroms.

Further, the thickness of the second silicon oxide layer is more than 100 angstroms, preferably 100-2000 angstroms.

Further, the first wafer includes a SiC substrate and a SiC epitaxial layer formed on the SiC substrate, and the first silicon oxide layer is formed on the surface of the SiC epitaxial layer.

Further, the second silicon oxide layer is formed by thermally oxidizing the surface layer of the second semiconductor layer.

Further, the second semiconductor layer is obtained by separating from the second wafer.

Further, the second wafer includes a silicon wafer.

The embodiment of the present application also provides a compound structure of a semiconductor wafer, which includes the semiconductor wafer; wherein, a second silicon oxide layer is formed on the first surface of the second semiconductor layer, which is the same as the first surface. The opposite second surface is sequentially bonded with the release layer and the first semiconductor layer.

Further, the first semiconductor layer, the peeling layer, and the second semiconductor layer are all distributed in the second wafer, the second silicon oxide layer is formed on the surface of the first wafer, and the peeling layer is formed on the second wafer. at the set depth within the circle.

Further, the peeling layer is formed by performing hydrogen ion implantation on the second wafer.

The embodiment of the present application also provides the use of the semiconductor wafer or the composite structure of the semiconductor wafer in preparing a semiconductor chip.

Compared with the prior art, the advantages of the present application include:

1) The preparation method of a semiconductor wafer provided in the embodiment of the present application avoids the C pollution problem caused by SiC thermal oxidation, improves the quality of SiC thermal oxidation layer, reduces the interface defects of SiO ₂ /SiC, and improves The mobility of the semiconductor wafer channel carriers;

2) A semiconductor wafer preparation method provided in the embodiment of the present application provides a high-quality thermal silicon oxide gate dielectric layer for SiC;

3) In the method for preparing a semiconductor wafer provided in the embodiment of the present application, the remaining silicon layer after thinning can be directly combined with the thermally oxidized silicon gate dielectric layer, which has few defects and can be used to replace the polysilicon gate.

Description of drawings

Figure 1 is a schematic diagram of the structure and manufacturing principle of a traditional SiC wafer;

FIG. 2 is a schematic structural view of a silicon donor wafer provided in a typical implementation case of the present application;

Fig. 3 is a schematic structural diagram of a silicon carbide support wafer provided in a typical implementation case of the present application;

Fig. 4 is a schematic structural diagram of a silicon carbide wafer with high-quality thick gate oxide provided in a typical implementation case of the present application;

Fig. 5 is a schematic structural diagram of a SiC LDMOS device provided in a typical implementation case of the present application;

6a-6i are schematic diagrams of the fabrication process of a silicon carbide wafer with high-quality thick gate oxide provided in a typical implementation case of the present application;

Fig. 7 is a graph of the channel mobility of the SiC MOSFET device with a 10 angstrom thin gate oxide in Example 1 of the present application and the SiC MOSFET device with a 100 angstrom thick gate oxide in Comparative Example 1.

Detailed ways

In view of the deficiencies in the prior art, the inventor of the present case was able to propose the technical solution of the present application after long-term research and extensive practice. The technical solution, its implementation process and principle will be further explained as follows.

Silicon carbide is a third-generation semiconductor material with wide bandgap and high thermal conductivity. It is widely used in rail transit, new energy vehicles, power grids, aerospace, radar, microwave base stations and other fields, such as SiC MOSFET, SiC IGBT, SiC LDMOS , SiC VDMOS and other devices are widely used in high-voltage power conversion and power systems, and are mainly used to make power control units, inverters, DC-DC converters, power amplifiers, etc.

This application provides a method for manufacturing a high-quality gate oxide layer (gate oxide) on a SiC wafer. First, the SiC on the surface layer of the first wafer is thermally oxidized to form an extremely thin first oxide layer; and in the second A second oxide layer is formed on the surface of the wafer, and a peeling layer is formed at a selected depth in the second wafer, thereby separating the first semiconductor layer and the second semiconductor layer in the second wafer, and the second semiconductor layer is set between the lift-off layer and the second oxide layer; then combine the first oxide layer and the second oxide layer to form a thick gate oxide layer, and use the lift-off layer to remove the first semiconductor layer, thereby realizing Fabrication of high-quality gate oxide (gate oxide) on SiC wafers.

The preparation method provided in the embodiment of the present application can significantly improve the mobility of carriers at the SiC wafer interface, thereby significantly improving the high-frequency performance of SiC devices (MOSFET, IGBT, VDMOS, and LDMOS, etc.), providing the above-mentioned existing commercial applications. A wider space.

The preparation method of a silicon carbide wafer with high-quality thick gate oxide provided by this application greatly reduces the interface defects of SiO ₂ /SiC, improves the mobility of channel carriers, and thus improves the The high-frequency performance of the device prepared by the wafer; and, the preparation method can realize the arbitrary thickness of the _SiO2 dielectric layer in a large range, which solves the long-term reliability problem caused by the gate leakage problem and the gate high voltage; and , the preparation method can also use the existing silicon production line equipment to achieve large-scale mass production, which reduces the problems of industrialization and promotion of the preparation method.

The following will further explain the technical solution, its implementation process and principles in conjunction with the accompanying drawings and specific implementation cases. Unless otherwise specified, the epitaxy, thinning, polishing and other processes adopted in the embodiments of the present application can all be Use known to those skilled in the art.

The inventors of this case found that when the surface layer of SiC is oxidized by thermal oxidation, and the thickness of the formed _SiO2 layer is less than 20 angstroms, the gas flow and impurities below the _SiO2 layer can easily diffuse through the _SiO2 layer. , the by-products produced during the thermal oxidation process are not easy to remain in the SiO ₂ layer or the SiO ₂ /SiC interface, so that the SiO ₂ layer and the SiO ₂ /SiC interface are very clean, and the defect density can be controlled at 10 ¹¹ cm ^- Below ² , the carrier mobility can reach 300cm ² /Vs, or even higher.

The method for preparing a silicon carbide wafer with high-quality thick gate oxide provided in the embodiment of the present application is divided into several steps to produce a high-quality thick gate oxide SiO ₂ layer.

In a more specific embodiment, a method for preparing a silicon carbide wafer with high-quality thick gate oxide specifically includes the following steps:

1) The first _SiO2 layer (or the first thermally oxidized _SiO2 layer) with a thickness less than 20 angstroms is formed by thermal oxidation on the surface of the SiC wafer, and the SiC wafer after thermal oxidation treatment is called a supporting wafer or SiC supporting wafer, its structure is shown in Figure 2;

2) Form a second SiO ₂ layer (or referred to as the second thermal oxidation SiO 2 ) with a thickness of 600-1000 angstroms on _the surface of the silicon wafer by means of thermal oxidation or thin film deposition (such as chemical deposition and physical deposition, etc.) layer), and then implant hydrogen ions from the surface of the silicon wafer facing away from the second _SiO2 layer to form an ion implantation layer at a selected depth of the silicon wafer, and the ion implantation layer is used as a substrate for subsequent silicon wafers the peeled-off layer, the silicon wafer is referred to as a donor wafer or si donor wafer;

3) contacting the first _SiO2 layer of the SiC support wafer with the second _SiO2 layer of the Si donor wafer, and bonding the SiC support wafer and the Si donor wafer together by bonding, wherein the The first SiO ₂ layer and the second SiO ₂ layer are combined to form a thick gate oxide layer; then, at an ambient temperature of 400-600 ° C, part of the silicon wafer is removed from the H ⁺ injection layer (Smart Cut technology), so as to obtain 4 shows a silicon carbide wafer with high-quality thick gate oxide.

Specifically, in the embodiment of the present application, the method for thermally oxidizing the surface of the SiC wafer to form a first _SiO2 layer with a thickness less than 20 angstroms may include the following two methods:

In some more specific implementation cases, a method for thermal oxidation of the surface layer of a SiC wafer includes:

Put the SiC wafer into the reaction chamber;

Use the protective gas supply mechanism to input protective gas into the reaction chamber to isolate oxygen and water vapor, and then use the heating mechanism to quickly raise the temperature in the reaction chamber to 1200-1400 °C under the condition of maintaining the positive pressure of the reaction chamber to the environment, and then supply oxygen The source gas supply mechanism inputs oxygen source gas preheated to 1200-1400°C into the reaction chamber to carry out the thermal oxidation reaction;

After the thermal oxidation reaction is over, while keeping the temperature in the reaction chamber constant, stop inputting the oxygen source gas into the reaction chamber, and at the same time input the oxygen source gas preheated to 1200-1400°C into the reaction chamber through the protective gas supply mechanism. Protective gas to exhaust oxygen from the reaction chamber;

The heating of the reaction chamber is stopped, and the protective gas at room temperature is input into the reaction chamber by the protective gas supply mechanism, so as to rapidly cool down the SiC wafer to below 300°C.

Further, the protective gas includes nitrogen and/or inert gas, but is not limited thereto.

Further, the method specifically includes: keeping the pressure in the reaction chamber above 1.05 atm, increasing the temperature in the reaction chamber to 1200-1400° C. at a heating rate of 10-50° C./s.

Further, the method specifically includes: rapidly reducing the temperature of the SiC wafer to below 300° C. under vacuum conditions.

Further, the method specifically includes: rapidly reducing the temperature of the SiC wafer to below 300° C. at a cooling rate of 100-400° C./s.

Put the SiC wafer into the reaction chamber;

Vacuumize the reaction chamber with a vacuum generating mechanism to remove the air therein;

The SiC wafer is heated in a vacuum environment to rapidly increase its temperature to 1000-1400°C, and then an oxygen source gas preheated to 1000-1400°C is fed into the reaction chamber by an oxygen source supply mechanism to perform the above-mentioned thermal oxidation reaction;

After the thermal oxidation reaction is finished, while keeping the temperature in the reaction chamber constant, stop inputting the oxygen source gas into the reaction chamber, and simultaneously use the vacuum generating mechanism to evacuate the reaction chamber again;

The heating of the reaction chamber is stopped, and the cooling medium supply mechanism is used to input gas as a cooling medium into the reaction chamber, so as to quickly cool down the SiC wafer to below 300°C.

Further, the gas used as the cooling medium is a gas at room temperature.

Further, the gas used as the cooling medium includes any one or a combination of two or more of nitrogen monoxide, nitrogen and inert gases, but is not limited thereto.

Further, the method specifically includes raising the temperature in the reaction chamber to 1000-1400° C. at a rate of 10-50° C./s.

Further, the method specifically includes: rapidly cooling the SiC wafer to below 300° C. under vacuum conditions.

This application forms a layer of high-quality ultra-thin SiO ₂ on the SiC epitaxial interface, while the thick SiO ₂ is provided by the silicon donor wafer, and there is a remaining 200-3000 angstrom silicon layer on the surface of the donor wafer for the fabrication of gates. pole to replace the polysilicon gate; the remaining silicon donor wafer after stripping can be reused after CMP (polishing), called a new donor wafer.

Specifically, most of the thick gate oxide layer of the silicon carbide wafer obtained in this application is provided by the silicon donor wafer, while the ultra-thin _SiO2 at the interface is thermally oxidized by SiC itself, which ensures The thick gate oxide requirement for high-voltage applications is greatly reduced, and the defect density at the SiO ₂ /SiC interface is greatly reduced, thereby increasing the carrier mobility of the channel. The thermal oxidation of the silicon donor wafer and the final silicon peeling can be utilized Some silicon line equipment, so mass production can be achieved.

The silicon carbide wafer with high-quality thick gate oxide prepared in this application can be used to manufacture SiC MOSFET, SiC VDMOS, SiC LDMOS and SiC IGBT, etc.

Example 1

A method for preparing a silicon carbide wafer with high-quality thick gate oxide, specifically comprising the steps of:

1) Referring to Figure 6a, a silicon carbide wafer is provided, the silicon carbide wafer includes a silicon carbide substrate and a silicon carbide epitaxial layer stacked in sequence, and the surface layer of the silicon carbide epitaxial layer is oxidized to form a silicon carbide epitaxial layer by thermal oxidation treatment. a first silicon oxide layer with a layer thickness of 10 angstroms;

2) Referring to FIG. 6b, a silicon wafer is provided, and the surface layer of the silicon wafer is oxidized by thermal oxidation treatment to form a second silicon oxide layer with a thickness of 800 angstroms;

3) Referring to FIG. 6c, the silicon wafer is implanted with hydrogen ions from the side surface of the silicon wafer facing away from the second silicon oxide layer, and the implantation depth is 3000 angstroms, thereby forming hydrogen ion implantation inside the silicon wafer. layer, the hydrogen ion implantation layer separates the silicon wafer to form a first silicon layer and a second silicon layer, wherein the hydrogen ion implantation layer will be used as a peeling layer for peeling off a thick silicon wafer or a silicon wafer;

4) Referring to Figure 6d and Figure 6e, the silicon wafer processed in step 3) is used as the donor wafer, and the silicon carbide wafer processed in step 1) is used as the support wafer, the donor wafer is turned over and the second aligning the silicon oxide layer with the first silicon oxide layer, and then performing wafer bonding, so that the second silicon oxide layer is combined with the first silicon oxide layer to form a thick gate oxide layer;

5) Using Smart Cut technology, peel off the first silicon layer from the hydrogen ion implantation layer at 400-600°C, and separate to obtain the silicon donor wafer (ie, the first silicon layer and part of the hydrogen ion implantation layer) shown in Figure 6f and the SiC support wafer, followed by high-temperature rapid annealing of the separated SiC support wafer to remove residual hydrogen in the thick gate oxide layer, thereby improving the fusion degree of the interface between the first silicon oxide layer and the second silicon oxide layer, The remaining second silicon layer with a thickness of _200-3000 angstroms replaces polysilicon as _the gate. Carried out under the condition of mixed gas atmosphere, the temperature of the high-temperature rapid annealing is 900-1700°C, and the time is 5-15h;

6) Process the silicon donor wafer obtained in step 5) by means of chemical mechanical polishing (CMP) to obtain a silicon wafer as shown in Figure 6g, which can be reused as a donor wafer; chemical mechanical polishing ( CMP) and other methods to process the SiC support wafer obtained in step 5) to remove the hydrogen ion implantation layer remaining on the top peeled off surface to obtain a silicon carbide wafer as shown in Figure 6h, wherein the second silicon layer can be subsequently In the process of processing, it is processed into a gate. If the quality requirements of the device are not high, the CMP process can be omitted, and the silicide is directly generated to improve the resistivity of the gate;

7) As shown in FIG. 6i, patterning the second silicon layer on the top layer of the silicon carbide wafer by means of etching to form the gate of the silicon carbide device;

8) On the basis of the epitaxial structure formed in step 7, process and form the SiC-based enhanced RF LDMOS device as shown in Figure 5, wherein, 11 is a SiC-based P-type heavily doped substrate, and 12 is a SiC-based P-type epitaxy 21 is the SiC-based N-type drift region, 22 is the SiC-based N-type heavily doped source region, 23 is the SiC-based N-type heavily doped drain region, 25' is the SiC-based P-type well region, and 26 is the SiC-based P-type well region. 31 is the gate oxide layer, 32 is the silicon gate, 33 is the metal SiC compound used to connect the source region and the metal electrode of the source region, 34 is the side wall of the gate, 35 is the field plate, and 41 is the connection source The conductive channel between the pole and the substrate, in this example, is a tungsten plug via hole, 42 is the metal of the contact hole, 51 is the insulating dielectric layer, and 61 is the metal electrode.

A method for fabricating a SiC-based enhanced RF LDMOS device provided in an embodiment of the present application mainly includes: forming an N-type doped channel region, an offset region, a source region, and a drain region in a SiC-based P-type epitaxial layer The steps are as follows: use the method provided in the embodiment of the present application to obtain a SiC wafer, as shown in Figure 5, wherein the SiC-based p-type epitaxy 12 has a thickness of 2-20um, and the epitaxy is on the SiC heavily doped substrate 11, and the SiC The thickness of the gate oxide is 155 angstroms, and the thickness of the silicon layer is 3000 angstroms;

2) using photolithography and etching to form a silicon gate 32;

3) Implanting N-type into the SiC-based P-type lightly doped epitaxial layer 12 by photolithography and implantation to form a SiC-based N-type drift region;

4) Implanting P-type impurities into the SiC-based P-type lightly doped epitaxial layer 12 by photolithography and implantation to form a SiC-based P-type well region 25';

5) Implanting N-type impurities into the SiC-based P-type lightly doped epitaxial layer 12 by photolithography and implantation to form heavily doped SiC-based N-type heavily doped source regions 22 and SiC-based N-type heavily doped drain regions twenty three;

According to the test, compared with the Si LDMOS device, the heat transfer coefficient of the SiC LDMOS device is increased by 6 times, the breakdown voltage is increased by 6 times, and the carrier mobility is equivalent to that of the Si LDMOS device. Therefore, the SiC LDMOS device can be used in Working under higher voltage and higher frequency conditions, and SiC LDMOS devices have higher output power density, amplification efficiency and linearity, and have good heat dissipation performance, so that their thermal impact on the system will also be reduced to lowest.

Comparative example 1

The preparation method of a silicon carbide wafer with high-quality thick gate oxide in Comparative Example 1 is basically the same as that of Example 1, except that the surface layer of the silicon carbide epitaxial layer is oxidized by thermal oxidation treatment in Comparative Example 1. A first silicon oxide layer is formed with a thickness of 100 angstroms.

After testing, the channel mobility curves of SiC LDMOS devices with 10 angstrom thin gate oxide and 100 angstrom thick gate oxide are shown in Figure 7, and the electron mobility of SiC LDMOS devices in Example 1 and Comparative Example 1 are respectively 300cm ² /(VS) and from 58cm ² /(VS), which fully demonstrates that the thermally oxidized thin gate oxide at the silicon carbide interface is the key to forming high-quality, low-defect channels.

Comparative example 2

A method for preparing a silicon carbide wafer, as shown in Figure 1, directly adopts the traditional thermal oxidation method to oxidize the surface of the silicon carbide wafer to form a gate oxide layer with a thickness of 800 angstroms; however, in the In the traditional SiC thermal oxidation process, the following reactions inevitably occur: (a) SiC+O ₂ →SiO ₂ (s)+C(s); (b) SiC+O ₂ →SiO(g)+CO;

Both of these reactions will lead to channel interface defects. In the initial stage of SiC thermal oxidation, the typical oxide layer thickness is within 10 angstroms. C (carbon) and SiO (silicon monoxide) and these by-products can continue to reoxidize, C After being oxidized, it escapes from the SiC interface in gaseous form, and the defects are less formed at this stage. However, when the thermal oxidation continues until the gate oxide layer of 800 angstroms is formed, a large amount of C elements remain in the gate oxide, resulting in low quality of the gate oxide, and the channel carrier mobility is as low as 20cm ² /(VS), thus The high-frequency characteristics of devices manufactured on this basis are very poor.

Comparative example 3

The preparation method of the silicon carbide wafer in Comparative Example 3 is basically the same as that in Example, the difference being that step 1) of Comparative Example 3 is:

1) A silicon carbide wafer is provided, which includes a silicon carbide substrate and a silicon carbide epitaxial layer stacked in sequence, and the surface layer of the silicon carbide epitaxial layer is oxidized to form a layer with a thickness of 30 angstroms by thermal oxidation treatment. The first silicon oxide layer of m; After testing, the gate oxide layer obtained in Comparative Example 3 has low electron mobility, poor quality, and many defects, and the device performance is close to that obtained by the traditional method.

Comparative example 4

The preparation method of the silicon carbide wafer in Comparative Example 4 is basically the same as that in Example, the difference being that step 5) of Comparative Example 4 is: 5) Using Smart Cut technology, hydrogen ions are implanted from the layer at 400-600°C The silicon wafer is peeled off, and the silicon donor wafer and the SiC support wafer shown in FIG. 6f are separated, but the high-temperature rapid annealing treatment is not performed on the separated SiC support wafer. After testing, the gate oxide layer obtained in Comparative Example 4 has low electron mobility, poor quality, and many defects, and the device performance is close to that obtained by the traditional method.

It should be noted that the second _SiO2 layer in the embodiment of the present application can _be formed by a conventional thermal oxidation process, or can be formed by chemical deposition and physical deposition. Concrete limitation; In the embodiment of the present application, the method of hydrogen injection (Smart Cut) is mainly used for the stripping of the top silicon wafer. Of course, those skilled in the art can also use other silicon wafer stripping techniques to realize the stripping of the top silicon wafer, such as porous silicon The stripping technology, Sim Split (200810038335.7) technology, etc. are not specifically limited here.

The method for preparing a semiconductor wafer provided by the embodiment of the present application avoids the C pollution problem caused by SiC thermal oxidation, improves the quality of SiC thermal oxidation layer, reduces the interface defects of SiO ₂ /SiC, and improves the The mobility of the channel carriers; and, the method for preparing a semiconductor wafer provided by the embodiment of the present application provides a high-quality thermal silicon oxide gate dielectric layer for SiC.

In the method for preparing a semiconductor wafer provided in the embodiment of the present application, the remaining silicon layer after thinning treatment can be directly combined with the thermally oxidized silicon gate dielectric layer, which has few defects and can be used to replace the polysilicon gate.

It should be understood that the above-mentioned embodiments are only to illustrate the technical concept and features of the present application. The purpose is to enable those familiar with this technology to understand the content of the present application and implement it accordingly, and not to limit the protection scope of the present application. All equivalent changes or modifications made according to the spirit of the present application shall fall within the protection scope of the present application.

Claims

A method for preparing a semiconductor wafer, characterized in that it comprises:

thermally oxidizing SiC on the surface layer of the first wafer to form a first oxide layer;

A second oxide layer is formed on the surface of the second wafer, and a lift-off layer is formed at a selected depth in the second wafer, thereby separating the first semiconductor layer and the second semiconductor layer in the second wafer, the second semiconductor layer a layer disposed between the release layer and the second oxide layer;

The first oxide layer is combined with the second oxide layer, and the first semiconductor layer is removed using the lift-off layer.
The preparation method according to claim 1, characterized in that: both the first oxide layer and the second oxide layer are silicon oxide layers.
The preparation method according to claim 1, is characterized in that specifically comprising:

The oxygen source gas is contacted with the silicon carbide material at a temperature of 1200-1400° C. for a thermal oxidation reaction, thereby forming a first oxide layer with a predetermined thickness on the surface of the silicon carbide material. The oxygen source gas includes oxygen, oxygen-containing gas or water vapor;

After the thermal oxidation reaction is finished, the temperature of the silicon carbide material is rapidly lowered to below 300°C.
The preparation method according to claim 1 or 3, characterized in that: the thickness of the first oxide layer is greater than 0 and less than 20 angstroms.
The preparation method according to claim 1, characterized in that: the thickness of the second oxide layer is above 20 angstroms, preferably 20-2000 angstroms.
The preparation method according to claim 1, characterized in that: the thickness of the second semiconductor layer is more than 200 angstroms, preferably 200-3000 angstroms.
The manufacturing method according to claim 1, wherein the first wafer comprises a SiC substrate and a SiC epitaxial layer formed on the SiC substrate, and the first oxide layer is formed on the surface of the SiC epitaxial layer.
The manufacturing method according to claim 1, wherein the second wafer comprises a silicon wafer.
The preparation method according to claim 1 or 8, characterized in that: the second oxide layer is formed by thermal oxidation of the surface layer of the second wafer.
The preparation method according to claim 1, characterized in that it specifically comprises: forming the peeling layer at a selected depth in the second wafer by means of hydrogen ion implantation.
The preparation method according to claim 1, characterized in that it specifically comprises: combining the first oxide layer and the second oxide layer into one by bonding.
The preparation method according to claim 1, further comprising: after removing the first semiconductor layer, removing the peeling layer remaining on the second semiconductor layer; and/or, combining the removed removing the lift-off layer on the first semiconductor layer, and then using the first semiconductor layer as a donor wafer.
The wafer preparation method according to claim 1, further comprising: after removing the first semiconductor layer, performing annealing treatment on the obtained semiconductor wafer, and the annealing treatment is carried out under N 2 , NO, N 2 O The annealing treatment is carried out under the condition of any one gas atmosphere or a mixed gas atmosphere formed by two or more gases, and the temperature of the annealing treatment is 900-1700°C and the time is 5-15h.
A kind of semiconductor wafer is characterized in that comprising:

first wafer,

a first silicon oxide layer formed by SiC thermal oxidation of the surface layer of the first wafer,

second semiconductor layer,

forming a second silicon oxide layer on the second semiconductor layer,

Wherein the first silicon oxide layer is combined with the second silicon oxide layer.
The semiconductor wafer according to claim 14, wherein the first silicon oxide layer and the second silicon oxide layer are integrally bonded.
The semiconductor wafer according to claim 14, wherein the thickness of the first silicon oxide layer is greater than 0 and less than 20 angstroms.
The semiconductor wafer according to claim 14, wherein the thickness of the second silicon oxide layer is more than 100 angstroms, preferably 20-2000 angstroms.
The semiconductor wafer according to claim 14, characterized in that: the thickness of the second semiconductor layer is more than 200 angstroms, preferably 200-3000 angstroms.
The semiconductor wafer according to claim 14, wherein the first wafer comprises a SiC substrate and a SiC epitaxial layer formed on the SiC substrate, and the first silicon oxide layer is formed on the surface of the SiC epitaxial layer .
The semiconductor wafer according to claim 14, wherein the second silicon oxide layer is formed by thermally oxidizing the surface layer of the second semiconductor layer.
The semiconductor wafer according to claim 14, wherein the second semiconductor layer is separated from the second wafer.
The semiconductor wafer according to claim 14, wherein the second wafer comprises a silicon wafer.
A compound structure of a semiconductor wafer, characterized in that it comprises the semiconductor wafer described in any one of claims 14-22; wherein, a second silicon oxide layer is formed on the first surface of the second semiconductor layer, and The second surface opposite to the first surface is sequentially combined with a peeling layer and a first semiconductor layer.
The compound structure of semiconductor wafer according to claim 23, characterized in that: the first semiconductor layer, the peeling layer, and the second semiconductor layer are all distributed in the second wafer, and the second silicon oxide layer is formed on On the surface of the first wafer, the peeling layer is formed at a set depth in the second wafer.
The composite structure of semiconductor wafers according to claim 24, wherein the peeling layer is formed by performing hydrogen ion implantation on the second wafer.
Use of the semiconductor wafer described in any one of claims 14-22 or the compound structure of the semiconductor wafer described in any one of claims 23-25 in the preparation of semiconductor chips.