JPH09321323A - Silicon carbide substrate, manufacture thereof and silicon carbide semiconductor device using the same substrate - Google Patents

Silicon carbide substrate, manufacture thereof and silicon carbide semiconductor device using the same substrate

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Publication number
JPH09321323A
JPH09321323A JP8336511A JP33651196A JPH09321323A JP H09321323 A JPH09321323 A JP H09321323A JP 8336511 A JP8336511 A JP 8336511A JP 33651196 A JP33651196 A JP 33651196A JP H09321323 A JPH09321323 A JP H09321323A
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JP
Japan
Prior art keywords
silicon carbide
carbide semiconductor
semiconductor substrate
layer
base plate
Prior art date
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Granted
Application number
JP8336511A
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Japanese (ja)
Other versions
JP3230650B2 (en
Inventor
Ryuichi Asai
隆一 浅井
Tanio Urushiya
多二男 漆谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP33651196A priority Critical patent/JP3230650B2/en
Priority to DE19712796A priority patent/DE19712796B4/en
Publication of JPH09321323A publication Critical patent/JPH09321323A/en
Application granted granted Critical
Publication of JP3230650B2 publication Critical patent/JP3230650B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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    • H01L21/02378—Silicon carbide
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608—Silicon carbide

Abstract

PROBLEM TO BE SOLVED: To eliminate characteristic dispersion of a silicon carbide semiconductor device using a substrate having an epitaxially grown low-concn. silicon carbide layer on a silicon carbide base. SOLUTION: The surface of a silicon carbide base 1 is etched, a conductivity correcting layer 2 having the same conductivity type as that of the base 1 and approximately the same impurity concn. is laminated 3μm or more, and a low-concn. layer 3 is laminated thereon. Crystal defects from the base 1 stop from propagating in the conductivity correcting layer 2 to result in a low-concn. layer 3 which is good in crystallinity. In this layer 2, the influence of the crystal defects on the electric conductivity is masked by a doped high concn. impurity.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体素子を形成
する炭化けい素基板とその表面処理方法およびその炭化
けい素基板を用いた炭化けい素半導体素子に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silicon carbide substrate for forming a semiconductor device, a surface treatment method for the same, and a silicon carbide semiconductor device using the silicon carbide substrate.

【０００２】[0002]

【従来の技術】高周波、大電力の制御を目的として、シ
リコンを用いた電力用半導体素子（以下パワーデバイス
と称する）では、各種の工夫により高性能化が進められ
ている。しかし、パワーデバイスは高温や放射線等の存
在下で使用されることもあり、そのような条件下ではシ
リコンデバイスは使用できないこともある。また、シリ
コンのパワーデバイスより更に高性能のパワーデバイス
を求める声に対して、新しい材料の適用が検討されてい
る。例えば、炭化けい素は広い禁制帯幅（６Ｈ型で２．
９３Ｖ）をもつため、高温での電気伝導度の制御性や耐
放射線性に優れ、またシリコンより約１桁高い絶縁破壊
電圧をもつため、高耐圧デバイスへの適用が可能と見ら
れる。さらに、炭化けい素はシリコンの約２倍の電子飽
和ドリフト速度をもつので、高周波大電力制御にも適す
ると見られている。最近６Ｈ−や４Ｈ−炭化けい素の単
結晶が、かなり高品質で製造できるようになってきてい
る。これらは、閃亜鉛鉱型とウルツ鉱型とが積層された
形のアルファ相炭化けい素である。2. Description of the Related Art For the purpose of controlling high frequency and high power, a power semiconductor element using silicon (hereinafter referred to as a power device) has been improved in performance by various measures. However, the power device may be used in the presence of high temperature or radiation, and the silicon device may not be used under such conditions. In addition, application of new materials is being considered in response to the demand for higher performance power devices than silicon power devices. For example, silicon carbide has a wide bandgap (6H type 2.
Since it has a voltage of 93 V), it has excellent controllability of electric conductivity at high temperature and radiation resistance, and has a dielectric breakdown voltage approximately one digit higher than that of silicon, so that it can be applied to a high breakdown voltage device. Further, silicon carbide has an electron saturation drift velocity that is about twice that of silicon, and is therefore considered suitable for high frequency and high power control. Recently, single crystals of 6H- and 4H- silicon carbide have become able to be manufactured with considerably high quality. These are alpha-phase silicon carbide in the form of laminated zinc blende type and wurtzite type.

【０００３】しかし、このように材質的に優れた炭化け
い素でも、その優れた材料特性をパワーデバイスに応用
するためには、シリコンデバイスと同様に、炭化けい素
基板の表面を鏡面に仕上げた後、炭化けい素層をエピタ
キシャル成長させたり、ドナー不純物やアクセプタ不純
物をドーピングしたり、金属膜や酸化膜を形成する等の
工程が必要となる。However, in order to apply the excellent material characteristics to the power device even with silicon carbide excellent in material as described above, the surface of the silicon carbide substrate is mirror-finished like the silicon device. After that, steps such as epitaxially growing the silicon carbide layer, doping with a donor impurity or an acceptor impurity, and forming a metal film or an oxide film are required.

【０００４】[0004]

【発明が解決しようとする課題】ところで、炭化けい素
においては、シリコン基板と違って、不純物の拡散が起
き難く、特に拡散深さの深い拡散領域の形成は困難であ
る。そのため、エピタキシャル成長による層形成が多用
されている。パワーデバイスを指向する炭化けい素デバ
イスの基板としては、６Ｈ−ＳｉＣや、４Ｈ−ＳｉＣが
一般的に用いられている。電気伝導度の大きい（すなわ
ち高不純物濃度の）６Ｈ−ＳｉＣ単結晶の小片上に電気
伝導度の小さい（すなわち低不純物濃度の）層をエピタ
キシャル成長し、その層の表面にショットキー電極を設
けて、炭化けい素のショットキーダイオードを試作した
ところ、耐圧、漏れ電流、オン電圧等の特性が安定せ
ず、非常にばらつきが見られた。In silicon carbide, unlike a silicon substrate, it is difficult for impurities to diffuse, and it is particularly difficult to form a diffusion region having a large diffusion depth. Therefore, layer formation by epitaxial growth is often used. 6H-SiC or 4H-SiC is generally used as a substrate for a silicon carbide device oriented to a power device. A layer of low electrical conductivity (ie, low impurity concentration) is epitaxially grown on a small piece of 6H—SiC single crystal with high electrical conductivity (ie, high impurity concentration), and a Schottky electrode is provided on the surface of the layer. When a silicon carbide Schottky diode was prototyped, the characteristics such as withstand voltage, leakage current, and on-state voltage were not stable, and very wide variations were observed.

【０００５】不良原因調査のため点接触電流電圧法（以
下ＰＣＩＶ法と略す）により、ショットキーダイオード
の厚さ方向の電気伝導度の分布を測定した。その測定結
果を図２に示す。図から、成長層の厚さ方向に電気伝導
度の分布があることがわかる。すなわち、炭化けい素下
地板１とエピタキシャル成長層１０との界面付近で、、
電気伝導度が次第に低下する領域がある。このような分
布が現れる原因として以下のものを挙げることができ
る。To investigate the cause of defects, the electrical conductivity distribution in the thickness direction of the Schottky diode was measured by the point contact current-voltage method (hereinafter abbreviated as PCIV method). FIG. 2 shows the measurement results. From the figure, it can be seen that there is a distribution of electric conductivity in the thickness direction of the growth layer. That is, near the interface between the silicon carbide base plate 1 and the epitaxial growth layer 10,
There is a region where the electrical conductivity gradually decreases. The following can be mentioned as a cause of such a distribution.

【０００６】エピタキシャル成長に用いられる下地板用
の炭化けい素単結晶の結晶性は現状ではシリコン基板に
遠く及ばず、積層欠陥をはじめとする結晶欠陥や表面不
完全層を多く含んでいる。また欠陥の面内分布がかなり
大きいことも観察されている。そのような炭化けい素単
結晶を下地板として気相成長をするため、下地板上に成
長するエピタキシャル成長層にも下地板の結晶欠陥が引
き継がれ、電気伝導度の分布となって現れていると考え
られる。炭化けい素下地板とエピタキシャル成長層との
界面に近い部分は、ドーピングされた不純物量は少な
く、本来電気伝導度が小さいはずであるが、多数の結晶
欠陥のため電気伝導度が大きくなっているのである。こ
のような、厚さ方向の伝導度分布によって、ショットキ
ーデバイスの半導体デバイス特性にバラツキを生じたも
のと考えられる。下地板の結晶性の改善や、成膜プロセ
スの改良のためには、日々努力が払われているが、今の
ところこの分布を解消できる方法はない。At present, the crystallinity of a silicon carbide single crystal for a base plate used for epitaxial growth is far inferior to that of a silicon substrate, and contains many crystal defects such as stacking faults and surface imperfect layers. It has also been observed that the in-plane distribution of defects is quite large. Since vapor phase growth is performed using such a silicon carbide single crystal as a base plate, the crystal defects of the base plate are inherited in the epitaxial growth layer grown on the base plate, and the electric conductivity distribution appears. Conceivable. The portion near the interface between the silicon carbide base plate and the epitaxial growth layer has a small amount of doped impurities and should have a low electrical conductivity, but the electrical conductivity is high due to many crystal defects. is there. It is considered that such a conductivity distribution in the thickness direction causes variations in the semiconductor device characteristics of the Schottky device. Although efforts are being made every day to improve the crystallinity of the base plate and the film forming process, there is currently no method for eliminating this distribution.

【０００７】以上の問題に鑑みて本発明の目的は、電気
伝導度の厚さ方向の分布の影響を解消するように炭化け
い素下地板上にエピタキシャル成長した炭化けい素基板
とその製造方法、およびその基板を使用して特性の安定
した炭化けい素半導体素子を提供することにある。In view of the above problems, an object of the present invention is to provide a silicon carbide substrate epitaxially grown on a silicon carbide base plate so as to eliminate the influence of the distribution of electrical conductivity in the thickness direction, and a method for manufacturing the same. The substrate is used to provide a silicon carbide semiconductor device having stable characteristics.

【０００８】[0008]

【課題を解決するための手段】上記課題を解決するため
に、本発明の炭化けい素半導体基板は、炭化けい素単結
晶の下地板上に、下地板と同じ導電型で、結晶欠陥の影
響をマスクする程高濃度の不純物を含んだ炭化けい素の
伝導度矯正層および下地板より電気伝導度の小さい炭化
けい素の低濃度層をエピタキシャル成長したものとす
る。In order to solve the above problems, a silicon carbide semiconductor substrate of the present invention is provided on a silicon carbide single crystal base plate having the same conductivity type as that of the base plate and being affected by crystal defects. It is assumed that the conductivity correction layer of silicon carbide containing a high concentration of impurities so as to mask and the low concentration layer of silicon carbide having an electric conductivity smaller than that of the base plate are epitaxially grown.

【０００９】そのようにすれば、伝導度矯正層のドープ
した不純物の電気伝導度への寄与が、欠陥によるものよ
り圧倒的に大きく、従来見られたような欠陥の伝播によ
る電気伝導度の分布は解消される。特に、炭化けい素基
板がアルファ相炭化けい素単結晶でであるものとする。
アルファ相炭化けい素であれば、結晶性の良い単結晶が
比較的容易に得られ、＜０００１＞方向は、キャリアの
移動度が大きい。By doing so, the contribution of the doped impurities of the conductivity straightening layer to the electric conductivity is overwhelmingly larger than that due to the defect, and the distribution of the electric conductivity due to the propagation of the defect as conventionally seen. Is eliminated. In particular, it is assumed that the silicon carbide substrate is an alpha phase silicon carbide single crystal.
With alpha-phase silicon carbide, a single crystal with good crystallinity can be obtained relatively easily, and the carrier mobility is high in the <0001> direction.

【００１０】そして、エピタキシャル成長をおこなう下
地面が（０００１）けい素面から＜１１、−２、０＞方
向へ３度以上オフ研磨された面、または（０００、−
１）炭素面から＜１１、−２、０＞方向へ３度以上オフ
研磨された面であるものとする。（０００１）けい素面
または（０００、−１）炭素面から＜１１、−２、０＞
方向へ３度以上オフ研磨された面であれば、結晶面間の
ステップが多く、エピタキシャル成長し易い。The underlying surface for epitaxial growth is off-polished from the (0001) silicon surface in the <11, -2, 0> direction three or more times, or (000,-).
1) A surface that has been off-polished 3 or more times in the <11, -2, 0> direction from the carbon surface. From (0001) silicon surface or (000, -1) carbon surface <11, -2, 0>
If the surface is off-polished 3 times or more in the direction, there are many steps between crystal planes, and epitaxial growth is easy.

【００１１】更に、伝導度矯正層の不純物濃度が１×１
０18ｃｍ-3以上であるものとする。また、伝導度矯正層
が、下地板とほぼ同じ電気伝導度をもつものでもよい。
そのような不純物濃度、電気伝導度であれば、結晶欠陥
の影響が不純物によってマスクされる。そして、伝導度
矯正層の厚さが３μｍ以上であることが重要である。Further, the impurity concentration of the conductivity straightening layer is 1 × 1.
It should be 0 18 cm -3 or more. Further, the conductivity correction layer may have substantially the same electric conductivity as that of the base plate.
With such impurity concentration and electric conductivity, the influence of crystal defects is masked by the impurities. Then, it is important that the thickness of the conductivity correction layer is 3 μm or more.

【００１２】伝導度矯正層の厚さが厚いため、結晶欠陥
の伝播が伝導度矯正層内で止まり、その上に成長した炭
化けい素結晶膜は、結晶性がよくなる。伝導度矯正層お
よび低濃度層を炭化けい素基板の製造方法としては、ま
ず、エピタキシャル成長前の下地板の表面層を、０．５
〜１０μｍ除去することが重要である。Since the thickness of the conductivity straightening layer is large, the propagation of crystal defects is stopped in the conductivity straightening layer, and the silicon carbide crystal film grown thereon has good crystallinity. As a method for manufacturing the silicon carbide substrate with the conductivity correcting layer and the low concentration layer, first, the surface layer of the base plate before the epitaxial growth is changed to 0.5.
It is important to remove 10 μm.

【００１３】炭化けい素半導体基板の表面状態の分布を
小さくするため第一段階として、市販の下地板にはμｍ
オーダーの研磨キズが残っているので、これをまず取り
除く。上記研磨キズを消すため、取り除く表面厚さは
０．５〜１０μｍ必要である。０．５μｍ未満では不十
分であり、１０μｍ超過では無駄である。表面層除去の
方法としては、例えば、直径が１μｍ以下の研磨砥粒の
ダイヤモンドペーストにより鏡面研磨する方法がある。
１μｍ以上の研磨砥粒では、傷が消えない。In order to reduce the distribution of the surface state of the silicon carbide semiconductor substrate, the first step is to add μm to a commercially available base plate.
The polishing scratches on the order remain, so remove them first. In order to eliminate the polishing scratches, the surface thickness to be removed needs to be 0.5 to 10 μm. If it is less than 0.5 μm, it is insufficient, and if it exceeds 10 μm, it is useless. As a method of removing the surface layer, for example, there is a method of mirror-polishing with a diamond paste of abrasive grains having a diameter of 1 μm or less.
The scratches will not disappear with abrasive grains of 1 μm or more.

【００１４】他の方法としては、ふっ素を含む反応性ガ
スと酸素またはアルゴンの混合ガス中において、例え
ば、ガスの全圧力は１〜１００Ｐａ、時間は５〜３０
分、パワーは１〜１０Ｗ・ｃｍ-2なる条件の反応性イオ
ンエッチングにより除去することもできる。このような
条件で０．５〜１０μｍの表面層が除去できる。更に、
他の方法として、ドライまたはウェットの雰囲気におい
て１０００〜１３００℃に加熱して、下地板上に厚さ１
μｍ以上の酸化けい素膜を形成し、その酸化膜をエッチ
ング除去する方法でもよい。As another method, in a mixed gas of a reactive gas containing fluorine and oxygen or argon, for example, the total gas pressure is 1 to 100 Pa, and the time is 5 to 30.
The power can also be removed by reactive ion etching under the condition that the power is 1 to 10 W · cm −2 . Under such conditions, the surface layer of 0.5 to 10 μm can be removed. Furthermore,
As another method, it is heated to 1000 to 1300 ° C. in a dry or wet atmosphere and the thickness of 1
A method of forming a silicon oxide film having a thickness of μm or more and removing the oxide film by etching may be used.

【００１５】ある厚さの酸化けい素膜を形成すれば、そ
の約１／２の厚さの炭化けい素が消費される。従って、
１μｍの酸化けい素膜を形成すれば、０．５μｍ以上の
表面層が除去されたことになる。１０００℃未満の温度
での酸化速度は非常に遅く、実用的でない。１３００℃
超過の温度での酸化は、容器、治具類として用いる石英
が軟化してしまう。When a silicon oxide film having a certain thickness is formed, about half that thickness of silicon carbide is consumed. Therefore,
If the silicon oxide film of 1 μm is formed, the surface layer of 0.5 μm or more is removed. The oxidation rate at temperatures below 1000 ° C. is very slow and not practical. 1300 ° C
Oxidation at excessive temperatures softens the quartz used as containers and jigs.

【００１６】最終的な表面仕上げの方法としては、基板
の被成長面をＨ2 希釈したＨＣｌ濃度が０．１〜５％の
雰囲気中で１２００〜１５００℃に加熱し、１〜３０分
間気相エッチングして０．１μｍ以上エッチングするの
がよい。炭化けい素の（０００１）けい素面と（００
０、−１）炭素面ではエッチング材に対する性質が異な
るためそれぞれの面で違う方法を用いなければならな
い。この方法は、エピタキシャル成長直前の基板処理法
として、（０００１）けい素面に対して有効な方法であ
ると言われた［特開平７−６９７１号公報参照］が、本
発明者らの実験によれば、むしろ成長面が（０００、−
１）炭素面である場合に有効な方法であって、表面不完
全層を取り除き原子オーダーの平坦面が得られる。０．
１％未満のＨＣｌ濃度や１２００℃未満の温度では、エ
ッチングをおこなえない。また５％を越える濃度や１５
００℃を越える温度では、下地板を不均一にエッチング
し、表面を粗面にしてしまう。As a final surface finishing method, the growth surface of the substrate is heated to 1200 to 1500 ° C. in an atmosphere of H 2 diluted HCl concentration of 0.1 to 5%, and vapor phase is applied for 1 to 30 minutes. It is advisable to etch to 0.1 μm or more. (0001) silicon surface of silicon carbide and (00)
Since 0, -1) carbon faces have different properties with respect to etching materials, different methods must be used for each face. This method was said to be effective for the (0001) silicon surface as a substrate processing method immediately before epitaxial growth [see Japanese Patent Laid-Open No. 7-6971], but according to the experiments by the inventors, Rather, the growth side is (000,-
1) This method is effective when the surface is a carbon surface, and an incomplete surface layer is removed to obtain an atomically flat surface. 0.
When the HCl concentration is less than 1% or the temperature is less than 1200 ° C., etching cannot be performed. Also, if the concentration exceeds 5% or 15
If the temperature exceeds 00 ° C, the base plate is unevenly etched and the surface is roughened.

【００１７】別の最終的な表面仕上げの方法としては、
基板の被処理面をＨ2 雰囲気中で１５００〜１７００℃
の間で加熱し、５〜９０分間気相エッチングして０．１
μｍ以上エッチングしてもよい。この方法は、特に成長
面が（０００１）けい素面である場合に有効な方法であ
る。［例えば、Hallin, C. 他：Inst. Phys. Conf. Se
r. No.142: p.613 (1996) 参照] 上記のような炭化けい素基板を用いた炭化けい素半導体
素子では、従来見られたような欠陥の伝播による電気伝
導度の分布はほとんど解消される。また伝導度矯正層表
面は処理を施した基板表面よりもさらに結晶性がよくな
っており、この面上に成長する低濃度層内の伝導度分布
は安定したものとなる。また同一ウェハ上から作製した
デバイス間のばらつきも小さくなる。As another final surface finishing method,
The surface to be processed of the substrate is 1500 to 1700 ° C. in an H 2 atmosphere.
And then vapor-etching for 5 to 90 minutes to 0.1.
You may etch by more than μm. This method is particularly effective when the growth surface is a (0001) silicon surface. [For example, Hallin, C. et al .: Inst. Phys. Conf. Se
r. No. 142: p. 613 (1996)] In the silicon carbide semiconductor device using the silicon carbide substrate as described above, the electric conductivity distribution due to the propagation of defects, which has been conventionally observed, is almost eliminated. To be done. Further, the surface of the conductivity straightening layer has better crystallinity than the surface of the substrate subjected to the treatment, and the conductivity distribution in the low concentration layer grown on this surface becomes stable. Further, variations among devices manufactured on the same wafer are reduced.

【００１８】半導体素子としては、二つの主電極が、炭
化けい素半導体基板の対向する面上に設けられているも
の特に、低濃度層上にシヨットキー電極を形成したショ
ットキーダイオード、低濃度層の表面層に下地板と逆導
電型の拡散領域を形成した接合型ダイオードとする。そ
のようないわゆる縦型の半導体素子では、空乏層が炭化
けい素単結晶基板の厚さ方向に延び、また電流は主面に
対して垂直方向に流れ、下地板と成長層との界面を通過
する。従ってその方向の電気伝導度に分布があると、そ
の影響を受けやすい半導体素子であったが、電気伝導度
の分布が解消され、特性が安定する。As a semiconductor device, two main electrodes are provided on opposite surfaces of a silicon carbide semiconductor substrate, particularly, a Schottky diode having a Schottky key electrode formed on a low concentration layer and a low concentration layer. A junction type diode having a diffusion layer of a conductivity type opposite to that of the base plate is formed on the surface layer. In such a so-called vertical semiconductor device, the depletion layer extends in the thickness direction of the silicon carbide single crystal substrate, and the current flows in the direction perpendicular to the main surface, passing through the interface between the base plate and the growth layer. To do. Therefore, if the electric conductivity in that direction has a distribution, the semiconductor element is susceptible to the influence, but the distribution of the electric conductivity is eliminated and the characteristics are stabilized.

【００１９】[0019]

【発明の実施の形態】上記課題解決のため本発明は、下
地基板となる炭化けい素単結晶に表面処理を施し、この
下地基板上にエピタキシャル成長した成長層が、下地板
と同じ導電型で、例えば、不純物濃度が１×１０18ｃｍ
-3以上というように下地板から伝播する結晶欠陥の影響
をマスクする程高濃度の不純物を含んだ炭化けい素の伝
導度矯正層および下地板より電気伝導度の小さい炭化け
い素の低濃度層とからなる炭化けい素成長層を積層した
炭化けい素基板を使用するものである。BEST MODE FOR CARRYING OUT THE INVENTION In order to solve the above problems, the present invention applies a surface treatment to a silicon carbide single crystal as a base substrate, and a growth layer epitaxially grown on the base substrate has the same conductivity type as that of the base plate. For example, the impurity concentration is 1 × 10 18 cm
-3 or more, such as a conductivity correction layer of silicon carbide containing a high concentration of impurities that masks the effect of crystal defects propagating from the base plate and a low concentration layer of silicon carbide having a lower electrical conductivity than the base plate. A silicon carbide substrate is used in which a silicon carbide growth layer consisting of and is laminated.

【００２０】以下図面を参照しながら本発明の実施例を
説明する。 ［実施例１］本発明第一の実施例のショットキーダイオ
ードの断面を図３に示す。導電型はｎ型で、不純物濃度
が１×１０18ｃｍ-3の６Ｈ型炭化けい素単結晶の下地板
１の上に、ｎ型で不純物濃度が１×１０18ｃｍ-3、厚さ
５μｍの高濃度層（以下、この層を伝導度矯正層２と呼
ぶ）および、ｎ型で不純物濃度が１×１０ 16ｃｍ-3、厚
さ５μｍの低濃度層３が積層されている。４は下地板１
の裏面に蒸着したオーミック電極、５は金蒸着膜のショ
ットキー電極である。Embodiments of the present invention will now be described with reference to the drawings.
explain. [Embodiment 1] The Schottky dio of the first embodiment of the present invention.
The cross section of the cord is shown in FIG. The conductivity type is n-type and the impurity concentration
Is 1 × 1018cm-36H type silicon carbide single crystal base plate
1 and n-type with an impurity concentration of 1 × 1018cm-3,thickness
High-concentration layer of 5 μm (hereinafter, this layer is referred to as conductivity correction layer 2)
B) and n-type with an impurity concentration of 1 × 10 16cm-3, Thick
A low-concentration layer 3 having a thickness of 5 μm is laminated. 4 is a base plate 1
The ohmic electrode 5 deposited on the back surface of the
It is a key electrode.

【００２１】このショットキーダイオードの製造方法を
以下に述べる。伝導度矯正層２および低濃度層３の成長
方法は熱気相成長法である。まず、研磨された６Ｈ型炭
化けい素単結晶の下地板１を用意する。下地板１はダイ
サーにより５ｍｍ角のチップに切り分ける。本実施例で
は、（０００１）けい素面から＜１１、−２、０＞方向
に約３．５度傾けて研磨した面を使用した。砥粒径が１
μｍのダイヤモンドペーストを用いてバフで鏡面研磨し
た後、下地板１の表面を有機溶剤洗浄と酸洗浄とで清浄
にする。A method of manufacturing this Schottky diode will be described below. The growth method of the conductivity correction layer 2 and the low-concentration layer 3 is a thermal vapor deposition method. First, a ground plate 1 of polished 6H-type silicon carbide single crystal is prepared. The base plate 1 is cut into 5 mm square chips by a dicer. In this example, a surface polished by being inclined by about 3.5 degrees in the <11, -2, 0> direction from the (0001) silicon surface was used. Abrasive grain size is 1
After mirror polishing with a buff using a diamond paste of μm, the surface of the base plate 1 is cleaned by organic solvent cleaning and acid cleaning.

【００２２】次にエピタキシャル成長する（０００１）
けい素面（正確にはその３．５度のオフアングル面）を
上にして下地板１を、炭化けい素で被覆した黒鉛のサセ
プタに載せる。下地板１を載せたサセプタを気相成長装
置の反応管内に挿入し、１Ｐａ以下の真空に引く。そし
て、１３００℃に加熱し、水素ガスと塩化水素ガスとが
それぞれ毎分１Ｌ、３ｍＬの流量の混合ガスを流して、
下地板１の表面を５分間エッチングする。サセプタの加
熱法は高周波誘導加熱である。Next, epitaxial growth is performed (0001)
The base plate 1 is placed on a graphite susceptor coated with silicon carbide with the silicon surface (more precisely, its 3.5-degree off-angle surface) facing up. The susceptor on which the base plate 1 is placed is inserted into the reaction tube of the vapor phase growth apparatus, and a vacuum of 1 Pa or less is drawn. Then, the mixture is heated to 1300 ° C., and a mixed gas of hydrogen gas and hydrogen chloride gas at a flow rate of 1 L / min and 3 mL / min, respectively,
The surface of the base plate 1 is etched for 5 minutes. The heating method for the susceptor is high frequency induction heating.

【００２３】続いて１５００℃に加熱して、水素ガス、
モノシランガス、プロパンガスと窒素ガスがそれぞれ毎
分３Ｌ、０．３ｍＬ、０．２５ｍＬ、０．２ｍＬの流量
の混合ガスを２時間流す。すると、下地板１上に６Ｈ型
炭化けい素の伝導度矯正層２がエピタキシャル成長す
る。伝導度矯正層２の膜厚は５μｍである。続いて低濃
度層の成長をおこなうが、その前にいったん試料を反応
管より取り出し、治具等を交換する。下地板１の洗浄を
おこない、伝導度矯正層を成膜した場合と同じ方法で気
相エッチングをして熱気相成長をする。１５００℃で水
素ガス、モノシランガス、プロパンガス、チッソガスが
それぞれ毎分３Ｌ、０．３ｍＬ、０．２５ｍＬ、０．０
０２ｍＬの流量の混合ガスを１時間流す。すると、６Ｈ
型炭化けい素の低濃度層３が、エピタキシャル成長す
る。低濃度層３の膜厚は２．５μｍである。Subsequently, it is heated to 1500 ° C. and hydrogen gas,
A mixed gas of monosilane gas, propane gas, and nitrogen gas at a flow rate of 3 L / min, 0.3 mL, 0.25 mL, and 0.2 mL per minute is flowed for 2 hours. Then, the conductivity-correcting layer 2 of 6H-type silicon carbide is epitaxially grown on the base plate 1. The film thickness of the conductivity correction layer 2 is 5 μm. Subsequently, the low-concentration layer is grown, but before that, the sample is once taken out from the reaction tube and the jig or the like is exchanged. The base plate 1 is washed, and vapor phase etching is performed by the same method as in the case of forming the conductivity straightening layer to perform hot vapor phase growth. Hydrogen gas, monosilane gas, propane gas, and nitrogen gas at 1500 ° C. are 3 L, 0.3 mL, 0.25 mL, and 0.0 L / min, respectively.
Flow the mixed gas with a flow rate of 02 mL for 1 hour. Then 6H
The low-concentration layer 3 of type silicon carbide is epitaxially grown. The film thickness of the low concentration layer 3 is 2.5 μm.

【００２４】次に、電極を形成する。基板の裏面すなわ
ち（０００、−１）炭素面にニッケルを２００ｎｍの厚
さになるように真空蒸着し、アルゴン雰囲気中におい
て、１２００℃で１０分間、加熱処理をおこなって、オ
ーミックなカソード電極４とする。それから、（０００
１）けい素面に厚さが２００ｎｍ、直径が２００μｍと
なるように金を真空蒸着し、ショットキー電極５とす
る。Next, electrodes are formed. Nickel was vacuum-deposited to a thickness of 200 nm on the back surface of the substrate, that is, the (000, −1) carbon surface, and heat-treated at 1200 ° C. for 10 minutes in an argon atmosphere to form an ohmic cathode electrode 4. To do. Then (000
1) Gold is vacuum-deposited on the silicon surface so as to have a thickness of 200 nm and a diameter of 200 μm to form a Schottky electrode 5.

【００２５】図１は、上記方法で作製したショットキー
ダイオードの炭化けい素基板のＰＣＩＶ測定の結果であ
る。伝導度矯正層２の電気伝導度が下地板１のそれとほ
ぼ同じであり厚さ方向の分布がないことがわかる。これ
は、伝導度矯正層２にドープされた窒素原子の濃度が高
いためである。すなわち、窒素原子の濃度が１×１０ 18
ｃｍ-3程度あれば、結晶欠陥の影響をマスクできる程多
いと思われる。低濃度側の限界は厳密に調べたわけでは
ないが、一つの目安としては、下地板と同じ不純物濃度
が基準になるであろう。FIG. 1 shows a Schottky manufactured by the above method.
It is the result of the PCIV measurement of the silicon carbide substrate of the diode.
You. The electric conductivity of the conductivity correction layer 2 is almost the same as that of the base plate 1.
It can be seen that they are almost the same and there is no distribution in the thickness direction. this
Has a high concentration of nitrogen atoms doped in the conductivity correction layer 2.
This is because That is, the concentration of nitrogen atoms is 1 × 10 18
cm-3If the degree is large enough, the effect of crystal defects can be masked.
I think it is. The limit on the low concentration side was not strictly investigated
There is no, but one guideline is the same impurity concentration as the base plate.
Will be the standard.

【００２６】また、伝導度矯正層２と低濃度層３の界面
で急峻に変化しているが、これは、下地板１からの結晶
欠陥の伝播が、５μｍの伝導度矯正層２内でほぼ終わっ
ているためと考えられる。追加実験によれば、高濃度に
ドープされた伝導度矯正層２を４μｍ以上堆積すれば、
低濃度層３は下地板１の結晶欠陥の影響が避けられるこ
とがわかった。Further, there is a sharp change at the interface between the conductivity-correcting layer 2 and the low-concentration layer 3, which means that the propagation of crystal defects from the base plate 1 is almost within the conductivity-correcting layer 2 of 5 μm. It seems that it is over. According to additional experiments, if the highly doped conductivity correction layer 2 is deposited to a thickness of 4 μm or more,
It was found that the low-concentration layer 3 can avoid the influence of crystal defects of the base plate 1.

【００２７】以上の方法により得られたショットキーダ
イオードの逆方向耐圧特性は、室温で均一に５００Ｖ以
上あり、５００Ｖ印加時の漏れ電流は約１０ｍＡ・ｃｍ
-2であった。これは、低濃度層３の厚さとそのキャリア
濃度から得られる理論耐圧とほぼ等しい値である。 ［実施例２］実施例１の方法で、同一ロットのウェハ
（３０ｍｍφ）から切り出した多数の炭化けい素小片
（５ｍｍ角）を用いてショットキーダイオードを試作し
たところ、半導体素子特性にばらつきが見出される場合
があった。この原因は炭化けい素下地板の表面状態の不
均一性、すなわち平坦性や結晶性の分布によると考え、
前処理法を改良した方法を試みた。The reverse breakdown voltage characteristic of the Schottky diode obtained by the above method is uniformly 500 V or more at room temperature, and the leakage current when 500 V is applied is about 10 mA.cm.
It was -2 . This is a value approximately equal to the theoretical breakdown voltage obtained from the thickness of the low concentration layer 3 and its carrier concentration. [Example 2] A method of Example 1 was used to fabricate a Schottky diode by using a large number of silicon carbide small pieces (5 mm square) cut out from a wafer (30 mmφ) of the same lot. There were cases where It is thought that the cause is non-uniformity of the surface state of the silicon carbide base plate, that is, the distribution of flatness and crystallinity,
An improved pretreatment method was tried.

【００２８】上記の実施例１の素子作製では、下地板１
の被成長面を、１μｍのダイヤモンドペーストを用いて
バフ研磨し、有機溶剤洗浄と酸洗浄とで清浄にした後、
気相エッチングを経て熱気相成長をおこなったが、本実
施例では、研磨処理した後、更に表面不完全層を取り除
くため、下地板１表面の反応性イオンエッチング（以下
ＲＩＥ）と熱酸化をおこなった。ＲＩＥは例えば８３％
の四フッ化炭素（ＣＦ 4 ）と１７％の酸素（Ｏ2 ）との
混合ガスを用い、圧力を約５Ｐａ、パワーを２Ｗ・ｃｍ
-2、時間を２０分とした。（０００１）けい素面をその
まま酸化すると、表面に凹凸を生じるので、その前に上
記のようにＲＩＥをおこなった方がよい。下地板１の熱
酸化の条件は１２００℃×２５時間のウェット酸化であ
る。このとき、酸化けい素膜の厚さは、約１μｍにな
る。更に有機溶剤洗浄と酸洗浄で清浄にする。酸洗浄で
はふっ酸処理を含み、上記の酸化膜がエッチング除去さ
れる。In the device fabrication of Example 1 above, the base plate 1
The surface to be grown on with 1 μm diamond paste
After buffing and cleaning with organic solvent cleaning and acid cleaning,
Thermal vapor deposition was performed after vapor phase etching.
In the example, after the polishing treatment, the incomplete surface layer was further removed.
In order to save power, reactive ion etching (below)
RIE) and thermal oxidation. RIE is, for example, 83%
Carbon tetrafluoride (CF Four) And 17% oxygen (OTwo) With
Using mixed gas, pressure about 5Pa, power 2W · cm
-2The time was 20 minutes. The (0001) silicon surface
If it is oxidized as it is, unevenness will occur on the surface.
It is better to perform RIE as described above. Heat of base plate 1
The oxidation conditions are wet oxidation at 1200 ° C. for 25 hours.
You. At this time, the thickness of the silicon oxide film is about 1 μm.
You. Further, clean with organic solvent cleaning and acid cleaning. With acid wash
Includes hydrofluoric acid treatment and the above oxide film is removed by etching.
It is.

【００２９】次にエピタキシャル成長する（０００１）
けい素面（正確にはその３．５度のオフアングル面）を
上にして下地板１を、炭化けい素で被覆した黒鉛のサセ
プタにのせる。下地基板１を載せたサセプタを気相成長
装置の反応管内に挿入し、１Ｐａ以下の真空に引く。そ
して下地板１上に生じた自然酸化膜を取り除くため気相
エッチングをおこなう。ここでは水素ガスを毎分１Ｌの
流量で流しながら１６００℃で３０分間加熱する。サセ
プタの加熱法は高周波誘導加熱である。後述する（００
０、−１）炭素面の場合のように、塩化水素を添加する
と、表面に凹凸を生じるので、水素のみを使用する。Next, epitaxial growth is performed (0001).
The base plate 1 is placed on a graphite susceptor coated with silicon carbide with the silicon surface (to be exact, an off-angle surface of 3.5 degrees) facing up. The susceptor on which the base substrate 1 is placed is inserted into the reaction tube of the vapor phase growth apparatus, and a vacuum of 1 Pa or less is drawn. Then, vapor phase etching is performed to remove the natural oxide film formed on the base plate 1. Here, heating is performed at 1600 ° C. for 30 minutes while flowing hydrogen gas at a flow rate of 1 L per minute. The heating method for the susceptor is high frequency induction heating. It will be described later (00
0, -1) When hydrogen chloride is added, as in the case of a carbon surface, unevenness occurs on the surface, so only hydrogen is used.

【００３０】続いて実施例１と同様にして、伝導度矯正
層２および低濃度層３の成長をおこなった。更に、基板
の裏面すなわち（０００、−１）炭素面にカソード電極
４、それから、（０００１）けい素面に厚さが２００ｎ
ｍ、直径が２００μｍの金のショットキー電極５を形成
し、ショットキーダイオードとした。以上の方法により
得られたショットキーダイオードの逆方向耐圧特性は、
室温で均一に５００Ｖ以上あり、５００Ｖ印加時の漏れ
電流は約１０ｍＡ・ｃｍ-2であった。さらに直径３０ｍ
ｍの炭化けい素基板から５ｍｍ角のチップを５個任意に
切り出して、上記方法で多数のショットキーダイオード
の作製を繰り返したが、チップ内およびチップ間の逆方
向耐圧特性のばらつきはほとんど無かった。これは本実
施例の前処理の効果を示していると考えられる。Subsequently, in the same manner as in Example 1, the conductivity straightening layer 2 and the low concentration layer 3 were grown. Further, a cathode electrode 4 is formed on the back surface of the substrate, that is, a (000, -1) carbon surface, and a thickness of 200 n is formed on the (0001) silicon surface.
A gold Schottky electrode 5 having a diameter of m and a diameter of 200 μm was formed as a Schottky diode. The reverse breakdown voltage characteristics of the Schottky diode obtained by the above method are
The voltage was uniformly 500 V or more at room temperature, and the leakage current when 500 V was applied was about 10 mA · cm −2 . 30m in diameter
Five pieces of 5 mm square chips were arbitrarily cut out from the silicon carbide substrate of m, and a large number of Schottky diodes were repeatedly manufactured by the above method, but there was almost no variation in reverse breakdown voltage characteristics within the chips and between the chips. . This is considered to indicate the effect of the pretreatment of this example.

【００３１】上記方法で作製したショットキーダイオー
ドの炭化けい素基板のＰＣＩＶ測定は、図１とほぼ同じ
になった。伝導度矯正層２の電気伝導度は下地基板１の
それとほぼ同じであり厚さ方向の分布がなく、伝導度矯
正層２と低濃度層３の界面で急峻に変化し、伝導度矯正
層２内では、再び厚さ方向の分布がない。これは下地基
板１からの結晶欠陥の伝播が５μｍの伝導度矯正層２内
で終わっているためと考えられる。The PCIV measurement of the silicon carbide substrate of the Schottky diode manufactured by the above method was almost the same as that in FIG. The electrical conductivity of the conductivity correction layer 2 is almost the same as that of the base substrate 1, has no distribution in the thickness direction, and changes sharply at the interface between the conductivity correction layer 2 and the low-concentration layer 3, and the conductivity correction layer 2 Within, there is again no thickness distribution. It is considered that this is because the propagation of crystal defects from the base substrate 1 ends within the conductivity correction layer 2 of 5 μm.

【００３２】実施例１で、伝導度矯正層２を成長する前
に下地基板を研磨等で表面処理しない場合には伝導度矯
正層は４μｍ必要であったが、実施例２のように、基板
の表面処理をおこなった場合には、高濃度にドープされ
た伝導度矯正層２を３μｍ以上堆積すれば、低濃度層３
は下地基板１の結晶欠陥の影響を避けられることがわか
った。In Example 1, if the underlying substrate was not surface-treated by polishing or the like before growing the conductivity straightening layer 2, the conductivity straightening layer was required to have a thickness of 4 μm. When the surface treatment is performed, if the conductivity-correcting layer 2 doped at a high concentration is deposited to a thickness of 3 μm or more, the low-concentration layer 3 is formed.
It was found that the influence of crystal defects of the base substrate 1 can be avoided.

【００３３】［実施例３］実施例１、２の素子作製で
は、下地板１の（０００１）けい素面（正確にはその
３．５度のオフアングル面）上にエピタキシャル法で伝
導度矯正層２と低濃度層３を成長し、（０００、−１）
炭素面上にカソード電極４を形成した。一方、成長プロ
セスを適切なものとすることによって、下地板の（００
０、−１）炭素面上にエピタキシャル層を成長し、（０
００１）けい素面にカソード電極を形成したショットキ
ーダイオードとすることも可能である。[Embodiment 3] In the fabrication of the devices of Embodiments 1 and 2, the conductivity straightening layer was epitaxially formed on the (0001) silicon surface of the base plate 1 (more precisely, its off-angle surface of 3.5 degrees). 2 and low-concentration layer 3 are grown, (000, -1)
The cathode electrode 4 was formed on the carbon surface. On the other hand, by optimizing the growth process, (00
An epitaxial layer is grown on the (0, -1) carbon surface and (0
It is also possible to use a Schottky diode in which a cathode electrode is formed on the 001) silicon surface.

【００３４】このショットキーダイオードの作製方法を
以下に述べる。まず研磨された６Ｈ型炭化けい素単結晶
の下地基板１を用意する。下地基板１はダイサーにより
５ｍｍ角のチップに切り分ける。本実施例では、（００
０、−１）炭素面から＜１１、−２、０＞方向に３．５
度傾けて研磨した面を使用した。下地基板１の表面を１
μｍのダイヤモンドペーストを用いてバフ研磨する。次
に表面不完全層を取り除くため下地基板の酸化をおこな
う。酸化条件は１２００℃×４時間のウェット酸化であ
る。このとき、酸化けい素膜の厚さは、約１．２μｍに
なる。実施例２の（０００１）けい素面の酸化の場合に
比べて、酸化速度が速く、短時間で厚い酸化膜を形成す
ることができる。更に有機溶剤洗浄と酸洗浄で清浄にす
る。酸洗浄にはふっ酸処理を含み、上記の酸化膜がエッ
チング除去される。A method of manufacturing this Schottky diode will be described below. First, a ground substrate 1 of a polished 6H-type silicon carbide single crystal is prepared. The base substrate 1 is cut into 5 mm square chips by a dicer. In this embodiment, (00
0, -1) 3.5 in the <11, -2, 0> direction from the carbon face
The surface which was inclined and polished was used. The surface of the base substrate 1
Buffing is performed using a diamond paste of μm. Next, the base substrate is oxidized to remove the incomplete surface layer. The oxidizing condition is wet oxidation at 1200 ° C. for 4 hours. At this time, the thickness of the silicon oxide film is about 1.2 μm. Compared with the case of oxidizing the (0001) silicon surface of Example 2, the oxidation rate is faster and a thick oxide film can be formed in a short time. Further, clean with organic solvent cleaning and acid cleaning. The acid cleaning includes hydrofluoric acid treatment, and the above oxide film is removed by etching.

【００３５】次にエピタキシャル成長する（０００、−
１）炭素面（正確にはその３．５度のオフアングル面）
を上にして、下地板１を炭化けい素で被覆した黒鉛のサ
セプタにのせる。下地板１をのせたサセプタを気相成長
装置の反応管内に挿入し、約１Ｐａの真空にひく。そし
て下地基板１上に生じた自然酸化膜を取り除くため気相
エッチングをおこなう。ここでは水素ガスと塩化水素ガ
スをそれぞれ毎分１Ｌ、３ｍＬの流量で混ぜた混合ガス
を流しながら１４００℃で５分間加熱する。サセプタの
加熱法は高周波誘導加熱である。Next, epitaxial growth is performed (000,-
1) Carbon surface (more precisely, its 3.5 degree off-angle surface)
, The base plate 1 is placed on a graphite susceptor coated with silicon carbide. The susceptor on which the base plate 1 is placed is inserted into the reaction tube of the vapor phase growth apparatus and evacuated to a vacuum of about 1 Pa. Then, vapor phase etching is performed to remove the natural oxide film formed on the base substrate 1. Here, heating is performed at 1400 ° C. for 5 minutes while flowing a mixed gas in which hydrogen gas and hydrogen chloride gas are mixed at a flow rate of 1 L / min and 3 mL / min, respectively. The heating method for the susceptor is high frequency induction heating.

【００３６】続いて１５００℃に加熱して、水素ガス、
モノシランガス、プロパンガスと窒素ガスをそれぞれ毎
分３Ｌ、０．３ｍＬ、０．２５ｍＬ、０．２ｍＬの流量
の混合ガスを２時間流す。すると下地板１上に６Ｈ型炭
化けい素の伝導度矯正層２がエピタキシャル成長する。
続いて低濃度層の成長をおこなうが、その前にいったん
試料を反応管より取り出し、治具等を交換する。下地板
１の洗浄をおこない、伝導度矯正層を成膜する場合と同
じ方法で気相エッチングをして成長にはいる。１５００
℃に加熱して、水素ガス、モノシランガス、プロパンガ
スと窒素ガスとをそれぞれ毎分３Ｌ、０．３ｍＬ、０．
２５ｍＬ、０．００２ｍＬの流量の混合ガスを１時間流
す。すると伝導度矯正層２上に６Ｈ型炭化けい素の低濃
度層３がエピタキシャル成長する。伝導度矯正層２の膜
厚は５μｍ、低濃度層３の膜厚は２．５μｍである。伝
導度矯正層２および低濃度層３の成長方法は熱気相成長
法である。Subsequently, it is heated to 1500 ° C., and hydrogen gas,
A mixed gas of monosilane gas, propane gas, and nitrogen gas at a flow rate of 3 L, 0.3 mL, 0.25 mL, and 0.2 mL per minute is supplied for 2 hours. Then, the conductivity-correcting layer 2 of 6H-type silicon carbide is epitaxially grown on the base plate 1.
Subsequently, the low-concentration layer is grown, but before that, the sample is once taken out from the reaction tube and the jig or the like is exchanged. The base plate 1 is washed, and vapor phase etching is carried out for growth in the same manner as in the case of forming the conductivity straightening layer. 1500
It is heated to 0 ° C., and hydrogen gas, monosilane gas, propane gas and nitrogen gas are supplied at 3 L / min, 0.3 mL / min.
A mixed gas having a flow rate of 25 mL and 0.002 mL is allowed to flow for 1 hour. Then, the low concentration layer 3 of 6H-type silicon carbide is epitaxially grown on the conductivity straightening layer 2. The conductivity correction layer 2 has a film thickness of 5 μm, and the low concentration layer 3 has a film thickness of 2.5 μm. The growth method of the conductivity correction layer 2 and the low-concentration layer 3 is a thermal vapor deposition method.

【００３７】次に電極を形成する。基板の裏面すなわち
（０００１）けい素面にニッケルを２００ｎｍの厚さに
なるように真空蒸着し、アルゴン雰囲気中において１２
００℃で１０分間加熱しオーミックなカソード電極４と
する。それから（０００−１）炭素面に厚さが２００ｎ
ｍ、直径が２００μｍとなるように金を真空蒸着し、シ
ョットキー電極５とする。Next, electrodes are formed. Nickel was vacuum-deposited on the back surface of the substrate, that is, the (0001) silicon surface so as to have a thickness of 200 nm.
It is heated at 00 ° C. for 10 minutes to form the ohmic cathode electrode 4. Then, the thickness is 200n on the (000-1) carbon surface.
m is used, and gold is vacuum-deposited so as to have a diameter of 200 μm to form a Schottky electrode 5.

【００３８】以上の方法により得られたショットキーダ
イオードの逆方向耐圧特性は、室温で均一に５００Ｖ以
上であった。５００Ｖ印加時の漏れ電流は約１０ｍＡ・
ｃｍ -2であった。さらに直径３０ｍｍの炭化けい素基板
から５ｍｍ角のチップを５個任意に切り出して、上記方
法で多数のショットキーダイオードの作製を繰り返した
が、チップ内およびチップ間の逆方向耐圧特性のばらつ
きはほとんど無かった。これは本実施例の前処理の効果
を示していると考えられる。The shot keeper obtained by the above method
The reverse withstand voltage characteristic of Iodo is 500V or more evenly at room temperature.
Was on. Leakage current when applying 500V is about 10mA
cm -2Met. Furthermore, a silicon carbide substrate with a diameter of 30 mm
5 pieces of 5mm square chips are arbitrarily cut out from
Repeated fabrication of many Schottky diodes
However, there are variations in reverse breakdown voltage characteristics within and between chips.
There was almost nothing. This is the effect of the pretreatment of this embodiment.
Is considered to indicate.

【００３９】上記方法で作製したショットキーダイオー
ドの炭化けい素基板のＰＣＩＶ測定は、図１とほぼ同じ
になった。この実施例でも高濃度にドープされた伝導度
矯正層２を３μｍ以上堆積すれば、低濃度層３は下地基
板１の結晶欠陥の影響を避けられることがわかった。 ［実施例４］図４は本発明第二の実施例のプレーナ型の
ｐｎダイオードの断面を示している。The PCIV measurement of the silicon carbide substrate of the Schottky diode manufactured by the above method was almost the same as that in FIG. Also in this example, it was found that the influence of crystal defects of the underlying substrate 1 can be avoided in the low-concentration layer 3 by depositing the highly-doped conductivity correction layer 2 in a thickness of 3 μm or more. [Embodiment 4] FIG. 4 shows a cross section of a planar type pn diode according to a second embodiment of the present invention.

【００４０】導電型がｎ型で、不純物濃度が１×１０18
ｃｍ-3の６Ｈ型炭化けい素単結晶の下地板１の（０００
１）けい素面の３．５度オフアングル面上に、ｎ型で不
純物濃度が１×１０18ｃｍ-3、厚さ５μｍの伝導度矯正
層２および、ｎ型で不純物濃度が１×１０16ｃｍ-3、厚
さ２．５μｍの低濃度層３が堆積されている。その低濃
度層３の表面層に、ｐアノード領域６が形成されてい
る。４は下地板１の裏面に蒸着したオーミック電極、７
はｐアノード領域６に接触して設けられたアルミニウム
蒸着膜のアノード電極である。以下にこの素子の作製方
法を述べる先ず、実施例２のショットキーダイオードの
製造方法と同様の方法で、伝導度矯正層２と低濃度層３
をエピタキシャル成長する。次に低濃度層３の表面に酸
化けい素膜８を形成する。酸化はウェット酸素の雰囲気
中で、１２００℃、６０分間行う。酸化けい素膜８の厚
さは約５０ｎｍである。ホトリソグラフィ技術を用いて
その酸化けい素膜８に直径２００μｍの窓を開ける。こ
の窓から加速電圧３０、９０、１８０ｋｅＶでアルミニ
ウムをイオン注入する。ドーズ量はそれぞれの加速電圧
に対して、６．１１×１０13、１．５７×１０14、２．
８０×１０14ｃｍ-2である。注入温度は室温である。こ
の試料をアルゴン雰囲気中で１７００℃、１０分間アニ
ールして、ｐアノード領域６が形成される。その後、窓
開口部にアルミニウムをマスクで選択蒸着して、アノー
ド電極７を形成し、下地板１の裏面にニッケルの真空蒸
着により、カソード電極４を形成する。The conductivity type is n-type and the impurity concentration is 1 × 10 18.
cm -3 of 6H type silicon carbide single crystal base plate 1 (000
1) An n-type impurity concentration of 1 × 10 18 cm −3 and a conductivity correction layer 2 having a thickness of 5 μm and an n-type impurity concentration of 1 × 10 16 are formed on a 3.5 ° off-angle surface of a silicon surface. A low-concentration layer 3 having a thickness of cm −3 and a thickness of 2.5 μm is deposited. A p anode region 6 is formed on the surface layer of the low concentration layer 3. 4 is an ohmic electrode deposited on the back surface of the base plate 1, 7
Is an anode electrode of an aluminum vapor deposition film provided in contact with the p anode region 6. A method of manufacturing this element will be described below. First, the conductivity straightening layer 2 and the low concentration layer 3 are formed by the same method as the method of manufacturing the Schottky diode of the second embodiment.
Epitaxially grow. Next, a silicon oxide film 8 is formed on the surface of the low concentration layer 3. Oxidation is performed at 1200 ° C. for 60 minutes in a wet oxygen atmosphere. The thickness of the silicon oxide film 8 is about 50 nm. A window having a diameter of 200 μm is opened in the silicon oxide film 8 by using the photolithography technique. Aluminum is ion-implanted through this window at acceleration voltages of 30, 90, and 180 keV. The dose amount is 6.11 × 10 13 , 1.57 × 10 14 , and 2.
It is 80 × 10 14 cm -2 . The injection temperature is room temperature. This sample is annealed in an argon atmosphere at 1700 ° C. for 10 minutes to form the p anode region 6. After that, aluminum is selectively vapor-deposited with a mask in the window opening to form the anode electrode 7, and nickel is vacuum-deposited on the back surface of the base plate 1 to form the cathode electrode 4.

【００４１】この実施例２のｐｎ接合ダイオードの逆方
向耐圧は、室温で５００Ｖ以上で、ほぼ設計耐圧と同じ
であり、５００Ｖ印加時の漏れ電流は１０ｍＡ・ｃｍ-2
であった。 ［実施例５］実施例４と同様にして、下地板の（００
０、−１）炭素面上にエピタキシャル層を成長し、（０
００１）けい素面にカソード電極を形成したプレーナ型
のｐｎダイオードとすることも可能である。The reverse breakdown voltage of the pn junction diode of Example 2 is 500 V or more at room temperature, which is almost the same as the design breakdown voltage, and the leakage current when 500 V is applied is 10 mA · cm −2.
Met. [Embodiment 5] In the same manner as in Embodiment 4, (00
An epitaxial layer is grown on the (0, -1) carbon surface and (0
It is also possible to use a planar type pn diode in which a cathode electrode is formed on the 001) silicon surface.

【００４２】実施例３のショットキーダイオードの作製
方法と同様の方法で、すなわち導電型がｎ型で不純物濃
度が１×１０18ｃｍ-3の６Ｈ型炭化けい素単結晶の下地
板の（０００、−１）炭素面の３．５度オフアングル面
上に、表面処理を施してからｎ型で不純物濃度が１×１
０18ｃｍ-3、厚さ５μｍの伝導度矯正層および、ｎ型で
不純物濃度が１×１０16ｃｍ-3、厚さ２．５μｍの低濃
度層をエピタキシャル成長する。次に低濃度層の表面に
酸化けい素膜を形成する。酸化はウェット酸素の雰囲気
で１２００℃、６０分間おこなう。酸化けい素膜の厚さ
は約３００ｎｍである。ホトリソグラフィ技術を用いて
その酸化けい素膜に直径２００μｍの窓を開ける。この
窓から加速電圧３０、９０、１８０ｋｅＶでアルミニウ
ムをイオン注入する。ドーズ量はそれぞれの加速電圧に
対して、６×１０13、２×１０14、３×１０14ｃｍ-2で
ある。注入温度は室温である。この試料をアルゴン雰囲
気中で１８００℃、１０分間アニールして、ｐアノード
領域が形成される。その後、窓開口部にアルミニウムを
マスクで選択蒸着してアノード電極を形成し、下地板の
裏面にニッケルの真空蒸着によりカソード電極を形成す
る。In the same manner as the method for manufacturing the Schottky diode of Example 3, that is, (000) of the 6H-type silicon carbide single crystal base plate having the n-type conductivity and the impurity concentration of 1 × 10 18 cm −3. , -1) n-type with an impurity concentration of 1 × 1 after the surface treatment on the 3.5 ° off-angle surface of the carbon surface
A conductivity correction layer having a thickness of 0 18 cm −3 and a thickness of 5 μm, and an n-type low concentration layer having an impurity concentration of 1 × 10 16 cm −3 and a thickness of 2.5 μm are epitaxially grown. Next, a silicon oxide film is formed on the surface of the low concentration layer. Oxidation is performed at 1200 ° C. for 60 minutes in a wet oxygen atmosphere. The thickness of the silicon oxide film is about 300 nm. A window having a diameter of 200 μm is opened in the silicon oxide film by using the photolithography technique. Aluminum is ion-implanted through this window at acceleration voltages of 30, 90, and 180 keV. The dose amount is 6 × 10 13 , 2 × 10 14 , 3 × 10 14 cm −2 for each acceleration voltage. The injection temperature is room temperature. This sample is annealed in an argon atmosphere at 1800 ° C. for 10 minutes to form a p anode region. Then, aluminum is selectively vapor-deposited with a mask in the window opening to form an anode electrode, and a cathode electrode is formed on the back surface of the base plate by vacuum vapor deposition of nickel.

【００４３】この実施例５のｐｎ接合ダイオードの逆方
向耐圧は、室温で５００Ｖ以上でほぼ設計耐圧と同じで
あり、５００Ｖ印加時の漏れ電流は１０ｍＡ・ｃｍ-2で
あった。更に、直径３０ｍｍの炭化けい素基板から５ｍ
ｍ角のチップを５個切り出して、上記方法で多数のｐｎ
ダイオードの作製を繰り返したが、チップ内およびチッ
プ間の逆方向耐圧特性のばらつきはほとんど無かった。The reverse breakdown voltage of the pn junction diode of Example 5 was about the same as the design breakdown voltage at room temperature of 500 V or higher, and the leakage current when 500 V was applied was 10 mA · cm −2 . Furthermore, 5m from a silicon carbide substrate with a diameter of 30mm
Cut 5 m-square chips and use the above method to make a large number of pn
The production of the diode was repeated, but there was almost no variation in the reverse breakdown voltage characteristics within and between the chips.

【００４４】［実施例６］図５は本発明第三の実施例の
トレンチ型ＭＯＳＦＥＴの断面を示している。導電型が
ｎ型で、不純物濃度が１×１０18ｃｍ-3の６Ｈ型炭化け
い素単結晶の下地板１の（０００１）けい素面の３．５
度オフアングル面上に、ｎ型で不純物濃度が１×１０18
ｃｍ-3、厚さ５μｍの伝導度矯正層２および、ｎ型で不
純物濃度が１×１０16ｃｍ-3、厚さ５μｍの低濃度層
３、ｐ型で不純物濃度が４×１０ 17ｃｍ-3、厚さ１μｍ
のｐベース層９が順次堆積されている。ｐベース層９堆
積時のドーパントとしては、アルミニウムを用いた。そ
のｐベース層９の表面層に、窒素イオンの注入および熱
処理によりｎソース領域１１が形成されている。ｎソー
ス領域１１の表面から低濃度層３に達するトレンチ１２
が形成され、そのトレンチ１２の内部には、酸化けい素
膜のゲート絶縁膜１３を介して多結晶けい素のゲート電
極層１４が埋めこまれている。１５は下地板１の裏面に
形成したニッケル蒸着膜のドレイン電極、１６はｎソー
ス領域１１に接触して設けられたソース電極である。図
示していないが、ゲート電極層１４に接触する金属膜の
ゲート電極が設けられることもある。[Sixth Embodiment] FIG. 5 shows a third embodiment of the present invention.
The section of a trench type MOSFET is shown. Conductivity type
n-type with an impurity concentration of 1 × 1018cm-36H type carbonization
3.5 of (0001) silicon surface of silicon single crystal substrate 1
N-type impurity concentration of 1 × 10 on the off-angle surface18
cm-3, A conductivity correction layer 2 having a thickness of 5 μm and an n-type
Pure substance concentration is 1 × 1016cm-3, 5 μm thick low concentration layer
3, p-type with an impurity concentration of 4 × 10 17cm-3, Thickness 1 μm
P base layer 9 is sequentially deposited. p base layer 9 stack
Aluminum was used as a dopant at the time of stacking. So
Of nitrogen ions and heat on the surface layer of the p-base layer 9 of
The n source region 11 is formed by the processing. n saw
Trench 12 reaching the low-concentration layer 3 from the surface of the region 11
A silicon oxide is formed inside the trench 12.
A gate electrode of polycrystalline silicon is provided through the gate insulating film 13 of the film.
The polar layer 14 is embedded. 15 is on the back surface of the base plate 1.
The drain electrode of the formed nickel vapor deposition film, 16 is an n-saw
The source electrode is provided in contact with the source region 11. Figure
Although not shown, the metal film contacting the gate electrode layer 14
A gate electrode may be provided.

【００４５】［実施例７］下地板の（０００、−１）炭
素面上にエピタキシャル層を成長し、（０００１）けい
素面にドレイン電極を形成したトレンチ型ＭＯＳＦＥＴ
とすることも可能である。そのようなトレンチ型ＭＯＳ
ＦＥＴの断面図は図５に示した実施例６のものとほぼ同
じになる。製造方法も、下地板およびその上のエピタキ
シャル層の成層工程が変わるだけで、それ以降の工程は
同じでよい。[Embodiment 7] A trench MOSFET in which an epitaxial layer is grown on a (000, -1) carbon surface of a base plate and a drain electrode is formed on a (0001) silicon surface.
It is also possible to Such trench type MOS
The sectional view of the FET is almost the same as that of the sixth embodiment shown in FIG. The manufacturing method may be the same except for the step of forming the base plate and the epitaxial layer thereon, and the subsequent steps may be the same.

【００４６】実施例７のトレンチ型ＭＯＳＦＥＴは、実
施例６のトレンチ型ＭＯＳＦＥＴと同様に、チップ内と
チップ間の耐圧、漏れ電流等のばらつきがなく、均一な
特性を示した。 ［実施例８］図６は本発明第四の実施例の炭化けい素サ
イリスタの断面を示している。Similar to the trench type MOSFET of the sixth embodiment, the trench type MOSFET of the seventh embodiment has uniform characteristics without variations in withstand voltage, leakage current and the like within and between chips. [Embodiment 8] FIG. 6 shows a cross section of a silicon carbide thyristor according to a fourth embodiment of the present invention.

【００４７】導電型がｐ型で、不純物濃度が１×１０18
ｃｍ-3の６Ｈ型炭化けい素単結晶の下地板１の（０００
１）けい素面の３．５度オフアングル面上に、ｐ型で不
純物濃度が１×１０18ｃｍ-3、厚さ５μｍの伝導度矯正
層２および、ｎ型で不純物濃度が１×１０16ｃｍ-3、厚
さ５μｍの低濃度層３、ｐ型で不純物濃度が４×１０ 17
ｃｍ-3、厚さ１μｍのｐベース層９が堆積されている。
そのｐベース層９の表面層に、窒素イオンの選択的な注
入および熱処理により、ｎカソード領域１７が形成され
ている。ｐベース層９の表面には、アルミニウム蒸着膜
のゲート電極１８が形成されている。１９は下地板１の
裏面に蒸着したアノード電極、２０はｎカソード領域１
７に接触して設けられたカソード電極である。The conductivity type is p-type and the impurity concentration is 1 × 10.18
cm-36H-type silicon carbide single crystal base plate 1 (000
1) A p-type film is formed on the 3.5 degree off-angle surface of the silicon surface.
Pure substance concentration is 1 × 1018cm-3, Thickness 5μm conductivity correction
Layer 2 and n-type with an impurity concentration of 1 × 1016cm-3, Thick
5 μm thick low-concentration layer 3, p-type with an impurity concentration of 4 × 10 17
cm-3, A 1 μm thick p-base layer 9 is deposited.
The surface layer of the p base layer 9 is selectively injected with nitrogen ions.
The n-cathode region 17 is formed by the heat treatment and the heat treatment.
ing. An aluminum vapor deposition film is formed on the surface of the p base layer 9.
Gate electrode 18 is formed. 19 of the base plate 1
An anode electrode deposited on the back surface, 20 is an n cathode region 1
7 is a cathode electrode provided in contact with 7.

【００４８】［実施例９］下地板の（０００、−１）炭
素面上にエピタキシャル層を成長し、（０００１）けい
素面にアノード電極を形成したサイリスタとすることも
可能である。そのようなサイリスタの断面図は図６に示
した実施例８のものとほぼ同じになる。製造方法も、下
地板およびその上のエピタキシャル層の成層工程が変わ
るだけで、それ以降の工程は同じでよい。[Embodiment 9] A thyristor in which an epitaxial layer is grown on the (000, -1) carbon surface of a base plate and an anode electrode is formed on the (0001) silicon surface can be used. The sectional view of such a thyristor is almost the same as that of the eighth embodiment shown in FIG. The manufacturing method may be the same except for the step of forming the base plate and the epitaxial layer thereon, and the subsequent steps may be the same.

【００４９】実施例９のサイリスタは、実施例８のサイ
リスタと同様に、チップ内とチップ間の耐圧、漏れ電流
等のばらつきがなく、均一な特性を示した。Similar to the thyristor of the eighth embodiment, the thyristor of the ninth embodiment has uniform characteristics without variations in withstand voltage and leakage current between chips.

【００５０】[0050]

【発明の効果】以上説明したように本発明においては、
炭化けい素単結晶の下地板上に、下地板と同じ導電型
で、結晶欠陥の影響をマスクできる高濃度の不純物を含
んだ炭化けい素の伝導度矯正層および下地板より電気伝
導度の小さい炭化けい素の低濃度層をエピタキシャル成
長した炭化けい素半導体基板を用い半導体装置を製造し
た。 特に、表面不完全層を取り除く適切な表面処理を
施し、その上にエピタキシャル成長した炭化けい素半導
体基板を用いることにより、下地板の結晶欠陥の影響を
除去し、炭化けい素半導体素子の特性の安定化が実現で
き、また再現性も大きく向上した。As described above, in the present invention,
Silicon carbide single crystal base plate has the same conductivity type as the base plate, but has lower electrical conductivity than the conductivity correction layer of silicon carbide containing a high concentration of impurities that can mask the effects of crystal defects and the base plate. A semiconductor device was manufactured using a silicon carbide semiconductor substrate obtained by epitaxially growing a low concentration layer of silicon carbide. In particular, by applying an appropriate surface treatment to remove the incomplete surface layer and using a silicon carbide semiconductor substrate epitaxially grown on it, the effect of crystal defects of the base plate is removed and the characteristics of the silicon carbide semiconductor device are stabilized. It was possible to achieve this, and the reproducibility was greatly improved.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の実施例１のショットキーダイオードの
炭化けい素基板断面における電気伝導度分布図FIG. 1 is an electric conductivity distribution diagram in a cross section of a silicon carbide substrate of a Schottky diode of Example 1 of the present invention.

【図２】従来のショットキーダイオードの断面における
電気伝導度分布図FIG. 2 is an electric conductivity distribution diagram in a cross section of a conventional Schottky diode.

【図３】本発明の実施例１のショットキーダイオードの
断面図FIG. 3 is a sectional view of the Schottky diode according to the first embodiment of the present invention.

【図４】本発明の実施例４のｐｎ接合ダイオードの断面
図FIG. 4 is a sectional view of a pn junction diode according to a fourth embodiment of the present invention.

【図５】本発明の実施例６のＭＯＳＦＥＴの断面図FIG. 5 is a sectional view of a MOSFET according to a sixth embodiment of the present invention.

【図６】本発明の実施例８のサイリスタの断面図FIG. 6 is a sectional view of a thyristor according to an eighth embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１ 下地板 ２ 伝導度矯正層 ３ 低濃度層 ４ カソード電極 ５ ショットキー電極 ６ ｐアノード領域 ７ アノード電極 ８ 酸化けい素膜 ９ ｐベース領域 １０ エピタキシャル成長層 １１ ｎソース領域 １２ トレンチ １３ ゲート絶縁膜 １４ ゲート電極層 １５ ドレイン電極 １６ ソース電極 １７ ｎカソード領域 １８ ゲート電極 １９ アノード電極 ２０ カソード電極 DESCRIPTION OF SYMBOLS 1 Base plate 2 Conductivity correction layer 3 Low concentration layer 4 Cathode electrode 5 Schottky electrode 6 p Anode region 7 Anode electrode 8 Silicon oxide film 9 p Base region 10 Epitaxial growth layer 11 n Source region 12 Trench 13 Gate insulating film 14 Gate Electrode layer 15 Drain electrode 16 Source electrode 17 n Cathode region 18 Gate electrode 19 Anode electrode 20 Cathode electrode

Claims (26)

【特許請求の範囲】[Claims] 【請求項１】炭化けい素単結晶の下地板上に、下地板と
同じ導電型で、結晶欠陥の影響をマスクする程高濃度の
不純物を含んだ炭化けい素の伝導度矯正層および下地板
より電気伝導度の小さい炭化けい素の低濃度層をエピタ
キシャル成長したことを特徴とする炭化けい素半導体基
板。1. A silicon carbide single crystal underlayer having the same conductivity type as that of the underlayer, and a silicon carbide conductivity straightening layer containing a high concentration of impurities so as to mask the influence of crystal defects and the underlayer. A silicon carbide semiconductor substrate, which is obtained by epitaxially growing a low-concentration layer of silicon carbide having a smaller electric conductivity. 【請求項２】炭化けい素半導体基板がアルファ相炭化け
い素単結晶であることを特徴とする請求項１記載の炭化
けい素半導体基板。2. The silicon carbide semiconductor substrate according to claim 1, wherein the silicon carbide semiconductor substrate is an alpha phase silicon carbide single crystal. 【請求項３】エピタキシャル成長をおこなう下地面が
（０００１）けい素面から＜１１、−２、０＞方向へ３
度以上オフ研磨された面であることを特徴とする請求項
２記載の炭化けい素半導体基板。3. The base surface on which epitaxial growth is performed is 3 in the <11, -2, 0> direction from the (0001) silicon surface.
The silicon carbide semiconductor substrate according to claim 2, wherein the surface is off-polished more than once. 【請求項４】エピタキシャル成長をおこなう下地面が
（０００、−１）炭素面から＜１１、−２、０＞方向へ
３度以上オフ研磨された面であることを特徴とする請求
項２記載の炭化けい素半導体基板。4. The surface of an underlayer on which epitaxial growth is performed is a surface which is off-polished from the (000, -1) carbon surface in the <11, -2, 0> direction by 3 or more times. Silicon carbide semiconductor substrate. 【請求項５】伝導度矯正層の不純物濃度が１×１０18ｃ
ｍ-3以上であることを特徴とする請求項１ないし４のい
ずれかに記載の炭化けい素半導体基板。5. The impurity concentration of the conductivity correction layer is 1 × 10 18 c.
The silicon carbide semiconductor substrate according to claim 1, wherein the silicon carbide semiconductor substrate has a size of m −3 or more. 【請求項６】伝導度矯正層が、下地板とほぼ同じ電気伝
導度をもつことを特徴とする請求項５記載の炭化けい素
半導体基板。6. The silicon carbide semiconductor substrate according to claim 5, wherein the conductivity correcting layer has substantially the same electric conductivity as that of the base plate. 【請求項７】伝導度矯正層の厚さが３μｍ以上であるこ
とを特徴とする請求項１ないし６のいずれかに記載の炭
化けい素半導体基板。7. The silicon carbide semiconductor substrate according to claim 1, wherein the conductivity correction layer has a thickness of 3 μm or more. 【請求項８】炭化けい素単結晶の下地板上に、下地板と
同じ導電型で、結晶欠陥の影響をマスクする程高濃度の
不純物を含んだ炭化けい素の伝導度矯正層および下地板
より電気伝導度の小さい炭化けい素の低濃度層をエピタ
キシャル成長した炭化けい素半導体基板の製造方法にお
いて、エピタキシャル成長前の下地板の表面層を、０．
５〜１０μｍ除去することを特徴とする炭化けい素半導
体基板の製造方法。8. A silicon carbide single crystal base plate having the same conductivity type as that of the base plate, and a silicon carbide conductivity-correcting layer and a base plate containing a high concentration of impurities so as to mask the effect of crystal defects. In the method for manufacturing a silicon carbide semiconductor substrate in which a low-concentration layer of silicon carbide having a smaller electric conductivity is epitaxially grown, the surface layer of the base plate before the epitaxial growth is changed to 0.
A method for manufacturing a silicon carbide semiconductor substrate, which comprises removing 5 to 10 μm. 【請求項９】エピタキシャル成長前の下地板の表面を、
ダイヤモンドペーストで鏡面研磨することを特徴とする
請求項８記載の炭化けい素半導体基板の製造方法。9. The surface of the base plate before the epitaxial growth,
9. The method for manufacturing a silicon carbide semiconductor substrate according to claim 8, wherein mirror polishing is performed with diamond paste. 【請求項１０】直径が１μｍ以下の研磨砥粒を用いるこ
とを特徴とする請求項９記載の炭化けい素半導体基板の
製造方法。10. The method for manufacturing a silicon carbide semiconductor substrate according to claim 9, wherein polishing abrasive grains having a diameter of 1 μm or less are used. 【請求項１１】エピタキシャル成長前の下地板の表面層
を、反応性イオンエッチングにより除去することを特徴
とする請求項８ないし１０のいずれかに記載の炭化けい
素半導体基板の製造方法。11. The method for manufacturing a silicon carbide semiconductor substrate according to claim 8, wherein the surface layer of the base plate before epitaxial growth is removed by reactive ion etching. 【請求項１２】基板の被成長面をふっ素を含む反応性ガ
スと酸素またはアルゴンの混合ガス中においてエッチン
グすることを特徴とする請求項１１記載の炭化けい素半
導体基板の製造方法。12. The method for manufacturing a silicon carbide semiconductor substrate according to claim 11, wherein the growth surface of the substrate is etched in a mixed gas of a reactive gas containing fluorine and oxygen or argon. 【請求項１３】ガスの全圧力は１〜１００Ｐａ、時間は
５〜３０分、パワーは１〜１０Ｗ・ｃｍ-2なる条件で反
応性イオンエッチングをおこなうことを特徴とする請求
項１２記載の炭化けい素半導体基板の製造方法。13. The carbonization according to claim 12, wherein the reactive ion etching is performed under the conditions that the total gas pressure is 1 to 100 Pa, the time is 5 to 30 minutes, and the power is 1 to 10 W · cm −2. Manufacturing method of silicon semiconductor substrate. 【請求項１４】エピタキシャル成長前の下地板の表面を
熱酸化し、その酸化けい素膜をエッチング除去すること
を特徴とする請求項８ないし１３のいずれかに記載の炭
化けい素半導体基板の製造方法。14. The method for manufacturing a silicon carbide semiconductor substrate according to claim 8, wherein the surface of the base plate before the epitaxial growth is thermally oxidized and the silicon oxide film is removed by etching. . 【請求項１５】下地板の表面をドライ酸化またはウェッ
ト酸化の雰囲気において１０００〜１３００℃に加熱
し、酸化けい素膜を形成することを特徴とする請求項１
４記載の炭化けい素半導体基板の製造方法。15. A silicon oxide film is formed by heating the surface of a base plate to 1000 to 1300 ° C. in an atmosphere of dry oxidation or wet oxidation.
4. The method for manufacturing a silicon carbide semiconductor substrate according to 4. 【請求項１６】形成する酸化けい素膜の厚さが１μｍ以
上であることを特徴とする請求項１５記載の炭化けい素
半導体基板の製造方法。16. The method for manufacturing a silicon carbide semiconductor substrate according to claim 15, wherein the thickness of the silicon oxide film to be formed is 1 μm or more. 【請求項１７】エピタキシャル成長前の被成長面がほぼ
（０００１）けい素面であることを特徴とする請求項１
１ないし１６のいずれかに記載の炭化けい素半導体基板
の製造方法。17. The growth surface before epitaxial growth is a (0001) silicon surface.
17. The method for manufacturing a silicon carbide semiconductor substrate according to any one of 1 to 16. 【請求項１８】基板の被処理面である（０００１）けい
素面をＨ2 雰囲気中で１５００〜１７００℃に加熱し、
気相エッチングすることを特徴とする請求項１７に記載
の炭化けい素半導体基板の製造方法。18. A (0001) silicon surface which is a surface to be processed of a substrate is heated to 1500 to 1700 ° C. in an H 2 atmosphere,
The method for manufacturing a silicon carbide semiconductor substrate according to claim 17, wherein vapor etching is performed. 【請求項１９】気相エッチングの時間が５〜９０分であ
ることを特徴とする請求項１８記載の炭化けい素半導体
基板の製造方法。19. The method for producing a silicon carbide semiconductor substrate according to claim 18, wherein the vapor phase etching time is 5 to 90 minutes. 【請求項２０】基板の被成長面である（０００、−１）
炭素面をＨ2 希釈したＨＣｌ雰囲気中で１２００〜１５
００℃に加熱し、気相エッチングすることを特徴とする
請求項８ないし１６のいずれかに記載の炭化けい素半導
体基板の製造方法。20. The growth surface of a substrate (000, -1)
1200 to 15 in HCl atmosphere with carbon surface diluted with H 2
17. The method for manufacturing a silicon carbide semiconductor substrate according to claim 8, wherein heating is performed at 00 ° C. and vapor etching is performed. 【請求項２１】気相エッチングの時間が１〜３０分であ
り、ＨＣｌ濃度が０．１〜５％であることを特徴とする
請求項２０記載の炭化けい素半導体基板の製造方法。21. The method for producing a silicon carbide semiconductor substrate according to claim 20, wherein the vapor phase etching time is 1 to 30 minutes, and the HCl concentration is 0.1 to 5%. 【請求項２２】気相エッチングにより被エッチング面を
０．１μｍ以上除去することを特徴とする請求項１８な
いし２１のいずれかに記載の炭化けい素半導体基板の製
造方法。22. The method of manufacturing a silicon carbide semiconductor substrate according to claim 18, wherein the surface to be etched is removed by 0.1 μm or more by vapor phase etching. 【請求項２３】請求項１ないし７のいずれかに記載の炭
化けい素半導体基板を用いたことを特徴とする炭化けい
素半導体素子。23. A silicon carbide semiconductor device using the silicon carbide semiconductor substrate according to any one of claims 1 to 7. 【請求項２４】二つの主電極が、炭化けい素半導体基板
の対向する面上に設けられていることを特徴とする請求
項２３記載の炭化けい素半導体素子。24. The silicon carbide semiconductor device according to claim 23, wherein the two main electrodes are provided on opposing surfaces of the silicon carbide semiconductor substrate. 【請求項２５】炭化けい素の低濃度層上にシヨットキー
電極、下地板の表面にオーミック電極を設けたことを特
徴とする請求項２４記載の炭化けい素半導体素子。25. The silicon carbide semiconductor device according to claim 24, wherein a Sikey key electrode is provided on the low concentration layer of silicon carbide and an ohmic electrode is provided on the surface of the base plate. 【請求項２６】炭化けい素の低濃度層の表面層に下地板
と逆導電型の拡散領域を形成し、その拡散領域の表面上
にオーミック電極、下地板の表面にオーミック電極を設
けたことを特徴とする請求項２４記載の炭化けい素半導
体素子。26. A diffusion region having a conductivity type opposite to that of the base plate is formed on the surface layer of the low concentration layer of silicon carbide, and an ohmic electrode is provided on the surface of the diffusion region and an ohmic electrode is provided on the surface of the base plate. 25. The silicon carbide semiconductor device according to claim 24.
JP33651196A 1996-03-27 1996-12-17 Silicon carbide semiconductor substrate, method of manufacturing the same, and silicon carbide semiconductor device using the substrate Expired - Lifetime JP3230650B2 (en)

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