JP2005136386A - Silicon carbide-oxide laminate, manufacturing method therefor, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a silicon carbide-oxide laminate for producing a low-loss high-reliability MISFET or the like, a manufacturing method therefor, and a semiconductor device. <P>SOLUTION: A gate insulating film 7' which is an oxide layer mainly made of SiO<SB>2</SB>is formed on a SiC substrate 10 through thermal oxidation, and then a resultant structure is annealed in an inert gas atmosphere in a chamber 20. Thereafter, the SiC substrate 10 is placed in a chamber 30 which has a vacuum pump 31, and the silicon carbide-oxide layered structure A is exposed to an NO gas atmosphere, of reduced pressure at a high temperature which is higher than 1,100°C but lower than 1,250°C, whereby nitrogen diffuses to the gate insulating film 7'. As a result, a gate insulating film 7 which is a group V element, containing oxide layer, the lower part of which includes a region with high nitrogen concentration, and the relative dielectric constant of which is 3.0 or higher, is obtained. The interface state density of an interface region between the V-group element containing oxide layer and the silicon carbide layer decreases. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a silicon carbide-oxide stack having a silicon carbide layer, a method for manufacturing the same, and a semiconductor device using the same.

  In recent years, silicon carbide (SiC) has a structure in which Si and C are combined at a composition ratio of 1: 1, and has a higher dielectric breakdown resistance than other wide band gap semiconductor materials. Application to low-loss power devices is expected.

When SiC is applied to a power device, the structure of an insulated gate transistor, that is, a SiC-MISFET, can be formed by utilizing the fact that a high-quality SiO ₂ film can be formed on a SiC layer by thermally oxidizing SiC. Application to a power-driven SiC device having the above is promising.

In order to realize a low-loss power device having a SiC-MISFET structure, defects in the gate insulating film and at the interface between the SiC layer and the gate insulating film are greatly reduced, and the channel mobility is 200 cm ² / Vs. The above needs to be realized.

Here, an inversion MISFET formed using a 4H—SiC (1 1-20) substrate whose main surface is a (11-20) plane achieves a channel mobility of 200 cm ² / Vs or more. However, the 4H—SiC (1 1-2 0) substrate is not suitable for mass production and is difficult to use as a substrate for actual devices.

On the other hand, a number of techniques for forming a gate insulating film on a SiC (0 0 0 1) plane substrate suitable for mass production have been proposed so far (for example, Non-Patent Document 1). The most standard process is to form a thermal oxide film in a dry or wet atmosphere at a high temperature of 1100 ° C. or higher, anneal the thermal oxide film in an argon atmosphere, and then in an oxygen atmosphere containing high-concentration water vapor. Thus, a gate insulating film is formed by performing POA at 950 ° C. for 3 hours. Under the condition that the high-temperature heat treatment for forming the gate electrode is not performed, the inversion MISFET formed on the 4H—SiC (00 1) substrate having a flat surface with unevenness of 10 nm or less is 50 cm ² / It has a channel mobility of about Vs.
LALipkin and JAPalmer, J. Electron. Mater. 25, 909 (1999) GYChung, CCTin, JRWilliams, K. McDonald, RKChanara, Robert A. Weller, ST Pantelide, Leonard C. Feldman, OWHolland, MKDas, and John W. Palmour, “Improved Inversion Channel Mobility for 4H-SiC MOSFETs Following High Temperature Anneals in Nitric Oxide ”IEEE Electron Device Lett., Vol. 22, pp.176-178, 2000)

However, in a MISFET having a gate insulating film made of a thermal oxide film formed by the standard process as described above, if a heat treatment at 950 ° C. or higher is performed when the gate electrode is formed, practical channel mobility is obtained. Deteriorates to 20 cm ² / Vs or less. Furthermore, with a step on the surface, the flatness poor 4H-SiC (0 0 0 1 ) substrate, the channel mobility of a MISFET formed by applying these standard process is below 10 cm ² / Vs In addition, the channel mobility on the surface of the SiC substrate has a large anisotropy. A large current flows in the direction along the step, whereas the amount of current decreases by an order of magnitude in the direction across the step. Therefore, it is a great obstacle to apply these technologies to practical devices.

  An object of the present invention is to provide a silicon carbide-oxide laminate having a high quality oxide layer on a silicon carbide layer and a method for manufacturing the same, and thus has high channel mobility and high current driving capability. Therefore, it is possible to realize a power device having a silicon carbide-MISFET structure and a MIS capacitor.

  The silicon carbide-oxide laminate of the present invention has a region having a high V group element concentration of nitrogen, phosphorus, etc. at least in the lower part on the silicon carbide layer and has a relative dielectric constant of 3.0 or more. A group V element-containing oxide layer is provided.

  Thereby, the interface state in the region near the interface between the V group element-containing oxide layer and the silicon carbide layer is reduced, and a high dielectric constant is obtained. Therefore, when the silicon carbide-oxide stack is used for MISFET, high current driving force and high carrier mobility can be obtained.

  The full width at half maximum of the peak portion in the V group element concentration distribution in the lower part of the V group element-containing oxide layer is preferably 5 nm or less.

The V group element-containing oxide layer is preferably a SiO ₂ film whose base material is formed by thermal oxidation.

When the group V element is nitrogen or phosphorus, the maximum value of the group V element concentration in the lower portion of the group V element-containing oxide layer is 1 × 10 ²⁰ cm ⁻³ or more and 1 × 10 ²² cm ⁻³ or less. As a result, the effect of improving the relative dielectric constant and the effect of reducing the interface state density are remarkably obtained.

The interface state density in the region near the boundary between the V-group element-containing oxide layer and the silicon carbide layer is in the range of 0.15 to 0.4 eV from at least one of the conduction band and the valence band. It is preferable that it is 1 × 10 ¹² cm ⁻³ / eV or less in a certain region.

  The semiconductor device according to the present invention includes a group V element-containing oxide layer provided on a silicon carbide layer, and a gate electrode provided on the group V element-containing oxide layer. An impurity diffusion region, a channel region, and a second conductivity type contact region whose surface portion is removed by etching are provided at positions facing the channel region across the impurity diffusion region.

  As a result, the region rich in the group V element in the contact region is removed, so that a semiconductor device with high channel mobility can be obtained.

  In the first method for producing a silicon carbide-oxide laminate according to the present invention, after forming the oxide layer on the surface of the silicon carbide layer, the oxide layer is heated to a temperature range higher than 1100 ° C. and lower than 1250 ° C. In this method, the oxide layer is exposed to an atmosphere containing a group V element-containing gas to change the oxide layer into a group V element-containing oxide layer having a relative dielectric constant of 3.0 or more.

  By this method, it is possible to efficiently diffuse the V group element into the V group element-containing oxide layer while preventing the deterioration of the characteristics of the V group element-containing oxide layer. The interface state in the region near the interface of the silicon carbide layer is reduced, and a high dielectric constant is obtained. Therefore, it can be used for forming a MISFET having a high current driving force and a high carrier mobility.

The atmosphere containing the group V element-containing gas is preferably an atmosphere that is decompressed to a range of 6.67 × 10 ³ Pa to 5.33 × 10 ⁴ Pa.

  After the oxide is formed by thermal oxidation, the oxide layer is annealed in an inert gas atmosphere so as to be exposed to a gas containing a group V element-containing gas, thereby making the oxide layer a denser film. Can do.

  In the step of forming the oxide film, it is preferable to further perform an oxidation process in an oxidizing gas atmosphere at a temperature of 850 ° C. or higher and 950 ° C. or lower after annealing in an inert gas atmosphere.

The group V element-containing gas preferably contains nitrogen or phosphorus. In this case, the group V element-containing gas is selected from NO gas, N ₂ O gas, NO ₂ gas, and PH ₃ gas. It is preferred to use at least one gas.

  In the second method for producing a silicon carbide-oxide laminate according to the present invention, after the first oxide layer is formed on the surface of the silicon carbide layer, the first oxide layer is further formed into a group V element-containing gas. The first oxide layer is formed after being exposed to a gas atmosphere containing oxygen, and annealed in an inert gas atmosphere at a temperature of 900 ° C. to 1100 ° C. The group V element-containing oxide layer is changed to a group V element-containing oxide layer having a relative dielectric constant of 3.0 or more.

  By this method, it is possible to efficiently diffuse the group V element into the group V element-containing oxide layer while preventing the deterioration of the characteristics of the oxide layer, so that the group V element-containing oxide layer-silicon carbide layer The interface state in the region near the interface is reduced, and a high dielectric constant is obtained. Therefore, it can be used for forming a MISFET having a high current driving force and a high carrier mobility.

The atmosphere containing the group V element-containing gas is preferably an atmosphere that is decompressed to a range of 6.67 × 10 ³ Pa to 5.33 × 10 ⁴ Pa.

In the step of forming an oxide film, it is preferable to form a thermal oxide film having a thickness of less than 20 nm. In the step of exposing to a gas atmosphere containing a group V element-containing gas, NO gas, N _{2 is used} as the group V element-containing gas. It is preferable to use at least one gas selected from O gas, NO ₂ gas, and PH ₃ gas.

  The silicon carbide-oxide laminate of the present invention or a method for manufacturing the same can be used for manufacturing a MISFET or the like having a high current driving force and a high carrier mobility.

  In the embodiment of the present invention, a method for forming a silicon carbide-oxide stacked body in which a group V element-containing oxide layer having good characteristics is provided on a silicon carbide layer (SiC layer) will be described.

(First embodiment)
FIG. 1 is a cross-sectional view showing the structure of a storage MISFET using an SiC substrate according to a first embodiment of the present invention. Although only a partial cross-sectional structure is disclosed in FIG. 1, the planar structure of the MISFET has a structure as disclosed in FIG. 2 or FIG. 10 of the international application PCT / JP01 / 07810, for example.

  In this embodiment, nitrogen is used as the group V element, but other group V elements such as phosphorus (P) and arsenic (As) may be used.

  The “SiC layer (silicon carbide layer)” in the present invention most preferably represents a bulk single crystal SiC substrate or an epitaxially grown SiC layer on the bulk single crystal SiC substrate. SiC has many polytypes, of which 3C, 4H, 6H, and 15R polytypes are particularly useful for electronic devices, and the present invention provides suitable results using these polytypes. In the following embodiments, a case where the SiC layer is a 4H—SiC (0 0 0 1) layer epitaxially grown on a bulk SiC substrate will be described.

As shown in FIG. 1, this double-implant MISFET has a low-resistance SiC substrate 1 containing an n-type impurity (dopant) having a concentration of 1 × 10 ¹⁸ cm ⁻³ or more, and a main surface of the SiC substrate 1. A high resistance SiC layer 2 which is provided and is doped with an n-type impurity having a concentration of about 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁶ cm ^−3, and a concentration on a part of the surface portion of the high resistance SiC layer 2. Is doped with a p-type impurity of 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ , and a concentration of about 1 × 10 ¹⁹ cm ⁻ is formed in a part of the p well region 3. A source region 6 formed by doping ³ n-type impurities and a p ⁺ contact region formed by doping a portion of the p-well region 3 located immediately below the source region with a high-concentration p-type impurity 11 and a laminated doped layer structure formed over the p-well region 3 and the high-resistance SiC layer 2. From the channel layer 5, the gate insulating film 7, which is a V-group element-containing oxide layer, made of a thermal oxide film provided on the surface of the channel layer 5, and the Al alloy film provided on the gate insulating film 7 And a source electrode 8 provided on the wall surface of the trench that reaches the p ⁺ contact region 11 through the source region 6 and is in contact with the p ⁺ contact region 11 and the source region 7. And a drain electrode 9 formed in ohmic contact with the back surface of the SiC substrate 1.

Each of the source region 6 that is an n-type semiconductor layer and the high-resistance SiC layer 2 are in an electrically connected state via a channel layer 5 that is an N-type semiconductor layer. In addition, a part of the channel layer 5 located above the source region is removed. The source electrode 8, the source region 6 and the p ⁺ contact region 11 are heat-treated so as to be in ohmic contact with each other. SiC substrate 1 and drain electrode 9 are in ohmic contact with each other.

  FIGS. 2A to 2E and FIGS. 3A to 3E are cross-sectional views showing manufacturing steps of the MISFET of the first embodiment.

  First, in the step shown in FIG. 2A, a high resistance SiC layer 2 having a higher resistance (lower dopant concentration) than that of the SiC substrate 1 is epitaxially grown on the low resistance SiC substrate 1.

  Next, in the step shown in FIG. 2B, for example, a TEOS film is deposited, and a silicon dioxide film 21 x having a thickness of 3 μm is deposited on the high resistance SiC layer 2. Thereafter, photolithography is performed to form a resist mask Re1 having a P well formation region opened on the silicon dioxide film 21x.

Next, in the step shown in FIG. 2C, the silicon dioxide film 21x is patterned by dry etching using the resist mask Re1 as an etching mask to form a silicon dioxide mask 21 (ion implantation mask). Then, after removing the resist mask Re1, ion implantation of p-type impurities is performed on a part of the surface portion of the high resistance SiC layer 2 while the substrate is held at a high temperature of 500 ° C. or higher using the silicon dioxide mask 21. In line, the p-well region 3 is formed. The concentration of the p-type impurity in the p-well region 3 is usually about 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ , and the depth of the p-well region 3 is about 1 μm so as not to pinch off.

  Next, in the step shown in FIG. 2 (d), the silicon dioxide mask 21 is removed, and annealing is performed to activate the implanted impurities, and then on the surfaces of the p-well region 3 and the high-resistance SiC layer 2. Next, the channel layer 5 containing an n-type impurity is epitaxially grown.

  Next, in the step shown in FIG. 2E, for example, a TEOS film is deposited, and a silicon dioxide film 24 x having a thickness of 3 μm is deposited on the channel layer 5. Thereafter, photolithography is performed to form a resist mask Re2 having a source formation region opened on the silicon dioxide film 24x.

  Next, in the step shown in FIG. 3A, the silicon dioxide film 24x is patterned by dry etching using the resist mask Re2 as an etching mask to form a silicon dioxide mask 24 (ion implantation mask). Then, after removing the resist mask Re2, using the silicon dioxide mask 24, a high-concentration n-type impurity is added to the channel layer 5 and a part of the p-well region 3 while maintaining the substrate at a high temperature of 500 ° C. or higher. By performing ion implantation, source region 6 that penetrates channel layer 5 and reaches the inside of p well region 3 is formed. At this time, the source region 6 that is an n-type semiconductor layer and the high-resistance SiC layer 2 are in an electrically connected state via a channel layer 5 that is an n-type semiconductor layer.

Next, in the step shown in FIG. 3B, ion implantation of high-concentration p-type impurities is performed to form a p ⁺ contact region 11 in a part of the p-well region 3 located immediately below the source region 6. To do. Then, after removing the silicon dioxide mask 24, annealing for activating the impurities implanted into the p ⁺ contact region 11 and the source region 6 is performed. Further, after forming the grooves 4 reaching the top of the p ⁺ contact region 11 through the source region 6, the channel layer 5, the surface portion which is exposed in the source region 6 and p ⁺ contact region 11 is thermally oxidized Then, a thermal oxide film is formed. At this time, the thermal oxide film is formed in a dry atmosphere at 1200 ° C. or higher, and the film thickness is 40 nm to 80 nm. Thereby, silicon carbide-oxide laminate A is formed. Furthermore, the thermal oxide film is annealed in NO gas that is a group V element-containing gas, and is subjected to nitridation to introduce nitrogen, which is a group V element, into the thermal oxide film. A gate insulating film 7 as a layer is formed. At this time, the temperature of the nitriding treatment is in the range of 1050 ° C. to 1250 ° C., and the processing pressure is in the range of 6.67 × 10 ³ Pa to 5.33 × 10 ⁴ Pa.

Next, in the step shown in FIG. 3C, the portion of the gate insulating film 7 on the wall surface of the groove 4 and the portion around the groove 4 are removed. Thereafter, the source region 6 and the p ⁺ contact region 11 exposed by removing the gate insulating film 7 are wet-etched to a depth of about 300 nm to remove a region having a high interface state density.

  Next, in the step shown in FIG. 3D, the source electrode 8 is formed on the portion of the source region 6 where the gate insulating film 7 is removed and exposed. Further, drain electrode 9 is formed on the back surface of SiC substrate 1.

Next, the gate electrode 10 is formed on the gate insulating film 7 in the step shown in FIG. It should be noted that heat treatment is performed so that source electrode 8 and source region 7 and p ⁺ contact region 11 are in ohmic contact, and SiC substrate 1 and drain electrode 9 are in ohmic contact.

  Here, the process shown in FIG. 3B, which is a NO annealing process in the manufacturing process, will be described.

  FIGS. 4A and 4B are cross-sectional views illustrating a procedure for forming the V group element-containing oxide layer (gate insulating film 7) in the first embodiment. 4A to 4B schematically show a silicon carbide-oxide stack. In this embodiment, nitrogen is used as the group V element, but other group V elements such as phosphorus (P) and arsenic (As) may be used.

In the step shown in FIG. 4A, a silicon carbide-oxide stack A having a gate insulating film 7 ′, which is a thermal oxide film, formed on the surface is placed in the chamber 20, and an inert gas (Ar , N ₂ , He, Ne, etc.) at a temperature of 1000 ° C. or higher (for example, 1000 ° C. to 1300 ° C.). By this annealing treatment, the gate insulating film 7 ′, which is a thermal oxide film, is densified in advance. In this state, the gate insulating film 7 ′ is in a state where the V group element introduction treatment is not performed.

Next, in the step shown in FIG. 4B, the silicon carbide-oxide stack A is moved into a chamber 30 provided with an exclusion device (not shown) and a vacuum pump 31 as a decompression device. While reducing the pressure in the chamber 30 to about 150 Torr (2.0 × 10 ⁴ Pa) by the vacuum pump 31, NO gas (or nitrogen other than phosphorus (P) or the like other than nitrogen gas having a flow rate of 500 (ml / min) is contained in the chamber 30. A group V element-containing gas is flown, and the inside of the chamber 30 is heated to a sufficiently high temperature (for example, about 1150 ° C.) so that nitrogen (N) (or a group V element other than nitrogen) diffuses into the gate insulating film 7 ′. To do. At this time, by exposing the gate insulating film 7 ′ to a group V element-containing gas such as nitrogen under reduced pressure, a group V element such as nitrogen diffuses into the gate insulating film 7, and the relative dielectric constant is larger. Gate insulating film 7 which is a dense V group element-containing oxide layer is formed. The exposure is sufficient for forming a dense group V element-containing oxide layer, and for a time sufficient for improving the characteristics of the gate insulating film 7 (group V element-containing oxide layer) (for example, 1 Hr). For the duration.

FIG. 5 is data showing a nitrogen concentration profile in which the nitrogen concentration in the thickness direction of the gate insulating film 7 which is the V group element-containing oxide layer formed by the manufacturing method of the present embodiment is measured by SIMS. In the data shown in the figure, the thickness of the gate insulating film 7 (group V element-containing oxide layer) is about 50 nm. As shown in the figure, nitrogen is diffused in the gate insulating film 7 (group V element-containing oxide layer) by the exposure treatment to NO gas, and in particular, the gate insulating film 7 (group V element-containing). A sharp peak portion having a nitrogen concentration of 6 × 10 ²⁰ atoms / 10 ³ appears in a region near the underlying SiC layer (source region 6 or P ⁺ contact region 11) in the oxide layer). And the dimension of the thickness direction of a peak part is 3 nm in a half value width. The relative dielectric constant of the entire gate insulating film 7 (group V element-containing oxide layer) is about 3.3.

FIG. 6 shows the concentration of the nitrogen concentration peak (region near the SiO ₂ -SiC interface) in a sample different from the sample from which the data shown in FIG. 5 was collected and in which the thickness of the V group-containing oxide layer was increased. It is a figure which extracts and shows distribution. The data shown in the figure is obtained by quantifying nitrogen at the SiO ₂ -SiC interface with CsN ¹⁴⁷ .

  As shown in the figure, the half-value width of this peak portion is 3 nm, and it can be seen that nitrogen is intensively introduced at a high concentration in a very narrow region. The full width at half maximum of the peak portion is preferably 5 nm or less.

  Thus, by introducing a group V element such as nitrogen or phosphorus (P) into the oxide layer, a group V element-containing oxide layer having a high relative dielectric constant can be formed. And according to the MISFET having the gate insulating film 7 which is the V group element-containing oxide layer of the present embodiment, the gate bias can be efficiently applied to the underlayer, and a high current driving force can be realized.

  Even when a MIS capacitor using a group V element-containing oxide layer as a capacitive insulating film is formed, a MIS capacitor having a high relative dielectric constant is formed on the SiC substrate.

  FIG. 7 shows a MIS capacitor (gate electrode 10, gate insulating film 7 and channel layer 5) provided with a gate insulating film 7 (group V element-containing oxide layer) formed by the method of this embodiment as a capacitive insulating film. It is a figure which shows the result of CV measurement of a capacitor. The horizontal axis of the figure represents the voltage between the electrodes, and the vertical axis of the figure represents the capacitance. This sample undergoes a heat treatment at 950 ° C. or higher when the gate electrode 10 that is the upper electrode of the capacitor is formed on the gate insulating film 7 that is the V-group element-containing oxide layer. Comparing the Quasi-static CV curve in the figure with the CV curve measured at a high frequency (1 MHz), it can be seen that the interface state density is reduced because the difference between the two is slight.

FIGS. 8A to 8B are diagrams showing the interface state density calculated by the High-Low method based on the data shown in FIG. 8A and 8B, the horizontal axis represents the potential difference (E-Ev (eV)) from the valence band Ev, and the vertical axis represents the interface state density Dit (cm ⁻² eV). ^-1 ). When the carrier is an electron (N-channel MISFET), the interface state acting as a trap is an interface state in the potential range (E-Ev = 2.95 eV to 3.05 eV) near the end of the conduction band. When the carrier is a hole (P channel type MISFET), the interface state acting as a hole trap is the interface state in the potential range (E-Ev = 0.3 eV to 0.4 eV) near the edge of the valence band. However, as shown in FIGS. 8A to 8B, in this embodiment, an interface state density of 1 × 10 ¹² cm ⁻² · eV ⁻¹ or less is obtained in the potential range near each band edge. ing. The average concentration of nitrogen in the entire gate insulating film 7 (group V element-containing oxide layer) is 8.3 × 10 ¹⁹ cm ⁻³ .

  Thus, when a MIS capacitor having a group V element-containing oxide layer as a capacitive insulating film is configured, the interface state density in the region near the interface between the capacitive insulating film and the SiC layer as the lower electrode is reduced. You can see that you can.

  Therefore, even when a MISFET is formed using a MIS capacitor, the carrier mobility can be improved by reducing the interface state density that becomes a carrier trap.

In particular, the maximum value of the nitrogen concentration in the lower portion of the gate insulating film 7 which is a V group element-containing oxide layer is 1 × 10 ²⁰ cm ⁻³ or more and 1 × 10 ²² cm ⁻³ or less, so The effect of improving the rate and the effect of reducing the interface state density are remarkably obtained.

-Preferred conditions in the step shown in Fig. 4 (b)-
Examples of the gas containing nitrogen used in FIG. 4B include NO gas, N ₂ O gas, NO ₂ gas, PH ₃ gas, and the like, and particularly by using NO gas or N ₂ O gas. Great effect. That is, the gas that is actually optimal as the gas containing nitrogen is NO gas and N ₂ O gas, and these are also gases containing oxygen. In that case, the following conditions are preferable from the viewpoint of suppressing oxidation of the underlying SiC layer.

[Pressure conditions]
FIG. 9 is a diagram showing the pressure dependence of the channel mobility of the MISFET of the first embodiment in NO annealing. This figure is a graph of data on a sample that was annealed by changing the temperature between 1050 ° C. and 1150 ° C. FIG. Further, the channel mobility is the highest when the gate bias is 5 V to 20 V, and is data in the vicinity thereof.

As shown in the figure, high channel mobility is obtained in a range (preferable range) of 50 Torr to 400 Torr (6.67 × 10 ³ Pa to 5.33 × 10 ⁴ Pa)). The reason why the peak position is about 150 Torr (2.0 × 10 ⁴ Pa) will be described below.

  When the SiC layer is thermally oxidized in the step shown in FIG. 4B or when the oxide is deposited, a single crystal SiC substrate or an epilayer (epitaxially grown SiC layer) is usually used. Along the silicon face and carbon face, or along one of the A axes perpendicular to these faces (eg, [1 1 2 0] direction or [1 1 0 0] direction) Supplied. Carbon (C) oxidizes somewhat more easily than silicon (Si) (and therefore is faster if all other factors are substantially equal), and oxidation on the carbon surface occurs at temperatures between 900 ° C and 1300 ° C. The oxidation on the silicon surface proceeds at a temperature of about 1000 ° C. to 1400 ° C.

  Therefore, in the step shown in FIG. 4B, even when a gas containing oxygen is used as the gas containing nitrogen, the oxidation on the carbon surface proceeds at a temperature of 900 ° C. to 1300 ° C., and on the silicon surface. Oxidation proceeds at a temperature of 1000 ° C to 1400 ° C. The same applies when a gas containing a group V element other than nitrogen is used.

As described above, in an atmosphere containing oxygen, it is generally observed that SiC is thermally oxidized at a temperature of 900 ° C. or higher. However, even at a high temperature of 900 ° C. or higher, oxidation is suppressed on both the carbon surface and the silicon surface under reduced pressure. In particular, under a pressure of 400 Torr (5.33 × 10 ⁴ Pa) or less, oxidation proceeds and the effect of improving channel mobility decreases. In particular, when the oxide layer (gate insulating film 7 ′) is annealed using a gas that also contains oxygen as a gas containing nitrogen, such as NO gas in the present embodiment, the pressure is reduced under a reduced pressure, particularly 400 Torr. It is preferable to carry out under a pressure of (5.33 × 10 ⁴ Pa) or less. However, since the diffusion of nitrogen into the oxide layer (gate insulating film 7 ′) is suppressed under a low pressure atmosphere, it is performed under a pressure of 50 Torr (6.67 × 10 ³ Pa) or more. preferable. Therefore, the treatment for exposing the oxide layer to the nitrogen-containing gas shown in FIG. 4B is performed under a pressure in the range of 6.67 × 10 ³ Pa to 5.33 × 10 ⁴ Pa. preferable.

However, the partial pressure of the V element-containing gas is 6.67 × 10 ³ even in a reduced-pressure atmosphere in which an inert gas (Ar or N ₂ gas) is also flowed and the pressure of the whole atmosphere is at or near atmospheric pressure. The same effect can be exhibited if it is in the range of Pa to 5.33 × 10 ⁴ Pa or less.

[Temperature conditions]
FIG. 10 is a diagram showing the NO annealing temperature dependence of the channel mobility of the MISFET of the first embodiment. The data in this figure is for a sample that was annealed under conditions of an annealing time of 1 hour and a pressure of 150 Torr (2.00 × 10 ⁴ Pa). As shown in the figure, a relatively high channel mobility is obtained in the range of more than 1100 ° C. and less than 1250 ° C., more preferably in the range of 1150 ° C. to 1200 ° C. The reason will be described below.

  In general, it is known that when an exposure treatment to a gas containing nitrogen is performed at a temperature exceeding 1100 ° C., nitrogen is quickly diffused into the oxide layer (gate insulating film 7 ′). However, in order to suppress diffusion of oxygen into the oxide layer, the temperature is preferably 1250 ° C. or lower.

FIG. 11 is a diagram showing the NO annealing temperature dependence of the interface state density of the MISFET of the first embodiment. The data in the figure shows the interface state at the potential position (E-Ev) of 3.0 eV for the sample annealed under the conditions of an annealing time of 1 hour and a pressure of 150 Torr (2.00 × 10 ⁴ Pa). The density is shown. As shown in the figure, the interface state density is very small in the range of more than 1100 ° C. and less than 1250 ° C., more preferably in the range of 1150 ° C. to 1200 ° C. It can be seen that the degree is obtained.

  Therefore, a preferable temperature range in the step shown in FIG. 4B is 1100 ° C. to 1250 ° C., and more preferably 1150 ° C. to 1200 ° C. The same applies when using a group V element other than nitrogen, such as phosphorus (P).

  Furthermore, generally, the surface roughness of the oxide layer hardly occurs at 1300 ° C. or lower.

In the above embodiment, the oxide layer (gate insulating film 7 ′) on the SiC layer (channel layer 5, source region 6 and P ⁺ contact region 11) is formed by thermal oxidation, but the oxide layer is not necessarily heated. It is not necessary to form by an oxidation method. Other methods [for example, low pressure chemical vapor deposition (LPCVD) using silane bath (SiH ₄ ) and oxygen (O ₂ ), formation of oxide layers by plasma vapor deposition, CVD, vapor deposition, thermal oxidation The combination can also be used to deposit an oxide layer on the SiC layer.

  Although the storage type MISFET has been described in the present embodiment, it is merely for evaluating the interface state density itself based on the channel mobility of the storage type MISFET. Therefore, it can be seen that a high channel mobility can be obtained also in the inverting MISFET according to the conditions of the present embodiment.

(Second Embodiment)
In the present embodiment, the structure of the silicon carbide-oxide stacked body is basically the same as that of the first embodiment, and thus description thereof will be omitted and only the manufacturing process will be described.

In the present embodiment, a first oxide layer is formed on the surface of the SiC layer before the step shown in FIG. At this time, the thickness of the first oxide layer is preferably less than 20 nm, for example, about 8 nm. Thereafter, annealing is performed at a temperature of 1000 ° C. or higher (eg, 1000 ° C. to 1150 ° C.) in an inert gas (Ar, N ₂ , He, Ne, etc.) atmosphere. By this annealing treatment, the first oxide layer is densified in advance.

Next, in a gas containing nitrogen such as NO gas, N ₂ O gas, or a gas containing phosphorus (P), for example, under the conditions of 1150 ° C. and the pressure in the chamber being 150 Torr (about 2.00 × 10 ⁴ Pa), Annealing is performed for 1 hour.

Next, by ECR-pCVD at a temperature of about 300 ° C., a second oxide layer (for example, SiO ₂ , SiN, HfO _2, etc.) having a thickness of about 75 nm is formed on the first oxide layer. High dielectric film).

  Thereafter, annealing is performed at a temperature of 900 ° C. to 1100 ° C. (eg, 1000 ° C.) in an inert gas atmosphere (eg, Ar atmosphere) for about 1 hour.

  FIG. 12 is a diagram showing a result of CV measurement of a MIS capacitor provided with a group V element-containing oxide layer formed by the method of the second embodiment as a capacitive insulating film. The horizontal axis of the figure represents the voltage between the electrodes, and the vertical axis of the figure represents the capacitance. Comparing the experimental curve and the theoretical curve in the figure, it can be seen that the interface state density is reduced because the difference between the two is small.

  Therefore, also by the method of the second embodiment, the same effect as that of the first embodiment can be obtained by reducing the interface state density by the V group element-containing oxide layer composed of the first and second oxide layers. It can be demonstrated.

  In addition, according to the manufacturing method of the present embodiment, a high-quality silicon carbide-oxide stack can be obtained even when a V-group element-containing oxide layer having a thickness exceeding 40 nm is formed.

  The silicon carbide-oxide laminate of the present invention and the manufacturing method thereof can be used for manufacturing vertical and horizontal MISFET power devices and MIS capacitors.

(A)-(c) is sectional drawing which shows the structure of the inversion type MISFET using the SiC substrate which concerns on the 1st Embodiment of this invention. (A)-(e) is sectional drawing which shows the first half part in the manufacturing process of MISFET of 1st Embodiment. (A)-(e) is sectional drawing which shows the latter half part in the manufacturing process of MISFET of 1st Embodiment. (A)-(b) is sectional drawing which shows the procedure which forms the V group element containing oxide layer in 1st Embodiment. It is data which shows the nitrogen concentration profile which measured the nitrogen concentration in the thickness direction of the oxide layer formed by the manufacturing method of a 1st embodiment by SIMS. It is a diagram illustrating only the concentration distribution of the peak portion of the nitrogen concentration (area near SiO ₂ -SiC interface). It is a figure which shows the result of the CV measurement of the MIS capacitor provided with the gate insulating film (V group element containing oxide layer) formed by the method of 1st Embodiment as a capacitive insulating film. (A)-(b) is a figure which shows the interface state density calculated by the High-Low method based on the data shown in FIG. It is a figure which shows the pressure dependence in NO annealing of the channel mobility of MISFET of 1st Embodiment. It is a figure which shows NO annealing temperature dependence of the channel mobility of MISFET of 1st Embodiment. It is a figure which shows NO annealing temperature dependence of the interface state density of MISFET of 1st Embodiment. It is a figure which shows the result of the CV measurement of the MIS capacitor provided with the V group element containing oxide layer formed by the method of 2nd Embodiment as a capacity | capacitance insulating film.

Explanation of symbols

10 SiC substrate 11 Oxide layer 12 Group V element-containing oxide layer 20 Chamber 30 Chamber 31 Vacuum pump

Claims (17)

A silicon carbide layer;
Silicon carbide formed on the silicon carbide layer and having a group V element-containing oxide layer having at least a region having a high group V element concentration and a relative dielectric constant of 3.0 or more An oxide laminate. In the silicon carbide-oxide laminate according to claim 1,
A silicon carbide-oxide stacked body, wherein a half value width of a peak portion in a V group element concentration distribution at a lower portion of the V group element-containing oxide layer is 5 nm or less. In the silicon carbide-oxide laminate according to claim 1 or 2,
The group V element-containing oxide layer is a silicon carbide-oxide stack in which a base material is composed of SiO ₂ . In the silicon carbide-oxide laminate according to any one of claims 1 to 3,
The group V element is nitrogen or phosphorus,
A silicon carbide-oxide stack in which the maximum value of the group V element concentration in the lower portion of the group V element-containing oxide layer is 1 × 10 ²⁰ cm ⁻³ or more and 1 × 10 ²² cm ⁻³ or less. In the silicon carbide-oxide laminate according to any one of claims 1 to 4,
The interface state density in the region near the boundary between the V group element-containing oxide layer and the silicon carbide layer is 1 × 10 ¹² cm in the potential range near the band edge of at least one of the conduction band and the valence band. ^-3 / eV or less, a silicon carbide-oxide laminate. A silicon carbide layer, a V group element-containing oxide layer formed on the silicon carbide layer and having a region having a high V group element concentration at least below, and at least a part of the V group element containing oxide layer A semiconductor device comprising a gate electrode provided in
The silicon carbide layer is
A first conductivity type impurity diffusion region functioning as at least one of a source region and a drain region;
A channel region located on the side of the impurity diffusion region;
A second conductivity type contact region provided at a position facing the channel region across the impurity diffusion region and having a surface portion removed by etching;
The group V element-containing oxide layer includes a gate oxide film provided on the channel region. Forming an oxide layer on the surface of the silicon carbide layer (a);
After the step (a), the silicon carbide layer is placed in a chamber, and the oxide layer is exposed to an atmosphere containing a group V element-containing gas in a temperature range higher than 1100 ° C. and lower than 1250 ° C. And a step (b) of changing the oxide layer into a V group element-containing oxide layer having a relative dielectric constant of 3.0 or more. In the manufacturing method of the silicon carbide-oxide laminated body of Claim 7,
The said process (b) is a manufacturing method of the silicon carbide-oxide laminated body performed in the atmosphere pressure-reduced to the range of 6.67 * 10 < ³ > Pa or more and 5.33 * 10 < ⁴ > Pa or less. In the manufacturing method of the silicon carbide-oxide laminated body of Claim 7 or 8,
In the step (b), the pressure of the atmosphere containing the group V element-containing gas is atmospheric pressure, and the partial pressure of the group V element-containing gas is 6.67 × 10 ³ Pa or more and 5.33 × 10 ⁴ Pa or less. A method for producing a silicon carbide-oxide laminate, which is performed in an atmosphere in a range of In the manufacturing method of the silicon carbide-oxide laminated body as described in any one of Claims 7-9,
In the step (a), the oxide layer is formed by thermal oxidation, and then annealing is performed in an inert gas atmosphere. In the manufacturing method of the silicon carbide-oxide laminated body of Claim 10,
In the step (a), after annealing in the inert gas atmosphere, a process of further oxidizing in an oxidizing gas atmosphere at a temperature of 850 ° C. or higher and 950 ° C. or lower is further performed. Production method. In the manufacturing method of the silicon carbide-oxide laminated body as described in any one of Claims 7-11,
The said group V element containing gas is a manufacturing method of the silicon carbide-oxide laminated body in which nitrogen or phosphorus is included. In the manufacturing method of the silicon carbide-oxide laminated body of Claim 12,
A method for producing a silicon carbide-oxide laminate, wherein at least one gas selected from NO gas, N ₂ O gas, NO ₂ gas, and PH ₃ gas is used as the group V element-containing gas. Forming a first oxide layer on the surface of the silicon carbide layer (a);
(B) after the step (a), placing the silicon carbide layer in a chamber and exposing the oxide layer to a gas atmosphere containing a group V element-containing gas;
(C) depositing a second oxide layer on the first oxide layer after the step (b);
After the step (c), the oxide layer composed of the first oxide layer and the second oxide layer is compared by annealing in an inert gas atmosphere at a temperature of 900 ° C. to 1100 ° C. And a step (d) of changing to a group V element-containing oxide layer having a dielectric constant of 3.0 or more. In the manufacturing method of the silicon carbide-oxide laminated body of Claim 14,
The said process (b) is a manufacturing method of the silicon carbide-oxide laminated body performed in the atmosphere pressure-reduced to the range of 6.67 * 10 < ³ > Pa or more and 5.33 * 10 < ⁴ > Pa or less. In the manufacturing method of the silicon carbide-oxide laminated body of Claim 14 or 15,
In the step (a), a method for producing a silicon carbide-oxide laminate, wherein a thermal oxide film having a thickness of less than 20 nm is formed. In the manufacturing method of the silicon carbide-oxide laminated body as described in any one of Claims 14-16,
In the step (b), at least one gas selected from NO gas, N ₂ O gas, NO ₂ gas, and PH ₃ gas is used as the group V element-containing gas. Production method.

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