JP7054403B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device using SiC.

In recent years, the use of SiC (silicon carbide: silicon carbide) has been studied as a next-generation power device material that realizes high withstand voltage and low on-resistance.
Further, a trench gate structure is known as a structure for miniaturizing a power device and reducing on-resistance. For example, power MOSFETs that employ a trench gate structure are becoming mainstream.

FIG. 11 is a schematic cross-sectional view of a semiconductor device having a conventional trench gate type VD MOSFET in which SiC is used.
The semiconductor device 201 has a structure in which unit cells of a trench gate type VD MOSFET are arranged in a matrix.
The semiconductor device 201 includes an N ⁺ type SiC substrate 202 that forms a substrate of the semiconductor device 201. An N ^- type epitaxial layer 203 made of SiC (silicon carbide: silicon carbide) doped with N-type impurities at a lower concentration than that of the SiC substrate 202 is laminated on the Si surface (silicon surface) of the SiC substrate 202. Has been done. The base layer portion of the epitaxial layer 203 forms an N ^- type drain region 204 in which the state after the epitaxial growth is maintained. Further, in the epitaxial layer 203, a P-shaped body region 205 is formed on the drain region 204 in contact with the drain region 204.

A gate trench 206 is formed in the epitaxial layer 203 by digging from its surface 217 (Si surface). The gate trench 206 penetrates the body region 205 in the layer thickness direction, and the deepest portion (bottom surface 216) thereof reaches the drain region 204.
In the gate trench 206, a gate insulating film 207 made of SiO ₂ is formed over the entire inner surface of the gate trench 206 by thermally oxidizing the side surface 214 and the bottom surface 216 of the gate trench 206.

The gate electrode 208 is embedded in the gate trench 206 by filling the inside of the gate insulating film 207 with polysilicon doped with a high concentration of N-type impurities.
On the surface layer portion of the epitaxial layer 203, N ⁺ type source regions 209 are formed on both sides in a direction orthogonal to the gate width (left-right direction in FIG. 11) with respect to the gate trench 206. The source region 209 extends along the gate trench 206 in the direction along the gate width, and its bottom portion is in contact with the body region 205 from the surface 217 side of the epitaxial layer 203.

Further, the epitaxial layer 203 is formed with a P ⁺ type body contact region 210 that penetrates the central portion of the source region 209 in the direction orthogonal to the gate width from the surface 217 and is connected to the body region 205. ..
An interlayer insulating film 211 made of SiO ₂ is laminated on the epitaxial layer 203. The source wiring 212 is formed on the interlayer insulating film 211. The source wiring 212 is formed on the nickel silicide layer 218 and the nickel silicide layer 218 that are in contact with the source region 209 and the body contact region 210 via the contact holes 213 formed in the interlayer insulating film 211 and the gate insulating film 207. It has an aluminum layer 219 and the like.

A drain wiring 215 is formed on the back surface (carbon surface: C surface) of the SiC substrate 202. The drain wiring 215 has a nickel silicide layer 220 in contact with the SiC substrate 202 and an aluminum layer 221 formed on the nickel silicide layer 220.
A gate is obtained by applying a predetermined voltage (voltage equal to or higher than the gate threshold voltage) to the gate electrode 208 in a state where a predetermined potential difference is generated between the source wiring 212 and the drain wiring 215 (between the source and the drain). The electric field from the electrode 208 forms a channel in the vicinity of the interface with the gate insulating film 207 in the body region 205. As a result, a current flows between the source wiring 212 and the drain wiring 215, and the VD MOSFET is turned on.

JP-A-2007-258465

In the method for manufacturing a semiconductor device according to an embodiment of the present invention, a body forming region in which a second conductive type ion is selectively injected into a surface layer portion and a first conductive type ion are selected in a surface layer portion of the body forming region. The first step of forming a carbon film on the surface of a first conductive type SiC semiconductor layer having a source forming region in which the carbon film is formed, and heating the SiC semiconductor layer on which the carbon film is formed to form the body. By activating the ions in the region and the source forming region, the surface layer portion of the SiC semiconductor layer has a second conductive type body region, and the surface layer portion of the body region has a first conductive type source region and the body region. On the other hand, a second step of forming a first conductive type drain region on the back surface side of the SiC semiconductor layer, and a third step of removing the carbon film and oxidizing the SiC semiconductor layer to form a gate oxide film. And include .

FIG. 1 is a schematic cross-sectional view of a semiconductor device according to the first embodiment of the present invention. FIG. 2A is a schematic cross-sectional view for explaining a method for manufacturing the semiconductor device shown in FIG. FIG. 2B is a diagram showing the next step of FIG. 2A. FIG. 2C is a diagram showing the next step of FIG. 2B. FIG. 2D is a diagram showing the next step of FIG. 2C. FIG. 2E is a diagram showing the next step of FIG. 2D. FIG. 2F is a diagram showing the next step of FIG. 2E. FIG. 2G is a diagram showing the next step of FIG. 2F. FIG. 2H is a diagram showing the next step of FIG. 2G. FIG. 2I is a diagram showing the next step of FIG. 2H. FIG. 2J is a diagram showing the next step of FIG. 2I. FIG. 2K is a diagram showing the next step of FIG. 2J. FIG. 2L is a diagram showing the next step of FIG. 2K. FIG. 2M is a diagram showing the next step of FIG. 2L. FIG. 2N is a diagram showing the next step of FIG. 2M. 3 (a) and 3 (b) are schematic plan views of the semiconductor device according to the second embodiment of the present invention, FIG. 3 (a) is an overall view, and FIG. 3 (b) is an internal enlarged view. show. FIG. 4 is a schematic cross-sectional view of the semiconductor device according to the second embodiment of the present invention, showing a cut surface at the cut line IV-IV of FIG. 3 (b). FIG. 5A is a schematic cross-sectional view for explaining a method for manufacturing the semiconductor device shown in FIG. FIG. 5B is a diagram showing the next step of FIG. 5A. FIG. 5C is a diagram showing the next step of FIG. 5B. FIG. 5D is a diagram showing the next step of FIG. 5C. FIG. 5E is a diagram showing the next step of FIG. 5D. FIG. 5F is a diagram showing the next step of FIG. 5E. FIG. 5G is a diagram showing the next step of FIG. 5F. FIG. 5H is a diagram showing the next step of FIG. 5G. FIG. 5I is a diagram showing the next step of FIG. 5H. FIG. 5J is a diagram showing the next step of FIG. 5I. FIG. 5K is a diagram showing the next step of FIG. 5J. FIG. 5L is a diagram showing the next step of FIG. 5K. FIG. 5M is a diagram showing the next step of FIG. 5L. FIG. 5N is a diagram showing the next step of FIG. 5M. FIG. 5O is a diagram showing the next step of FIG. 5N. FIG. 5P is a diagram showing the next step of FIG. 5N. FIG. 5Q is a diagram showing the next step of FIG. 5N. FIG. 5R is a diagram showing the next step of FIG. 5N. FIG. 5S is a diagram showing the next step of FIG. 5N. FIG. 5T is a diagram showing the next step of FIG. 5N. FIG. 5U is a diagram showing the next step of FIG. 5N. FIG. 6 is a graph showing the temperature change in the resistance heating furnace. It is a schematic cross-sectional view for demonstrating the modification of the semiconductor device shown in FIG. FIG. 8 is a schematic cross-sectional view of a planar gate type semiconductor device. 9A is a schematic cross-sectional view illustrating the method for manufacturing the semiconductor device of FIG. 9B is a schematic cross-sectional view showing the next step of FIG. 9A. 9C is a schematic cross-sectional view showing the next step of FIG. 9B. 9D is a schematic cross-sectional view showing the next step of FIG. 9C. 9E is a schematic cross-sectional view showing the next step of FIG. 9D. 9F is a schematic cross-sectional view showing the next step of FIG. 9E. FIG. 9G is a schematic cross-sectional view showing the next step of FIG. 9F. 9H is a schematic cross-sectional view showing the next step of FIG. 9G. 9I is a schematic cross-sectional view showing the next step of FIG. 9H. 9J is a schematic cross-sectional view showing the next step of FIG. 9I. 9K is a schematic cross-sectional view showing the next step of FIG. 9J. 9L is a schematic cross-sectional view showing the next step of FIG. 9K. 10 (a), (b) and (c) are graphs in which the thickness of the oxide film is plotted for each oxidation gas supply time, (a) is a graph of Reference Example 1, and (b) is a graph of Reference Example 2. The graph of (c) and (c) show the graph of Reference Example 3, respectively. FIG. 11 is a schematic cross-sectional view of a semiconductor device having a conventional trench gate type VD MOSFET in which SiC is used.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic cross-sectional view of a semiconductor device according to the first embodiment of the present invention.
The semiconductor device 1 has a structure in which unit cells of a trench gate type VD MOSFET are arranged in a matrix. Note that FIG. 1 shows a part of the plurality of unit cells.

The semiconductor device 1 includes a SiC substrate 2 that forms a substrate of the semiconductor device 1. The SiC substrate 2 is doped with N-type impurities at a high concentration (for example, 1e18 to 1e21cm ^-3 ). The surface surface 21 (upper surface) of the SiC substrate 2 is the Si surface, and the back surface (lower surface) thereof is the C surface.
An N ^- type epitaxial layer 3 made of SiC (silicon carbide: silicon carbide) doped with N-type impurities at a lower concentration than that of the SiC substrate 2 is laminated on the surface 21 of the SiC substrate 2. The epitaxial layer 3 as a semiconductor layer is formed on the SiC substrate 2 by so-called epitaxial growth. The epitaxial layer 3 formed on the surface 21 which is the Si surface is grown with the Si surface as the main growth surface. Therefore, the surface 31 of the epitaxial layer 3 formed by growth is a Si surface like the surface 21 of the SiC substrate 2.

The portion of the epitaxial layer 3 on the C-plane side (base layer portion) opposite to the portion on the Si-plane side (surface layer portion) has an N ^- type drain region 4 in which the entire region is maintained in the state after epitaxial growth. No. The concentration of N-type impurities in the drain region 4 is, for example, 1e15 to 1e17 cm ^-3 .
On the other hand, a P-shaped body region 5 is formed on the surface layer portion of the epitaxial layer 3. The body region 5 is in contact with the drain region 4 from the surface 31 side (Si surface side) of the epitaxial layer 3. The concentration of P-type impurities in the body region 5 is, for example, 1e16 to 1e19 cm ^-3 .

A gate trench 6 is formed in the epitaxial layer 3 by digging from the surface 31. Although not shown in FIG. 1, a plurality of gate trenches 6 are formed at regular intervals, and they are parallel to each other and have the same direction (direction perpendicular to the paper surface of FIG. 1, hereinafter, this direction is referred to as “gate width”. It extends in the direction along the line, for example, and has a striped structure.

Each gate trench 6 has a pair of planar side surfaces 7 facing each other at intervals and each orthogonal to the surface 31, and a bottom surface 8 having a portion parallel to the surface 31. The gate trench 6 penetrates the body region 5 in the layer thickness direction, and the deepest portion (bottom surface 8) thereof reaches the drain region 4.
A gate insulating film 9 is formed on the inner surface of the gate trench 6 and the surface 31 of the epitaxial layer 3 so as to cover the entire inner surface (side surface 7 and bottom surface 8) of the gate trench 6. The gate insulating film 9 is made of a nitrogen-containing oxide film, for example, a silicon nitride film formed by thermal oxidation using a nitrogen-containing gas. The nitrogen content (nitrogen concentration) in the gate insulating film 9 is, for example, 0.1 to 10%.

Further, in the gate insulating film 9, the thickness T ₂ of the portion on the bottom surface 8 (insulating film bottom portion 11) is smaller than the thickness T ₁ of the portion on the side surface 7 (insulating film side portion 10). Specifically, the ratio of the thickness T ₂ of the insulating film bottom 11 to the thickness T ₁ of the insulating film side 10 (thickness T ₂ of the insulating film bottom 11 / thickness T ₁ of the insulating film side 10) is , 0.3 to 1.0, preferably 0.5 to 1.0. The specific size of both thicknesses is, for example, that the thickness T ₁ of the insulating film side portion 10 is 300 to 1000 Å and the thickness T ₂ of the insulating film bottom portion 11 is 150 to 500 Å.

The gate electrode 12 is embedded in the gate trench 6 by filling the inside of the gate insulating film 9 with a polysilicon material doped with a high concentration of N-type impurities.
On the surface layer portion of the body region 5, N ⁺ -shaped source regions 13 are formed on both sides in a direction orthogonal to the gate width (left-right direction in FIG. 1) with respect to the gate trench 6. The source region 13 is a region in which the concentration of N-type impurities is higher than that of the drain region 4 and the concentration of N-type impurities is high. The concentration of N-type impurities in the source region 13 is, for example, 1e18 to 1e21cm ^-3 . The source region 13 extends in a direction along the gate width at a position adjacent to the gate trench 6.

Further, the epitaxial layer 3 is formed with a P ⁺ type body contact region 14 that penetrates the central portion of the source region 13 in the direction orthogonal to the gate width from the surface 31 and is connected to the body region 5. .. The body contact region 14 is a region in which the P-type impurity concentration is higher than that of the body region 5 and the P-type impurity is doped at a high concentration. The concentration of P-type impurities in the body contact region 14 is, for example, 1e18 to 1e21cm ^-3 .

That is, the gate trench 6 and the source region 13 are alternately provided in a direction orthogonal to the gate width, and each extends in a direction along the gate width. Then, on the source region 13, a boundary between unit cells adjacent to each other in a direction orthogonal to the gate width is set along the source region 13. At least one body contact region 14 is provided between two unit cells adjacent to each other in a direction orthogonal to the gate width. Further, the boundary between the unit cells adjacent to each other in the direction along the gate width is set so that the gate electrode 12 included in each unit cell has a constant gate width.

An interlayer insulating film 15 made of SiO ₂ is laminated on the epitaxial layer 3. The interlayer insulating film 15 and the gate insulating film 9 are formed with contact holes 16 that expose the surfaces of the source region 13 and the body contact region 14.
The source wiring 17 is formed on the interlayer insulating film 15. The source wiring 17 is contacted (electrically connected) to the source region 13 and the body contact region 14 via the contact hole 16. The source wiring 17 has a polysilicon layer 18 at a contact portion with the source region 13 and the body contact region 14, and has a metal layer 20 on the polysilicon layer 18.

The polysilicon layer 18 is a dope layer formed by using an impurity-doped doped layer, for example, a high-concentration doped layer in which impurities are doped at a high concentration of 10 ¹⁹ to 10 ²¹ cm ^-3 . It is preferable to have. As impurities when the polysilicon layer 18 is formed as a doping layer (including a high-concentration doping layer), N-type impurities such as phosphorus (P) and As ( _arsenic ) and P-type impurities such as B (boron) are used. Can be used. Further, the polysilicon layer 18 fills the contact hole 16. The thickness of such a polysilicon layer 18 varies depending on the depth of the contact hole 16, and is, for example, 5000 to 10000 Å.

The metal layer 20 is formed by using, for example, aluminum (Al), gold (Au), silver (Ag), copper (Cu), alloys thereof, and a metal material containing them. The metal layer 20 forms the outermost layer of the source wiring 17, and for example, a metal wire or the like is connected (bonded). The thickness of the metal layer 20 is, for example, 1 to 5 μm.
In the source wiring 17, an intermediate layer 19 containing titanium is interposed between the polysilicon layer 18 and the metal layer 20. The intermediate layer 19 is composed of a single layer of a layer containing titanium (Ti) or a plurality of layers having the layer. The layer containing titanium can be formed by using titanium, titanium nitride or the like. The thickness of the intermediate layer 19 is, for example, 200 to 500 nm.

The source wiring 17 having the polysilicon layer 18, the intermediate layer 19 and the metal layer 20 as described above includes polyvinyl (polysilicon layer 18), titanium (intermediate layer 19), titanium nitride (intermediate layer 19) and aluminum (metal). It is preferable to have a laminated structure (Po—Si / Ti / TiN / Al) in which the layers 20) are laminated in order.
A drain wiring 23 is formed on the back surface 22 of the SiC substrate 2. The drain wiring 23 is in contact (electrically connected) to the SiC substrate 2. The drain wiring 23 has a polysilicon layer 24 at a contact portion with the SiC substrate 2, and has a metal layer 26 on the polysilicon layer 24.

The polysilicon layer 24 can be formed by using the same material as the material constituting the polysilicon layer 18 described above. Further, the thickness of the polysilicon layer 24 is, for example, 1000 to 2000 Å.
The metal layer 26 can be formed by using the same material as the material constituting the metal layer 20 described above. The metal layer 26 forms the outermost layer of the drain wiring 23, and is bonded to the die pad, for example, when the SiC substrate 2 is bonded to the die pad of the lead frame. The thickness of the metal layer 26 is, for example, 0.5 to 1 μm.

In the drain wiring 23, an intermediate layer 25 containing titanium is interposed between the polysilicon layer 24 and the metal layer 26. The intermediate layer 25 can be formed by using the same material as the material constituting the intermediate layer 19 described above.
The gate wiring 27 is contacted (electrically connected) to the gate electrode 12 via a contact hole (not shown) formed in the interlayer insulating film 15.

When a predetermined voltage (voltage equal to or higher than the gate threshold voltage) is applied to the gate wiring 27 in a state where a predetermined potential difference is generated between the source wiring 17 and the drain wiring 23 (between the source and the drain), the gate is gated. The electric field from the electrode 12 forms a channel in the vicinity of the interface with the gate insulating film 9 in the body region 5. As a result, a current flows between the source wiring 17 and the drain wiring 23, and the VD MOSFET is turned on.

2A to 2N are schematic cross-sectional views for explaining a method of manufacturing the semiconductor device shown in FIG. 1.
First, as shown in FIG. 2A, an epitaxial growth method such as a CVD (Chemical Vapor Deposition) method, an LPE (Liquid Phase Epitaxy) method, or an MBE (Molecular Beam Epitaxy) method is used. , SiC crystals are grown on the surface 21 (Si surface) of the SiC substrate 2 while doping impurities. As a result, an N ^- type epitaxial layer 3 is formed on the SiC substrate 2. Subsequently, the P-type impurity is implanted (injected) from the surface 31 of the epitaxial layer 3 into the inside of the epitaxial layer 3. The injection conditions at this time differ depending on the type of P-type impurity, but for example, the acceleration energy is 200 to 400 keV.

As a result, as shown in FIG. 2B, a region (P-type implanter region 28) in which P-type impurities are implanted is formed on the surface layer portion of the epitaxial layer 3. By forming the P-type impla region 28, a drain region 4 that is separated from the P-type impla region 28 and maintains the state after epitaxial growth is formed in the base layer portion of the epitaxial layer 3.
Next, as shown in FIG. 2C, a mask 29 made of SiO ₂ is formed on the epitaxial layer 3 by the CVD method. Subsequently, the mask 29 is etched via a photoresist (not shown) to be patterned into a pattern having an opening 30 in the region where the body contact region 14 should be formed. After the opening 30 is formed, the P-type impurity is implanted (injected) from the surface 31 of the epitaxial layer 3 into the inside of the epitaxial layer 3. The injection conditions at this time differ depending on the type of P-type impurity, but for example, the acceleration energy is 30 to 200 keV. As a result, a region (P ⁺ type implanter region 32) in which P-type impurities are implanted at a high concentration is formed on the surface layer portion of the P-type implanter region 28. After injecting the P-type impurities, the mask 29 is removed.

Next, as shown in FIG. 2D, a mask 33 made of SiO ₂ is formed on the epitaxial layer 3 by a CVD (Chemical Vapor Deposition) method. Subsequently, the mask 33 is etched via a photoresist (not shown) to be patterned into a pattern having an opening 34 in the region where the source region 13 should be formed. After the opening 34 is formed, N-type impurities are implanted (injected) from the surface 31 of the epitaxial layer 3 into the inside of the epitaxial layer 3. The injection conditions at this time differ depending on the type of N-type impurity, but for example, the acceleration energy is 30 to 200 keV. After injecting the N-type impurities, the mask 33 is removed. As a result, a region (N ⁺ type implanter region 35) in which N-type impurities are implanted at a high concentration is formed on the surface layer portion of the P-type implanter region 28.

Then, as shown in FIG. 2E, the epitaxial layer 3 is heat-treated at, for example, 1400 to 2000 ° C. As a result, the injected N-type and P-type impurities are activated to form the body region 5 on the surface layer portion of the epitaxial layer 3, and the source region 13 and the body contact region 14 are formed on the surface layer portion of the body region 5. Will be done.
Next, as shown in FIG. 2F, a mask 36 made of SiO ₂ is formed over the entire surface 31 of the epitaxial layer 3 by a CVD method, a thermal oxidation method, or the like. The mask 36 can also be formed of SiN or the like by using the CVD method.

Then, as shown in FIG. 2G, the mask 36 is etched via a photoresist (not shown) to pattern a pattern having an opening 37 in the region where the gate trench 6 should be formed.
Then, as shown in FIG. 2H, a mixed gas (SF6 / O ₂ gas) containing SF6 (sulfur hexafluoride) and O ₂ (oxygen) is incident on the surface 31 of the epitaxial layer 3 through the opening 37. .. As a result, the epitaxial layer 3 is dry-etched from the surface 31 (Si surface) to form a bottom surface 8 having a portion parallel to the surface 31 (Si surface) and a gate trench 6 having a side surface 7 orthogonal to the Si surface. Will be done. After forming the gate trench 6, the mask 36 is removed.

Next, as shown in FIG. 2I, the SiC substrate 2 is carried into the diffusion furnace, and the nitrogen-containing gas is supplied while the inside of the diffusion furnace is heated, so that the inner surface (side surface 7 and bottom surface 8) of the gate trench 6 is supplied. ) And the surface 31 of the epitaxial layer 3 are thermally oxidized. As the nitrogen _- containing gas, for example, N2O gas, NO gas and the like can be used. The heater temperature (heating temperature) of the diffusion furnace is, for example, 1200 to 1350 ° C., and the supply time (oxidation time) of the nitrogen-containing gas is, for example, 3 to 5 hours. Since the gate trench 6 is formed in the epitaxial layer 3 made of SiC, the oxidation of the inner surface of the gate trench 6 is the oxidation rate of the bottom surface 8 having the Si surface and the oxidation rate of the side surface 7 which is a surface orthogonal to the Si surface. However, the process proceeds under the condition that the relational expression: the oxidation rate of the bottom surface 8 / the oxidation rate of the side surface 7 <0 is satisfied. As a result, the gate insulating film 9 is formed in which the thickness of the portion on the bottom surface 8 (insulating film bottom portion 11) is smaller than the thickness of the portion on the side surface 7 (insulating film side portion 10).

Then, as shown in FIG. 2J, the doped polysilicon material is deposited on the epitaxial layer 3 by the CVD method. The deposited polysilicon material is etched back until the etchback surface is flush with the surface 31 of the epitaxial layer. As a result, the portion outside the gate trench 6 in the polysilicon material is removed, and the gate electrode 12 made of the polysilicon material remaining in the gate trench 6 is formed.

Next, as shown in FIG. 2K, the interlayer insulating film 15 made of SiO ₂ is laminated on the epitaxial layer 3 by the CVD method. Then, by patterning the interlayer insulating film 15 and the gate insulating film 9, a contact hole 16 that exposes the source region 13 and the body contact region 14 is formed in the interlayer insulating film 15 and the gate insulating film 9.
Then, as shown in FIG. 2L, the polysilicon material 38 is deposited by the CVD method until the contact hole 16 is filled.

Then, as shown in FIG. 2M, N-type or P-type impurities are implanted (injected) into the deposited polysilicon material 38. The injection conditions at this time differ depending on the type of impurities, but for example, the acceleration energy is 10 to 100 keV. As a result, the polysilicon layer 18 in which impurities are heavily doped is formed.
Next, as shown in FIG. 2N, titanium and titanium nitride are deposited on the surface of the polysilicon layer 18 in this order by a method such as a sputtering method or a thin-film deposition method to form an intermediate layer 19. Subsequently, aluminum is deposited on the surface of the intermediate layer 19 by a method such as a sputtering method or a thin-film deposition method to form the metal layer 20. Then, the metal layer 20, the intermediate layer 19, and the polysilicon layer 18 are patterned in a predetermined wiring pattern to form the source wiring 17. Subsequently, the gate wiring 27 connected to the gate electrode 12 is formed. After that, the drain wiring 23 having the polysilicon layer 24, the intermediate layer 25, and the metal layer 26 is formed on the back surface 22 of the SiC substrate 2 by the same method as the source wiring 17.

Through the above steps, the semiconductor device 1 shown in FIG. 1 is obtained.
As described above, according to the semiconductor device 1, the gate trench 6 is formed by digging from the surface 31 (Si surface) of the epitaxial layer 3 made of SiC. Therefore, in the oxidation of the inner surface of the gate trench 6, the oxidation rate of the bottom surface 8 having the Si surface and the oxidation rate of the side surface 7 which is a surface orthogonal to the Si surface are related to the relational expression: the oxidation rate of the bottom surface 8 / the oxidation rate of the side surface 7. Proceed under the condition that <0 is satisfied.

In the above manufacturing method, the oxidation of the inner surface of the gate trench 6 is different from the thermal oxidation using oxygen gas (Dry oxidation) and the thermal oxidation using steam ( _H2O ) gas (Wet oxidation), and is a nitrogen-containing gas. It is carried out by thermal oxidation using. Therefore, the ratio of the oxidation rate of the bottom surface 8 to the oxidation rate of the side surface 7 (oxidation rate of the bottom surface 8 / oxidation rate of the side surface 7) should be increased as compared with the case where the gate insulating film is formed by Dry oxidation or Wet oxidation. Can be done.

The gate insulating film 9 thus formed has a ratio of the thickness T ₂ of the insulating film bottom 11 to the thickness T ₁ of the insulating film side portion 10 (thickness T ₂ of the insulating film bottom 11 / insulating film). The thickness T ₁ ) of the side portion 10 is in the range of 0.3 to 1.0.
Even if the thickness T ₂ of the insulating film bottom 11 is increased to the extent that dielectric breakdown can be suppressed, the lower limit of (thickness T ₂ of the insulating film bottom 11 / thickness T 1 of the insulating film side 10) is 0.3. Therefore, it is possible to suppress an excessive increase in the thickness T ₁ of the insulating film side portion 10. On the other hand, since the upper limit is 1.0, the thickness T ₁ of the insulating film side portion 10 does not become excessively small when the thickness T ₂ of the insulating film bottom portion 11 is designed to have an appropriate size. As a result, by appropriately designing the thickness T ₂ of the insulating film bottom portion 11, it is possible to suppress the increase in the thickness T ₁ of the insulating film side portion 10 while suppressing the dielectric breakdown of the insulating film bottom portion 11. can.

Further, since the gate insulating film 9 is made of a silicon nitride film formed by thermal oxidation using a nitrogen-containing gas, the channel mobility of the VD MOSFET can be improved.
3 (a) and 3 (b) are schematic plan views of the semiconductor device according to the second embodiment of the present invention, FIG. 3 (a) is an overall view, and FIG. 3 (b) is an internal enlarged view. show.
The semiconductor device 41 is a trench gate type power VDD MOSFET (individual element) using SiC, and is, for example, a chip shape having a square view in a plan view. The chip-shaped semiconductor device 41 has a length of about several mm in the left-right (up-down) direction on the paper surface of FIG. 3A.

The semiconductor device 41 has a SiC substrate 42 and a large number of unit cells 44 formed on the SiC substrate 42 and partitioned by a planar grid-like gate trench 43. That is, on the SiC substrate 42, the rectangular parallelepiped unit cells 44 arranged in each window portion of the grid-like gate trench 43 are arranged in a matrix. Each unit cell 44 has, for example, a length of 10 μm or less in the left-right (up-down) direction on the paper surface of FIG. The source trench 45 is formed.

A source pad 46 is formed on the surface of the semiconductor device 41. The source pad 46 has a substantially square shape in a plan view in which the four corners are curved outward, and is formed so as to cover almost the entire surface of the semiconductor device 41. The source pad 46 is formed with a removal region 47 in which a part of the source pad 46 is removed in a substantially square shape in a plan view on the left-right side of the paper surface of FIG. 3A.

A gate pad 48 is arranged in the removal area 47. Spacing is provided between the gate pad 48 and the source pad 46, which are isolated from each other.
FIG. 4 is a schematic cross-sectional view of the semiconductor device according to the second embodiment of the present invention, showing a cut surface at the cut line IV-IV of FIG. 3 (b).
The cross-sectional structure of the semiconductor device 41 will be described with reference to FIG. The semiconductor device 41 includes an N ⁺ type (for example, a concentration of 1e18 to 1e21 cm ^-3 ) SiC substrate 42. The surface 49 (upper surface) of the SiC substrate 42 is the Si surface, and the back surface 50 (lower surface) thereof is the C surface.

On the SiC substrate 42, an epitaxial layer 51 made of N ^- type (for example, a concentration of 1e15 to 1e17 cm ^-3 ), which has a lower concentration than that of the SiC substrate 42, is laminated. The epitaxial layer 51 as a semiconductor layer is formed on the SiC substrate 42 by so-called epitaxial growth. The epitaxial layer 51 formed on the surface 49, which is the Si surface, is grown with the Si surface as the main growth surface. Therefore, the surface 52 of the epitaxial layer 51 formed by growth is a Si surface like the surface 49 of the SiC substrate 42.

On the surface 52 side (Si surface side) of the epitaxial layer 51, a P-shaped body region 53 is formed in a well shape over a wide range, and the concentration thereof is, for example, 1e16 to 1e19 cm ^-3 . Further, in the epitaxial layer 51, the region on the SiC substrate 42 side (C surface side) with respect to the body region 53 becomes an N ^- type drain region 54 (drift region) in which the state after epitaxial growth is maintained. There is.

In the body region 53, an N ⁺ type (for example, a concentration of 1e18 to 1e21 cm ^-3 ) source region 55 is located almost entirely on the surface 52 side, and P is located on the SiC substrate 42 side (below) of the source region 55. A ⁺ type (for example, a concentration of 1e18 to 1e21 cm ^-3 ) body contact region 56 is formed. A large number of body contact regions 56 are formed in a matrix.

The same number of source trenches 45 as the body contact regions 56 are formed so as to penetrate the individual body contact regions 56, and a grid-like gate trench is formed so as to surround each body contact region 56 in which the source trench 45 is formed. 43 is formed. As a result, a large number of unit cells 44, each of which functions as a field effect transistor, are formed on the epitaxial layer 51. That is, in the unit cell 44, the body contact region 56 is formed so as to surround the source trench 45, and the body region 53 is further formed so as to surround the body contact region 56. The opposite side of the body region 53 on the body contact region 56 side is exposed on the side surface of the gate trench 43. Further, in the unit cell 44, the depth direction of the gate trench 43 is the gate length direction, and the circumferential direction of each unit cell 44 orthogonal to the gate length direction is the gate width direction.

Both the source trench 45 and the gate trench 43 penetrate the body region 53 from the surface 52 of the epitaxial layer 51 to reach the drain region 54, and in this embodiment, they have the same depth. The distance D1 between the side surface 59 of the source trench 45 and the side surface 57 of the gate trench 43 is, for example, 0.5 to 3 μm. When the distance D1 is within this range, an increase in the resistance value (on resistance) when each unit cell 44 is turned on can be suppressed, and the electric field applied to the bottom of the gate trench 43 can be relaxed.

In the gate trench 43, both end corners 61 in a direction orthogonal to the gate width at the bottom thereof (direction facing the adjacent unit cell 44) are curved toward the drain region 54 side, and the side surfaces 57 and the bottom surface facing each other are curved. 58 is a U-shaped cross section continuous with the curved surface. Further, the source trench 45 also has a U-shaped cross section in which the side surfaces 59 and the bottom surface 60 facing each other are continuous with each other via a curved surface, like the gate trench 43. As a result, when the unit cell 44 is turned off, the electric field applied to both end corners 61 at the bottom of the gate trench 43 can be dispersed to a portion other than the end corners 61, so that the electric field can be dispersed to a portion other than the end corners 61. Dielectric breakdown of the portion (insulation film bottom 64) can be suppressed.

In the drain region 54, an implanter layer formed by implantation of P-type impurities (for example, B (boron), Al (aluminum), etc.) in a portion extending from the bottom surface 58 of the gate trench 43 to the middle portion in the thickness direction thereof. Impurity active layer 62 is formed. The impla active layer 62 is formed in a grid pattern overlapping the gate trench 43 in a plan view, and has a shape narrower than the distance between adjacent unit cells 44. The depth of the impla active layer 62 is, for example, 0.1 to 0.5 μm in this embodiment.

The impla active layer 62 is a high resistance layer having a higher resistance value than the surrounding region (for example, the drain region 54) in the epitaxial layer 51, and the resistance value is, for example, several tens k to several hundreds kΩ / □. be. The concentration of P-type impurities in the impla active layer 62 is, for example, 1e16 to 1e21cm ^-3 .
A gate insulating film 63 is formed on the inner surface of the gate trench 43 so as to cover the entire area thereof. The gate insulating film 63 is made of a nitrogen-containing oxide film, for example, a silicon nitride film formed by thermal oxidation using a gas containing nitrogen and oxygen. The nitrogen content (nitrogen concentration) in the gate insulating film 63 is, for example, 0.1 to 10%.

In the gate insulating film 63, the thickness T 4 of the portion on the bottom surface 58 of the gate trench 43 (insulating film bottom portion 64) is the thickness T ₃ of the portion _on the side surface 57 of the gate trench 43 (insulating film side portion 65). The ratio of the thickness T ₄ to the thickness T ₃ (thickness T ₄ / thickness T ₃ ) is 0.3 to 1.0, preferably 0.5 to 1.0. .. The specific magnitudes of both thicknesses are, for example, a thickness T ₃ of 300 to 1000 Å and a thickness T ₄ of 150 to 500 Å. When the thickness T ₃ of the insulating film side portion 65 is within the above range, the semiconductor device 41 can be operated with an appropriate gate-on voltage, and efficient transistor operation can be achieved.

The gate electrode 66 is embedded in the gate trench 43 by filling the inside of the gate insulating film 63 with a polysilicon material doped with a high concentration of N-type impurities.
An interlayer insulating film 67 made of SiO ₂ is laminated on the epitaxial layer 51. The interlayer insulating film 67 and the gate insulating film 63 are formed with contact holes 68 that expose the surfaces of the source trench 45 and the source region 55 of each unit cell 44.

A source wiring 69 is formed on the interlayer insulating film 67. The source wiring 69 collectively enters the source trench 45 of all the unit cells 44 through each contact hole 68, and in each unit cell 44, the drain region 54 and the body contact are sequentially formed from the bottom side of the source trench 45. It is in contact with the region 56 and the source region 55. That is, the source wiring 69 is common wiring for all the unit cells 44. An interlayer insulating film (not shown) is formed on the source wiring 69, and the source wiring 69 is connected to the source pad 46 (see FIG. 3A) via the interlayer insulating film (not shown). ) Is electrically connected. On the other hand, the gate pad 48 (see FIG. 3A) is electrically connected to the gate electrode 66 via a gate wiring (not shown) routed over the interlayer insulating film (not shown). ing.

Further, the source wiring 69 has a polysilicon layer 70, an intermediate layer 71, and a metal layer 72 in this order from the contact side with the epitaxial layer 51.
The polysilicon layer 70 is a dope layer formed by using an impurity-doped doped layer, for example, a high-concentration doped layer in which impurities are doped at a high concentration of 1e19 to 1e21cm ^-3 . Impurities when the polyvinyl silicon layer 70 is formed as a doping layer (including a high-concentration doping layer) include N-type impurities such as N (nitrogen), P (phosphorus), and As (arsenic), Al (aluminum), and B. P-type impurities such as (boron) can be used. Further, the thickness of the polysilicon layer 70 is, for example, 5000 to 10000 Å.

Further, in this embodiment, the polysilicon layer 70 is formed so as to cover the entire surface of the unit cell 44 exposed in the contact hole 68, and the drain region 54, the body contact region 56, and the source are formed in the source trench 45. It is in contact with the region 55.
By using polysilicon for the contact layer with the drain region 54, the body contact region 56, and the source region 55 in the source wiring 69, the source wiring 69 is provided to both the body contact region 56 and the source region 55, which are high-concentration impurity regions. Can be ohmic-bonded to. On the other hand, for the low-concentration drain region 54, the junction barrier is smaller than the diffusion potential of the body diode 73 (PN diode formed by the junction between the body region 53 and the drain region 54) inherent in the semiconductor device 41. Heterojunction junctions can be formed.

By the way, when a current flows through the body diode 73 inherent in the semiconductor device 41, the holes moved from the body region 53 to the drain region 54 are recombined with electrons in the drain region 54, and the binding energy generated at that time is generated. As a result, defects in the SiC crystal in the epitaxial layer 51 may spread in the plane. Since this crystal defect has a high resistance value, if the crystal defect expands toward the gate trench 43, the crystal defect may interfere with normal transistor operation and the on-resistance may increase.

On the other hand, if a heterojunction junction is formed by contact between the polysilicon layer 70 and the drain region 54 as in this embodiment, a reverse voltage is applied between the source and drain, and a current is applied to the body diode 73. Even if the current flows, the current can flow preferentially to the heterojunction junction side rather than the body diode 73 side. As a result, it is possible to prevent the expansion of the crystal defects of SiC and suppress the increase of the on-resistance.

The intermediate layer 71 is laminated on the polysilicon layer 70, and is composed of a single layer of a layer containing Ti (titanium) or a plurality of layers having the layer thereof. The layer containing Ti can be formed by using Ti, TiN (titanium nitride) or the like. The thickness of the intermediate layer 71 is, for example, 200 to 500 nm.
The metal layer 72 is laminated on the intermediate layer 71 and contains, for example, Al (aluminum), Au (gold), Ag (silver), Cu (copper), Mo (molybdenum), their alloys and them. It is formed using a metal material. The metal layer 72 forms the outermost layer of the source wiring 69. The thickness of the metal layer 72 is, for example, 1 to 5 μm.

Specific examples of the combination of the polysilicon layer 70, the intermediate layer 71, and the metal layer 72 as described above include Poly-Si (polysilicon layer 70), Ti (intermediate layer 71), TiN (intermediate layer 71), and TiN (intermediate layer 71). An example is a laminated structure (Poly—Si / Ti / TiN / Al) in which Al (metal layer 72) is laminated in order.
A drain electrode 74 is formed on the back surface 50 of the SiC substrate 42 so as to cover the entire area thereof. The drain electrode 74 is a common electrode for all unit cells 44. As the drain electrode 74, for example, a laminated structure (Ti / Al) in which Ti and Al are laminated in order from the SiC substrate 42 side can be exemplified.

A predetermined voltage (voltage equal to or higher than the gate threshold voltage) is applied to the gate pad 48 in a state where a predetermined potential difference is generated between the source pad 46 (source wiring 69) and the drain electrode 74 (between the source and the drain). As a result, the electric field from the gate electrode 66 forms a channel in the vicinity of the interface with the gate insulating film 63 in the body region 53. As a result, a current flows between the source wiring 69 and the drain electrode 74, and the VD MOSFET is turned on.

5A to 5U are schematic cross-sectional views for explaining a method of manufacturing the semiconductor device shown in FIG.
First, as shown in FIG. 5A, an epitaxial growth method such as a CVD (Chemical Vapor Deposition) method, an LPE (Liquid Phase Epitaxy) method, or an MBE (Molecular Beam Epitaxy) method is used. , SiC crystals are grown on the surface 49 (Si surface) of the SiC substrate 42 while doping impurities. As a result, an N ^- type epitaxial layer 51 is formed on the SiC substrate 42.

Subsequently, as shown in FIG. 5B, the P-type impurity is implanted (injected) from the surface 52 of the epitaxial layer 51 into the inside of the epitaxial layer 51. The injection conditions at this time differ depending on the type of P-type impurity, but for example, the acceleration energy is 200 to 3000 keV.
Next, as shown in FIG. 5C, a mask 75 made of SiO ₂ is formed on the epitaxial layer 51 by the CVD method. Subsequently, the mask 75 is etched via a photoresist (not shown) to pattern a pattern having an opening 76 in the region where the body contact region 56 should be formed. After the opening 76 is formed, P-type impurities are implanted (injected) from the surface 52 of the epitaxial layer 51 into the inside of the epitaxial layer 51. The injection conditions at this time differ depending on the type of P-type impurity, but for example, the acceleration energy is 30 to 400 keV. After injecting the P-type impurities, the mask 75 is removed.

Then, as shown in FIG. 5D, the N-type impurity is implanted (injected) from the surface 52 of the epitaxial layer 51 into the inside of the epitaxial layer 51. The injection conditions at this time differ depending on the type of N-type impurity, but for example, the acceleration energy is 30 to 400 keV.
Next, as shown in FIG. 5E, a mask 77 made of SiO ₂ is formed over the entire surface 52 of the epitaxial layer 51 by a CVD method, a thermal oxidation method, or the like. The mask 77 can also be formed of SiN or the like by using the CVD method. Subsequently, the mask 77 is etched via a photoresist (not shown) to pattern a pattern having openings 78 in the regions where the gate trench 43 and the source trench 45 should be formed. After forming the opening 78, for example, a mixed gas containing SF6 (sulfur hexafluoride) and O ₂ (oxygen) (SF6 / O ₂ gas), a mixed gas containing SF6, O ₂ and HBr (hydrogen bromide) (SF6). / O ₂ / HBr gas) is incident on the surface 52 of the epitaxial layer 51 through the opening 78. As a result, the epitaxial layer 51 is dry-etched from the surface 52 (Si surface) to form the gate trench 43 and the source trench 45 at the same time. At the same time, a large number of unit cells 44 are formed in the epitaxial layer 51.

Next, as shown in FIG. 5F, the inner surface of the gate trench 43 and the inner surface of the source trench 45 are oxidized by a thermal oxidation method (dry oxidation) using O ₂ gas. As a result, the stopper film 79 is formed. The thickness of the stopper film 79 may not be uniform as a whole, but FIGS. 5F to 5I show a case where the stopper film 79 has a uniform thickness for convenience.

Next, as shown in FIG. 5G, a polysilicon material, which is a material different from the material (SiO ₂ ) of the mask 77 for forming the gate trench 43 and the source trench 45, is put on the epitaxial layer 51 by the CVD method. It is deposited until the entire surface of the film 79 and the entire surface of the mask 77 are covered. As a result, the protective mask 80 is formed on the stopper film 79 and the mask 77. The thickness of the protective mask 80 is controlled to be, for example, 0.1 to 0.5 μm.

Then, as shown in FIG. 5H, the protective mask 80 is etched back from above the epitaxial layer 51. Etching back is performed in a state where the portion of the protective mask 80 on the bottom surface 60 of the source trench 45 is masked, and is continued until the etching is stopped by the stopper film 79 and the mask 77. As a result, only the portion of the protective mask 80 on the bottom surface 58 of the gate trench 43 is removed, and the portion of the protective mask 80 that covers the side surface 57 of the gate trench 43 and the bottom surface 60 and the side surface 59 of the source trench 45 remains.

Then, as shown in FIG. 5I, the P-type impurity is implanted (injected) into the epitaxial layer 51 from the bottom surface 58 of the gate trench 43 via the stopper membrane 79. The injection conditions at this time differ depending on the type of P-type impurity, but for example, the acceleration energy is 30 to 400 keV.
Then, as shown in FIG. 5J, the protective mask 80 is removed by wet etching, followed by the mask 77 and the stopper film 79.

After that, as shown in FIG. 5K, the organic material film 81 is formed over the entire surface 52 of the epitaxial layer 51. The organic material film 81 is a material containing carbon (carbon), and for example, an organic material used as a photoresist (for example, polyimide) can be applied. Such an organic material film 81 is formed by using, for example, a spin coater or the like.

After the formation of the organic material film 81, the SiC substrate 42 is charged into the resistance heating furnace 82. The resistance heating furnace 82 is not particularly limited as long as it is a device capable of ensuring airtightness in the resistance heating furnace 82 in which the heating element is set and introducing various gases into the resistance heating furnace 82. The heating method may be either a direct heating method or an indirect heating method.
Then, with the SiC substrate 42 set in the resistance heating furnace 82, an inert gas (for example, _N2 , Ar, etc.) is introduced into the resistance heating furnace 82, and the resistance heating furnace 82 is controlled to raise the temperature. (First temperature rise control).

In this first temperature rise control, as shown in FIG. 6, the heating temperature is controlled to rise from 100 ° C. to 1000 ° C. over, for example, 35 to 45 minutes, and after the rise, for example, 5 to 10 minutes. , The heating temperature is maintained at 1000 ° C. (first temperature retention). By this temperature rise and temperature maintenance, the elements other than carbon in the organic material film 81 evaporate, and as shown in FIG. 5L, the organic material film 81 is transformed into the carbon film 83. Therefore, the entire surface 52 of the epitaxial layer 51 is covered with the carbon film 83.

Subsequently, the resistance heating furnace 82 is further controlled to raise the temperature (second temperature rise control) while maintaining the inside of the resistance heating furnace 82 in the inert atmosphere.
In this second temperature rise control, as shown in FIG. 6, the heating temperature is controlled to rise from 1000 ° C. to 1600 ° C. over, for example, 30 to 60 minutes. After the rise, the heating temperature is maintained at 1600 ° C. (second temperature retention) for, for example, 5 to 10 minutes. By this temperature rise and temperature maintenance, the ions of the individual N-type impurities and P-type impurities injected into the surface layer portion of the epitaxial layer 51 are activated, and as shown in FIG. 5M, the body is subjected to the injection location. A region 53, a source region 55, and a body contact region 56 are formed, respectively. Further, a drain region 54 that maintains the state after epitaxial growth is formed in the base layer portion of the epitaxial layer 51.

Next, the temperature of the resistance heating furnace 82 is controlled to be lowered while the inside of the resistance heating furnace 82 is maintained in the inert atmosphere.
In the temperature lowering control, as shown in FIG. 6, the heating temperature is limited (temperature lowering limitation) so as to drop from 1600 ° C. to 1300 ° C. over 15 to 30 minutes, for example. After the temperature is lowered, the nitrogen / oxygen-containing gas is introduced into the resistance heating furnace 82 in a state where the heating temperature is maintained at 1300 ° C. (third temperature retention) for, for example, 5 to 10 minutes. By introducing the nitrogen / oxygen-containing gas, as shown in FIG. 5N, the carbon film 83 reacts with oxygen in the gas to be oxidized and removed. As the nitrogen / oxygen-containing gas to be introduced, a gas containing at _least N2O (nitrous oxide) can be used, and NO (nitrogen monoxide) may be contained. Further, the N2O gas is supplied at a flow rate ratio of 30% or less, preferably ₁ to 30%, based on the total flow rate of the introduced gas.

After that, while introducing the nitrogen / oxygen-containing gas into the resistance heating furnace 82 at the same flow rate, the heating temperature is further maintained at 1300 ° C. (fourth temperature retention) for, for example, 200 to 240 minutes. As a result, the surface 52 of the epitaxial layer 51 is oxidized, and as shown in FIG. 5O, a silicon nitride film (gate insulating film 63) covering the entire surface 52 is formed.
After the formation of the gate insulating film 63, the inert gas (for example, N2, Ar, etc.) is introduced again into the resistance heating furnace 82, and the heating temperature is controlled to drop from 1300 ° C to 300 ° C. After the temperature is lowered, the SiC substrate 42 is taken out from the resistance heating furnace 82.

Then, as shown in FIG. 5P, the doped polysilicon material 84 is deposited from above the epitaxial layer 51 by the CVD method. The deposition of the polysilicon material 84 continues until at least the gate trench 43 and the source trench 45 are filled.
Then, as shown in FIG. 5Q, the deposited polysilicon material 84 is etched back until the etchback surface is flush with the surface 52 of the epitaxial layer 51.

Subsequently, as shown in FIG. 5R, only the polysilicon material 84 remaining in the source trench 45 is removed by dry etching. As a result, the gate electrode 66 made of the polysilicon material 84 remaining in the gate trench 43 is formed.
Next, as shown in FIG. 5S, the interlayer insulating film 67 made of SiO ₂ is laminated on the epitaxial layer 51 by the CVD method.

Then, as shown in FIG. 5T, the interlayer insulating film 67 and the gate insulating film 63 are continuously patterned to form a contact hole 68 in the interlayer insulating film 67 and the gate insulating film 63.
Then, as shown in FIG. 5U, the polysilicon material is deposited by the CVD method until the contact hole 68 is filled. After this, N-type or P-type impurities are implanted (injected) into the deposited polysilicon material. The injection conditions at this time differ depending on the type of impurities, but for example, the acceleration energy is 10 to 100 keV. Then, for example, impurity diffusion is performed at 900 ° C. for 20 minutes. As a result, the polysilicon layer 70 in which impurities are heavily doped is formed. Next, Ti and TiN are deposited on the surface of the polysilicon layer 70 in this order by a method such as a sputtering method or a vapor deposition method to form an intermediate layer 71. Subsequently, a metal such as Al is deposited on the surface of the intermediate layer 71 by a method such as a sputtering method or a thin-film deposition method to form the metal layer 72. As a result, the source wiring 69 is formed. Next, the drain electrode 74 is formed on the back surface 50 of the SiC substrate 42.

After that, the interlayer insulating film (not shown), the source pad 46, the gate pad 48, and the like are formed to obtain the semiconductor device 41 shown in FIG.
As described above, according to the semiconductor device 41, the gate trench 43 is formed by digging from the surface 52 (Si surface) of the epitaxial layer 51 made of SiC, similarly to the semiconductor device 1 of the first embodiment. There is. Therefore, in the oxidation of the inner surface of the gate trench 43 (see FIG. 5O), the oxidation rate of the bottom surface 58 having the Si surface and the oxidation rate of the side surface orthogonal to the Si surface are related to the relational expression: oxidation rate of the bottom surface 58 / side surface. It proceeds under the condition that the oxidation rate <0 of 57 is satisfied.

In the above production method, the oxidation of the inner surface of the gate trench 43 is not thermal oxidation (Dry oxidation) using O ₂ gas or thermal oxidation (Wet oxidation) using H ₂ O (steam) gas, but nitrogen. -It is performed by thermal oxidation using oxygen-containing gas. Further, an impla active layer 62 in which P-type impurities are implanted is formed immediately below the bottom surface 58 of the gate trench 43. Therefore, the ratio of the oxidation rate of the bottom surface 58 to the oxidation rate of the side surface 57 (oxidation rate of the bottom surface 58 / oxidation rate of the side surface 57) is increased as compared with the case where the gate insulating film 63 is formed by Dry oxidation or Wet oxidation. be able to.

The gate insulating film 63 thus formed has a ratio (thickness T ₄ / thickness T ₃ ) of the thickness T ₄ of the insulating film bottom 64 to the thickness T ₃ of the insulating film side portion 65 being 0. It is in the range of .3 to 1.0.
That is, even if the thickness T ₄ of the insulating film bottom 64 is increased to the extent that dielectric breakdown can be suppressed, the lower limit of (thickness T ₄ / thickness T ₃ ) is 0.3, so that the insulating film side portion 65 It is possible to suppress an excessive increase in the thickness T ₃ of the. On the other hand, since the upper limit is 1.0, the thickness T ₃ of the insulating film side portion 65 does not become excessively small when the thickness T ₄ of the insulating film bottom portion 64 is designed to have an appropriate size. As a result, by appropriately designing the thickness T ₄ of the insulating film bottom 64, it is possible to suppress the increase in the thickness T ₃ of the insulating film side 65 and suppress the dielectric breakdown of the insulating film bottom 64. can.

Further, since the gate insulating film 63 is made of a silicon nitride film formed by thermal oxidation using a nitrogen-containing gas, the channel mobility of the VD MOSFET can be improved.
Further, since the impla active layer 62 is formed directly under the gate trench 43, the energy barrier formed between the impla active layer 62 and the epitaxial layer 51 can be increased. Therefore, it is possible to make it difficult for the current to flow through the impla active layer 62. As a result, the electric field concentration on the bottom surface 58 of the gate trench 43 can be suppressed.

Further, since the source trench 45 is formed in the center of each unit cell 44 surrounded by the gate trench 43, it is possible to suppress the concentration of equipotential lines in the vicinity of both end corners 61 of the gate trench 43. As a result, the electric field applied to both end corners 61 at the bottom of the gate trench 43 can be relaxed, so that dielectric breakdown of the insulating film bottom 64 can be suppressed.
The source trench 45 may be deeper than the gate trench 43 as in the semiconductor device 85 shown in FIG. As a result, the electric field applied to both end corners 61 at the bottom of the gate trench 43 can be further relaxed.

Further, in the semiconductor device 41, since the source wiring 69 has the polysilicon layer 70 in the contact portion between the source region 55 and the body contact region 56, the source wiring 69 is the body contact which is a high-concentration impurity region. Ohmic junctions can be made to both the region 56 and the source region 55.
Therefore, unlike the case where the layer made of only a metal such as Al is directly contacted with the impurity region in the manufacturing of the semiconductor device 41, the step of forming the Ni layer on the surface 52 of the epitaxial layer 51 can be omitted, and further. The step of silicidizing such a Ni layer can be omitted. Therefore, it is possible to prevent the generation of the carbon layer on the surface 52 of the epitaxial layer 51.

As a result, layer peeling between the source wiring 69 and the epitaxial layer 51 can be suppressed. Therefore, the connection reliability of the source wiring 69 can be improved.
Further, since the layer (polysilicon layer 70) that enters the source trench 45 and contacts the drain region 54, the body contact region 56, and the source region 55 is made of polysilicon having excellent coverage, the coverage of the source wiring 69 is improved. Can be made to. As a result, the connection reliability of the source wiring 69 can be further improved.

Further, an intermediate layer 71 having a laminated structure of a Ti layer and a TiN layer is interposed between the polysilicon layer 70 and the metal layer 72. The Ti-containing material has excellent adhesion to both the polysilicon material and the metal material. Therefore, the adhesion between the polysilicon layer 70 and the metal layer 72 can be improved. As a result, the connection reliability of the source wiring 69 can be further improved.

Further, when Al is contained in the metal layer 72, the TiN layer can be used as a barrier layer for preventing the diffusion of Al from the metal layer 72 to the polysilicon layer 70, so that the excess Al is polysilicon. It is possible to prevent the layer 70 from diffusing. As a result, the impurity concentration of the polysilicon layer 70 can be stabilized, so that the resistance value of the polysilicon layer 70 can be stabilized.

Next, an embodiment relating to the invention of a method for manufacturing a SiC semiconductor device using a resistance heating furnace will be shown.
FIG. 8 is a schematic cross-sectional view of a planar gate type semiconductor device.
The semiconductor device 101 has a structure in which unit cells of a planar gate type VD MOSFET are arranged in a matrix. Note that FIG. 8 shows a part of the plurality of unit cells.

The semiconductor device 101 includes an N ⁺ type SiC substrate 102 that forms a substrate of the semiconductor device 101. An N ^- type epitaxial layer 103 made of SiC (silicon carbide: silicon carbide) doped with N-type impurities at a lower concentration than that of the SiC substrate 102 is laminated on the surface 121 of the SiC substrate 102. The surface 131 of the epitaxial layer 103 is composed of, for example, the (0001) plane of SiC.

The epitaxial layer 103 is formed with an N ^- type drain region 104, which is maintained in the state after the epitaxial growth.
Further, a P-shaped body region 105 is formed on the surface layer portion of the epitaxial layer 103. Although not shown in FIG. 8, a plurality of body regions 105 are formed at regular intervals, and they are parallel to each other and extend in the same direction (direction perpendicular to the paper surface of FIG. 8), for example, a stripe shape or a matrix. They are arranged in a shape (matrix). The drain region 104 is exposed between the body regions 105 adjacent to each other.

An N ⁺ -shaped source region 106 is formed on the surface layer portion of the body region 105 at a distance from the peripheral edge thereof.
Further, on the surface 131 of the epitaxial layer 103, a gate insulating film 107 straddling the drain region 104, the body region 105, and the source region 106 is formed. The gate insulating film 107 is made of SiO ₂ .

Then, on the gate insulating film 107, a gate electrode 108 made of polysilicon in which N-type impurities are doped at a high concentration is formed. The gate electrode 108 faces the drain region 104, the body region 105, and the source region 106 via the gate insulating film 107.
An interlayer insulating film 109 made of SiO ₂ is laminated on the epitaxial layer 103. The source wiring 111 is formed on the interlayer insulating film 109. The source wiring 111 is electrically connected to the body region 105 and the source region 106 via the contact hole 110 formed in the interlayer insulating film 109.

The gate wiring 112 is electrically connected to the gate electrode 108 via a contact hole (not shown) formed in the interlayer insulating film 109.
A drain electrode 113 is formed on the back surface of the SiC substrate 102.
When the source wiring 111 is grounded and the potential of the gate electrode 108 is controlled while applying a positive voltage of an appropriate magnitude to the drain electrode 113, the electric field from the gate electrode 108 causes the interface with the gate insulating film 107 in the body region 105. Channels can be formed in the vicinity. As a result, a current can flow between the source wiring 111 and the drain electrode 113.

9A to 9L are schematic cross-sectional views illustrating a method for manufacturing the semiconductor device of FIG.
First, as shown in FIG. 9A, the epitaxial layer 103 is formed on the surface 121 of the SiC substrate 102 by the epitaxial growth method. At this time, the growth main surface (surface 121) of the SiC substrate 102 is the (0001) surface. Since the surface 121 of the SiC substrate 102 is a (0001) plane, the epitaxial layer 103 formed on the SiC substrate 102 by epitaxial growth is also formed with the (0001) plane as the main surface. Therefore, the surface 131 of the epitaxial layer 103 parallel to the surface 121 of the SiC substrate 102 becomes a (0001) plane.

Then, by a known photolithography technique, a photoresist 114 having an opening 115 in a portion facing the region where the body region 105 should be formed is formed on the surface 131 of the epitaxial layer 103. Then, ions of P-type impurities (for example, boron ions) are incident on the surface 131 of the epitaxial layer 103 from above the photoresist 114. As a result, as shown in FIG. 9B, the P-type impurity is injected into the surface layer portion of the portion exposed from the opening 115 of the epitaxial layer 103.

Subsequently, a photoresist 116 having an opening 117 is formed on the surface 131 of the epitaxial layer 103 by a known photolithography technique in a portion facing the region where the source region 106 should be formed. Then, ions of N-type impurities (for example, arsenic ions) are incident on the surface 131 of the epitaxial layer 103 from above the photoresist 116. As a result, as shown in FIG. 9C, the N-type impurity is injected into the surface layer portion (the surface 131 side of the injection location of the P-type impurity) of the portion exposed from the opening 117 of the epitaxial layer 103.

After implanting the impurity ions into the surface layer portion of the epitaxial layer 103, the organic material film 118 is formed over the entire surface 131 of the epitaxial layer 103 as shown in FIG. 9D. The organic material film 118 is a material containing carbon (carbon), and for example, an organic material used as a photoresist (for example, polyimide) can be applied. Such an organic material film 118 is formed by using, for example, a spin coater or the like.

After the formation of the organic material film 118, the SiC substrate 102 is charged into the resistance heating furnace 122. The resistance heating furnace 122 is not particularly limited as long as it is a device capable of ensuring airtightness in the resistance heating furnace 122 in which the heating element is set and introducing various gases into the resistance heating furnace 122. The heating method may be either a direct heating method or an indirect heating method.
Then, with the SiC substrate 102 set in the resistance heating furnace 122, an inert gas (for example, _N2 , Ar, etc.) is introduced into the resistance heating furnace 122, and the resistance heating furnace 122 is controlled to raise the temperature. (First temperature rise control).

In this first temperature rise control, as shown in FIG. 6, the heating temperature is controlled to rise from 100 ° C. to 1000 ° C. over, for example, 35 to 45 minutes, and after the rise, for example, 5 to 10 minutes. , The heating temperature is maintained at 1000 ° C. (first temperature retention). By this temperature rise and temperature maintenance, elements other than carbon in the organic material film 118 evaporate, and as shown in FIG. 9E, the organic material film 118 is transformed into a carbon film 119. Therefore, the entire surface 131 of the epitaxial layer 103 is covered with the carbon film 119.

Subsequently, the resistance heating furnace 122 is further controlled to raise the temperature (second temperature rise control) while maintaining the inside of the resistance heating furnace 122 in the inert atmosphere.
In this second temperature rise control, as shown in FIG. 6, the heating temperature is controlled to rise from 1000 ° C. to 1600 ° C. over, for example, 30 to 60 minutes. After the rise, the heating temperature is maintained at 1600 ° C. (second temperature retention) for, for example, 5 to 10 minutes. By this temperature rise and temperature maintenance, ions of N-type impurities and P-type impurities injected into the surface layer portion of the epitaxial layer 103 are activated, and as shown in FIG. 9F, the body region 105 and the body region 105 and the surface layer portion of the epitaxial layer 103 are activated. The source region 106 is formed. Further, in the base layer portion of the epitaxial layer 103, a drain region 104 which is separated from the body region 105 and maintains the state after the epitaxial growth is formed.

Next, the temperature of the resistance heating furnace 122 is controlled to be lowered while the inside of the resistance heating furnace 122 is maintained in the inert atmosphere.
In the temperature lowering control, as shown in FIG. 6, the heating temperature is limited (temperature lowering limitation) so as to drop from 1600 ° C. to 1300 ° C. over 15 to 30 minutes, for example. After the temperature is lowered, the oxygen-containing gas is introduced into the resistance heating furnace 122 in a state where the heating temperature is maintained at 1300 ° C. (third temperature retention) for, for example, 5 to 10 minutes. By introducing the oxygen-containing gas, as shown in FIG. 9G, the carbon film 119 reacts with the oxygen of the oxygen-containing gas and is oxidized and removed. However, as the oxygen-containing gas introduced into the resistance heating furnace 122, it is preferable to use a gas containing oxygen and nitrogen, and specifically, NO (nitric oxide) and _N2 O (nitrous oxide). ) And the like can be used.

Then, while introducing the oxygen-containing gas into the resistance heating furnace 122, the heating temperature is maintained at 1300 ° C. (fourth temperature retention) for, for example, 200 to 240 minutes. As a result, the surface 131 of the epitaxial layer 103 is oxidized, and as shown in FIG. 9H, an oxide film 120 covering the entire surface 131 is formed.
After the oxide film 120 is formed, the inert gas (for example, _N2 , Ar, etc.) is introduced again into the resistance heating furnace 122, and the heating temperature is controlled to drop from 1300 ° C to 300 ° C. After the temperature is lowered, the SiC substrate 102 is taken out from the resistance heating furnace 122.

Then, the conductive material is formed into a film by the sputtering method. Then, the conductive material is patterned by a known photolithography and etching technique, and the gate electrode 108 is formed on the oxide film 120 as shown in FIG. 9I.
Then, as shown in FIG. 9J, the interlayer insulating film 109 is laminated on the epitaxial layer 103 by the CVD (Chemical Vapor Deposition) method.

Then, as shown in FIG. 9K, the contact hole 110 is formed in the interlayer insulating film 109 and the oxide film 120 by a known photolithography technique and etching technique. The remaining portion of the oxide film 120 becomes the gate insulating film 107.
Next, a conductive material is formed on the epitaxial layer 103 by a sputtering method. The conductive material fills the contact hole 110 and is adhered (deposited) so as to form a thin film on the interlayer insulating film 109. Then, the conductive material on the interlayer insulating film 109 is patterned by a known photolithography technique and etching technique. As a result, the source wiring 111 is formed as shown in FIG. 9L. Further, a gate wiring 112 electrically connected to the gate electrode 108 is formed. Further, the drain electrode 113 is formed on the back surface of the SiC substrate 102.

Through the above steps, the semiconductor device 101 shown in FIG. 8 is obtained.
According to the above manufacturing method, after the formation of the organic material film 118, the organic material film 118 in the resistance heating furnace 122 is heated by the first temperature rise control of the resistance heating furnace 122 to be transformed into a carbon film 119. A carbon film 119 is formed on the surface 131 of the epitaxial layer 103.
After the formation of the carbon film 119, the epitaxial layer 103 is heated by the second temperature rise control of the resistance heating furnace 122 while maintaining the inside of the resistance heating furnace 122 in an inert atmosphere, and the N-type impurities in the epitaxial layer 103 and Ions of P-type impurities are activated.

Then, the temperature lowering control (for example, the temperature lowering from 1600 ° C. to 1300 ° C.) is executed while the inside of the resistance heating furnace 122 is maintained in the inert state. Then, the oxygen-containing gas is introduced for, for example, 5 to 10 minutes while the heating temperature is maintained at 1300 ° C. (third temperature retention). As a result, the carbon film 119 is oxidized and removed, and the surface 131 of the epitaxial layer 103 is exposed.

After the removal of the carbon film 119, the temperature of the resistance heating furnace 122 is maintained (fourth temperature maintenance) while continuously introducing an oxygen-containing gas into the resistance heating furnace 122, so that the exposed surface 131 is oxidized and oxidized. The film 120 is formed.
Since the carbon film 119 is formed on the surface 131 of the epitaxial layer 103 prior to heating for ionic activity (second temperature rise control), Si escape from the surface 131 is prevented when the epitaxial layer 103 is heated. be able to. Therefore, the roughness of the surface 131 of the epitaxial layer 103 can be suppressed, and the flatness of the surface 131 can be maintained. As a result, the interface between the epitaxial layer 103 and the gate insulating film 107 can be smoothed, so that the channel mobility of the semiconductor device 101 can be improved.

Further, a step of heating the organic material film 118 to transform it into a carbon film 119 (first temperature rise control), a step of heating the epitaxial layer 103 to activate ions (second temperature rise control), and oxygen content. The four steps consisting of a step of oxidizing and removing the carbon film 119 with gas (temperature reduction control and third temperature holding) and a step of oxidizing the surface of the SiC layer to form an oxide film (fourth temperature holding) are described in 1. It can be carried out continuously in two resistance heating furnaces 122. Since a separate device for removing the carbon film is not required, it is possible to suppress an increase in device cost. Moreover, since the resistance heating furnace 122 is used, the first temperature rise control, the second temperature rise control, the temperature decrease limit control, the third temperature holding, and the fourth temperature holding can be performed precisely and easily. can.

Further, the surface 131 of the epitaxial layer 103 on which the oxide film 120 is formed is the (0001) plane, and the oxygen-containing gas introduced into the heating furnace is a gas containing oxygen and nitrogen.
For example, when the (0001) plane of the SiC layer is oxidized with O ₂ gas, H ₂ O gas (steam) and N ₂ O gas to form an oxide film, the channel mobility of the MOSFET provided with the SiC layer is determined. For example, they are 1 to 5 cm ² / V · s, 5 to 15 cm ² / V · s and 15 to 25 cm ² / V · s, _respectively , and the N2O gas has the best channel mobility.

In the semiconductor device 101 of this embodiment, the (0001) surface ₍ surface 131) of the epitaxial layer 103 is oxidized by NO gas or N2O gas to form the oxide film 120, so that the channel mobility of the semiconductor device 101 is formed. Can be further improved.
Although the embodiment of the present invention has been described above, the present invention can also be implemented in other embodiments.
For example, a configuration in which the conductive type of each semiconductor portion of the semiconductor device 1 is inverted may be adopted. That is, in the semiconductor devices 1, 41, 85, the P-type portion may be N-type and the N-type portion may be P-type.

Further, the source wirings 17 and 69 and the drain wiring 23 (drain electrode 74) may have a laminated structure of a layer in which nickel (Ni) and titanium (Ti) are silicated and the above-mentioned metal layer.
In addition, various design changes can be made within the scope of the matters described in the claims.

In addition to the inventions described in the claims, the following features can be extracted from the contents of the above-described embodiment.
For example, in FIG. 11, since the surface 217 of the epitaxial layer 203 is a Si surface, the bottom surface 216 of the gate trench 206 dug down from the surface 217 is a Si surface.
Therefore, when the gate insulating film 207 is formed by Dry oxidation or Wet oxidation, the ratio of the oxidation rate of the bottom surface 216 to the oxidation rate of the side surface 214 (oxidation rate of the bottom surface 216 / oxidation rate of the side surface 214) is 0.2 or It will be less than that. Therefore, in the gate insulating film 207, the thickness of the portion on the bottom surface 216 is smaller than the thickness of the portion on the side surface 214.

On the other hand, in the semiconductor device 201, when the VD MOSFET is turned off, a high potential difference is generated between the gate electrode 208 and the drain wiring 215 (between the gate and the drain), and the electric field is concentrated on the bottom surface 216 of the gate trench 206. As described above, in the gate insulating film 207 having a small thickness on the bottom surface 216, dielectric breakdown due to the concentration of the electric field is likely to occur.
To deal with this problem, measures are considered to increase the thickness of the portion on the bottom surface 216 by lengthening the oxidation time when the gate insulating film 207 is formed. However, since the oxidation of the side surface 214 proceeds in parallel with the oxidation of the bottom surface 216, the thickness of the portion on the side surface 214 becomes very large due to the difference in the oxidation rate.

The purpose of the features described below is to manufacture a semiconductor device and its manufacture capable of suppressing the dielectric breakdown of the portion on the bottom surface of the gate trench while suppressing the increase in the thickness of the portion on the side surface of the gate trench in the gate insulating film. To provide a method.
(Item 1) A first conductive type semiconductor layer made of SiC whose surface is a Si surface, a gate trench dug from the surface of the semiconductor layer, and a side surface formed on the bottom surface and side surfaces of the gate trench. A gate insulating film in which the ratio of the thickness of the portion on the bottom surface to the thickness of the upper portion is 0.3 to 1.0, and a gate electrode embedded in the gate trench via the gate insulating film. Including semiconductor devices.

According to this configuration, a gate trench is formed by digging from the surface of the first conductive type semiconductor layer which is made of SiC and whose surface is a Si surface. A gate insulating film is formed on the bottom surface and the side surface of the gate trench. Further, a gate electrode is embedded in the gate trench via a gate insulating film.
As a result, the semiconductor device has a MOS (Metal Oxide Semiconductor) structure in which the gate electrode (Metal) faces the semiconductor layer (Semiconductor) via the side surface portion (Oxide) of the gate trench in the gate insulating film. A gate type MOSFET is formed.

In the MOSFET, the ratio of the thickness of the portion on the bottom surface to the thickness of the portion on the side surface of the gate insulating film is 0.3 to 1.0. Even if the thickness of the portion on the bottom surface is increased to the extent that dielectric breakdown can be suppressed, the lower limit of (thickness of the portion on the bottom surface / thickness of the portion on the side surface) is 0.3, so that it is on the side surface. Excessive increase in the thickness of the portion can be suppressed. On the other hand, since the upper limit is 1.0, when the thickness of the portion on the bottom surface is designed to be an appropriate size, the thickness of the portion on the side surface does not become excessively small. As a result, by appropriately designing the thickness of the portion on the bottom surface, it is possible to suppress the dielectric breakdown of the portion on the bottom surface while suppressing the increase in the thickness of the portion on the side surface.
(Item 2) In the semiconductor layer, a second conductive type body region formed on the side of the gate trench and in contact with the gate insulating film on the side surface of the gate trench, and the gate in the surface layer portion of the body region. Item 2. The semiconductor device according to Item 1, which includes a first conductive type source region formed adjacent to a trench and contains nitrogen in the gate insulating film.

In this configuration, in the semiconductor layer, a second conductive type body region in contact with the gate insulating film is formed on the side surface of the gate trench on the side surface of the gate trench. A first conductive type source region is formed adjacent to the gate trench on the surface layer portion of the body region. Therefore, in the trench gate type MOSFET in the semiconductor device, the portion in the body region near the interface with the gate insulating film is the channel portion where the channel is formed by the electric field from the gate electrode. In this semiconductor device, since the gate insulating film contains nitrogen, the channel mobility of the MOSFET can be improved.
(Item 3) The semiconductor device according to Item 2, wherein the concentration of the second conductive type impurity in the body region is 1e19 cm ^-3 or less.

When the impurity concentration in the body region on the side of the gate trench exceeds 1e19 cm ^-3 , when the bottom surface and side surface of the gate trench are oxidized, the side surface of the trench is oxidized at a very high oxidation rate relative to the bottom surface of the trench. Therefore, the portion on the side surface of the gate insulating film becomes very thick.
On the other hand, when the impurity concentration in the body region is 1e19 cm ^-3 or less, the ratio of the oxidation rate of the trench side surface to the oxidation rate of the trench bottom surface is maintained at an appropriate size when oxidizing the bottom surface and the side surface of the gate trench. be able to. As a result, it is possible to suppress an increase in the thickness of the portion on the side surface of the gate insulating film.
(Item 4) Any of Items 1 to 3, further comprising an implanter layer formed by implantation of impurities in a portion of the semiconductor layer extending from the bottom surface of the gate trench to an intermediate portion in the thickness direction of the semiconductor layer. The semiconductor device according to paragraph 1.

By forming the implanter layer directly under the bottom surface of the gate trench, after the formation of the implanter layer, when the bottom surface and the side surface of the gate trench are oxidized, the bottom surface of the trench is oxidized at a relatively high oxidation rate with respect to the side surface of the trench. The ratio of the thickness of the portion on the bottom surface to the thickness of the portion on the side surface of the gate insulating film can be 0.3 to 1.0.
Item 5. The semiconductor device according to Item 3, wherein the implanter layer is formed by implantation of the second conductive type impurity.

If the impla layer is formed by implantation of a second conductive type impurity different from the conductive type of the semiconductor layer, the energy barrier formed between the impla layer and the semiconductor layer can be increased. Therefore, it is possible to make it difficult for the current to flow to the impla layer. As a result, the electric field concentration on the bottom surface of the gate trench can be suppressed.
(Item 6) The semiconductor device according to any one of Items 1 to 5, wherein the thickness of the portion of the gate insulating film on the side surface of the gate trench is 2000 Å or less.

If the thickness of the portion on the side surface of the gate trench exceeds 2000 Å, it becomes necessary to operate the semiconductor device with a high gate-on voltage (for example, about 20 V), and efficient transistor operation may not be executed.
On the other hand, if the thickness of the portion on the side surface of the gate trench is 2000 Å or less, the semiconductor device can be operated with an appropriate gate-on voltage, and efficient transistor operation can be achieved.
Item 7. The semiconductor device according to any one of Items 1 to 6, wherein the end of the bottom of the gate trench in a direction orthogonal to the gate width is curved outward.

In this configuration, by bending the end of the bottom of the gate trench where the electric field tends to concentrate at the time of turn-off, the electric field applied to the end can be dispersed to a portion other than the end. As a result, it is possible to suppress dielectric breakdown of the portion on the bottom surface of the gate insulating film.
(Item 8) A source wiring formed on the semiconductor layer and contacted with the source region is included, and the source wiring has a polysilicon layer at a contact portion with the source region and is on the polysilicon layer. Item 2. The semiconductor device according to Item 2, which has a metal layer.

For example, in the semiconductor device 201 shown in FIG. 11, in order to form the source wiring 212, first, the surface (source region 209 and body contact region) of the impurity-doped region (impurity region) in the epitaxial layer 203 is formed by a sputtering method. Ni is deposited on the surface of 210). Next, in order to ohmic-bond Ni to the impurity region, Si in SiC is reacted with Ni by heat treatment at a high temperature (for example, about 1000 ° C.) to silicide Ni. As a result, the nickel silicide layer 218 is formed. Then, Al is deposited on the nickel silicide layer 218 by the sputtering method. As a result, the aluminum layer 219 is formed and the source wiring 212 is formed.

However, when the nickel silicide layer 218 is formed, residual carbon (C) in SiC is deposited near the interface between the surface of the nickel silicide layer 218 and the impurity region in the nickel silicide layer 218, and carbon containing a large amount of C is deposited. Layers are formed. Since the carbon layer has poor adhesion to metal and SiC, layer peeling is likely to occur between the aluminum layer 219 and the nickel silicide layer 218, and between the nickel silicide layer 218 and the impurity region.

Therefore, in the configuration of Item 8, the source wiring contacted with the source region has a polysilicon layer at the contact portion with the source region and a metal layer on the polysilicon layer.
Polysilicon can form a good ohmic contact with the impurity-doped region (impurity region) in SiC. Therefore, silication, which is indispensable for the structure in which the metal layer is in direct contact with the source region, can be omitted. Therefore, it is possible to prevent the generation of the carbon layer in the vicinity of the interface between the surface of the polysilicon layer and the source region in the polysilicon layer. As a result, layer peeling between the polysilicon layer and the metal layer and between the polysilicon layer and the source region can be suppressed. Therefore, the connection reliability of the source wiring can be improved.
Item 9. The semiconductor device according to Item 8, wherein an intermediate layer containing Ti is interposed between the polysilicon layer and the metal layer.

Titanium-containing materials have excellent adhesion to both polysilicon and metal materials. Therefore, in a semiconductor device having a structure in which a layer containing titanium is interposed between the polysilicon layer and the metal layer, the adhesion between the polysilicon layer and the metal layer can be improved. As a result, the connection reliability of the source wiring can be further improved.
Item 9. The item 9 has a structure in which the metal layer has a layer containing Al, and the intermediate layer has a structure in which a Ti layer and a TiN layer are laminated in this order from the side of the polysilicon layer. Semiconductor equipment.

Al can be used as an impurity for imparting conductivity to the polysilicon layer, but the resistance value of the polysilicon layer used as source wiring is unstable unless it is mixed in an appropriate amount in the polysilicon layer. May become.
Therefore, in the configuration of Item 10, a TiN layer is interposed between the Al-containing layer and the polysilicon layer as a barrier layer for preventing the diffusion of Al into the polysilicon layer. As a result, the excess Al does not diffuse into the polysilicon layer, so that the impurity concentration of the polysilicon layer can be stabilized. As a result, the resistance value of the polysilicon layer can be stabilized.
(Item 11) A step of forming a gate trench dug down from the surface of a first conductive type semiconductor layer made of SiC and having a Si surface on the surface, and nitrogen on the bottom surface and side surfaces of the gate trench. A step of forming a gate insulating film on the bottom surface and the side surface of the gate trench by oxidizing the gate trench in a gas containing oxygen at a heat treatment temperature of 1200 ° C. or higher, and the gate trench on the gate insulating film. A method for manufacturing a semiconductor device, which comprises a step of forming a gate electrode so as to fill the space.

If the bottom surface and the side surface of the gate trench are oxidized under the conditions in this method (atmospheric gas and heat treatment temperature), the ratio of the thickness of the bottom surface portion to the thickness of the side surface portion of the gate insulating film is 0.3. It can be set to ~ 1.0.
Further, in the step of forming the gate insulating film, as (Item 12), it is preferable to oxidize the bottom surface and the side surface of the gate trench in a gas containing at least N ₂ O, and further, N ₂ O gas. (Item 13), it is preferable to supply the gas at a flow rate ratio of 30% or less with respect to the total flow rate of the gas to be supplied.

The steps for forming the gate insulating film include a step of charging the semiconductor layer into a resistance heating furnace and a nitrogen and oxygen-containing gas atmosphere by introducing a gas containing nitrogen and oxygen into the resistance heating furnace. It may include a step of controlling the heating temperature of the resistance heating furnace to 1200 ° C. or higher while maintaining the gas atmosphere.
For example, the following findings are known as background techniques for heating a semiconductor layer made of SiC (for example, Japanese Patent Application Laid-Open No. 2003-318388).

Specifically, as a semiconductor device in which SiC is adopted, for example, a SiC layer having an activated ion region on the surface layer portion, a gate oxide film formed on the surface of the SiC layer, and a gate oxide film formed on the gate oxide film. A MOSFET having a MOS (Metal Oxide Semiconductor) structure including a gate electrode facing an ion region via a gate oxide film is known.
In order to fabricate such a MOS structure, for example, first, impurity ions are injected into the surface layer portion of the SiC layer. Next, the injected ions are activated by heating the SiC layer in the resistance heating furnace. After activation of the ions, a gate oxide film is formed on the surface of the SiC layer by supplying an oxygen-containing gas in a CVD (Chemical Vapor Deposition) apparatus. Then, the gate electrode is formed on the gate oxide film by the sputtering method. As a result, a layer structure (MOS structure) of a gate electrode (Metal) -gate oxide film (Oxide) -SiC layer (Semiconductor) is produced.

In order to activate the ions in the SiC layer, for example, it is necessary to perform an annealing treatment at a temperature of 1600 to 1700 ° C. In a resistance heating furnace, the heating time to a high temperature range becomes long, so that Si sublimates from the surface of the SiC layer, that is, so-called Si omission occurs during heating for ionic activity, and the surface of the SiC layer becomes rough. As a result, the interface between the SiC layer and the gate oxide film becomes uneven, and the channel mobility of the MOSFET decreases.

Therefore, a method is adopted in which the surface roughness of the SiC layer is suppressed by shortening the heating time to a high temperature range by using a high-frequency induction heating furnace, and then a gate oxide film is formed by using a gate oxidation furnace. ing.
However, in such a method, two devices, a high-frequency induction heating furnace and a gate oxidation furnace, are required separately, which causes a problem that the device cost increases.

As another method, it has been proposed to maintain the flatness of the surface of the SiC layer by forming a carbon film on the surface of the SiC layer prior to the activation of ions and preventing Si loss by the carbon film. ..
The carbon film is formed, for example, by forming a film containing carbon on the surface of the SiC layer and heating the film containing carbon in a high-frequency induction heating furnace to evaporate elements other than carbon from the film.

However, as a result of diligent research, the present inventors have found that the heating temperature for forming the carbon film may be about 1000 ° C., which is lower than the temperature for activating ions (1600-1700 ° C.). Therefore, it is necessary to control the heating temperature in two stages, but it has been found that it is difficult to precisely control the temperature of the high frequency induction heating furnace.
Further, after the activation of the ions, the carbon film becomes unnecessary. This unnecessary carbon film is oxidized and removed by an oxidizing gas in a device different from the high frequency induction heating furnace. It is also considered to introduce an oxidation gas into the high frequency induction heating furnace and remove the carbon film following the activation of ions, but since the carbon material is used for the heating element of the high frequency induction heating furnace, it is oxidized. When the gas is supplied, the carbon material is oxidized. Therefore, we have also found that a carbon film removing device is indispensable separately, and an increase in device cost is unavoidable.

Therefore, in order to achieve the object of providing a method for manufacturing a semiconductor device capable of suppressing the roughness of the surface of the SiC layer by simple temperature control without increasing the device cost, the following invention was made.
Specifically, the invention includes a step of forming an organic material film on the surface of a SiC layer in which ions are injected into a surface layer portion, and the organic material film in a resistance heating furnace after the formation of the organic material film. By heating the organic material film into a carbon film, and by heating the SiC layer on which the carbon film is formed in the resistance heating furnace, the ions in the SiC layer are activated. A step of oxidizing and removing the carbon film by introducing an oxygen-containing gas into the resistance heating furnace, and a step of removing the carbon film and then continuing to contain the oxygen in the resistance heating furnace. A method for manufacturing a semiconductor device, which comprises a step of oxidizing the surface of the SiC layer with a gas to form an oxide film.

According to this manufacturing method, after the formation of the organic material film, the organic material film is heated in the resistance heating furnace to change the quality of the organic material film into a carbon film, and the carbon film is formed on the surface of the SiC layer. After the formation of the carbon film, the SiC layer is heated to activate the ions in the SiC layer. After that, the carbon film is oxidized and removed by introducing an oxygen-containing gas into the resistance heating furnace. After the carbon film is removed, the surface of the SiC layer is oxidized by the oxygen-containing gas in the resistance heating furnace to form an oxide film.

Since the carbon film is formed on the surface of the SiC layer prior to heating for ionic activity, it is possible to prevent Si from coming off from the surface of the SiC layer when the SiC layer is heated. Therefore, the roughness of the surface of the SiC layer can be suppressed, and the flatness of the surface of the SiC layer can be maintained. As a result, the interface between the SiC layer and the oxide film can be smoothed, so that the channel mobility of the semiconductor device can be improved.

Further, a step of heating the organic material film to transform it into a carbon film, a step of heating the SiC layer to activate ions, a step of oxidizing and removing the carbon film with an oxygen-containing gas, and a step of oxidizing the surface of the SiC layer to oxidize it. The four steps of forming the film can be continuously performed in one resistance heating furnace. Since a separate device for removing the carbon film is not required, it is possible to suppress an increase in device cost. Moreover, since the resistance heating furnace is used, the heating temperature for forming the carbon film and the heating temperature for activating the ions can be precisely and easily controlled.

Further, the oxygen-containing gas may be a gas containing oxygen and nitrogen. If the oxygen-containing gas for forming the oxide film is a gas containing oxygen and nitrogen, the channel mobility of the semiconductor device can be further improved.
As the gas containing oxygen and nitrogen, for example, a gas containing NO (nitric oxide), N2O ₍ nitrous oxide) and the like can be used.

Further, the surface of the SiC layer is preferably a (0001) plane, that is, a Si plane.
As described above, the present inventors have invented an invention using a resistance heating furnace as an invention relating to heating of a semiconductor layer made of SiC.
Therefore, the step of forming the gate insulating film is a step of charging the semiconductor layer into the resistance heating furnace and a step of introducing a gas containing nitrogen and oxygen into the resistance heating furnace to create a nitrogen and oxygen-containing gas atmosphere. When the step of creating the above-mentioned gas atmosphere and the step of controlling the heating temperature of the resistance heating furnace to 1200 ° C. or higher while maintaining the gas atmosphere are included, in addition to the action and effect of the present invention, the above-mentioned resistance heating furnace can be used. You can enjoy the effects of the invention you used.

Next, the present invention will be described based on the reference examples of the present invention, but the present invention is not limited to the following reference examples.
Reference Example ₁ (N2O oxidation)
First, a SiC crystal was grown while doping N-type impurities on the Si surface of a wafer-shaped SiC substrate (manufactured by Cree) to form an epitaxial layer made of SiC. Next, a SiO ₂ mask having a predetermined pattern was formed on the surface (Si surface) of the epitaxial layer, and a trench was formed by injecting SF ₆ / O ₂ gas onto the surface of the epitaxial layer through the SiO ₂ mask.

Next, the SiC substrate was carried into the diffusion furnace, and N2O gas was supplied for ₃ hours while the inside of the diffusion furnace was heated to 1275 ° C. As a result, the inner surface of the trench was oxidized to form an oxide film.
Further, the oxide film when the supply time (oxidation time) of the N2O gas was ₈ hours and 12 hours was also formed by the same operation as described above.
Reference Example 2 (Dry Oxidation)
The same process as in Reference Example 1 was performed up to the process of forming the trench. After the trench was formed, the SiC substrate was carried into the diffusion furnace, and O ₂ gas was supplied for 4 hours while the inside of the diffusion furnace was heated to 1150 ° C. As a result, the inner surface of the trench was oxidized to form an oxide film.

Further, the oxide film when the supply time (oxidation time) of the O ₂ gas was 6 hours and 8 hours was also formed by the same operation as described above.
Reference Example 3 (Wet Oxidation)
The same process as in Reference Example 1 was performed up to the process of forming the trench. After forming the trench, the SiC substrate was carried into the diffusion furnace, and steam ( _H2O gas was supplied for 15 minutes while the inside of the diffusion furnace was heated to 1275 ° C., thereby oxidizing the inner surface of the trench to form an oxide film. bottom.

Further, the oxide film when the supply time (oxidation time) of the _H2O gas was 25 minutes and 35 minutes was also formed by the same operation as described above.
1) Measurement of oxide film thickness The thickness of each oxide film formed by Reference Examples 1 to 3 was measured for each portion on the side surface of the trench and the portion on the bottom surface of the trench. The results are shown in FIGS. 10 (a) to 10 (c) (FIG. 10 (a): Reference Example 1, FIG. 10 (b): Reference Example 2, FIG. 10 (c): Reference Example 3).
2) Thickness ratio of oxide film Using the thickness of each oxide film shown in FIGS. 10 (a) to 10 (c), the ratio of the thickness of the portion on the bottom surface to the thickness of the portion on the side surface of the oxide film. (Bottom / Side) was calculated. The results are shown in FIGS. 10 (a) to 10 (c).

According to FIG. 10 (a), the ratio of the thickness of the portion on the bottom surface (bottom surface / side surface) to the thickness of the portion on the side surface of the oxide film is about 0.54 (3 hours), 0 for each supply time. It was confirmed that it was .46 (8 hours) and 0.48 (12 hours).
Further, according to FIG. 10B, the ratio of the thickness of the portion on the bottom surface (bottom surface / side surface) to the thickness of the portion on the side surface of the oxide film is about 0.20 (4 hours) for each supply time. , 0.20 (6 hours), 0.19 (8 hours).

Further, according to FIG. 10 (c), the ratio of the thickness of the portion on the bottom surface (bottom surface / side surface) to the thickness of the portion on the side surface of the oxide film is about 0.23 (15 minutes) for each supply time. , 0.21 (25 minutes) and 0.22 (35 minutes).

1 Semiconductor device 3 epitaxial layer 5 body region 6 gate trench 9 gate insulating film 10 insulating film side 11 insulating film bottom 12 gate electrode 13 source region 18 polysilicon layer 25 intermediate layer 26 metal layer 41 semiconductor device 43 gate trench 51 epitaxial layer 53 Body area 55 Source area 61 Square part 62 Impla active layer 63 Gate insulating film 64 Insulating film bottom 65 Insulation film side 66 Gate electrode 69 Source wiring 70 Polysilicon layer 71 Intermediate layer 72 Metal layer 85 Semiconductor device

Claims (13)

A method for manufacturing a SiC semiconductor device in which a MOSFET having a gate trench is formed on the surface layer of a first conductive type SiC semiconductor layer.
A body-forming region in which second conductive ions are selectively injected so that a part is exposed on the inner surface of the gate trench, and a surface layer portion of the body-forming region so that a part is exposed on the inner surface of the gate trench. A carbon film is formed on the surface of the SiC semiconductor layer having a source forming region in which the first conductive ion is selectively injected so as to cover the inner surface of the body forming region, the source forming region and the gate trench. First step and
By heating the SiC semiconductor layer on which the carbon film is formed to activate the ions in the body forming region and the source forming region, a second conductive type body region is formed on the surface layer portion of the SiC semiconductor layer. A second step of forming a first conductive type source region on the surface layer portion of the body region and a first conductive type drain region on the back surface side of the SiC semiconductor layer with respect to the body region.
A third step of forming a gate insulating film on the inner surface of the gate trench and the surface of the SiC semiconductor layer after removing the carbon film is included.
The first step includes a step of holding the temperature at the first temperature for a predetermined time.
The second step includes a step of holding the temperature at a second temperature higher than the first temperature for a predetermined time.
In the step of forming the gate insulating film, the ratio of the first thickness of the portion on the bottom surface of the gate trench to the second thickness of the portion on the side surface of the gate trench (first thickness / second thickness). Including the step of forming the gate insulating film so that the ratio is 0.3 to 1.0.
The process of embedding polysilicon in the gate trench until the gate trench is filled,
A method for manufacturing a SiC semiconductor device, further comprising a step of etching back the polysilicon until the etched surface of the polysilicon is flush with the surface of the SiC semiconductor layer . The method for manufacturing a SiC semiconductor device according to claim ₁ , wherein the step of forming the gate insulating film is performed in a gas containing NO or N2O. The first step includes a step of forming an organic material film on the surface of the SiC semiconductor layer and heating the organic material film to the first temperature to change the quality of the organic material film into the carbon film. The method for manufacturing a SiC semiconductor device according to claim 1 or 2. The method for manufacturing a SiC semiconductor device according to claim 3, wherein polyimide is used as the organic material film. Further including the step of forming a source contact wiring that is ohmic-bonded to the source region.
The method for manufacturing a SiC semiconductor device according to any one of claims 1 to 4 , wherein the step of forming the source contact wiring includes a step of forming a polysilicon layer at a joint portion with the source region. The SiC semiconductor device according to claim 5 , further comprising a step of forming a source trench that penetrates the source forming region and the body forming region from the surface of the SiC semiconductor layer before the step of forming the carbon film. Production method. The method for manufacturing a SiC semiconductor device according to claim 6 , wherein the step of forming the source contact wiring includes a step of embedding the polysilicon layer in the source trench until the source trench is filled. The method for manufacturing a SiC semiconductor device according to any one of claims 5 to 7 , further comprising a step of injecting a first conductive type or a second conductive type impurity into the polysilicon layer. A method for manufacturing a SiC semiconductor device in which a MOSFET having a gate trench is formed on the surface layer of a first conductive type SiC semiconductor layer.
A body-forming region in which second conductive ions are selectively injected so that a part is exposed on the inner surface of the gate trench, and a surface layer portion of the body-forming region so that a part is exposed on the inner surface of the gate trench. A carbon film is formed on the surface of the SiC semiconductor layer having a source forming region into which the first conductive type ion is selectively injected so as to cover the inner surface of the body forming region, the source forming region and the gate trench. First step and
By heating the SiC semiconductor layer on which the carbon film is formed to activate the ions in the body forming region and the source forming region, a second conductive type body region is formed on the surface layer portion of the SiC semiconductor layer. A second step of forming a first conductive type source region on the surface layer portion of the body region and a first conductive type drain region on the back surface side of the SiC semiconductor layer with respect to the body region.
A third step of forming a gate insulating film on the inner surface of the gate trench and the surface of the SiC semiconductor layer after removing the carbon film is included.
The first step includes a step of holding the temperature at the first temperature for a predetermined time.
The second step includes a step of holding the temperature at a second temperature higher than the first temperature for a predetermined time.
Further including the step of forming a source contact wiring that is ohmic-bonded to the source region.
The step of forming the source contact wiring includes a step of forming a polysilicon layer at a joint portion with the source region.
A method for manufacturing a SiC semiconductor device, further comprising a step of forming a source trench that penetrates the source forming region and the body forming region from the surface of the SiC semiconductor layer before the step of forming the carbon film. A method for manufacturing a SiC semiconductor device in which a MOSFET having a gate trench is formed on the surface layer of a first conductive type SiC semiconductor layer.
A body-forming region in which second conductive ions are selectively injected so that a part is exposed on the inner surface of the gate trench, and a surface layer portion of the body-forming region so that a part is exposed on the inner surface of the gate trench. A carbon film is formed on the surface of the SiC semiconductor layer having a source forming region in which the first conductive ion is selectively injected so as to cover the inner surface of the body forming region, the source forming region and the gate trench. First step and
By heating the SiC semiconductor layer on which the carbon film is formed to activate the ions in the body forming region and the source forming region, a second conductive type body region is formed on the surface layer portion of the SiC semiconductor layer. A second step of forming a first conductive type source region on the surface layer portion of the body region and a first conductive type drain region on the back surface side of the SiC semiconductor layer with respect to the body region.
A third step of forming a gate insulating film on the inner surface of the gate trench and the surface of the SiC semiconductor layer after removing the carbon film is included.
The first step includes a step of holding the temperature at the first temperature for a predetermined time.
The second step includes a step of holding the temperature at a second temperature higher than the first temperature for a predetermined time.
The first step includes a step of forming an organic material film on the surface of the SiC semiconductor layer and heating the organic material film to the first temperature to change the quality of the organic material film into the carbon film.
The third step includes a step of oxidizing and removing the carbon film with an oxygen-containing gas and oxidizing the SiC semiconductor layer to form the gate insulating film.
A method for manufacturing a SiC semiconductor device, wherein the first step, the second step, and the third step are continuously performed in one heating furnace without taking out the SiC semiconductor layer from the heating furnace. The SiC semiconductor device according to any one of claims 1 to 10 , wherein the step of forming the gate insulating film includes a step of forming a gate insulating film containing nitrogen at a concentration of 0.1 to 10%. Production method. The third step includes a step of oxidizing and removing the carbon film with an oxygen-containing gas and oxidizing the SiC semiconductor layer to form the gate insulating film.
The method for manufacturing a SiC semiconductor device according to claim 3, wherein the first step, the second step, and the third step are continuously performed in one heating furnace without taking out the SiC semiconductor layer from the heating furnace. .. A method for manufacturing a SiC semiconductor device in which a MOSFET having a gate trench is formed on the surface layer of a first conductive type SiC semiconductor layer.
A body-forming region in which second conductive ions are selectively injected so that a part is exposed on the inner surface of the gate trench, and a surface layer portion of the body-forming region so that a part is exposed on the inner surface of the gate trench. A carbon film is formed on the surface of the SiC semiconductor layer having a source forming region in which the first conductive ion is selectively injected so as to cover the inner surface of the body forming region, the source forming region and the gate trench. First step and
By heating the SiC semiconductor layer on which the carbon film is formed to activate the ions in the body forming region and the source forming region, a second conductive type body region is formed on the surface layer portion of the SiC semiconductor layer. A second step of forming a first conductive type source region on the surface layer portion of the body region and a first conductive type drain region on the back surface side of the SiC semiconductor layer with respect to the body region.
A third step of forming a gate insulating film on the inner surface of the gate trench and the surface of the SiC semiconductor layer after removing the carbon film is included.
The first step includes a step of holding the organic material film at the first temperature for a predetermined time, and by forming an organic material film on the surface of the SiC semiconductor layer and heating the organic material film to the first temperature, the organic material film is formed. Including the step of transforming the material film into the carbon film.
The second step includes a step of holding the temperature at a second temperature higher than the first temperature for a predetermined time.
The third step includes a step of oxidizing and removing the carbon film with an oxygen-containing gas.
A method for manufacturing a SiC semiconductor device, wherein the first step, the second step, and the third step are continuously performed in one heating furnace without taking out the SiC semiconductor layer from the heating furnace.

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