CN116741639A - Method for manufacturing semiconductor device and semiconductor device - Google Patents
Method for manufacturing semiconductor device and semiconductor device Download PDFInfo
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- CN116741639A CN116741639A CN202310736843.7A CN202310736843A CN116741639A CN 116741639 A CN116741639 A CN 116741639A CN 202310736843 A CN202310736843 A CN 202310736843A CN 116741639 A CN116741639 A CN 116741639A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 63
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 238000000034 method Methods 0.000 title claims description 71
- 239000000758 substrate Substances 0.000 claims abstract description 177
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 149
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 142
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 46
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 46
- 239000010703 silicon Substances 0.000 claims abstract description 46
- 230000007547 defect Effects 0.000 claims abstract description 35
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- 229910052799 carbon Inorganic materials 0.000 claims description 18
- 239000013078 crystal Substances 0.000 claims description 16
- 238000002513 implantation Methods 0.000 claims description 15
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 14
- 238000005468 ion implantation Methods 0.000 claims description 14
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 11
- -1 hydrogen ions Chemical class 0.000 claims description 8
- 229910052757 nitrogen Inorganic materials 0.000 claims description 7
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 5
- 229910052698 phosphorus Inorganic materials 0.000 claims description 5
- 239000011574 phosphorus Substances 0.000 claims description 5
- 238000012545 processing Methods 0.000 claims description 5
- 239000012300 argon atmosphere Substances 0.000 claims description 4
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- 229910052734 helium Inorganic materials 0.000 claims description 3
- 239000001257 hydrogen Substances 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 239000000463 material Substances 0.000 abstract description 20
- 238000002360 preparation method Methods 0.000 abstract description 9
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- 239000010408 film Substances 0.000 description 26
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6835—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during build up manufacturing of active devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
- H01L2221/68386—Separation by peeling
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Recrystallisation Techniques (AREA)
Abstract
The application discloses a preparation method of a semiconductor device and the semiconductor device, wherein an epitaxial layer is homoepitaxial on a first silicon carbide substrate; manufacturing a doped well region on the epitaxial defect layer formed in the epitaxial layer, and bonding the doped well region with the second silicon carbide substrate; the substrate quality of the first silicon carbide substrate is higher than the substrate quality of the second silicon carbide substrate; stripping a portion of the device structure including the first silicon carbide substrate along the epitaxial defect layer and post-treating the stripped surface to expose a second side of the stripped epitaxial layer; bonding the second surface subjected to the conductive treatment with the silicon substrate; and removing the second silicon carbide substrate, activating the bonding interface, preparing the gate oxide layer and the metal layer, and forming the semiconductor device. Therefore, the difficulty in epitaxial silicon carbide on the silicon substrate is solved, the excellent performance of the silicon carbide material can be fully exerted, the performance of a semiconductor device is improved, and meanwhile, the dependence on high-quality silicon carbide material and the device cost are reduced.
Description
Technical Field
The present application relates to the field of semiconductor technologies, and in particular, to a method for manufacturing a semiconductor device and a semiconductor device.
Background
Silicon carbide (SiC) is taken as a representative material in a third-generation semiconductor, combines excellent characteristics of wide band gap (2.4 eV-3.2 eV), high physical strength, high heat conductivity, high corrosion resistance, high melting point, wide light transmission window (0.37-5.6 mu m), wide defect light emitting window (visible light to middle infrared) and the like, and is an ideal material for the current high-voltage power device.
Furthermore, silicon carbide materials have 200 more crystal forms, with the most commonly used being 3C-SiC,4H-SiC and 6H-SiC. The 3C-SiC film is mainly formed by using normal pressure chemical vapor deposition (APCVD) and Reduced Pressure Chemical Vapor Deposition (RPCVD) to deposit a silicon carbide film on the surface of a silicon substrate, however, the 3C-SiC film prepared by the method is mainly a polycrystalline film, and the crystal quality cannot reach single crystals. Although purer single crystal materials can be prepared by PVT (Physical Vapor Transport ) method, single crystal silicon carbide thin films cannot be grown on silicon substrates by conventional thin film deposition heteroepitaxy methods because the growth temperature of 4H-SiC is greater than the melting point temperature of silicon using PVT method. In addition, at present, the problems of defect control in the silicon carbide growth process, material loss caused by cutting, grinding and polishing and the like further highlight the problems of silicon carbide yield and cost, so that the manufacturing cost of homoepitaxy for producing a monocrystalline silicon carbide film on a large-size silicon carbide substrate is increased, and the large-scale use of silicon carbide in the semiconductor field is prevented.
Disclosure of Invention
Aiming at least one technical problem in the prior art, the application aims to provide a preparation method of a semiconductor device and the semiconductor device.
In order to solve the above technical problems, in one aspect, the present application provides a method for manufacturing a semiconductor device, including the steps of:
providing a first silicon carbide substrate, and homoepitaxially growing an epitaxial layer on the first silicon carbide substrate;
performing first ion implantation on the exposed first surface of the epitaxial layer to form an epitaxial defect layer in the epitaxial layer;
a doped well region is manufactured between the first surface and the epitaxial defect layer, and a first intermediate device structure is formed;
providing a second silicon carbide substrate and bonding with the first intermediate device structure based on the first face; the substrate quality of the first silicon carbide substrate is higher than the substrate quality of the second silicon carbide substrate;
stripping part of the device structure including the first silicon carbide substrate along the layer direction of the epitaxial defect layer, and carrying out post-treatment on the stripped surface to expose the second face in the stripped epitaxial layer;
conducting treatment is carried out on the second surface to form a second intermediate device structure;
providing a silicon substrate and bonding with the inverted second intermediate device structure based on the second face;
removing the second silicon carbide substrate, and activating a bonding interface to form a third intermediate device structure;
and preparing a gate oxide layer and a metal layer on the third intermediate device structure to form the semiconductor device.
In an alternative embodiment, the implantation parameters of the first ions include at least one of:
the implantation element of the first ion comprises one or more of hydrogen ions and helium ions;
the implantation dosage range of the first ion is 1E17/cm 2 ～1E20/cm 2 ；
The implantation energy of the first ions ranges from 2MeV to 10MeV.
In an alternative embodiment, the doping elements of the epitaxial layer comprise one or more of nitrogen and phosphorus, and the doping concentration ranges from 1E12 to 1E15/cm 3 ；
The dimension of the substrate quality includes one or more of a number of substrate forms, a type of substrate form, and a density of substrate defects.
In an alternative embodiment, the post-treating the lift-off surface to expose the second side of the lifted-off epitaxial layer includes:
thinning the peeling surface based on a preset thinning thickness;
taking the exposed thinned stripping surface as the second face in the stripped epitaxial layer;
wherein the preset reduced thickness is any value of 1.5-3 mu m.
In an alternative embodiment, the conducting treatment on the second surface, forming the second intermediate device structure includes:
performing second ion implantation on the second surface to form a conductive layer in the stripped epitaxial layer; the second ion is of a different type than the first ion; the upper edge of the conductive layer is flush with the second face;
and carrying out primary annealing treatment on the conductive layer and the doped well region to form the second intermediate device structure.
In an alternative embodiment, the processing conditions of the primary annealing process include at least one of:
the annealing environment is vacuum, nitrogen atmosphere or argon atmosphere;
the annealing temperature is 1500-1800 ℃, the annealing time is 0.5-5 hours, and the annealing time is inversely related to the annealing temperature;
and protecting the carbon film before annealing, wherein the thickness of the carbon film is 100-1000 nanometers, and the thickness of the carbon film is in a direct proportion relation with the annealing temperature and in an inverse proportion relation with the annealing air pressure.
In an alternative embodiment, the activating the bonding interface, forming the third intermediate device structure, includes:
and carrying out secondary annealing treatment on the device structure from which the second silicon carbide substrate is removed so as to activate a bonding interface between the silicon substrate and the inverted second intermediate device structure, thereby forming the third intermediate device structure.
In an alternative embodiment, the process conditions of the secondary annealing process include at least one of:
the annealing environment is vacuum or nitrogen atmosphere;
the annealing temperature is 1300-1370 ℃, the annealing time is 3-5 hours, and the annealing time is inversely related to the annealing temperature;
and protecting the carbon film before annealing, wherein the thickness of the carbon film is 100-500 nanometers, and the thickness of the carbon film is in a direct proportion relation with the annealing temperature and in an inverse proportion relation with the annealing air pressure.
In an alternative embodiment, the first silicon carbide substrate is a single crystal silicon carbide substrate;
the second silicon carbide substrate comprises at least one of a mixed crystal silicon carbide substrate and a polycrystalline silicon carbide substrate;
the resistance of the silicon substrate is lower than or equal to 10 ohms, and the conductivity type of the silicon substrate is the same as that of the first silicon carbide substrate.
On the other hand, the application also provides a semiconductor device, which is prepared by the method according to any one of the embodiments of the application.
The preparation method of the semiconductor device and the semiconductor device have at least the following beneficial effects:
in the embodiment of the application, the semiconductor device comprising the silicon substrate and the silicon carbide epitaxial layer is formed by adopting the high-quality first silicon carbide substrate homoepitaxial epitaxial layer, bonding the epitaxial layer and the low-quality second silicon carbide substrate, stripping part of the device structure comprising the high-quality first silicon carbide substrate through the epitaxial defect layer formed in the epitaxial layer, transferring the stripped device structure onto the silicon substrate and adopting a mode of manufacturing the doped well region, the gate oxide layer and the metal layer separately. And the prepared semiconductor device comprises the stripped part of silicon carbide epitaxial layer, so that the excellent performance of the silicon carbide material is brought into play, and the performance of the semiconductor device is improved. In addition, by transferring the epitaxial silicon carbide film onto a low-cost second silicon carbide substrate and then onto a silicon substrate through heterobonding, the cost of the silicon carbide monolithic is reduced on the basis of overcoming the difficulty in preparing silicon carbide materials by silicon base, the wafer size can be expanded to 8 inches along with the development of the industry, and meanwhile, the compatibility of the silicon carbide monolithic with the existing silicon base integrated circuit process is ensured. And the prepared semiconductor device does not contain a high-quality first silicon carbide substrate, and only the high-quality first silicon carbide substrate is used for epitaxy of the silicon carbide epitaxial layer, so that the dependence on high-quality silicon carbide materials is reduced, the device cost is reduced, and the wide application of silicon carbide in the field of semiconductors is facilitated.
Drawings
In order to more clearly illustrate the embodiments of the application or the technical solutions and advantages of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are only some embodiments of the application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of a device in step S102 in a method for manufacturing a semiconductor device according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a device in step S103 in a method for manufacturing a semiconductor device according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a device in step S105 in a method for manufacturing a semiconductor device according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of a device in step S106 in a method for manufacturing a semiconductor device according to an embodiment of the present application;
fig. 6 is a schematic structural diagram of a device in step S107 in a method for manufacturing a semiconductor device according to an embodiment of the present application;
fig. 7 is a schematic structural diagram of a device in step S108 in a method for manufacturing a semiconductor device according to an embodiment of the present application;
fig. 8 is a schematic structural diagram of a device in step S109 in a method for manufacturing a semiconductor device according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Reference hereinafter to "one embodiment" or "an embodiment" or the like means that a particular feature, structure, or characteristic may be included in at least one implementation of the application. In the description of the present application, unless explicitly specified and limited otherwise, the terms "upper", "lower", "left", "right", "top", "bottom", etc. indicate an orientation or a positional relationship based on that shown in the drawings, merely for convenience of description of the present application and to simplify the description, and do not indicate or imply that the apparatus or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may include one or more of the feature, either explicitly or implicitly. Moreover, the terms "first," "second," and the like, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be implemented in sequences other than those illustrated or otherwise described herein.
It will be understood that when a layer, an area, or a component is described as being "on" or "over" another layer, another area, it can be directly on the other layer, another area, or another layer or area can be included between the layer and the other layer, another area. And if the component is turned over, the one layer, region, would be "under" or "beneath" the other layer, region.
In the related art, although a purer single crystal material can be prepared by a PVT (Physical Vapor Transport ) method, a single crystal silicon carbide thin film cannot be grown on a silicon substrate by a conventional thin film deposition heteroepitaxy method because a growth temperature of 4H-SiC is greater than a melting point temperature of silicon by the PVT method. In addition, at present, the problems of defect control in the silicon carbide growth process, material loss caused by cutting, grinding and polishing and the like further highlight the problems of silicon carbide yield and cost, so that the manufacturing cost of homoepitaxy for producing a monocrystalline silicon carbide film on a large-size silicon carbide substrate is increased, and the large-scale use of silicon carbide in the semiconductor field is prevented. To this end, embodiments of the present application provide a method of manufacturing a silicon carbide-containing semiconductor device at low cost.
Fig. 1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present application. Fig. 2 to 8 are schematic views of devices at various steps in a method for manufacturing a semiconductor device according to some preferred embodiments of the present application. The drawings illustrate only those portions of the various embodiments that are common and possibly non-common, and that are different or distinct from each other are presented in a literal manner. To reduce redundant and unnecessary repetition of the description, those skilled in the art will appreciate and appreciate that they can readily use the industrial features and techniques to determine whether a single feature or a combination of any of the features described below can be utilized in a single embodiment or that multiple features that are mutually exclusive in nature can only be utilized in a single embodiment.
The preparation method of the semiconductor device provided by the embodiment of the application comprises the following steps.
In step S101, a first silicon carbide substrate is provided, and an epitaxial layer is homoepitaxially grown on the first silicon carbide substrate.
The first silicon carbide substrate may refer to a high quality silicon carbide substrate suitable for use in the fabrication of semiconductor devices. In particular, the first silicon carbide substrate may be a single crystal substrate having a low defect content, and the silicon carbide substrate may have a size greater than or equal to a preset size threshold, which may be 8 inches, for example. Of course, the preset size threshold may be a value below 8 inches or greater than 8 inches, depending on the actual needs.
In some embodiments, as shown in fig. 2, an epitaxial layer 220 may be homoepitaxially grown on the first silicon carbide substrate 210 by an epitaxial process. An epitaxial process refers to a process of growing a single crystal layer in complete alignment on a substrate. Generally, an epitaxial process is a process of growing a layer of crystals on a single crystal substrate that has the same lattice orientation as the original substrate, which corresponds to extending the crystals of the single crystal substrate outward a length. Here, the material of the epitaxial layer 220 is the same as that of the first silicon carbide substrate 210, and the lattice orientation is the same, that is, a monocrystalline silicon carbide epitaxial layer is obtained.
In some embodiments, the epitaxial layer 220 may have a thickness of 11 μm to 21 μm, specifically, 10 μm to 20 μm, such as 10.2 μm, 12 μm, 15 μm, 18.1 μm, 20 μm, and so on.
In some embodiments, the epitaxial layer 220 is the same material property as the first silicon carbide substrate 210. For example, if the first silicon carbide substrate 210 is an N-type silicon carbide substrate doped with a first dopant (e.g., nitrogen, phosphorus elements, combinations thereof, etc.), the epitaxial layer 220 is the N-region of the device. The n-region can be obtained by doping an initial epitaxial layer obtained by epitaxy, wherein the doping elements of the epitaxial layer can comprise one or more of nitrogen and phosphorus elements, and the doping concentration can be 1E 12-1E 15/cm 3 . For another example, if the first silicon carbide substrate 210 is a P-type silicon carbide substrate, the epitaxial layer 220 is the P-region of the device. The p-region can be obtained by doping an epitaxial layer obtained by epitaxy, wherein the doping element of the epitaxial layer comprises boron element, and the doping concentration range of the epitaxial layer can be 1E 12-1E 15/cm 3 。
Step S102, performing first ion implantation on the exposed first surface of the epitaxial layer to form an epitaxial defect layer in the epitaxial layer.
In some embodiments, as further shown in fig. 2, the first face a1 may be the top face of the epitaxial layer that is exposed. The first surface a1 exposed from the epitaxial layer 220 is subjected to a first ion implantation process to form an epitaxial defect layer 222 in the epitaxial layer 220. The distance between the epitaxial defect layer and the exposed first surface of the epitaxial layer is far greater than the distance between the epitaxial defect layer and the lower edge of the epitaxial layer.
In some embodiments, the implantation energy of the first ions may be 5 to 15 times the conventional ion implantation energy. For example only, the implantation energy of the first ion may range from 2MeV to 10MeV, such as 3MeV, 4MeV, 4.5MeV, 5.8MeV, 7MeV, 8MeV, 9MeV, 9.6MeV, and the like. The implantation energy of the first ions used herein is much higher than conventional ion implantation energy, so that the deeper the implantation depth of the obtained epitaxial defect layer 222 in the epitaxial layer 220 is by high ion implantation energy, the thicker the lift-off epitaxial film, i.e., the lift-off silicon carbide film, is facilitated for subsequent lift-off, so that the semiconductor device prepared to include the lift-off silicon carbide film fully utilizes the good performance of single crystal silicon carbide.
In some embodiments, the implanted element of the first ion comprises one or more of hydrogen ions, helium ions.
In some embodiments, the first ion is implanted at a dose range of 1E17/cm 2 ～1E20/cm 2 Any one of the values.
And step S103, manufacturing a doped well region between the first surface and the epitaxial defect layer to form a first intermediate device structure.
In some embodiments, as shown in fig. 3, the first well region 232a and the second well region 232b may be formed in the epitaxial layer by doping a second dopant between the first face a1 and the epitaxial defect layer 222. The first well region 232a and the second well region 232b are disposed side by side and spaced apart, for example, the first well region 232a and the second well region 232b may be disposed at two corner regions of the epitaxial layer. Thereafter, first dopants are doped into the first well region 232a and the second well region 232b, respectively, to form a first doped region 234a and a second doped region 234b, and an upper surface of the first doped region 234a and an upper surface of the second doped region 234b may be flush with an upper surface of the epitaxial layer 220, respectively. The first intermediate device structure is formed by the first well region 232a and the corresponding first doped region 234a, and the second well region 232b and the corresponding second doped region 234b forming the doped well region 230.
The preparation process for forming the well region and the corresponding doped region can be as follows: the well region and the corresponding doped region are generated by depositing a mask on the epitaxial layer and then doping the exposed portions through the mask.
Wherein the first dopant is of a different conductivity type than the second dopant. Taking the conductivity type of the first dopant as N-type as an example, the conductivity type of the second dopant is P-type, i.e., the doped well region includes a P-type first well region 232a and a P-type second well region 232b, and an N-type first doped region 234a and an N-type second doped region 234b covering a portion of each well region.
In addition, after the doped well region is prepared on the surface of the implanted epitaxial structure, the subsequent bonding step can be directly performed without doping activation treatment.
Step S104, providing a second silicon carbide substrate and bonding with the first intermediate device structure based on the first surface; the substrate mass of the first silicon carbide substrate is higher than the substrate mass of the second silicon carbide substrate.
In some embodiments, the substrate quality of the first silicon carbide substrate 210 is higher than the substrate quality of the second silicon carbide substrate 240. That is, the second silicon carbide substrate 240 does not employ high-quality single crystal silicon carbide, but uses low-quality silicon carbide. The dimension of the substrate quality includes one or more of a number of substrate forms, a type of substrate form, and a density of substrate defects.
For example only, the first silicon carbide substrate 210 comprises a high quality single crystal silicon carbide substrate, such as 4H-SiC or the like. The second silicon carbide substrate 240 may include one or more of a test grade (Dummy grade) single crystal silicon carbide substrate, a mixed crystal silicon carbide substrate, and a polycrystalline silicon carbide substrate. In addition, the defect density (e.g., micropipe density) content of the first silicon carbide substrate 210 is lower than the defect density of the second silicon carbide substrate 240.
In some embodiments, as shown in fig. 4, after the second silicon carbide substrate 240 is provided, the second silicon carbide substrate 240 may be bonded to the first face a1 of the first intermediate device structure by a wafer bonding process, resulting in a first bonded structure. The wafer bonding process includes, but is not limited to, one or more of direct bonding and hydrophilic bonding. Taking direct bonding as an example, plasma activation treatment is performed on the surface to be bonded, and the two surfaces are directly bonded, wherein the plasma activation type comprises but is not limited to nitrogen, oxygen or argon, and the bonding temperature can be 20-800 ℃.
And step S105, stripping part of the device structure including the first silicon carbide substrate along the layer direction of the epitaxial defect layer, and carrying out post-treatment on the stripped surface to expose the second face in the stripped epitaxial layer.
In some embodiments, continuing as shown in fig. 4, the first bonded structure may be stripped along the layer direction of the epitaxial defect layer 222 by a stripping process, stripping away a portion of the device structure including the first silicon carbide substrate 210, and post-treating the stripped surface to expose the second face a2 in the stripped epitaxial layer 220 a. The stripping process may include, but is not limited to, mechanical stripping or thermal stripping. By post-treating the release surface, the quality of the release surface can be improved and the adverse effects of the defect layer can be reduced.
Alternatively, the thickness of the stripped epitaxial layer 220a may be 10 μm to 20 μm, such as 10 μm, 11.8 μm, 14.9 μm, 18 μm, 19.8 μm, and so on. The difference in thickness between epitaxial layer 220 and stripped epitaxial layer 220a may be greater than or approximately equal to 0.
In some embodiments, post-treating the lift-off surface to expose the second face in the lifted-off epitaxial layer comprises: thinning the peeling surface based on a preset thinning thickness; taking the exposed thinned stripping surface as a second face in the stripped epitaxial layer; wherein, the preset thickness is any value of 1.5-3 mu m.
Specifically, the thinning treatment may be performed on the peeled surface by an etching thinning process in accordance with a preset thinning thickness, after which the thinned peeled surface is exposed, and the exposed thinned peeled surface is taken as the second face in the peeled epitaxial layer. The preset reduced thickness may take the value of 1.5 μm, 1.8 μm, 2 μm, 2.3 μm, 2.5 μm, 2.7 μm, or 3 μm.
And S106, conducting treatment is carried out on the second surface to form a second intermediate device structure.
Wherein the interface in the second intermediate device structure for bonding with the silicon substrate exhibits electrical conductivity. The conductive treatment may be achieved by ion implantation or the like.
In some embodiments, conducting the second side, forming the second intermediate device structure includes:
performing second ion implantation on the second surface to form a conductive layer in the stripped epitaxial layer; the type of the second ion is different from the type of the first ion; the upper edge of the conductive layer is flush with the second surface;
and carrying out primary annealing treatment on the conductive layer and the doped well region to form a second intermediate device structure.
In an embodiment of the present application, as shown in fig. 5, by performing the second ion implantation on the second face a2, the conductive layer 224 is formed in the stripped epitaxial layer 220a, and the upper edge of the conductive layer 224 may be flush with the second face. The second ion is different from the first ion in type, and is different from the first ion in film stripping, and can be one or more of N-type implanted ions such as nitrogen, phosphorus, etc. with an implantation dosage of 5E 13-1E 16/cm 2 The implantation energy is 5 keV-30 keV.
And, after the second ion implantation, an annealing treatment is performed on the conductive layer 224 and the doped well region 230 to activate all the implanted doped regions, thereby forming a second intermediate device structure. Therefore, the activation treatment is not needed immediately after the doped well region is prepared before, but the conductive layer and the doped well region are subjected to the activation treatment together, so that the activation treatment procedure is reduced, and the device preparation flow is shortened. In addition, by reducing the number of activations, defects or adverse effects caused by the activations can be reduced, which is beneficial to improving the recovery value and the overall device performance of the first silicon carbide substrate.
In some embodiments, the processing conditions of the primary annealing process may include at least one of:
the annealing environment is vacuum, nitrogen atmosphere or argon atmosphere (the pressure is 0.2-0.5 atmosphere);
the annealing temperature is 1500-1800 ℃, the annealing time is 0.5-5 hours, and the annealing time is inversely related to the annealing temperature;
the carbon film is protected before annealing, the thickness of the carbon film is 100-1000 nanometers, the thickness of the carbon film is in direct proportion to the annealing temperature, and in inverse proportion to the annealing air pressure.
Step S107, providing a silicon substrate and bonding with the inverted second intermediate device structure based on the second side.
Wherein the conductivity type of the silicon substrate may be the same as that of the first silicon carbide substrate 210, and the silicon substrate may be an N-type low-resistance silicon wafer, for example. Alternatively, the silicon substrate has a resistance value of less than or equal to 10 ohms, for example, the silicon substrate has a resistance value of 0.01 to 10 ohms.
As shown in fig. 6, after the N-type low-resistance silicon substrate 250 is obtained, the silicon substrate 250 and the inverted second intermediate device structure may be bonded by a wafer bonding process, where the bonding surface is the top surface of the second surface a2 of the second intermediate device structure after conducting treatment and the silicon substrate 250. The wafer bonding process includes, but is not limited to, one or more of direct bonding and hydrophilic bonding. Taking direct bonding as an example, plasma activation treatment is performed on the surface to be bonded, and the two surfaces are directly bonded, wherein the plasma activation type comprises but is not limited to nitrogen, oxygen or argon, and the bonding temperature can be 20-800 ℃.
And S108, removing the second silicon carbide substrate, and activating a bonding interface to form a third intermediate device structure.
As shown in fig. 7, after bonding with the silicon substrate, the second silicon carbide substrate 240 may be removed, for example, by a thinning process (e.g., mechanical grinding, etc.), leaving the epitaxial layer 220a, the conductive layer 224, and the silicon substrate 250. And then, activating a bonding interface between the silicon substrate and the second intermediate device structure through an activation process to form a third intermediate device structure.
In some embodiments, activating the bonding interface, forming the third intermediate device structure includes: the device structure from which the second silicon carbide substrate 240 was removed is subjected to a second anneal process to activate the bonding interface between the silicon substrate 250 and the inverted second intermediate device structure, forming a third intermediate device structure.
In some embodiments, the processing conditions of the secondary annealing process may include at least one of:
the annealing environment is vacuum, nitrogen atmosphere or argon atmosphere (the pressure is 0.2-0.5 atmosphere);
the annealing temperature is 1300-1370 ℃, the annealing time is 3-5 hours, and the annealing time is inversely related to the annealing temperature;
the carbon film is protected before annealing, the thickness of the carbon film is 100-500 nanometers, the thickness of the carbon film is in direct proportion to the annealing temperature, and in inverse proportion to the annealing air pressure.
And step S109, preparing a gate oxide layer and a metal layer on the third intermediate device structure to form the semiconductor device.
After forming the third intermediate device structure, a gate oxide layer and a metal layer may be prepared on the third intermediate device structure to form a semiconductor device.
In some embodiments, as shown in fig. 8, the gate oxide layer 260 may include a gate electrode 264 and an interlayer dielectric layer 262, the interlayer dielectric layer 262 being disposed on the top surface of the third intermediate device structure, the gate electrode 264 being disposed inside the interlayer dielectric layer 262.
The metal layer 280 includes a first metal layer 282 disposed on the back side of the third intermediate device structure for forming the drain electrode, and a second metal layer 284 disposed on the top side of the third intermediate device structure for forming the source electrode. The first metal layer 282 is disposed on the back side of the silicon substrate in the third intermediate device structure. The middle portion of the second metal layer 284 covers the gate oxide, and the two side portions of the second metal layer 284 cover the top surface of the third intermediate device structure and are flush with the side surfaces of the third intermediate device structure. Specifically, a second metal layer 284 is deposited on the upper surface of the third intermediate device structure and the upper surface of the gate oxide layer 260, and an annealing process is performed to form a source electrode. Wherein the material of the deposited metal includes but is not limited to Al, alCu (aluminum copper alloy) and AlSiCu (aluminum silicon copper alloy), and the thickness of the second metal layer can be 1-10 μm.
The semiconductor device formed here may be referred to as a planar MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) device, or may be a trench MOSFET device. In forming the trench MOSFET device, a trench (not shown) may be formed in the third intermediate device structure, and then a gate oxide and a metal layer may be formed on the third intermediate device structure after forming the trench to obtain the trench MOSFET device.
In the above embodiment, in the process of manufacturing the semiconductor device, only the high-quality first silicon carbide substrate homoepitaxial layer is adopted, bonding is performed between the epitaxial layer and the low-quality second silicon carbide substrate, and part of the device structure including the high-quality first silicon carbide substrate is stripped through the epitaxial defect layer formed in the epitaxial layer, and then the stripped device structure is transferred onto the silicon substrate, and the doped well region, the gate oxide layer and the metal layer are manufactured separately, so that the semiconductor device including the silicon substrate and the silicon carbide epitaxial layer is formed. And the prepared semiconductor device comprises the stripped part of silicon carbide epitaxial layer, so that the excellent performance of the silicon carbide material is brought into play, and the performance of the semiconductor device is improved. In addition, by transferring the epitaxial silicon carbide film onto a low-cost second silicon carbide substrate and then onto a silicon substrate through heterobonding, the cost of the silicon carbide monolithic is reduced on the basis of overcoming the difficulty in preparing silicon carbide materials by silicon base, the wafer size can be expanded to 8 inches along with the development of the industry, and meanwhile, the compatibility of the silicon carbide monolithic with the existing silicon base integrated circuit process is ensured. And the prepared semiconductor device does not contain a high-quality first silicon carbide substrate, and only the high-quality first silicon carbide substrate is used for epitaxy of the silicon carbide epitaxial layer, so that the dependence on high-quality silicon carbide materials is reduced, the device cost is reduced, and the wide application of silicon carbide in the field of semiconductors is facilitated.
In some embodiments, the above method further comprises: and recycling the stripped first silicon carbide substrate.
In some embodiments, the recycling process step may include: and finally, polishing the rest surface of the first silicon carbide substrate after being treated by hydrofluoric acid, thus obtaining the recovered first silicon carbide substrate. The recovered first silicon carbide substrate can be continuously applied to the preparation of semiconductor devices, and the recycling of the first silicon carbide substrate is realized. The recovery method is different from the conventional grinding and polishing process, and can ensure the wafer morphology of the substrate, and meanwhile, the use times of the substrate are kept to the maximum extent, so that the manufacturing cost of the prepared semiconductor device is reduced while the performance of silicon carbide is considered.
In one embodiment, the recycling step may specifically include: firstly, carrying out thermal oxidation treatment on the stripped first silicon carbide substrate, and carrying out wet oxidation for 2-5 hours in a pure oxygen environment at 1300 ℃; and etching by a hydrofluoric acid wet method to remove an oxide layer, and finally carrying out fine polishing treatment on the residual surface of the first silicon carbide substrate subjected to hydrofluoric acid treatment, wherein the film removal thickness is not more than 500nm, so that the recovered first silicon carbide substrate is obtained.
Because the ion implantation energy is large and the defect layer is deeper, the simple chemical mechanical polishing process is difficult to solve. The defect layer after implantation is easier to oxidize due to defects, and a high-temperature thermal oxidation treatment, especially a thermal oxidation temperature higher than the silicon oxidation temperature, such as 1300 ℃, is proposed, the efficiency is improved compared with the Si oxidation temperature, and after the defect layer is fully oxidized, the perfect crystal lattice below is better preserved due to the dual functions of single crystal and top oxide layer protection. The surface defect layer can be completely removed on the premise of ensuring the appearance of the wafer through wet etching of hydrofluoric acid and a small amount of removal. And finally, the high-quality silicon carbide substrate can be reserved to the maximum extent by less polishing removal amount, the wafer morphology of the substrate is ensured, and the use times of the substrate are maintained to the maximum extent.
The first silicon carbide substrate used in the above step may be a silicon carbide substrate obtained by the above recovery treatment.
The embodiment of the application also provides a semiconductor device, which is prepared by the preparation method of any semiconductor device.
In some embodiments, as further shown in fig. 8, the semiconductor device includes a silicon substrate 250, a stripped epitaxial layer 220a disposed on the silicon substrate 250, and a gate oxide layer 260 and a metal layer 280, the silicon substrate 250 being of a different material than the stripped epitaxial layer 220 a.
A conductive layer 226 is provided in the stripped epitaxial layer 220a near the silicon substrate 250, and an activated doped well region is provided in the stripped epitaxial layer 220 a. The doped well region comprises a first well region and a second well region which are arranged side by side and at intervals, and a first doped region and a second doped region which are respectively arranged in the first well region and the second well region and have opposite conduction types, the first well region and the second well region can be arranged in two corner regions of the epitaxial layer, and the upper surface of the first doped region and the upper surface of the second doped region can be flush with the upper surface of the stripped epitaxial layer respectively.
In some embodiments, the gate oxide layer 260 may include a gate electrode 264 and an interlayer dielectric layer 262, the interlayer dielectric layer 262 being disposed on a top surface of the third intermediate device structure, the gate electrode 264 being disposed inside the interlayer dielectric layer 262.
The metal layer 280 includes a first metal layer 282 disposed on the back side of the third intermediate device structure for forming the drain electrode, and a second metal layer 284 disposed on the top side of the third intermediate device structure for forming the source electrode. The first metal layer 282 is disposed on the back side of the silicon substrate in the third intermediate device structure. The middle portion of the second metal layer 284 covers the gate oxide, and the two side portions of the second metal layer 284 cover the top surface of the third intermediate device structure and are flush with the side surfaces of the third intermediate device structure. Specifically, a second metal layer 284 is deposited on the upper surface of the third intermediate device structure and the upper surface of the gate oxide layer, and the source electrode is formed through an annealing process. The material of the deposited metal includes, but is not limited to, al, alCu (aluminum copper alloy), alSiCu (aluminum silicon copper alloy), and the thickness of the second metal layer formed may be 1 to 10 μm.
The semiconductor device formed here may be referred to as a planar MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) device, or may be a trench MOSFET device. When forming the trench MOSFET device, a trench may be formed in the third intermediate device structure, and then a gate oxide and a metal layer may be formed on the third intermediate device structure after forming the trench to obtain the trench MOSFET device.
In some embodiments, the first silicon carbide substrate used in the manufacturing process of the semiconductor device may be a silicon carbide substrate obtained after the lift-off recovery process.
In some embodiments, the recycling process step may include: and finally, polishing the rest surface of the first silicon carbide substrate after being treated by hydrofluoric acid, thus obtaining the recovered first silicon carbide substrate. The recovered first silicon carbide substrate can be continuously applied to the preparation of semiconductor devices, and the recycling of the first silicon carbide substrate is realized. The recovery method is different from the conventional grinding and polishing process, and can keep the use times of the substrate to the maximum extent while ensuring the wafer morphology of the substrate.
In one embodiment, the recycling step may specifically include: firstly, carrying out thermal oxidation treatment on the stripped first silicon carbide substrate, and carrying out wet oxidation for 2-5 hours in a pure oxygen environment at 1300 ℃; and etching by a hydrofluoric acid wet method to remove an oxide layer, and finally carrying out fine polishing treatment on the residual surface of the first silicon carbide substrate subjected to hydrofluoric acid treatment, wherein the film removal thickness is not more than 500nm, so that the recovered first silicon carbide substrate is obtained. The recovery method is different from the conventional grinding and polishing process, and can ensure the wafer morphology of the substrate and keep the use times of the substrate to the maximum extent, so that the manufacturing cost of the prepared semiconductor device is greatly reduced while the performance of the silicon carbide is considered.
It should be noted that, specific details and beneficial effects in the above device embodiments may be referred to the above method embodiments, and are not described herein.
The foregoing description has fully disclosed specific embodiments of this application. It should be noted that any modifications to the specific embodiments of the application may be made by those skilled in the art without departing from the scope of the application as defined in the appended claims. Accordingly, the scope of the claims of the present application is not limited to the foregoing detailed description.
Claims (10)
1. A method of manufacturing a semiconductor device, comprising the steps of:
providing a first silicon carbide substrate, and homoepitaxially growing an epitaxial layer on the first silicon carbide substrate;
performing first ion implantation on the exposed first surface of the epitaxial layer to form an epitaxial defect layer in the epitaxial layer;
a doped well region is manufactured between the first surface and the epitaxial defect layer, and a first intermediate device structure is formed;
providing a second silicon carbide substrate and bonding with the first intermediate device structure based on the first face; the substrate quality of the first silicon carbide substrate is higher than the substrate quality of the second silicon carbide substrate;
stripping part of the device structure including the first silicon carbide substrate along the layer direction of the epitaxial defect layer, and carrying out post-treatment on the stripped surface to expose the second face in the stripped epitaxial layer;
conducting treatment is carried out on the second surface to form a second intermediate device structure;
providing a silicon substrate and bonding with the inverted second intermediate device structure based on the second face;
removing the second silicon carbide substrate, and activating a bonding interface to form a third intermediate device structure;
and preparing a gate oxide layer and a metal layer on the third intermediate device structure to form the semiconductor device.
2. The method of claim 1, wherein the implantation parameters of the first ions comprise at least one of:
the implantation element of the first ion comprises one or more of hydrogen ions and helium ions;
the implantation dosage range of the first ion is 1E17/cm 2 ～1E20/cm 2 ；
The implantation energy of the first ions ranges from 2MeV to 10MeV.
3. The method according to claim 1, wherein the doping elements of the epitaxial layer include one or more of nitrogen and phosphorus, and the doping concentration thereof is in the range of 1E 12-1E 15/cm 3 ；
The dimension of the substrate quality includes one or more of a number of substrate forms, a type of substrate form, and a density of substrate defects.
4. The method of claim 1, wherein post-treating the lift-off surface to expose the second side of the lifted-off epitaxial layer comprises:
thinning the peeling surface based on a preset thinning thickness;
taking the exposed thinned stripping surface as the second face in the stripped epitaxial layer;
wherein the preset reduced thickness is any value of 1.5-3 mu m.
5. The method of any of claims 1-4, wherein said conducting the second side to form a second intermediate device structure comprises:
performing second ion implantation on the second surface to form a conductive layer in the stripped epitaxial layer; the second ion is of a different type than the first ion; the upper edge of the conductive layer is flush with the second face;
and carrying out primary annealing treatment on the conductive layer and the doped well region to form the second intermediate device structure.
6. The method of claim 5, wherein the processing conditions of the primary annealing process include at least one of:
the annealing environment is vacuum, nitrogen atmosphere or argon atmosphere;
the annealing temperature is 1500-1800 ℃, the annealing time is 0.5-5 hours, and the annealing time is inversely related to the annealing temperature;
and protecting the carbon film before annealing, wherein the thickness of the carbon film is 100-1000 nanometers, and the thickness of the carbon film is in a direct proportion relation with the annealing temperature and in an inverse proportion relation with the annealing air pressure.
7. The method of any of claims 1-4, wherein activating the bonding interface to form a third intermediate device structure comprises:
and carrying out secondary annealing treatment on the device structure from which the second silicon carbide substrate is removed so as to activate a bonding interface between the silicon substrate and the inverted second intermediate device structure, thereby forming the third intermediate device structure.
8. The method of claim 7, wherein the processing conditions of the secondary annealing process include at least one of:
the annealing environment is vacuum or nitrogen atmosphere;
the annealing temperature is 1300-1370 ℃, the annealing time is 3-5 hours, and the annealing time is inversely related to the annealing temperature;
and protecting the carbon film before annealing, wherein the thickness of the carbon film is 100-500 nanometers, and the thickness of the carbon film is in a direct proportion relation with the annealing temperature and in an inverse proportion relation with the annealing air pressure.
9. The method of any of claims 1-4, wherein the first silicon carbide substrate is a single crystal silicon carbide substrate;
the second silicon carbide substrate comprises at least one of a mixed crystal silicon carbide substrate and a polycrystalline silicon carbide substrate;
the resistance of the silicon substrate is lower than or equal to 10 ohms, and the conductivity type of the silicon substrate is the same as that of the first silicon carbide substrate.
10. A semiconductor device, characterized in that it is manufactured by the method according to any one of claims 1-9.
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