201142091 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種碳化矽基板之製造方法。 【先前技術】 近年來’正推進採用SiC(碳化石夕）基板作為半導體裝置 之製造中所使用之半導體基板。相比更普遍使用之 si(矽），sic具有更大之帶隙。因此，使用Sic基板之半導 體裝置具有时壓較南、導通電阻較低、及高溫環境下之特 性降低較小等優點。 為了高效地製造半導體裝置，要求某程度以上之基板大 小。根據美國專利第7314520號說明書（專利文獻1}，指出 可製造76 mm(3英吋）以上之siC基板。 先前技術文獻 專利文獻 專利文獻1 :美國專利第7314520號說明書 【發明内容】 發明所欲解決之問題 工業上SiC單晶基板之大小停留在1〇〇 英吋）左右， 因此存在無法使用大型單晶基板高效地製造半導體裝置之 問題。尤其於六方晶系之Sic中，利用（〇〇〇1)面以外之面之 特性時’上述問題尤為嚴重。以下對此進行說明。 缺陷較少之SiC單晶基板通常係藉由自利用難以產生積 層缺陷之（0001)面成長所獲得的Sic結晶塊進行切取而製 造。因此’具有（0001)面以外之面方位之單晶基板會相對 151235.doc 201142091 於成長面而非平行地切取。因此，難以充分確保單晶基板 之大小，或者結晶塊之很多部分無法有效利用。因此，高 效地製造利用SiC之（0001)面以外之面的半導體裝置尤為困 難0 考慮使用包含支持部、及接合於其上之複數個小單晶基 板的碳化矽基板來代替伴隨此般困難之Sic單晶基板之大 型化。該碳化矽基板可藉由增加單晶基板之片數並視需要 而大型化》然而，如此般使支持部與單晶基板接合時，存 在其接合強度變得不充分之情形。 本發明係#於上述問題點而完成者，其目的在於提供一 種可提高單晶基板與支持部之間之接合強度的碳化石夕基板 之製造方法。 解決問題之技術手段 本發明之碳化矽基板之製造方法包括下述步驟。 準備分別具有背面且由碳化矽所製作之至少i個單晶 板、及具有主面且由碳化⑪所製作之支持部。於該準 中’背面及主面之至少一者係藉由機械加工形成 形成而於背面及主面之至少一者 曰 者^成具有結晶結構之應 :、面層。將表面層之至少一部分去除。於該去除之後 者面與主面互相接合。 根據本發明，藉由去除具有應變之表面層，可提高背 與主面之間之接合強度。 =為將表面層之至少一部分去除之步驟係藉由使表 曰升華而進行。藉此’可避免產生新的結晶結構之應變 151235.doc 201142091 且可間便地去除表面層之至少一部分 1個單晶基板、及支持部 為於準備至少 層，於將表面層之至少、面形成有表面 *之表面層之至少一;分步驟中™ 個草晶基板之背面之表面層的至二::：成於至少1 於將表面層之至少一 八去 刀去除。更佳為， ^ 0丨刀去除之步驟φ，十走 前使背面及主面彼此相向。夢此，於L 昇華之 點，背面與主面已彼此^表面層去除之時間 將表面層之至少一部八去/繼而合易將兩者接合。 行。將表面展 σ除之步驟可藉由犧牲氧化而進 佳。將表面層之至少-部分去除之步驟以化學方式進行為 之”去k =之至少—部分去除之步驟係以將表面層 之全π去除之方式進行。藉此 之間之接合強度… “走面與主面 較佳為將背面與主面互相接合之步驟係 面之間發生來自主面之碳化石夕”主 之再結晶化而進行4將表面 … 尨嗜丄 層之至少一部分去除之步驟 華=表面層昇華而進行之情形時，兩步驟均可使用昇 :來進订。進而，於將表面層之至少一部分去除之步驟 於表面層幵華之前使背面與主面彼此相向之情形時， 可在表面層昇華之後僅改變由昇華引起的物質之移動方向 而將背面與主面互相接合。又’於表面層不僅存在於背面 上而且亦存在於主面上之情形時，主面上之表面層可藉由 將背面與主面互相接合之步驟中之昇華而消失。 s 151235.doc 201142091 ^佳為至少1個單晶基板為複數個單晶基板。藉此，可 獲得具有較大面積之碳化矽基板。 上述將表面層之至卜部分去除之步驟可藉由钱刻表面 層而進行。該蝕刻例如為濕式蝕刻或氣體蝕刻。 於準備至少丨個單晶基板之步驟中，可對背面進行 研磨。藉此，可使背面實現平坦化。…使形成於背面 上之表面層之厚度變薄。 於準備至少i個單晶基板之步驟中，背面可藉由切片而 形成。即’背面為藉由切片而形成且其後未經研磨之面。 藉此’於背面上設置有起伏。由此，於藉由昇華法而於背 面上設置支持部之情形時，該起伏之凹部内之空間可用作 昇華氣體進行擴散之空隙。 較佳為至少1個單晶基板包含具有與背面相對向之第】表 面的第！單晶基板。第i表面具有相對於{麵1}面為5〇。以 上65。以下之偏離角。藉此，與第丨表面為{〇〇〇1丨面之情形 相比’可提高第1表面之通道遷移率。 更佳為第1表面之偏離方位與第！單晶基板之<ι ι〇〇>方向 所成之角為5。以下。進而更佳為第】表面相對於第ι單晶基 板之<M〇〇>方向之{03_38}面之偏離角為_3。以上5。以下。 發明之效果 由以上說明可明硝’根據本發明之碳化矽基板之製造方 法，可提高單晶基板與支持部之間之接合強度。 【實施方式】 "" 以下，基於圖式對本發明之實施形態進行說明。 15I235.doc 201142091 (實施形態1) 參照圖1及圖2,本實施形態之碳化矽基板81包含支持部 30、及單晶基板11〜13。支持部30為由碳化矽所製作之 層，該層具有主面F0。單晶基Wi〜19由碳化石夕所製作， 且如圖1所示配置成矩陣狀。單晶基板11〜19之各自之背面 與支持部30之主面FG互相接合。例如，單晶基板u(第π 晶基板）具有互相對向之表面F1(第i表面）與背面m(第1 面），單晶基板I2具有互相對向之表面F2(第2表面）與背面 B2(第2背面）。背面31及82之各個分別接合於主面f〇。 單晶基板η〜19之各自表面較佳為具有面方位{〇3 38}。 其中，亦可使用{0001}、{11_2〇}、或{1_1〇〇}作為面方 位又，亦可使用自上述各面方位偏離數度之面。 繼而，對碳化矽基板81之製造方法進行說明。再者，以 下為簡化說明，有時僅提到單晶基板11〜19中之單晶基板 11及12 ’但單晶基板丨Η 9亦與單晶基板丨丨及^ 2同樣地處 理。該點於其他實施形態之說明中亦相同。 參照圖3及圖4,準備支持部3〇、單晶基板…9(亦總稱 為單晶基板群10)、及加熱裝置。於該時間點，支持部3〇 並非必需為單晶體，例如亦可為多晶體或燒結體。 加熱裝置包含第1及第2加熱體91、92，隔熱容器40，加 熱器5〇，及加熱器電源150。隔熱容器40係由隔熱性較高 之材料所形成。加熱器5〇例如為電阻加熱器。第丨及第2加 熱體91、92具有藉由使吸收來自加熱器5〇之放射熱所獲得』 之熱再放射而加熱支持部3G與單晶基板群1()的功能。第丄， 151235.doc 201142091 及第2加熱體91、92例如由空隙率較小之石墨所形成。 繼而，將第1加熱體91、單晶基板群10、支持部30、及 第2加熱體92依照該順序堆積而配置。具體而言，首先， 於第1加熱體91上以㈣狀配置單晶基板u〜心繼而，於 單晶基板群1〇之表面上載置支持部3(^其次，於支持部3〇 上載置第2加熱體92。繼而，將經積層之第！加熱體91、單 bb基板群1 〇、支持部3〇、第2加熱體92收納於設置有加熱 器50之隔熱容器4〇内。 繼而，將隔熱容器40内之環境設為藉由對大氣環境進行 減壓而獲得之環境。環境之壓力較佳為高於1(rl pa且低於 104 Pa。 再者，上述環境可為惰性氣體環境。作為惰性氣體，例 如可使用He、Ar等稀有氣體、氮氣、或稀有氣體與氮氣之 混合氣體。於使用該混合氣體之情形時，氮氣比例例如為 60%。又，處理室内之壓力較佳為設為5〇让〜以下，更佳 為設為1 0 kPa以下。 進而，參照圖5，於如上述般所準備之單晶基板群1〇(圖 3)之月面上形成表面層71(圖5)。例如，於背面Bi及B2各 自之上形成表面層，71。表面層71為藉由準備單晶基板 12時’利用機械加工形成背面B1&B2而形成於背面…及 B 2上的具有結晶結構之應變的層。例如於單晶基板11〜19 藉由自碳化矽單晶之塊進行切片製造之情形時，進行該切 片時形成表面層。藉由切片所形成之上述表面層之厚度例 如為20 μιη左右。又，於切片後對背面B1&B2進行機械研 151235.doc -8- 201142091 磨時，雖可去除由切片產生之相對較厚之表面層，但藉由 該研磨，形成相對較薄之表面層。 支持部30僅載置於單晶基板丨丨及^各自之上，並未進行 接合。因此’於背面B1&B2之各個與支持部3〇之間存在 微小空隙GQ。因此，表面層71面對空隙GQ。 繼而’藉由加熱器50，經由第1及第2加熱體91、92之各 個，將包含單晶基板11及12之單晶基板群1〇、及支持部3〇 加熱至產生昇華再結晶反應之程度的溫度。該加熱首先係 以形成單晶基板群1 〇之溫度高於支持部30之溫度的溫度差 之形式進行。即，於圖中形成溫度自下朝上減低之溫度梯 度°該溫度梯度於單晶基板群1 〇與支持部3〇之間較佳為設 為lC/cm以上、i〇(rc/Cm以下，更佳為設為i〇〇c/cm以上 50°C /cm以下。 如上述般’若相比支持部30之溫度，單晶基板丨丨及丨二之 各自之溫度設得較高，則於空隙GQ中，如圖中箭頭M1* 示產生由昇華引起之物質移動。其結果，將表面層71之至 少一部分去除’較佳為將表面層71全部去除。昇華之碳化 石夕藉由在支持部3 0之主面F 0上進行再結晶化而被支持部3 〇 吸收。 參照圖6 ’相比單晶基板11及12之各自之溫度，支持部 30之溫度設得更高。即，於圖中形成溫度自上朝下減低之 溫度梯度。換言之，溫度梯度之方向發生逆轉。該溫度梯 度於單晶基板群10與支持部30之間較佳為設為1 °c /cin以 上、200°C /cm以下，更佳為設為1〇艺/cm以上5〇°C /cin以 151235.doc 201142091 下。藉由上述溫度梯度，於空隙Gq中，如圖中箭頭m2所 示產生由昇華引起之物質移動。 進而’參照圖7’反言之，圖5之箭頭M1所示之物質移 動與存在於空隙GQ之空洞的、圖7之箭頭所示之空洞移 動相對應。此處’空隙GQ之高度（圖中之縱方向之尺寸）中 存在較大之面内偏差，由於該偏差，而於對應空隙Gq之 空洞之移動（圖中箭頭H2)速度上產生較大之面内偏差。 進而，參照圖8，由於上述偏差，使對應於空隙gq(圖7) 之空洞無法一面保持其形狀一面移動，取而代之會分解成 複數個孔隙VD(圖7)。其結果，單晶基板丨丨及^之各個接 合於支持部30。 進而，若繼續加熱，則孔隙VD如箭頭H3所示，離開主 面F0。藉此，可進一步提高接合強度。又，支持部川之結 B曰釔構自罪近單晶基板群1 〇之區域開始緩緩變化為與單晶 基板群1 0之結晶結構對應者，根據以上步驟獲得碳化矽基 板8 1。 根據本發明，表面層71(圖5)並非藉由機械而是藉由昇 華而去除，故可避免伴隨該去除而於背面產生新 的結晶結構之應變，並且去除具有應變之表面層71。藉 此，可提高背面B1&B2之各個與主面F〇之間之接合^ 度。又，可藉由加熱處理之簡便步驟去除表面層71。又， 可抑制由該表面層71之結晶缺陷引起的厚度方向（圖2之縱 方向）之電阻增大。 又，於表面層71昇華之前，背面B1&B2與主面F〇如圖$ 151235.doc 201142091 所示彼此相向。藉此，於將表面層71去除之時間點，背面 B1及B2之各個與主面F〇已彼此相向，因而繼而可容易進 行接合兩者之步驟（圖6〜圖8)。 又，去除表面層71之步驟、及接合背面B1&B2之各個 與主面F0之步驟均使用昇華而進行。具體而言，僅使用以 昇華及再結晶化之溫度梯度逆轉便可進行兩步驟。藉此， 可簡化碳化矽基板81之製造步驟。 又’接合背面B1及B2之各個與主面FO時，如圖6所示， 產生來自主面FO之昇華，因而即便假設主面F〇上存在表面 層，亦可將該表面層去除。因此，可避免該表面層對接合 強度造成不良影響。 又，由於設置表面F1及F2(圖2)，故與僅設置表面^之 情形相比，可增大碳化矽基板81之表面積。 較佳為單晶基板11〜19之各自之結晶結構具有多型‘η 型。藉此’可獲得適合製造電力用半導體之碳化矽基板 81 〇 較佳為，為了防止碳化石夕基板8 1之斷裂而儘量減小碳化 石夕基板81中的支持部30之熱膨脹係數與單晶基板^〜^之 熱膨脹係數之差。藉此，可抑制產生碳化石夕基板8丨之勉 曲。因此，例如只要使支持部30之結晶結構與單晶基板 11〜19之結晶結構相同即可，具體而言，只要藉由充分進 行由昇華及再結晶化引起之物質移動（圖8 :箭頭H3)，使 支持部3 0之結晶結構與皁晶基板11〜19之結晶結構相同即 可。 151235.doc 201142091 較佳為儘量減小熱處理前所準備之支持部3G及單晶基板 群1〇(圖4)之各自之厚度之面内偏差。例如將該偏差設為1〇 μιη以下。為了抑制面内偏差，例如只要進行平坦化處理 即可。 較佳為將熱處理前所準備之支持部3〇之電阻率設為未達 50mi>cm ’更佳為設為未達10mn.cm。 較^為將碳化矽基板81中之支持部3〇之雜質濃度設為 5x10丨8 cm·3以上，更佳為設為lxl〇20 cm-3以上。藉由使用 上述碳化矽基板81而製造如縱型M〇SFET(Metai201142091 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a method of manufacturing a tantalum carbide substrate. [Prior Art] In recent years, a SiC (carbon carbide) substrate has been used as a semiconductor substrate used in the manufacture of a semiconductor device. Compared to the more commonly used si(矽), sic has a larger band gap. Therefore, the semiconductor device using the Sic substrate has advantages such as a relatively low voltage, a low on-resistance, and a small decrease in characteristics in a high-temperature environment. In order to efficiently manufacture a semiconductor device, a certain level or more of the substrate size is required. According to the specification of US Pat. No. 7314520 (Patent Document 1), it is pointed out that a siC substrate of 76 mm (3 inches) or more can be manufactured. PRIOR ART DOCUMENT Patent Document Patent Document 1: US Patent No. 7314520 [Invention] Solution to Problem The size of the SiC single crystal substrate in the industrial industry is about 1 inch, and there is a problem that a semiconductor device cannot be efficiently manufactured using a large single crystal substrate. Especially in the Sic of the hexagonal system, when the characteristics of the surface other than the (〇〇〇1) plane are utilized, the above problem is particularly serious. This is explained below. A SiC single crystal substrate having few defects is usually produced by cutting out a Sic crystal block obtained by growing a (0001) plane which is less likely to cause a buildup defect. Therefore, the single crystal substrate having a plane orientation other than the (0001) plane is cut on the growth surface rather than in parallel with respect to 151235.doc 201142091. Therefore, it is difficult to sufficiently ensure the size of the single crystal substrate, or many parts of the crystal block cannot be effectively utilized. Therefore, it is particularly difficult to efficiently manufacture a semiconductor device using a surface other than the (0001) plane of SiC. 0 It is conceivable to use a tantalum carbide substrate including a support portion and a plurality of small single crystal substrates bonded thereto instead of the above-mentioned difficulties. The Sic single crystal substrate is enlarged. The tantalum carbide substrate can be increased in size by increasing the number of single crystal substrates. However, when the support portion is bonded to the single crystal substrate in this manner, the bonding strength is insufficient. The present invention has been made in view of the above problems, and an object thereof is to provide a method for producing a carbonized carbide substrate which can improve the bonding strength between a single crystal substrate and a support portion. Means for Solving the Problem The method for producing a tantalum carbide substrate of the present invention comprises the following steps. At least i single crystal plates each having a back surface and made of tantalum carbide, and a support portion having a main surface and made of carbonized 11 are prepared. At least one of the back surface and the main surface is formed by machining, and at least one of the back surface and the main surface is formed into a crystal structure: a surface layer. At least a portion of the surface layer is removed. After the removal, the face and the main face are joined to each other. According to the present invention, the joint strength between the back and the main surface can be improved by removing the surface layer having strain. = The step of removing at least a portion of the surface layer is performed by sublimating the surface. Therefore, the strain 151235.doc 201142091 of the new crystal structure can be avoided, and at least a part of the single crystal substrate of the surface layer can be removed and the support portion can be prepared for at least one layer, at least the surface layer. Forming at least one of the surface layers of the surface*; wherein the surface layer of the back surface of the TM grass crystal substrates in the sub-step is at least 1 to remove at least one of the surface layers. More preferably, the step 0 of the 丨 去除 去除 removal step makes the back and the main faces face each other. Dreaming, at the point of L sublimation, the back and the main surface have been removed from each other. The surface layer is removed from at least one of the surface layers. Row. The step of dividing the surface extension σ can be improved by sacrificing oxidation. The step of removing at least a portion of the surface layer is carried out chemically "to k = at least - the partial removal step is carried out in such a manner as to remove the entire π of the surface layer. Thereby the bonding strength between..." The surface and the main surface are preferably a step of joining the back surface and the main surface to each other. Steps of removing the carbonized fossil from the main surface between the surface of the main surface and performing the step of removing at least a portion of the surface... In the case where the surface layer is sublimated, both steps can be used to advance the order. Further, the step of removing at least a part of the surface layer is such that the back surface and the main surface face each other before the surface layer is smashed. After the surface layer is sublimated, only the direction of movement of the substance caused by sublimation is changed to bond the back surface and the main surface. In the case where the surface layer exists not only on the back surface but also on the main surface, the main surface The surface layer can be eliminated by sublimation in the step of bonding the back surface and the main surface to each other. s 151235.doc 201142091 ^At least one single crystal substrate is a plurality of single crystal substrates. The ruthenium carbide substrate having a larger area. The step of removing the ruthenium portion of the surface layer may be performed by etching the surface layer. The etching is, for example, wet etching or gas etching. In the step, the back surface may be ground. Thereby, the back surface may be planarized. The thickness of the surface layer formed on the back surface is thinned. In the step of preparing at least i single crystal substrates, the back surface may be sliced by Formed, that is, 'the back surface is a surface formed by slicing and thereafter not polished. Thus, 'the undulation is provided on the back surface. Thus, when the support portion is provided on the back surface by the sublimation method, The space in the undulating recess may be used as a space for the sublimation gas to diffuse. Preferably, at least one of the single crystal substrates includes a first single crystal substrate having a surface opposite to the back surface. The ith surface has a relative surface. The surface 1} surface is 5 〇. The above 65 is the following deviation angle. Thereby, the channel mobility of the first surface can be improved as compared with the case where the second surface is {〇〇〇1丨 surface. More preferably 1 surface deviation orientation The angle formed by the <ι 〇〇> direction of the single crystal substrate is 5. or less. Further preferably, the surface of the first surface is {03_38 with respect to the <M〇〇> direction of the ι single crystal substrate. The angle of deviation of the surface is _3. The above is less than 5. The effect of the invention is as described above. The method for producing a ruthenium carbide substrate according to the present invention can improve the joint strength between the single crystal substrate and the support portion. [Embodiment] Hereinafter, an embodiment of the present invention will be described based on the drawings. 15I235.doc 201142091 (Embodiment 1) Referring to FIGS. 1 and 2, a silicon carbide substrate 81 of the present embodiment includes a support portion 30, and The single crystal substrates 11 to 13. The support portion 30 is a layer made of tantalum carbide, and this layer has a main surface F0. The single crystal bases Wi to 19 are made of carbon carbide, and are arranged in a matrix as shown in Fig. 1 . The back surfaces of the respective single crystal substrates 11 to 19 are bonded to the main surface FG of the support portion 30. For example, the single crystal substrate u (the π-th crystal substrate) has the surfaces F1 (i-th surface) and the back surface m (first surface) facing each other, and the single-crystal substrate I2 has the surface F2 (second surface) facing each other and Back B2 (2nd back). Each of the back faces 31 and 82 is joined to the main face f〇, respectively. The respective surfaces of the single crystal substrates η to 19 preferably have a plane orientation {〇3 38}. In addition, {0001}, {11_2〇}, or {1_1〇〇} may be used as the facet, and the face from which the face orientation is deviated by several degrees may also be used. Next, a method of manufacturing the tantalum carbide substrate 81 will be described. Further, in the following, for simplification of description, only the single crystal substrates 11 and 12' of the single crystal substrates 11 to 19 may be mentioned, but the single crystal substrate 丨Η 9 is also treated in the same manner as the single crystal substrate 丨丨 and . This point is also the same in the description of other embodiments. Referring to Fig. 3 and Fig. 4, a support portion 3, a single crystal substrate 9 (also collectively referred to as a single crystal substrate group 10), and a heating device are prepared. At this point of time, the support portion 3〇 is not necessarily a single crystal, and may be, for example, a polycrystal or a sintered body. The heating device includes first and second heating members 91 and 92, a heat insulating container 40, a heater 5, and a heater power source 150. The heat insulating container 40 is formed of a material having a high heat insulating property. The heater 5 is, for example, a resistance heater. The second and second heating elements 91 and 92 have a function of heating the support portion 3G and the single crystal substrate group 1 () by re-radiating the heat obtained by absorbing the radiant heat from the heater 5'. No. 151,235.doc 201142091 and the second heating bodies 91 and 92 are formed, for example, of graphite having a small void ratio. Then, the first heating body 91, the single crystal substrate group 10, the support portion 30, and the second heating body 92 are stacked in this order. Specifically, first, the single crystal substrate u to the core are placed in the (four) shape on the first heating body 91, and the support portion 3 is placed on the surface of the single crystal substrate group 1 (the second step is placed on the support portion 3). The second heating body 92. Next, the laminated first heating body 91, the single bb substrate group 1A, the support portion 3A, and the second heating body 92 are housed in the heat insulating container 4A in which the heater 50 is provided. Then, the environment in the heat insulating container 40 is an environment obtained by depressurizing the atmospheric environment. The pressure of the environment is preferably higher than 1 (rl pa and lower than 104 Pa. Further, the above environment may be As the inert gas, for example, a rare gas such as He or Ar, nitrogen gas, or a mixed gas of a rare gas and nitrogen gas may be used. When the mixed gas is used, the nitrogen gas ratio is, for example, 60%. The pressure is preferably set to 5 Å or less, more preferably 10 kPa or less. Further, with reference to Fig. 5, a single crystal substrate group 1 (Fig. 3) prepared as described above is formed on the moon surface. Surface layer 71 (Fig. 5). For example, a surface layer is formed on each of the back surfaces Bi and B2, 71 The surface layer 71 is a layer having a crystal structure strain formed on the back surface and B 2 by forming a back surface B1 & B2 by mechanical processing when preparing the single crystal substrate 12. For example, the single crystal substrates 11 to 19 are used by themselves. When the block of the tantalum carbide single crystal is subjected to slicing, the surface layer is formed when the slicing is performed. The thickness of the surface layer formed by the slicing is, for example, about 20 μm. Further, after the slicing, the back surface B1 & B2 is mechanically machined. Grinding 151235.doc -8- 201142091 While grinding, although the relatively thick surface layer produced by the slicing can be removed, a relatively thin surface layer is formed by the grinding. The support portion 30 is only placed on the single crystal substrate. There is no bonding on each of 丨 and ^. Therefore, there is a small gap GQ between each of the back faces B1 & B2 and the support portion 3〇. Therefore, the surface layer 71 faces the gap GQ. Then, by the heater 50 The single crystal substrate group 1A including the single crystal substrates 11 and 12 and the support portion 3 are heated to a temperature at which the sublimation recrystallization reaction occurs, via the first and second heating bodies 91 and 92. First to form a single crystal The temperature of the substrate group 1 is higher than the temperature difference of the temperature of the support portion 30. That is, the temperature gradient from the bottom to the top is formed in the figure. The temperature gradient is between the single crystal substrate group 1 and the support portion 3. Preferably, the crucible is set to be 1 C/cm or more, i 〇 (rc/cm or less, more preferably i 〇〇 c/cm or more and 50 ° C / cm or less. The temperature, the temperature of each of the single crystal substrate 丨 and 丨2 is set higher, and in the gap GQ, the movement of the substance caused by sublimation occurs as indicated by an arrow M1* in the figure. As a result, at least the surface layer 71 is formed. Part of the removal 'preferably removes all of the surface layer 71. The carbonized day of sublimation is absorbed by the support portion 3 藉 by recrystallization on the main surface F 0 of the support portion 30. Referring to Fig. 6', the temperature of the support portion 30 is set higher than the temperature of each of the single crystal substrates 11 and 12. That is, a temperature gradient in which the temperature is lowered from the top to the bottom is formed in the figure. In other words, the direction of the temperature gradient is reversed. The temperature gradient between the single crystal substrate group 10 and the support portion 30 is preferably 1 °c / cin or more and 200 ° C / cm or less, and more preferably 1 〇 / cm or more 5 〇 ° C / Cin is under 151235.doc 201142091. By the above temperature gradient, in the gap Gq, the substance movement caused by sublimation is generated as indicated by an arrow m2 in the figure. Further, referring to Fig. 7 in other words, the movement of the substance indicated by the arrow M1 in Fig. 5 corresponds to the movement of the cavity indicated by the arrow in Fig. 7 existing in the cavity of the gap GQ. Here, there is a large in-plane deviation in the height of the gap GQ (the dimension in the longitudinal direction in the drawing), and due to the deviation, the velocity of the cavity corresponding to the gap Gq (the arrow H2 in the figure) is large. In-plane deviation. Further, referring to Fig. 8, due to the above variation, the cavity corresponding to the gap gq (Fig. 7) cannot be moved while maintaining its shape, and is instead decomposed into a plurality of voids VD (Fig. 7). As a result, each of the single crystal substrates 接 and ^ is bonded to the support portion 30. Further, when the heating is continued, the pores VD are separated from the main surface F0 as indicated by an arrow H3. Thereby, the joint strength can be further improved. Further, in the case where the region of the single crystal substrate group 1 〇 is gradually changed to correspond to the crystal structure of the single crystal substrate group 10, the ruthenium carbide substrate 8 1 is obtained by the above procedure. According to the present invention, the surface layer 71 (Fig. 5) is removed not by mechanical means but by sublimation, so that the strain which generates a new crystal structure on the back side accompanying the removal can be avoided, and the strained surface layer 71 is removed. Thereby, the bonding between each of the back faces B1 & B2 and the main faces F 可 can be improved. Further, the surface layer 71 can be removed by a simple step of heat treatment. Further, the increase in electric resistance in the thickness direction (vertical direction in Fig. 2) caused by the crystal defects of the surface layer 71 can be suppressed. Further, before the surface layer 71 is sublimated, the back surface B1 & B2 and the main surface F 相 face each other as shown in Fig. 151235.doc 201142091. Thereby, at the time point when the surface layer 71 is removed, each of the back surfaces B1 and B2 and the main surface F〇 are opposed to each other, and thus the step of joining them can be easily performed (Figs. 6 to 8). Further, the step of removing the surface layer 71 and the step of bonding each of the back surfaces B1 & B2 to the main surface F0 are performed by sublimation. Specifically, the two steps can be carried out using only the temperature gradient of sublimation and recrystallization. Thereby, the manufacturing steps of the tantalum carbide substrate 81 can be simplified. Further, when each of the back surfaces B1 and B2 and the main surface FO are joined, as shown in Fig. 6, sublimation from the main surface FO occurs, and even if the surface layer is present on the main surface F, the surface layer can be removed. Therefore, the surface layer can be prevented from adversely affecting the joint strength. Further, since the surfaces F1 and F2 (Fig. 2) are provided, the surface area of the tantalum carbide substrate 81 can be increased as compared with the case where only the surface is provided. It is preferable that the crystal structures of the respective single crystal substrates 11 to 19 have a polytype 'n type. Therefore, it is preferable to obtain a silicon carbide substrate 81 suitable for manufacturing a semiconductor for electric power. Preferably, in order to prevent breakage of the carbonized carbide substrate 81, the thermal expansion coefficient and the single crystal of the support portion 30 in the carbonized carbide substrate 81 are minimized. The difference between the thermal expansion coefficients of the substrate ^~^. Thereby, the occurrence of the distortion of the carbonized carbide substrate 8 can be suppressed. Therefore, for example, the crystal structure of the support portion 30 may be the same as the crystal structure of the single crystal substrates 11 to 19, and specifically, the substance movement caused by sublimation and recrystallization may be sufficiently performed (FIG. 8: arrow H3). The crystal structure of the support portion 30 may be the same as the crystal structure of the soap crystal substrates 11 to 19. 151235.doc 201142091 It is preferable to minimize the in-plane variation of the thickness of each of the support portion 3G and the single crystal substrate group 1〇 (Fig. 4) prepared before the heat treatment. For example, the deviation is set to 1 〇 μηη or less. In order to suppress the in-plane variation, for example, a flattening process may be performed. Preferably, the resistivity of the support portion 3〇 prepared before the heat treatment is set to be less than 50 mi > cm Å and more preferably set to less than 10 nm.cm. The impurity concentration of the support portion 3 in the tantalum carbide substrate 81 is set to 5x10 丨 8 cm·3 or more, and more preferably 1×10 〇 20 cm-3 or more. A vertical M〇SFET (Metai) is fabricated by using the above-described tantalum carbide substrate 81.
Semi⑽duetor Fieki Effect τ—〇γ ’金屬氧化物半導體 場效電晶體）等般於縱方向上流通電流之縱型半導體裝 置’可降低縱型半導體裝置之導通電阻。 、 較佳為碳化矽基板81之電阻率之平均值較佳為設為$ mQ.cm以下，更佳為設為1 mQ.cm以下。 較佳為將碳化矽基板81之厚度（圖2之縱方向之尺寸）設 為300 μιη以上。 較佳為表面F1具有相對於{0001}面為50。以上65。以下之 偏離角。藉此，與表面^為{〇〇〇1}面之情形相比，可提高 表面F1之通道遷移率。更佳為滿足以下之第1或第2條件。 於第1條件下，表面F1之偏離方位與單晶基板U之 <1-1〇〇>方向所成之角為5。以下。進而更佳為表面η相對 於單晶基板"之”，方向之{〇3-38}面之偏離角為3。以 上5 °以下。 於第2條件下，表面以之偏離方位與單晶基板η之 151235.doc •12· 201142091 <11-20>方向所成之角為5〇以下。 再者’於上述中，所謂「表面F1相對於<1-1〇0>方向之 {03-38}面之偏離角」，係指表面F1之法線於<11〇〇>方向與 <οοοι>方向之延伸之投影面上的正投影、與{〇3 38)面之 法線所成的角度，關於其符號，於上述正投影相對於 <1-100>方向平行地接近之情形時為正，於上述正投影相 對於<0001>方向平行地接近之情形時為負。 又於上述中’對單晶基板11之表面F1之較佳方位進行 了忒明，較佳為對其他單晶基板12〜19之各自表面之方位 亦進行相同設置。 又，為了將單晶基板11〜19接合於支持部30，可於配置 前預先對單晶基板U〜19之背面進行機械研磨。藉由該研 磨可使表面層71之厚度變薄，因而可更容易地藉由表面層 71之昇華進行去除（圖5)。 又，作為加熱器50而例示了電阻加熱器。即，雖例示了 電阻加熱法，但亦可使用其他加熱法，例如亦可使用高頻 感應加熱法或燈退火法。 (實施形態2) 本實施形態之碳化矽基板具有與碳化矽基板81(圖丨及圖 2)大致相同之構成。以下，對其製造方法進行說明。 參照圖9及圖1〇，準備於背面m形成有表面層71之單晶 基板11。又’準備相同之單晶基板12〜19(圖丨）。又，準備 於主面F0形成有表面層73之支持部3〇。支持部川並非必需 為單晶體’例如亦可為多晶體或燒結體。 151235.doc •13· 201142091 繼而，將表面層71及73之至少一者之至少一部分以化學 方式去除。具體而言，對表面層71及73進行蝕刻。作為蝕 刻方法’例如可使用濕式蝕刻、氣體蝕刻' 反應性離子蝕 刻（RIE，Reactive i〇n Etching)、或利用犧牲氧化之蝕刻。 參照圖11，以背面B1及B2、與主面F0相向之方式，於 支持部3 0上載置單晶基板11及12。繼而，藉由對支持部 30、與單晶基板11及12進行加熱，而使背面B1及B2之各個 與主面F0接合。藉此，可獲得碳化矽基板81(圖2)。 再者，關於上述以外之構成，由於與上述實施形態i之 構成大致相同’故對相同或對應之要素標註相同之符號， 不重複其說明。 又，於本實施形態中，作為支持部3〇而準備了具有表面 層73者’亦可準備不具有表面層73之支持部又，作為 單晶基板11而準備了具有表面層71者，亦可準備不具有表 面層7 1之單晶基板丨i。 (實施形態3) 主要參照圖12，本實施形態之碳化矽基板85僅包含單晶 基板11而代替包含單晶基板丨丨〜丨”圖υ。關於其以外之構 成’由於與上述實施形態丨之構成大致相同，故對相同或 對應之·要素標註相同之符號，不重複其說明。 (實施形態4) 主要參照圖13 ’本實施形態之碳化矽基板86除了包含單 晶基板11以外亦包含單晶基板41。單晶基板41接合於單晶 基板11之表面F1。 151235.doc 201142091 (實施形態5) 參照圖14，本實施形態之半導體裝置1〇〇為縱型 DiMOSFET (Double Implanted Metal 〇xide Semiconductor Field Effect Transistor，雙重離子注入金屬氧化物半導體 場效電晶體），其包含碳化矽基板81、緩衝層121、耐壓保 持層122、p區域123 ' n+區域124、p+區域125、氧化膜 126、源極電極in、上部源極電極127、閘極電極11〇、及 沒極電極112。 於本實施形態中，碳化矽基板81具有n型之導電型， 又如貫麵形態1中所說明般，包含支持部3 〇及單晶基板 11。汲極電極112係以與單晶基板丨丨之間夾持支持部3〇之 方式設置於支持部30上。緩衝層121係以與支持部3〇之間 夾持單晶基板11之方式設置於單晶基板i i上。 緩衝層121之導電型為n型，其厚度例如為〇5 μιηβ又， 緩衝層121中之η型導電性雜質之濃度例如為5χ1〇17。爪-3。 耐壓保持層122形成於緩衝層121上，且包含導電型為n 型之碳化矽。例如，耐壓保持層122之厚度為1〇 μηι，其n 型導電性雜質之濃度為5x10i5 cm·3。 於該耐壓保持層122之表面互相隔開間隔而形成導電型 為P型之複數個p區域123。於ρ區域123之内部，於p區域 123之表面層形成n+區域124。又，於與該一區域124鄰接 之位置形成p區域125。以自一p區域123中之n+區域124上 延伸至p區域123、於2個p區域123之間露出之耐壓保持層 122、另一p區域123及該另一p區域123中之n+區域U4上為 151235.doc -15- 201142091 止的方式形成氧化膜126 »於氧化膜126上形成閘極電極 110 »又，於n+區域124及p+區域125上形成源極電極lu。 於該源極電極111上形成上部源極電極127。 自氧化膜126、與作為半導體層之n+區域124、p+區域 125、p區域123及耐壓保持層122之界面起1〇 nm以内之區 域的氮原子濃度之最大值為1χ1021 cm·3以上。藉此，尤其 可提高氧化膜126下之通道區域（與氧化膜126接觸且為^ 區域124與耐壓保持層122之間的p區域123之部分）之遷移 率0 繼而，對半導體裝置100之製造方法進行說明。再者， 於圖16〜圖19中’僅顯示單晶基板11〜19(圖1)中單晶基板u 之附近之步驟，但於各單晶基板12〜單晶基板19之附近亦 進行相同步驟。 首先’利用基板準備步驟（步驟S110:圖15)準備碳化石夕 基板81(圖1及圖2)。碳化石夕基板81之導電型設為n型。 參照圖16 ’藉由磊晶層形成步驟（步驟sl2〇 :圖15)，以 下述方式形成緩衝層121及耐壓保持層122 ^ 首先，於碳化矽基板81之單晶基板u上形成緩衝層 121。緩衝層121為包含導電型為11型之碳化矽，且厚度例 如為0.5 μπι之磊晶層。又，緩衝層121中之導電型雜質之 濃度例如設為5 X 1017 cm-3。 繼而，於緩衝層121上形成耐壓保持層122。具體而言， 藉由磊晶成長法而形成包含導電型為n型之碳化矽之層。 耐壓保持層122之厚度例如設為10 μιη。又，耐壓保^層 151235.doc 201142091 122中之η型V電性雜質之濃度例如為5xi〇15 cm·3。 參照圖17 ’藉由注入步驟（步驟sl3〇 :圖15)，以下述方 式形成p區域I23、n+區域丨24、及p+區域125。 首先，選擇性地將導電型為P型之雜質注入至耐壓保持 層122之一部分中，藉此形成p區域123。繼而，選擇性地 將η型導電性雜虞注入至特定區域，藉此形成n+區域124， 又，選擇性地將導電型為p型之導電性雜質注入至特定區 域，藉此形成P+區域125。再者，雜質之選擇性注入例如 使用包含氧化膜之遮罩而進行。 於上述注入步驟之後進行活化退火處理。例如，於氩氣 環境中，於1700。(：之加熱溫度下進行3〇分鐘之退火。 參照圖18，進行閘極絕緣膜形成步驟（步驟si4〇 :圖 15)。具體而言，以覆蓋耐壓保持層122、p區域i23、y區 域124、及p+區域125上之方式形成氧化膜126。該形成可 藉由乾式氧化（熱氧化）而進行。關於乾式氧化之條件，例 如加熱溫度為1200°C，又，加熱時間為30分鐘。 其後，進行氮氣退火步驟（步驟Sl5〇)。具體而言，於— 氧化氮⑽)環境中進行退火處理。關於該處理之料，'例 如加熱溫度為iioot：，加熱時間為12〇分鐘。其結果，於 耐壓保持層122、P區域123、n+區域124、及〆區域125各 自與氧化膜126之界面附近導入氮原子。 —再者’亦可於該使用—氧化氮之退火步驟之後進The vertical semiconductor device in which the current flows in the vertical direction, such as the semi(10)duetor Fieki effect τ-〇γ' metal oxide semiconductor field effect transistor, can reduce the on-resistance of the vertical semiconductor device. The average value of the specific resistance of the tantalum carbide substrate 81 is preferably set to be $mQ.cm or less, and more preferably set to 1 mq.cm or less. The thickness of the tantalum carbide substrate 81 (the dimension in the longitudinal direction of Fig. 2) is preferably 300 μm or more. Preferably, the surface F1 has a size of 50 with respect to the {0001} plane. Above 65. The following deviation angle. Thereby, the channel mobility of the surface F1 can be improved as compared with the case where the surface is {〇〇〇1}. More preferably, the first or second condition below is satisfied. Under the first condition, the angle of deviation of the surface F1 and the angle of the <1-1〇〇> direction of the single crystal substrate U were 5. the following. Further, it is more preferable that the surface η is offset from the single crystal substrate by a radius of 3 to 5. 5 degrees or less. Under the second condition, the surface is deviated from the orientation and the single crystal. The angle of the substrate η 151235.doc •12· 201142091 <11-20> direction is 5〇 or less. In addition, in the above, “the surface F1 is relative to the direction of <1-1〇0> 03-38}The deviation angle of the surface refers to the orthographic projection of the normal of the surface F1 on the projection surface of the <11〇〇> direction and the <οοοι> direction, and {〇3 38) The angle formed by the normal line is positive when the above-mentioned orthographic projection is close to the direction of the <1-100> direction, and is similar when the orthographic projection is parallel to the <0001> direction. Negative. Further, in the above, the preferred orientation of the surface F1 of the single crystal substrate 11 is clarified, and it is preferable that the orientations of the respective surfaces of the other single crystal substrates 12 to 19 are also set in the same manner. Further, in order to bond the single crystal substrates 11 to 19 to the support portion 30, the back surfaces of the single crystal substrates U to 19 can be mechanically polished before being placed. By this grinding, the thickness of the surface layer 71 can be made thinner, so that it can be removed more easily by sublimation of the surface layer 71 (Fig. 5). Further, as the heater 50, a resistance heater is exemplified. That is, although the resistance heating method is exemplified, other heating methods may be used, and for example, a high frequency induction heating method or a lamp annealing method may be used. (Embodiment 2) The tantalum carbide substrate of the present embodiment has substantially the same configuration as the tantalum carbide substrate 81 (Fig. 2 and Fig. 2). Hereinafter, the manufacturing method will be described. Referring to Fig. 9 and Fig. 1A, a single crystal substrate 11 having a surface layer 71 formed on the back surface m is prepared. Further, the same single crystal substrates 12 to 19 (Fig. 准备) are prepared. Further, the support portion 3A of the surface layer 73 is formed on the main surface F0. The support of the Chuanchuan is not necessarily a single crystal. For example, it may be a polycrystal or a sintered body. 151235.doc •13· 201142091 Next, at least a portion of at least one of the surface layers 71 and 73 is chemically removed. Specifically, the surface layers 71 and 73 are etched. As the etching method, for example, wet etching, gas etching 'Reactive ion etching (RIE), or etching using sacrificial oxidation can be used. Referring to Fig. 11, the single crystal substrates 11 and 12 are placed on the support portion 30 so that the back surfaces B1 and B2 face the main surface F0. Then, by heating the support portion 30 and the single crystal substrates 11 and 12, each of the back surfaces B1 and B2 is bonded to the main surface F0. Thereby, the tantalum carbide substrate 81 (FIG. 2) can be obtained. The components other than the above are substantially the same as those of the above-described embodiment i. Therefore, the same or corresponding elements are denoted by the same reference numerals, and the description thereof will not be repeated. Further, in the present embodiment, a support portion having a surface layer 73 is prepared as the support portion 3, and a support portion having no surface layer 73 is prepared. Further, as the single crystal substrate 11, a surface layer 71 is prepared. A single crystal substrate 丨i having no surface layer 71 can be prepared. (Embodiment 3) Referring mainly to Fig. 12, the tantalum carbide substrate 85 of the present embodiment includes only the single crystal substrate 11 instead of the single crystal substrate υ 丨 υ υ υ υ υ υ υ υ υ υ υ υ υ 由于 由于 由于The same or corresponding elements are denoted by the same reference numerals, and the description thereof will not be repeated. (Embodiment 4) Referring mainly to Fig. 13 'The carbonized germanium substrate 86 of the present embodiment includes the single crystal substrate 11 as well. The single crystal substrate 41. The single crystal substrate 41 is bonded to the surface F1 of the single crystal substrate 11. 151235.doc 201142091 (Embodiment 5) Referring to Fig. 14, the semiconductor device 1 of the present embodiment is a vertical DiMOSFET (Double Implanted Metal 〇 Xide Semiconductor Field Effect Transistor, which includes a tantalum carbide substrate 81, a buffer layer 121, a withstand voltage holding layer 122, a p region 123'n+ region 124, a p+ region 125, an oxide film 126, the source electrode in, the upper source electrode 127, the gate electrode 11A, and the electrodeless electrode 112. In the present embodiment, the tantalum carbide substrate 81 has an n-type guide The electric type includes the support portion 3 and the single crystal substrate 11 as described in the first embodiment. The drain electrode 112 is provided to support the support portion 3 between the single crystal substrate and the single crystal substrate. The buffer layer 121 is provided on the single crystal substrate ii so as to sandwich the single crystal substrate 11 between the support portion 3A. The buffer layer 121 has an n-type conductivity type, and has a thickness of, for example, 〇5 μmηβ. The concentration of the n-type conductive impurities in the buffer layer 121 is, for example, 5χ1〇17. Claw-3. The withstand voltage holding layer 122 is formed on the buffer layer 121 and contains a niobium carbide of a conductivity type. For example, withstand voltage The thickness of the holding layer 122 is 1 〇μηι, and the concentration of the n-type conductive impurities is 5×10 i5 cm·3. The surface of the pressure-resistant holding layer 122 is spaced apart from each other to form a plurality of p-regions 123 of a conductivity type P-type. Inside the p region 123, an n+ region 124 is formed on the surface layer of the p region 123. Further, a p region 125 is formed at a position adjacent to the region 124. The n+ region 124 extends from a p region 123 to The p region 123, the withstand voltage holding layer 122 exposed between the two p regions 123, and the other p region 123 The oxide film 126 is formed on the n+ region U4 of the other p region 123 in the manner of 151235.doc -15-201142091. The gate electrode 110 is formed on the oxide film 126. Further, on the n+ region 124 and the p+ region 125. A source electrode lu is formed. An upper source electrode 127 is formed on the source electrode 111. The maximum value of the nitrogen atom concentration in the region within 1 〇 nm from the interface between the self-oxidizing film 126 and the n+ region 124, the p+ region 125, the p region 123, and the withstand voltage holding layer 122 as the semiconductor layer is 1 χ 1021 cm·3 or more. Thereby, in particular, the mobility of the channel region under the oxide film 126 (which is in contact with the oxide film 126 and which is a portion of the p region 123 between the region 124 and the withstand voltage holding layer 122) can be increased, followed by the semiconductor device 100. The manufacturing method will be described. Further, in Fig. 16 to Fig. 19, 'only the steps of the vicinity of the single crystal substrate u in the single crystal substrates 11 to 19 (Fig. 1) are shown, but the same is also performed in the vicinity of the single crystal substrate 12 to the single crystal substrate 19. step. First, the carbon carbide substrate 81 (Figs. 1 and 2) is prepared by the substrate preparation step (step S110: Fig. 15). The conductivity type of the carbon carbide substrate 81 is set to n-type. Referring to FIG. 16', the buffer layer 121 and the withstand voltage holding layer 122 are formed in the following manner by the epitaxial layer forming step (step sl2: FIG. 15). First, a buffer layer is formed on the single crystal substrate u of the tantalum carbide substrate 81. 121. The buffer layer 121 is an epitaxial layer containing a tantalum carbide of a conductivity type of 11 and a thickness of, for example, 0.5 μm. Further, the concentration of the conductive type impurity in the buffer layer 121 is, for example, 5 × 10 17 cm -3 . Then, a pressure-resistant holding layer 122 is formed on the buffer layer 121. Specifically, a layer containing a conductive type n-type tantalum carbide is formed by an epitaxial growth method. The thickness of the pressure-resistant holding layer 122 is, for example, 10 μm. Further, the concentration of the n-type V electrical impurity in the pressure-resistant layer 151235.doc 201142091 122 is, for example, 5 xi 〇 15 cm·3. Referring to Fig. 17', by the implantation step (step s13: 图: Fig. 15), the p region I23, the n+ region 丨24, and the p+ region 125 are formed in the following manner. First, an impurity of a P-type conductivity type is selectively implanted into a portion of the withstand voltage holding layer 122, thereby forming a p region 123. Then, an n-type conductive dopant is selectively implanted into a specific region, thereby forming an n+ region 124, and selectively, a conductive impurity having a conductivity type of p-type is implanted into a specific region, thereby forming a P+ region 125. . Further, selective implantation of impurities is carried out, for example, using a mask including an oxide film. The activation annealing treatment is performed after the above implantation step. For example, in an argon atmosphere, at 1700. (: annealing at a heating temperature for 3 minutes. Referring to Fig. 18, a gate insulating film forming step (step si4: Fig. 15) is performed. Specifically, the pressure-resistant holding layer 122, the p-region i23, y are covered. The oxide film 126 is formed in a manner of the region 124 and the p+ region 125. The formation can be carried out by dry oxidation (thermal oxidation). For the conditions of dry oxidation, for example, the heating temperature is 1200 ° C, and the heating time is 30 minutes. Thereafter, a nitrogen annealing step (step S15) is performed. Specifically, annealing treatment is performed in a nitrogen oxide (10) atmosphere. Regarding the material of the treatment, 'for example, the heating temperature is iioot:, and the heating time is 12 〇 minutes. As a result, nitrogen atoms are introduced in the vicinity of the interface between the pressure-resistant holding layer 122, the P region 123, the n+ region 124, and the germanium region 125 and the oxide film 126. - again - can also be used after the annealing step of the use of nitrogen oxide
S 作為惰性氣體之氬氣⑽的退火處理。關於該處理 件，例如加熱溫度為1戰，加熱時間為60分鐘。 151235.doc •17· 201142091 參照圖19，藉由電極形成步驟（步驟si6〇 :圖15)，以下 述方式形成源極電極111及汲極電極112。 首先’使用光微影法，於氧化膜126上形成具有圖案之 光阻膜。使用該光阻膜作為遮罩，藉由蝕刻將氧化膜！26 中位於n+區域124及p+區域125上之部分去除。藉此，於氧 化膜126上形成開口部。繼而，於該開口部，以與n+區域 I24及p+區域125之各個接觸之方式形成導電體膜。繼而， 藉由去除光阻膜，將上述導體膜中位於光阻膜上之部分去 除（剝離）。該導體臈可為金屬膜，例如包含鎳（Ni)。該剝 離之結果，形成源極電極丨丨i。 再者’此處較佳為進行用於合金化之熱處理。例如，於 作為惰性氣體之氬氣（Ar)之環境中，於95(TC之加熱溫度 下進行2分鐘之熱處理。 再次參照圖14 ’於源極電極丨丨丨上形成上部源極電極 127»又’於碳化矽基板81之背面上形成汲極電極us。 又，於氧化膜126上形成閘極電極no。根據以上步驟獲得 半導體裝置100。 再者，亦可使用更換本實施形態之導電型之構成，即更 換P型與η型之構成。 又，用以製作半導體裝置1〇〇之碳化矽基板並不限定於 實施形態1之碳化矽基板8丨，例如亦可使用其他任一實施 形態之碳化矽基板。 又，雖例示了縱型DiM〇SFET，但亦可使用本發明之半 導體基板製造其他半導體裝置，例如亦可製造resurf_ 151235.doc -18. 201142091 JFET(Reduced Surface Field - Junction Field EffectS is annealed as an inert gas of argon (10). Regarding the treatment member, for example, the heating temperature was 1 war and the heating time was 60 minutes. 151235.doc • 17· 201142091 Referring to Fig. 19, the source electrode 111 and the drain electrode 112 are formed by the electrode forming step (step si6: Fig. 15). First, a patterned photoresist film is formed on the oxide film 126 by photolithography. Use this photoresist film as a mask, and etch the oxide film! The portion of 26 located on the n+ region 124 and the p+ region 125 is removed. Thereby, an opening portion is formed in the oxide film 126. Then, a conductor film is formed in the opening portion so as to be in contact with each of the n + region I24 and the p + region 125. Then, the portion of the above conductor film located on the photoresist film is removed (peeled) by removing the photoresist film. The conductor 臈 may be a metal film, for example, containing nickel (Ni). As a result of the stripping, the source electrode 丨丨i is formed. Further, it is preferable to carry out heat treatment for alloying. For example, in an atmosphere of argon (Ar) as an inert gas, heat treatment is performed for 2 minutes at a heating temperature of 95 (TC). Referring again to FIG. 14 'the upper source electrode 127 is formed on the source electrode »» Further, a gate electrode us is formed on the back surface of the tantalum carbide substrate 81. Further, a gate electrode no is formed on the oxide film 126. The semiconductor device 100 is obtained by the above steps. Alternatively, the conductivity type of the present embodiment may be replaced. The configuration of the P-type and the n-type is replaced. The silicon carbide substrate for forming the semiconductor device 1 is not limited to the tantalum carbide substrate 8 of the first embodiment, and any other embodiment may be used, for example. Further, although a vertical DiM〇SFET is exemplified, another semiconductor device can be manufactured using the semiconductor substrate of the present invention, for example, resurf_151235.doc -18. 201142091 JFET (Reduced Surface Field - Junction Field) Effect
Tr細翁，低表面電場·接面場效電晶體）或蕭特基二極 體。 實施例 (實施例1) 準備具有100 mm之直徑、3〇〇 μΓη之厚度、多型為4H、 (03-38)之面方位、lxl〇2。cm、n形雜質漢度卜w⑽ 之微管密度、cm-丨之積層缺陷密度的碳化矽晶圓 作為支持部30(圖3)。 又，準備具有35x35 mm之正方形狀、3〇〇 μπι之厚度、 多型為4Η、（03_38)之面方位、1χ1〇19 cm'n形雜^濃 度、0.2 cm之微官密度、及未達！。以丨之積層缺陷密度的 石反化矽晶圓作為單晶基板群1〇之各個。該碳化矽晶圓係藉 由自碳化矽單晶之塊進行切片而形成。對藉由進行切片而 形成之面不進行研磨。藉由該切片而形成厚度約2〇 ^^之 表面層71。 將單晶基板群以矩陣狀載置於第丨加熱體91上。繼而， 於單晶基板群10上載置支持部3〇。繼而，於支持部3〇上載 置第2加熱體92»藉此，準備了包含第1加熱體91、單晶基 板群1〇、支持部30、及第2加熱體92之積層體。 將上述積層體收納於石墨制之隔熱容器4〇(圖3)内。繼 而 以 1 〇〇 sccm 之流置（standard cubic centimeter per minute，每分鐘標準毫升）於隔熱容器4〇内導入氮氣，且將 隔熱容器40内之壓力控制在133 Pae ί 151235. doc ·19· 201142091 繼而’藉由加熱器5〇將隔熱容器4〇内之溫度加熱至約 2000 C °該加熱係以第1加熱體91之溫度高於第2加熱體92 之溫度的方式進行。藉此，面對第1加熱體91之單晶基板 群10之溫度高於面對第2加熱體92之支持部30之溫度藉 此’使碳化矽自單晶基板群1〇之背面（圖5 :背面Bi、B2) 昇華。為了調查昇華之厚度與所得碳化矽基板之特性的相 關f生，將—昇華之厚度設為〇 、2.5终瓜、5 μπι、1 〇 μπι、 15 μιη、20 μηι、25 μηι、及 50 μηι。 繼而，關於隔熱容器40内之環境及大致溫度，直接將單 晶基板群10與支持部30之間之溫度梯度逆轉。即，使支持 部30之溫度高於單晶基板群1〇之溫度。藉此，將單晶基板 群1〇與支持部30接合（圖7、圖8)。 繼而’調查接合強度與接合界面之微管密度。將其結果 示於以下表1中。 [表1] 昇華之厚度 (μηι) 0 2.5 5 10 15 20 25 50 接合強度 (相對值） 30 40 50 65 90 100 100 100 微管密度 (cm'2) 1χ1〇6 5χ105 50000 1000 100 10 10 10 由該結果可知，根據本實施例，藉由利用昇華去除表面 層7U圖5)，可使接合強度提高，且接合界面之微管密度降 低。又，可知該效果於昇華之厚度達到表面層之厚度即2〇 μηι時飽和。 151235.doc -20- 201142091 (實施例2) 使單晶基板11(圖9)之背面B1於溫度為5〇〇{)(：之熔融κ〇Η 中曝露ίο分鐘’藉此僅去除約10 μηι之厚度。繼而，使用 該單晶基板11製造碳化石夕基板（圊11)。 (實施例3) 藉由使用氫氣之氣體蝕刻，將單晶基板丨丨（圖9)之背面 Β1僅去除約3 μιη之厚度。蝕刻條件設為溫度15〇〇£>c、氫氣 流量3 slm(standard liter per如仙化，每分鐘標準升）、時 間60分鐘。繼而，使用該單晶基板丨丨製造碳化矽基板（圖 11)。 (實施例4) 藉由使用氫氣與氯化氫之混合氣體的氣體蝕刻，將單晶 基板11(圖9)之背面則僅去除約5 μηι之厚度。㈣條件設 為溫度1500。(：、氫氣流量3 slm、氯化氫流量〇.3 —、時 間60分鐘。繼而，使用該單晶基板丨丨製造碳化矽基板（圖 11)。 (實施例5) 藉由反應性離子蝕刻（RIE，Reactive I〇n Etching)，將單 晶基板11(圖9)之背面B1僅去除約5 μιη之厚度。蝕刻條件 設為四氟化碳（CF4)流量1〇 sccm、氧氣流量5 sccm、功率 300〜500 W、時間20分鐘。繼而，使用該單晶基板n製造 碳化矽基板（圖11)。 應認為，本次所揭示之實施形態及實施例於所有方面均 為例示，並非為限制性者。本發明之範圍並非藉由上述說 151235.doc -21 - 201142091 明而疋藉由申請專利範圍而表示，旨在包含與申請專利範 圍均4之含義及範圍内之所有變更。 【圖式簡單說明】 圖1係概略地表示本發明之實施形態1之碳化矽基板之構 成的平面圖。 圖2係沿著圖1之線η_π的概略剖面圖。 圖3係概略地表示本發明之實施形態丨之碳化矽基板之製 造方法的第1步驟之剖面圖。 圖4係圖3之部分放大圖。 圖5係概略地表示本發明之實施形態丨之碳化矽基板之製 造方法的第2步驟中由昇華引起的物質之移動方向之部分 杳J面圖。 圖6係概略地表示本發明之實施形態1之碳化矽基板之製 造方法的第3步驟中由昇華引起的物質之移動方向之部分 音1J面圖。 圖7係概略地表示本發明之實施形態1之碳化矽基板之製 造方法的第3步驟中由昇華引起的空隙之移動方向之部分 别面圖。 圖8係概略地表示本發明之實施形態1之碳化矽基板之製 造方法的第2步驟中由昇華引起的孔隙之移動方向之部分 別面圖。 圖9係概略地表示本發明之實施形態2之碳化矽基板之製 造方法的第1步驟中之單晶基板之構成的剖面圖。 圖10係概略地表示本發明之實施形態2之碳化矽基板之 151235-doc -22- 201142091 製造方法的第1步驟中之支持部之構成的剖面圖。 圖11係概略地表示本發明之實施形態2之碳化矽基板之 製造方法的一步驟之剖面圖。 圖12係概略地表示本發明之實施形態3之碳化矽基板之 構成的剖面圖。 圖13係概略地表示本發明之實施形態4之碳化矽基板之 構成的剖面圖。 圖14係概略地表示本發明之實施形態$之半導體裝置之 構成的部分剖面圖。 圖15係本發明之實施形態$之半導體裝置之製造方法之 概略的流程圖。 圖16係概略地表示本發明之實施形態$之半導體裝置之 製造方法的第1步驟之部分剖面圖。 圖17係概略地表示本發明之實施形態5之半導體裝置之 製造方法的第2步驟之部分剖面圖。 圖18係概略地表示本發明之實施形態5之半導體裝置之 製造方法的第3步驟之部分剖面圖。 圖19係概略地表示本發明之實施形態5之半導體裝置之 製造方法的第4步驟之部分剖面圖。 【主要元件符號說明】 早晶基板群 11 12-19 ' 41 30 單晶基板（第1單晶基板） 早晶基板 支持部 151235.doc -23- 201142091 40 隔熱容器 50 加熱器 71、73 表面層 81 、 85 、 86 碳化矽基板 91 第1加熱體 92 第2加熱體 100 半導體裝置 110 閘極電極 111 源極電極 112 >及極電極 121 緩衝層 122 耐壓保持層 123 p區域 124 n+區域 125 p+區域 126 氧化膜 127 上部源極電極 150 加熱器電源 B1 ' B2 背面 F0 主面 FI、F2 表面 GQ 空隙 H2、H3、Ml、M2 箭頭 VD 孔隙 -24- 151235.docTr fine, low surface electric field, junction field effect transistor) or Schottky diode. EXAMPLES (Example 1) A thickness of 100 mm, a thickness of 3 〇〇 μΓη, a face orientation of 4H, (03-38), and lxl〇2 were prepared. The niobium carbide density of cm, n-shaped impurity Handubu w(10), and the tantalum carbide wafer of the multilayer defect density of cm-丨 are used as the support portion 30 (Fig. 3). Further, it is prepared to have a square shape of 35x35 mm, a thickness of 3 〇〇μπι, a multi-type of 4 Η, a face orientation of (03_38), a concentration of 1χ1〇19 cm'n-shaped, a density of 0.2 cm, and a failure. ! . A stone-resolved ruthenium wafer having a stacking defect density of ruthenium is used as a single crystal substrate group. The tantalum carbide wafer is formed by slicing from a block of tantalum carbide single crystal. The surface formed by slicing is not polished. A surface layer 71 having a thickness of about 2 Å ^ ^ is formed by the slicing. The single crystal substrate group is placed in a matrix on the second heating body 91. Then, the support portion 3 is placed on the single crystal substrate group 10. Then, the second heating body 92» is placed on the support portion 3, whereby a laminate including the first heating body 91, the single crystal substrate group 1A, the support portion 30, and the second heating body 92 is prepared. The laminated body was housed in a graphite heat insulating container 4 (Fig. 3). Then, nitrogen gas was introduced into the insulated container 4〇 by a standard cubic centimeter per minute (standard milliliter per minute), and the pressure in the insulated container 40 was controlled at 133 Pae ί 151235. doc 19 · 201142091 Then, the temperature in the insulated container 4 is heated to about 2000 C by the heater 5, and the heating is performed such that the temperature of the first heating body 91 is higher than the temperature of the second heating body 92. Thereby, the temperature of the single crystal substrate group 10 facing the first heating body 91 is higher than the temperature of the support portion 30 facing the second heating body 92, thereby making the tantalum carbide from the back surface of the single crystal substrate group 1 (Fig. 5: Back Bi, B2) Sublimation. In order to investigate the thickness of the sublimation and the characteristics of the obtained tantalum carbide substrate, the thickness of the sublimation was set to 〇, 2.5, melon, 5 μπι, 1 〇 μπι, 15 μιη, 20 μηι, 25 μηι, and 50 μηι. Then, the temperature gradient between the single crystal substrate group 10 and the support portion 30 is directly reversed with respect to the environment and the approximate temperature in the heat insulating container 40. That is, the temperature of the support portion 30 is made higher than the temperature of the single crystal substrate group 1〇. Thereby, the single crystal substrate group 1A is joined to the support portion 30 (Figs. 7 and 8). Then, the joint strength and the micropipe density at the joint interface were investigated. The results are shown in Table 1 below. [Table 1] Thickness of sublimation (μηι) 0 2.5 5 10 15 20 25 50 Bonding strength (relative value) 30 40 50 65 90 100 100 100 Microtube density (cm'2) 1χ1〇6 5χ105 50000 1000 100 10 10 10 From this result, according to the present embodiment, by removing the surface layer 7U (Fig. 5) by sublimation, the joint strength can be improved and the micropipe density at the joint interface can be lowered. Further, it is understood that this effect is saturated when the thickness of the sublimation reaches the thickness of the surface layer, that is, 2 〇 μη. 151235.doc -20- 201142091 (Embodiment 2) The back surface B1 of the single crystal substrate 11 (Fig. 9) is exposed to a temperature of 5 〇〇{) (: 〇Η 熔融 熔融 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' The thickness of μηι. Then, a carbonized carbide substrate (圊11) was produced using the single crystal substrate 11. (Example 3) The back surface Β1 of the single crystal substrate 丨丨 (Fig. 9) was removed only by gas etching using hydrogen gas. A thickness of about 3 μm. The etching conditions are set to a temperature of 15 & c, a hydrogen flow rate of 3 slm (standard liter per standard liter per minute), and a time of 60 minutes. Then, the single crystal substrate is used. A tantalum carbide substrate (Fig. 11) was produced. (Example 4) By gas etching using a mixed gas of hydrogen gas and hydrogen chloride, only the thickness of about 5 μηι was removed from the back surface of the single crystal substrate 11 (Fig. 9). The temperature was 1500. (: hydrogen flow rate 3 slm, hydrogen chloride flow rate 〇.3 -, time 60 minutes. Then, the single crystal substrate was used to fabricate a tantalum carbide substrate (Fig. 11). (Example 5) By reactivity Ion etching (RIE, Reactive I〇n Etching), the back side of the single crystal substrate 11 (Fig. 9) B1 The thickness of about 5 μm is removed. The etching conditions are set to a carbon tetrafluoride (CF4) flow rate of 1 〇sccm, an oxygen flow rate of 5 sccm, a power of 300 to 500 W, and a time of 20 minutes. Then, the single crystal substrate n is used to manufacture a tantalum carbide substrate. It is to be understood that the embodiments and examples disclosed herein are illustrative and not restrictive. The scope of the present invention is not limited by the above-mentioned 151235.doc -21 - 201142091 The present invention is intended to cover all modifications within the meaning and scope of the appended claims. FIG. 1 is a schematic view showing the composition of a silicon carbide substrate according to Embodiment 1 of the present invention. Fig. 2 is a schematic cross-sectional view taken along line η_π of Fig. 1. Fig. 3 is a cross-sectional view schematically showing a first step of a method for manufacturing a tantalum carbide substrate according to an embodiment of the present invention. Fig. 5 is a partial view schematically showing a moving direction of a substance caused by sublimation in a second step of the method for producing a tantalum carbide substrate according to an embodiment of the present invention. The partial sound 1J surface view of the moving direction of the substance by sublimation in the third step of the method for producing a tantalum carbide substrate according to the first embodiment of the present invention. Fig. 7 is a view schematically showing the tantalum carbide substrate according to the first embodiment of the present invention. In the third step of the manufacturing method, the portions of the movement direction of the voids caused by the sublimation are respectively shown in Fig. 8. Fig. 8 is a schematic diagram showing the sublimation caused by the second step in the method of manufacturing the tantalum carbide substrate according to the first embodiment of the present invention. The parts of the direction of movement of the pores are respectively shown. Fig. 9 is a cross-sectional view showing the configuration of a single crystal substrate in the first step of the method for producing a tantalum carbide substrate according to the second embodiment of the present invention. Fig. 10 is a cross-sectional view showing the configuration of a support portion in the first step of the manufacturing method of the 151235-doc -22-201142091 method of the tantalum carbide substrate according to the second embodiment of the present invention. Figure 11 is a cross-sectional view showing a step of a method of manufacturing a tantalum carbide substrate according to Embodiment 2 of the present invention. Fig. 12 is a cross-sectional view schematically showing the configuration of a tantalum carbide substrate according to a third embodiment of the present invention. Figure 13 is a cross-sectional view showing the structure of a tantalum carbide substrate according to a fourth embodiment of the present invention. Fig. 14 is a partial cross-sectional view schematically showing the configuration of a semiconductor device according to an embodiment of the present invention. Fig. 15 is a flow chart showing the outline of a method of manufacturing a semiconductor device according to an embodiment of the present invention. Fig. 16 is a partial cross-sectional view schematically showing a first step of a method of manufacturing a semiconductor device according to an embodiment of the present invention. Figure 17 is a partial cross-sectional view showing a second step of the method of manufacturing the semiconductor device according to the fifth embodiment of the present invention. Figure 18 is a partial cross-sectional view showing a third step of a method of manufacturing a semiconductor device according to a fifth embodiment of the present invention. Figure 19 is a partial cross-sectional view showing a fourth step of the method of manufacturing the semiconductor device according to the fifth embodiment of the present invention. [Description of main component symbols] Early-crystal substrate group 11 12-19 ' 41 30 Single crystal substrate (first single crystal substrate) Early-crystal substrate support portion 151235.doc -23- 201142091 40 Insulated container 50 Heater 71, 73 Surface Layer 81, 85, 86 Tantalum carbide substrate 91 First heating body 92 Second heating body 100 Semiconductor device 110 Gate electrode 111 Source electrode 112 > and Polar electrode 121 Buffer layer 122 Withstand voltage holding layer 123 p region 124 n+ region 125 p+ region 126 oxide film 127 upper source electrode 150 heater power supply B1 'B2 back F0 main surface FI, F2 surface GQ void H2, H3, Ml, M2 arrow VD aperture-24- 151235.doc