JP2007059711A - Method for forming field plate structure and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for forming a field plate structure by the one time lithography. <P>SOLUTION: In the method for forming the field plate structure, the field plate structure has an operating layer formed on a main surface of a substrate, an insulating layer formed on the operating layer, and an electrode connected to both the operating layer, and the insulating layer. This method comprises the steps of forming the operating layer on the main surface of the substrate, forming the electric insulating layer on the operating layer, forming a photosensitive heat-shrinkable organic matter layer on the insulating layer, patterning the photosensitive organic matter layer by the lithography, using the patterned organic matter layer as a mask to etch the insulating layer, shrinking the organic matter layer by heating; forming an electrode material layer, and removing the heat-shrunk organic matter layer. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for forming a field plate structure with a small number of steps and a small positional shift, and to a semiconductor device with high withstand voltage.

In a semiconductor device made of Si, SiC, or the like, a field plate structure is often employed in order to increase the breakdown voltage. As a semiconductor device, an IGBT (insulated gate bipolar transistor) is taken as an example, and a field plate structure is shown in FIG. As shown in FIG. 2, the IGBT includes an n-type low impurity concentration (n ⁻ ) first semiconductor region 21, a p-type high impurity concentration (p ⁺ ) second semiconductor region 22, a p-type high impurity concentration (p ⁺ ) Third semiconductor region 23, insulating layer 24, emitter electrode 25, collector electrode 26, and pn junction 27. As shown in FIG. 2, the structure in which the electrode 25 is overlaid on the insulating layer 24 is called a field plate structure.

  In the IGBT, when a reverse voltage is applied between the emitter electrode 25 and the collector electrode 26 so that the voltage applied to the collector electrode 26 becomes positive compared with the voltage applied to the emitter electrode 25, the electric field obtained by the field plate As a result, a depletion layer is formed in the first semiconductor region 21, and as a result, the electric field concentration in the junction portion 27 between the first semiconductor region 21 and the second semiconductor region 22 is alleviated, compared with the case where no field plate structure is provided. Withstand voltage characteristics can be improved.

A method for manufacturing a SiC IGBT is shown in FIG. 3 (see Patent Document 1 and Non-Patent Document 1). First, as shown in FIG. 3A, a p-type impurity is ion-implanted into the main surface of the first semiconductor region 31 having an n-type low impurity concentration (n ⁻ ) to increase the p-type high impurity concentration (p ⁺ ). A second semiconductor region 32 is formed, and a pn junction surface 37 is obtained. Next, tantalum oxide is deposited on the exposed portion of the main surface of the first semiconductor region 31 and on the entire exposed surface of the second semiconductor region 32 by a CVD method to form an insulating layer 34 ′. Thereafter, as shown in FIG. 3B, unnecessary portions of the insulating layer 34 ′ are removed by dry etching, and an insulating film 34 is formed.

  Next, as shown in FIG. 3C, Al is vapor-deposited on the exposed portion of the main surface of the first semiconductor region 31, on the exposed surface of the second semiconductor region 32, and on the insulating film 34, and an Al layer is formed. 35 'is formed. Subsequently, as shown in FIG. 3D, unnecessary portions are removed by dry etching, and an emitter electrode 35 is formed. Thereafter, although not shown, when a collector electrode and a protective film are formed, a SiC IGBT is obtained. Therefore, according to the method shown in FIG. 3, two dry etching steps are required to form the field plate structure.

Another example of a semiconductor device having a field plate structure is illustrated in FIG. 4 (see Patent Document 2). As shown in FIG. 4, this semiconductor device has a p-type impurity diffusion layer 42 on the main surface of an n-type Si substrate 41, and covers the portion of the pn junction that is exposed on the main surface. An SiO ₂ layer 44a is formed. Further, a CVD / SiO ₂ layer 44b is provided on the thermal SiO ₂ layer 44a, and a step A is formed. Further, an intermediate insulating film 44c is provided on the CVD / SiO ₂ layer 44b, and a step B is formed. As shown in FIG. 4, the electrode 45 covers the stepped portion A from the exposed portion of the p-type impurity diffusion layer 42 through the thermal SiO ₂ layer 44a and further through the CVD / SiO ₂ layer 44b. B is covered and is drawn on the intermediate insulating film 44c. The thickness of the oxide film immediately below the lead end portion of the electrode 45 greatly affects the pressure resistance. The thickness of the oxide film 44 in this portion is the sum of the thermal SiO ₂ layer 44a + CVD / SiO ₂ layer 44b + intermediate insulating film 44c. Since it is a thickness, it exhibits high pressure resistance. In addition, since the conventional one step is composed of two steps of the stepped portion A and the stepped portion B, each stepped portion can be made thin, and the electrode 45 becomes difficult to be cut at the stepped portion. And the surface of the semiconductor device can be planarized.

A method of manufacturing this semiconductor device is shown in FIG. First, as shown in FIG. 5A, after forming a p-type impurity diffusion layer 52 on the main surface of an n-type semiconductor substrate 51, a thermal SiO ₂ layer is formed and the p-type impurity diffusion layer 52 is formed by lithography. The thermal SiO ₂ layer 54a is opened. Next, as shown in FIG. 5B, a SiO ₂ layer is formed on the thermal SiO ₂ layer 54a by a CVD method and patterned by lithography to form a CVD / SiO ₂ layer 54b. Form. Subsequently, as shown in FIG. 5C, an electrode material is deposited so as to be in contact with the p-type impurity diffusion layer 52 and cover the stepped portion A, and patterned to form an electrode 55a. Next, as shown in FIG. 5 (d), an intermediate insulating film is formed on the thermal SiO ₂ layer 54a and the CVD / SiO ₂ layer 54b by a CVD method, and then etched by lithography to form a stepped portion as an intermediate insulating film 54c. B is formed. Finally, when the electrode 55 is formed so as to cover the stepped portion B by vapor deposition and patterning of an electrode material, a semiconductor device having a field plate structure as shown in FIG. 5E is obtained. Therefore, according to the method shown in FIG. 5, a plurality of lithography steps are required to form the field plate structure.
Japanese Patent Application Laid-Open No. 11-299795 Japanese Patent Laid-Open No. 1-136366 Q. Wahab et al., “A 3 kV Schottky barrier diode in 4H-SiC” Appl. Phys. Lett. 72 (4), 26 January 1998 p 445-447

  When the field plate structure is formed by lithography a plurality of times, the manufacturing process becomes complicated, and misalignment of the patterns tends to occur, so that it is difficult to control the field plate width. Therefore, an object of the present invention is to provide a method capable of forming a field plate structure by one lithography. Another object of the present invention is to provide a semiconductor device having a field plate structure with a constant width by forming a field plate structure by one lithography, thereby reducing a shift in aligning the positions of patterns.

  The present invention is a method for forming a field plate structure having an operation layer formed on a main surface of a substrate, an insulating layer formed on the operation layer, and an electrode connected to both the operation layer and the insulating layer. A step of forming an operating layer on the main surface of the substrate, a step of forming an electrical insulating layer on the operating layer, a step of forming a photosensitive heat-shrinkable organic layer on the insulating layer, and a photosensitive organic layer A step of patterning by lithography, a step of etching the insulating layer using the patterned organic layer as a mask, a step of shrinking the organic layer by heating, a step of forming an electrode material layer, and a thermally contracted organic layer And a removing step.

  The operating layer can be a p-type layer and / or an n-type layer. An embodiment in which the organic layer is composed of a plurality of layers, the upper layer has photosensitivity, and the lower layer has heat shrinkability is preferable, and the heating step of the organic layer is preferably performed with heated water at 90 ° C. or higher. As the organic layer to be used, those having the property of being thermally contracted by 0.2 μm or more in the surface direction of the substrate by heating are suitable. The semiconductor device of the present invention includes a field plate structure formed by such a method.

  Since the field plate structure can be formed by one lithography, the process can be simplified, and the pattern shift can be suppressed by self-alignment. Further, as compared with a method that requires a plurality of times of lithography, alignment between patterns becomes unnecessary, the field plate width can be accurately controlled, and contamination of the substrate surface can be prevented.

A process diagram of a method for forming a field plate structure of the present invention is illustrated in FIG. First, as shown in FIG. 1A, an operation layer 2 is formed on the main surface of the substrate 1, an electric insulation layer 3 is formed on the operation layer 2, and then a photosensitive heat shrink is formed on the insulation layer 3. The organic material layer 4 is formed. As the substrate 1, a general material can be used. For example, SiC (4H, 6H, etc.), a wide band gap semiconductor material such as GaN, diamond, or the like can be used. On the other hand, a general material can be used for the insulating layer 3, and when an SiC substrate is used, an electric insulating layer made of SiO ₂ can be formed on the surface of the substrate by a thermal oxidation method.

  The operation layer 2 can be a p-type layer, an n-type layer, or a composite layer of a p-type layer and an n-type layer. For example, a Schottky barrier diode or a pn junction diode can be formed. In a Schottky barrier diode, when a Schottky electrode is formed on a substrate, by forming a field plate structure, the electric field concentration at the electrode end can be suppressed and the pressure resistance can be improved. Also in the pn junction diode, by forming the field plate structure, the electric field concentration at the pn junction portion can be relaxed and the breakdown voltage can be improved. According to the method of the present invention, since the field plate structure can be formed by one lithography, the operation process is simplified, and there is no alignment between patterns, so that no alignment shift occurs.

  In the case where the photosensitive heat-shrinkable organic layer 4 has a single layer structure, it is necessary to have photosensitivity that can be patterned by lithography in the next step, and heat-shrinkable by boiling water or the like. It is necessary that the material has both. In addition, since the organic layer is finally removed, a material having peelability is preferable for easy removal. As the organic substance that is photosensitive and heat-shrinkable, for example, a resist such as polymethacrylate such as polymethyl methacrylate (PMMA) is suitable. The term “having heat shrinkage” refers to a property of shrinking by 0.01% or more in the length direction when immersed in heated water at 90 ° C. to 100 ° C. for 10 minutes.

  When the organic material layer 4 has a multi-layer structure, the upper layer preferably has photosensitivity so that it can be easily patterned by photosensitivity. As such a photosensitive material, in addition to the resist described above, a chemically amplified resin material sensitive to ultraviolet rays, photosensitive polyimide, polyhalogen compounds, and the like are suitable. Moreover, since the lower layer ensures the area | region which forms a field plate by heat shrink, the aspect which has heat shrinkability is preferable. As the heat-shrinkable organic material, silicone or the like is suitable.

Next, as shown in FIG. 1B, the organic layer 4 is patterned by lithography, and the insulating layer 3 is etched using the patterned organic layer 4a as a mask. Thereafter, as shown in FIG. 1C, when the organic layer 4a is contracted by heating to form the organic layer 4b, a region C for forming a field plate is obtained. The heating of the organic layer 4a varies depending on the organic material, and is performed by appropriately selecting a liquid such as water heated to 90 ° C. or higher, a gas such as water vapor, or a heated inert gas such as N ₂ or Ar. Can do. For example, when a resist such as PMMA is used as a single organic layer, heated water at 90 ° C. or higher is preferable, heated at 94 ° C. or higher is more preferable, and an embodiment in which immersion treatment is performed in boiling water is particularly preferable. . Thus, from the viewpoint of securing a sufficient field plate region C by heat shrinkage, it is preferable that the organic layer 4a shrinks 0.2 μm or more in the surface direction of the substrate 1 by heating, and 0.5 μm or more shrinks. Is more preferable. Such a preferred embodiment can be adjusted by the heat treatment time or the like.

  Subsequently, as shown in FIG. 1D, the electrode material layer 5 (5a, 5b) is formed, and finally, the heat-shrinked organic material layer 4b is removed by lift-off or the like. Such a field plate structure is obtained. As shown in FIG. 1 (e), the field plate structure includes an operating layer 2 formed on the main surface of the substrate 1, an insulating layer 3a formed on the operating layer 2, the operating layer 2 and the insulating layer 3a. The electrode 5a is connected to both of the electrodes, and the electrode 5a is overlaid on the insulating layer 3a. Conventionally, lithography has been required at least twice for forming an insulating layer opening and for forming an electrode. However, according to the present invention, a field plate structure can be formed by one lithography. Therefore, the work process can be simplified, the misalignment between the patterns can be eliminated, the width of the field plate can be accurately controlled, and the substrate surface is hardly contaminated. The semiconductor device of the present invention has a field plate structure formed by such a method, and can provide, for example, a Schottky barrier diode or a pn junction diode having high breakdown voltage.

Example 1
As shown in FIG. 1, an n-type operation layer doped with N (doping concentration 7 × 10 ¹⁵ cm ⁻³ ) on the main surface of an n-type 4H—SiC 8 ° off substrate 1 having a thickness of 400 μm and a resistivity of 0.02 Ωcm. 2 (thickness 10 μm) was formed by a CVD epitaxial method. Next, an insulating layer 3 made of SiO ₂ was formed on the surface of the epitaxial layer by thermal oxidation, and then an Ni ohmic electrode was formed on the back surface by vapor deposition (not shown). Thereafter, a resist is formed as a photosensitive heat-shrinkable organic material layer 4 on the surface of the insulating layer 3 (FIG. 1A), and after patterning by lithography, the insulating layer 3 on the main surface is etched with buffered hydrofluoric acid ( FIG. 1 (b)). Subsequently, after being immersed in heated water at 94 ° C. to 100 ° C. for 10 minutes and thermally contracted (FIG. 1 (c)), Ni electrode 5 was deposited (FIG. 1 (d)), and the heat-shrinked organic layer 4b. Was lifted off to obtain a 1 mm × 1 mm Schottky barrier diode (FIG. 1E).

When the electrical characteristics of the obtained Schottky barrier diode were measured, the n value, which is an index representing the forward characteristics, was as good as 1.05. As for the reverse characteristics, the leakage current when applying -600 V was 1 × 10 ⁻⁸ A, indicating a high breakdown voltage. When this Schottky electrode 5a is observed with an SEM, the Ni Schottky electrode 5a is formed on the insulating layer 3a made of SiO _{2 so as} to have a width W of 0.5 μm, thereby forming a field plate structure. Was confirmed.

Comparative Example 1
A Schottky barrier diode was obtained in the same manner as in Example 1 except that it was washed with ultrapure water at room temperature instead of the heat treatment before the formation of the Ni Schottky electrode. When the electric characteristics of the obtained Schottky barrier diode were evaluated, the forward characteristic had an n value of 1.20, and the reverse characteristic had a leakage current of 1 × 10 ⁻⁴ A when −200 V was applied, In all cases, the characteristics deteriorated. When this Schottky electrode was observed with an SEM, a gap was formed between the Ni Schottky electrode and the SiO ₂ layer, and formation of a field plate structure could not be confirmed.

Example 2
As shown in FIG. 1, on the main surface of an n-type 4H—SiC 8 ° off substrate 1 having a thickness of 400 μm and a resistivity of 0.02 Ωcm, an n-type epitaxial layer doped with N (doping concentration 7 × 10 ¹⁵ cm ⁻³ ) (Thickness 10 μm) was formed by a CVD method. Next, Al was ion-implanted as a dopant (injection amount 1 × 10 ¹⁸ cm ⁻³ ) to form a p-type operation layer 2 having a depth of 0.5 μm. Next, an insulating layer 3 made of SiO ₂ was formed on the surface of the epitaxial layer by thermal oxidation, and then an Ni ohmic electrode was formed on the back surface by vapor deposition (not shown). Thereafter, a resist is formed on the surface of the SiO ₂ layer as a photosensitive heat-shrinkable organic layer 4 (FIG. 1 (a)), after patterning by lithography to etch the SiO ₂ layer on the main surface by buffered hydrofluoric acid ( FIG. 1 (b)). Subsequently, after being immersed in heated water at 94 ° C. to 100 ° C. for 10 minutes and thermally contracted (FIG. 1 (c)), an electrode material layer 5 made of Ti / Al was deposited (FIG. 1 (d)), The heat-shrinked organic layer 4b was lifted off to obtain a 1 mm × 1 mm pn diode (FIG. 1 (e)).

When the electrical characteristics of the obtained pn diode were measured, the reverse characteristics showed a high withstand voltage of 1 × 10 ⁻⁷ A when the leak current was −600 V applied. Further, when observed by SEM, it was confirmed that the Ti / Al electrode was formed on the SiO ₂ layer so as to have a width W of 0.5 μm, thereby forming a field plate structure.

Comparative Example 2
A pn diode was obtained in the same manner as in Example 2 except that the surface was washed with ultrapure water at room temperature instead of the heat treatment before forming the Ti / Al electrode on the surface. When the electrical characteristics of the obtained pn diode were evaluated, the reverse current characteristic was 1 × 10 ⁻⁴ A when −600 V was applied, which was larger than the heat-treated diode of Example 2. Moreover, although observed with SEM, the field plate structure was not confirmed.

Example 3
As shown in FIG. 1, an n-type operation layer doped with N (doping concentration 7 × 10 ¹⁵ cm ⁻³ ) on the main surface of an n-type 4H—SiC 8 ° off substrate 1 having a thickness of 400 μm and a resistivity of 0.02 Ωcm. 2 (thickness 10 μm) was formed by a CVD epitaxial method. Next, an insulating layer 3 made of SiO ₂ was formed on the surface of the epitaxial layer by thermal oxidation, and then an Ni ohmic electrode was formed on the back surface by vapor deposition (not shown). Thereafter, a resist is formed on the surface of the SiO ₂ layer as a photosensitive heat-shrinkable organic layer 4 (FIG. 1 (a)), after patterning by lithography to etch the SiO ₂ layer on the main surface by buffered hydrofluoric acid ( FIG. 1 (b)). Subsequently, after being immersed in heated water at 94 ° C. to 100 ° C. for 1 minute and thermally contracted (FIG. 1C), the electrode material 5 made of Ni was deposited (FIG. 1D) and thermally contracted. The organic layer 4b was lifted off to obtain a 1 mm × 1 mm Schottky barrier diode (FIG. 1E).

The electrical characteristics of the obtained Schottky barrier diode were measured. As for the reverse characteristics, the leakage current when applying −600 V was 1 × 10 ⁻⁷ A, indicating a high breakdown voltage. When this Schottky electrode is observed with an SEM, the Schottky electrode 5a made of Ni is formed on the insulating layer 3a made of SiO _{2 so as} to have a width W of 0.2 μm, thereby forming a field plate structure. It could be confirmed. Therefore, considering together with the result of Example 1 treated with the same heated water for 10 minutes, the reverse leakage current at −600 V is increased by 1 × by increasing the field plate width from 0.2 μm to 0.5 μm. It has been found that the pressure resistance is further increased by decreasing from 10 ⁻⁷ A → 1 × 10 ⁻⁸ A.

  It should be understood that the embodiments and examples disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  A Schottky barrier diode or a pn junction diode having high withstand voltage can be provided.

It is process drawing which shows the formation method of the field plate structure of this invention. It is a figure which shows the field plate structure in the conventional pn junction type semiconductor device. It is a figure which shows the formation method of the field plate structure in the conventional pn junction type semiconductor device. It is a figure which shows the field plate structure in the conventional pn junction type semiconductor device. It is a figure which shows the formation method of the field plate structure in the conventional pn junction type semiconductor device.

Explanation of symbols

  1 substrate, 2 working layers, 3 insulating layers, 4 organic layers, 5 electrodes.

Claims (6)

A method for forming a field plate structure comprising an operation layer formed on a main surface of a substrate, an insulating layer formed on the operation layer, and an electrode connected to both the operation layer and the insulating layer,
Forming an operating layer on the main surface of the substrate;
Forming an electrically insulating layer on the working layer;
Forming a photosensitive heat-shrinkable organic material layer on the insulating layer;
Patterning the photosensitive organic layer by lithography;
Etching the insulating layer using the patterned organic layer as a mask;
Shrinking the organic layer by heating;
Forming an electrode material layer;
And a step of removing the heat-shrinked organic material layer.   2. The method of forming a field plate structure according to claim 1, wherein the operation layer is a p-type layer and / or an n-type layer.   3. The method of forming a field plate structure according to claim 1, wherein the organic layer is composed of a plurality of layers, the upper layer has photosensitivity, and the lower layer has heat shrinkability.   The method for forming a field plate structure according to any one of claims 1 to 3, wherein the heating step of the organic layer is performed with heated water of 90 ° C or higher.   5. The method of forming a field plate structure according to claim 1, wherein the organic material layer is thermally shrunk by 0.2 μm or more in a surface direction of the substrate by heating.   A semiconductor device comprising a field plate structure formed by the method according to claim 1.

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