CN209766429U

CN209766429U - Silicon carbide MOSFET device

Info

Publication number: CN209766429U
Application number: CN201920197953.XU
Authority: CN
Inventors: 卓廷厚; 李钊君; 刘延聪
Original assignee: Xiamen Shinguangrunze Technology Co Ltd
Current assignee: Xiamen Shinguangrunze Technology Co Ltd
Priority date: 2019-02-14
Filing date: 2019-02-14
Publication date: 2019-12-10
Anticipated expiration: 2029-02-14

Abstract

a silicon carbide MOSFET device. The silicon carbide MOSFET device comprises a drain electrode, an N + substrate and an N-epitaxial layer from bottom to top; the N-epitaxial layer is provided with a first P-well region, and the first P-well region is provided with a P + region and an N + region; further comprising: the first metal forms a first ohmic contact with the upper surface of the P + region and the upper surface of part of the N + region; the second P-well region is positioned between two adjacent first P-well regions, a first interval is formed between the second P-well region and the first P-well regions on the two sides of the second P-well region, and the second P-well region is surrounded by a groove; and a second metal covering the surface of the trench to form a second ohmic contact, and simultaneously covering the upper surface of the first spacer to form a Schottky contact. The silicon carbide MOSFET device improves the follow current capability of the device and simultaneously prevents the problem that the leakage current of the Schottky contact region is overlarge when the device works in a high-voltage blocking mode.

Description

silicon carbide MOSFET device

Technical Field

The utility model relates to a semiconductor field especially relates to a carborundum MOSFET device.

Background

In recent years, with the continuous development of power electronic systems, higher requirements are put on power devices in the systems. Silicon (Si) -based power electronics have not been able to meet the requirements of system applications due to the limitations of the materials themselves.

Silicon carbide (SiC) materials, as representative of third generation semiconductor materials, are far better than silicon materials in many properties. Silicon carbide MOSFET devices, as commercial devices in recent years, have great potential to replace existing IGBTs in terms of on-resistance, switching time, switching loss, heat dissipation performance, and the like.

However, because the silicon carbide material has a large forbidden bandwidth, the turn-on voltage of a parasitic PiN diode integrated in the silicon carbide MOSFET device is mostly about 3V, and the parasitic PiN diode cannot provide a freewheeling function for the silicon carbide MOSFET device. Therefore, in the application of power electronic systems such as full bridge, a schottky diode is often connected in anti-parallel to be used as a freewheeling diode, which greatly increases the area of the system.

Silicon carbide MOSFET devices incorporating junction barrier schottky diodes solve this problem.

However, the silicon carbide MOSFET device integrated with the conventional junction barrier schottky diode still has many problems, which are mainly due to the fact that a larger schottky contact area is required to enable the schottky diode to have better follow current capability. The larger area of the Schottky contact region enables the MOSFET to have larger leakage current during normal work on the one hand, and on the other hand, the area of the unit cell of the silicon carbide MOSFET device is increased, and the preparation cost of the chip is increased.

For more details on existing silicon carbide MOSFET devices with integrated junction barrier schottky diodes, reference may be made to chinese patents (applications) with publication numbers CN106876485A and CN 108807504A.

SUMMERY OF THE UTILITY MODEL

The utility model provides a silicon carbide MOSFET device, which comprises a drain electrode, an N + substrate and an N-epitaxial layer from bottom to top; the N-epitaxial layer is provided with a first P-well region, and the first P-well region is provided with a P + region and an N + region (the depth of the first P-well region is larger than that of the N + region and the P + region); further comprising: a first metal forming a first ohmic contact with the upper surface of the P + region and a portion of the upper surface of the N + region; the grid dielectric layer is positioned on the upper surfaces of part of the N + region, part of the P-well region and part of the N-epitaxial layer; the grid electrode is positioned on the grid dielectric layer; the isolation dielectric layer covers the side surface of the grid electrode and the upper surface of the grid electrode; at least one second P-well region, the second P-well region being located between two adjacent first P-well regions, the second P-well region having a first spacing from the first P-well regions, the second P-well region surrounding a trench; a second metal overlying the trench surface to form a second ohmic contact, the second metal simultaneously overlying the first spacer upper surface to form a schottky contact; and the third metal covers the isolation medium layer, the first metal and the second metal. The first metal, the second metal and the third metal are all used as a part of the source electrode, or the source electrode comprises the first metal, the second metal and the third metal. Specifically, the first ohmic contact is a portion of the source ohmic contact, and then the first metal and the second metal are connected through the third metal. The first ohmic contact is connected to the second ohmic contact and the schottky contact, which form the source electrode of the corresponding MOS device.

From the above structure, the schottky contact is located between two adjacent first P-well regions, i.e. the corresponding trench junction barrier schottky diode is located between two adjacent sources (N + regions) in the MOS device.

the depth of the second P-well region is greater than the depth of the first P-well region.

Optionally, the depth of the groove is 0.5 μm to 2.5 μm, and the width is 0.5 μm to 20 μm. The depth of the groove is too large, so that the manufacturing difficulty is increased, and if the depth of the groove is too small, the effect of increasing the junction depth is not obvious. Too small a trench width is not conducive to a corresponding increase in junction depth.

Optionally, the distance between the first P-well region and the second P-well region is 1.5 μm to 5 μm. That is, the width of the first space is usually 1.5 μm to 5 μm. If the width of the first interval is too small, the corresponding Schottky contact region cannot be well conducted, if the width of the first interval is too large, the leakage current of the whole device is overlarge, and the area of the device is overlarge, so that the improvement of the performance of the device is not facilitated.

Optionally, more than two second P-well regions are disposed between two adjacent first P-well regions, a second space is disposed between two adjacent second P-well regions, and the second metal covers upper surfaces of the second space at the same time to form a schottky contact.

Optionally, the second metal is titanium, nickel, molybdenum or tungsten.

The utility model also provides a preparation method of carborundum MOSFET device, including following step:

forming an N-epitaxial layer on an N + substrate;

Forming a groove on the N-epitaxial layer;

Performing well implantation on the surface of the trench and part of the surface of the N-epitaxial layer to form a first P-well region and a second P-well region, wherein the second P-well region is located between two adjacent first P-well regions, a first interval is formed between the second P-well region and the first P-well region, and the second P-well region surrounds the trench (namely the trench is wrapped by the second P-well region);

Forming an N + region and a P + region in the first P-well region;

Forming a gate dielectric layer to cover part of the upper surface of the N + region, part of the upper surface of the first P-well region and part of the upper surface of the N-epitaxial layer;

Forming a grid electrode on the upper surface of the grid dielectric layer;

Forming isolation dielectric layers on the side surfaces and the upper surface of the grid;

forming a first metal to cover the upper surface of the P + region and part of the upper surface of the N + region so as to form a first ohmic contact;

Forming a second metal overlying the trench surface to form a second ohmic contact, the second metal overlying the first spacer upper surface to form a schottky contact;

And forming a third metal to cover the isolation dielectric layer, the first metal and the second metal.

the first metal, the second metal and the third electrode all serve as source electrodes.

The process of forming the trench may include forming a first mask layer (material may be SiO ₂) on the N-epitaxial layer, forming a first mask pattern on the first mask layer by a corresponding photolithography etching process, and forming the trench by ICP etching or the like.

The process of forming the first and second P-well regions may include respective ion implantations, which may include: removing the first mask layer (a cleaning method can be adopted), forming a second mask layer on the surface of the newly exposed N-epitaxial layer, and forming a second mask pattern by using a photoetching process; and then forming a preliminary structure of each P-well region by an Al ion injection means, and subsequently activating to form a first P-well region and a second P-well region.

The above process shows that the depth of the second P-well region is greater than that of the first P-well region, because the second P-well region is formed at the corresponding position of the trench, the second P-well region having a depth greater than that of the first P-well region can be directly formed in one step.

Optionally, the process of forming the N + region and the P + region in the first P-well region may include: removing the second mask layer (cleaning method can be adopted), forming a third mask layer on the surface of the N-epitaxial layer again, forming a third mask pattern by using processes such as photoetching and etching, and forming an N + region primary structure by using an N ion implantation means; removing the third mask layer (cleaning method can be adopted), reforming a fourth mask layer on the surface of the N-epitaxial layer, forming a fourth mask pattern by using the processes of photoetching, etching and the like, and forming a P + region primary structure by using an Al ion implantation means; and finally forming corresponding N + regions and P + regions through activation.

optionally, more than two second P-well regions are formed between two adjacent first P-well regions, and a second interval is formed between two adjacent second P-well regions; the second metal simultaneously covers the second spacer upper surfaces to form Schottky contacts.

Optionally, the activating process may include: and forming a carbon film protection on the surface of the N-epitaxial layer, activating implanted ions through high-temperature annealing, and removing the carbon film through an oxidation method.

Optionally, the forming process of the gate dielectric layer, the gate electrode and the isolation dielectric layer may include: and performing sacrificial oxidation on the surface of the N-epitaxial layer to form a sacrificial oxide layer, removing the sacrificial oxide layer, and depositing a dielectric layer (which can be silicon dioxide). Etching the dielectric layer by means of photoetching and the like to expose a source region part (the exposed part comprises the upper surface of an N + region, the upper surface of a part of a first P-well region, the upper surface of a part of an N-epitaxial layer and the like), growing a layer of silicon dioxide serving as a gate dielectric layer on the exposed surface by a thermal oxidation method, and annealing in a Nitrogen Oxide (NO) atmosphere after thermal oxidation; then, depositing high-doped polysilicon by adopting a chemical vapor deposition method, and forming a corresponding grid electrode by adopting the processes of photoetching, etching and the like; finally, a corresponding dielectric layer (which may be silicon dioxide) may be deposited as an isolation dielectric layer.

optionally, the forming process of the first ohmic contact includes: and carrying out a rapid thermal annealing process under an argon atmosphere. Specifically, the upper surface of the corresponding P + region and part of the upper surface of the N + region are exposed by using a process such as photolithography and etching, and then, the first metal may form corresponding metals on the front and back surfaces of an epitaxial wafer (i.e., an integrated structure of an N + substrate and an N-epitaxial layer), and the metal on the back surface of the epitaxial wafer becomes a part of the drain electrode. The metal on the back of the epitaxial wafer and the back of the N + substrate generally form an ohmic contact, and the formation process of the ohmic contact can also include performing a rapid thermal annealing process under an argon atmosphere. At this time, the rapid thermal annealing process may be performed on the front and back structures of the epitaxial wafer at the same time.

Optionally, the forming process of the second ohmic contact and the schottky contact includes: and annealing the second metal by adopting a low-temperature rapid thermal annealing process. Specifically, before forming the second metal, the metal on the back side of the epitaxial wafer may be protected, then the excess first metal on the front side is removed, and a gate window (for contacting with the gate) and a schottky contact window (for contacting the second metal with the corresponding upper surface of the first spacer, that is, the upper surface of a part of the N-epitaxial layer) are formed by etching, then the second metal is deposited (the second metal covers the upper surface of the first spacer and the surface of the trench), then a third metal (thick metal) is deposited, an electrode pattern is formed by a process such as a photolithography etching process (and the gate electrode is separated from the corresponding source electrode), and a schottky contact is formed in the corresponding schottky region by a low-temperature rapid thermal annealing process.

optionally, after forming the corresponding third metal (thick metal) on the upper surface of the N-epitaxial layer, another thick electrode may be continuously formed on the metal on the back surface of the epitaxial wafer.

Optionally, the width of the trench is less than or equal to the implantation width when the P + region is formed.

The utility model discloses in, provide a carborundum MOSFET device of groove type structure, in the device, corresponding grid in the whole cover source region of source electrode metal (first metal and second metal), is kept apart by the isolation dielectric layer between grid and the source electrode.

The utility model discloses a carborundum MOSFET device, in the integrated schottky diode structure in the device, introduce the slot structure to when promoting device afterflow ability, prevent that schottky area of contact is too big and extravagant device cellular area, thereby reduce device preparation cost simultaneously.

The utility model discloses technical scheme's one of them aspect, through the leading-in of slot structure for the degree of depth of middle second P-well region is greater than the degree of depth of the first P-well region in both sides, and the degree of depth that promotes the P-well region can effectively reduce schottky contact area's surface electric field, reduces the device leakage current. That is, the introduction of the trench can form a trench junction barrier in the schottky diode, and the corresponding junction depth can be increased, and the junction depth can be increased, so that the peak electric field of the schottky contact surface can be reduced. Therefore, the blocking leakage current of the Schottky diode can be effectively reduced, and the power consumption of the MOSFET is reduced.

Further, the utility model discloses technical scheme's another aspect, the peak electric field that reduces schottky contact surface can make schottky contact position adopt the relatively lower metal of barrier height, further reduces schottky diode's among them turn on the voltage drop, reduces the area of schottky contact zone. And further, the cell area of the whole MOSFET device can be reduced, and the integration capability of the MOSFET device is improved.

In addition, in the conventional method, even if a trench structure exists, an isolated P + region or other structures are implanted at the bottom, and the junction depth is not effectively increased due to the P + region, so that the leakage current of the schottky contact region during the bearing of the device cannot be effectively reduced. And among the carborundum MOSFET device of this application, structurally, pour into the well region structure of P in whole slot inside into, can effectively promote the junction depth of slot both sides schottky region P type knot like this, the increase of effective junction depth can reduce the surperficial electric field of schottky region, and then leakage current when reducing the device pressure-bearing.

drawings

FIG. 1 is a schematic diagram of a silicon carbide MOSFET device in an example embodiment;

FIGS. 2 through 5 are schematic structural diagrams corresponding to steps in the fabrication of the silicon carbide MOSFET device shown in FIG. 1;

FIG. 6 is a simulation result of blocking current-voltage characteristics of the silicon carbide MOSFET device of the embodiment and a conventional silicon carbide MOSFET device;

FIG. 7 is a schematic diagram of a silicon carbide MOSFET device in another embodiment;

FIGS. 8-11 are schematic structural diagrams corresponding to steps in the fabrication of the silicon carbide MOSFET device shown in FIG. 7;

Fig. 12 is a simulation result of blocking current curves of a silicon carbide MOSFET device in another embodiment and a conventional silicon carbide MOSFET device.

Detailed Description

The existing silicon carbide MOSFET device has the defects that in order to improve the follow current capability of the device, the Schottky contact area is too large, the cell area of the device is wasted, the preparation cost of the device is increased, and the like.

To this end, the present invention provides a new silicon carbide MOSFET device to solve the above-mentioned deficiencies. For a clearer illustration, the present invention will be described in detail with reference to the accompanying drawings.

example 1

The present embodiment provides a silicon carbide MOSFET device integrated with a trench junction barrier schottky diode, which has a cross-sectional structure as shown in fig. 1.

The device comprises, from bottom to top, a drain electrode comprising the metal 19 shown in fig. 1, an N + substrate 11 and an N-epitaxial layer 12. The N-epitaxial layer 12 has a first P-well region 14 with a P + region 16 and an N + region 17 in the first P-well region 14 (the first P-well region 14 is deeper than the N + region 17 and the P + region 16). The number of the first P-well regions 14 is more than two, and may be generally large.

The device further comprises: a first metal 18, the first metal 18 forming a first ohmic contact with the upper surface of the P + region 16 and a portion of the upper surface of the N + region 17. In addition, the first metal 18 also forms a good ohmic contact with a portion of the upper surface of the first P-well region 14 (although in other embodiments, the first metal does not form an ohmic contact with the upper surface of the first P-well region). The back side of the N + substrate 11 also has metal 19 (as described above, metal 19 is part of the drain electrode); a gate dielectric layer 20 positioned on the upper surfaces of the partial N + region 17, the partial first P-well region 14 and the partial N-epitaxial layer 12; a gate electrode 21 located on the gate dielectric layer 20; the isolation dielectric layer 22 covers the side surface of the grid 21 and the upper surface of the grid 21; a second P-well region 15 located between two adjacent first P-well regions 14, where the second P-well region 15 and the first P-well regions 14 on both sides have a first interval (not labeled), and the second P-well region 15 surrounds a trench 13 (in fig. 1, the trench 13 is already filled, and the trench 13 may refer to the manufacturing method contents corresponding to fig. 2 to 5 of the subsequent method contents); a second metal (not labeled, and subsequently both contacts are labeled with both contacts) covering the surface of the trench 13 to form a second ohmic contact 23 (it should be noted that the ohmic contact refers to the corresponding contact, but the reference line is labeled on the corresponding metal portion for the convenience of display and description), and the second metal simultaneously covers the upper surface of the first spacer to form a schottky contact 24 (likewise, the schottky contact refers to the corresponding contact, but the reference line is labeled on the corresponding metal portion for the convenience of display and description); a third metal 25, the third metal 25 covering the isolation dielectric layer 22, the first metal 18 and said second metal (the third metal 25 filling the remaining trench 13 is also shown in fig. 1).

The first metal 18, the second metal and the third metal 25 are all used as a part of the source electrode, or the source electrode includes the first metal 18, the second metal and the third metal 25. Specifically, the first ohmic contact is a portion of the source ohmic contact, and then the first metal 18 and the second metal are connected through the third metal 25. The first ohmic contact is connected to a second ohmic contact 23 and a schottky contact 24, which form the source electrodes of the respective MOS devices.

in this embodiment, the N + substrate 11 may be made of a silicon carbide material having a doping concentration of 5 × 10 ¹⁸ cm ^-3, and may have a thickness of 350 μm.

in this embodiment, the doping concentration of the N-epitaxial layer 12 may be 6 × 10 ¹⁵ cm ^-3, and the thickness may be 10 μm.

In this embodiment, the doping concentration of the first P-well region 14 and the second P-well region 15 is 5 × 10 ¹⁶ cm ^-3.

In this embodiment, the doping concentration of the N + region 17 is 1 × 10 ¹⁹ cm ^-3.

In this embodiment, the doping concentration of the P + region 16 is 1 × 10 ¹⁹ cm ^-3.

in this embodiment, the width of the first space is 2 μm. The trenches 13 have a width of 2 μm and a depth of 1 μm.

In this embodiment, the second P-well region 15 and the first P-well region 14 have the first spacing therebetween, and the first spacing on both sides is equal, i.e. the spacing between the second P-well region 15 and the first P-well region 14 on both sides is generally equal.

The present embodiment further provides a method for fabricating the silicon carbide MOSFET device, please refer to fig. 2 to fig. 5 in combination, and refer back to fig. 1 for a finally formed structure. The manufacturing method comprises the following steps:

Referring to fig. 2, an N-epitaxial layer 12 is formed on an N + substrate 11 by epitaxial growth, and the N + substrate 11 and the N-epitaxial layer 12 on which the N-epitaxial layer 12 is grown are referred to as an epitaxial wafer.

then, with continued reference to fig. 2, on the N-epitaxial layer 12, a first mask layer (not shown) is deposited, the first mask having a thickness of 2 μm. A first mask pattern is formed by a photoetching process, and a groove 13 is formed by an ICP etching method, wherein the width of the groove 13 is 2 μm, and the depth of the groove 13 is 1 μm.

Referring to fig. 3, well implantation is performed on the surface of the trench 13 and a portion of the surface of the N-epitaxial layer 12, the implanted ions are Al ions, so as to form a first P-well region 14 and a second P-well region 15, the second P-well region 15 is located between two adjacent first P-well regions 14, a first space (not labeled) is formed between the second P-well region 15 and the first P-well region 14, the width of the first space is controlled to be 2 μm, and the second P-well region 15 surrounds the trench 13. Since trench 13 is formed before and then together with first P-well region 14 and second P-well region 15, the depth of second P-well region 15 is greater than the depth of first P-well region 14.

Referring to fig. 4, an N + region 17 and a P + region 16 are formed in the first P-well region 14, wherein the ions implanted in the N + region 17 are N ions, and the ions implanted in the P + region 16 are Al ions.

Referring to fig. 5, a gate dielectric layer 20 is formed to cover the entire upper surface of the source region (including the upper surface of a portion of N + region 17, the upper surface of a portion of first P-well region 14, and the upper surface of a portion of N-epitaxial layer 12). A gate electrode 21 is formed on the upper surface of the gate dielectric layer 20. An isolation dielectric layer 22 is formed on the side and upper surfaces of the gate electrode 21.

Referring back to fig. 1, a first metal 18 is formed to cover the upper surface of the P + region 16 and a portion of the upper surface of the N + region 17 to form a first ohmic contact, and in this embodiment, the first metal 18 and a portion of the upper surface of the first P-well region 14 also form an ohmic contact (as mentioned above, the first metal and the upper surface of the first P-well region may not form an ohmic contact). At or after the first metal 18 is formed, a metal 19 is also formed on the back surface of the N + substrate 11 as a part of the drain electrode.

Referring back to fig. 1, the second metal is formed, which fills the trench 13 and covers the surface of the trench 13 to form a second ohmic contact 23, and covers the upper surface of the first spacer to form a schottky contact 24.

referring back to fig. 1, a third metal 25 is formed to cover the isolation dielectric layer 22, the first metal 18 and the second metal.

In the present embodiment, forming a carbon film (not shown) on the surface of the N-epitaxial layer 12 for protection includes performing carbon film on the surface of the N-epitaxial layer 12 using a carbon film sputtering machine. Then, the implanted ions (implanted ions) were activated by high-temperature annealing at 1650 ℃ for 45min, and thereafter, the carbon film was removed by an oxidation method. Thereafter, the carbon film is removed by an oxidation method.

In this embodiment, the process of forming the gate dielectric layer 20 includes performing sacrificial oxidation on the surface of the N-epitaxial layer 12, and depositing a layer of silicon dioxide after removing the oxide layer. And then, photoetching and etching are adopted, and after the dielectric window is etched, a source region is formed. And growing a layer of silicon dioxide serving as the gate dielectric layer 20 by adopting a thermal oxidation method, and annealing in the atmosphere of nitric oxide at the annealing temperature of 1200 ℃ for 1 h.

in this embodiment, the process of forming the gate 21 includes depositing a highly doped polysilicon layer by a chemical vapor deposition method, and forming the gate 21 of polysilicon by photolithography and etching.

In this embodiment, forming the isolation dielectric layer 22 includes depositing another silicon dioxide layer and forming the isolation dielectric layer 22 by etching.

In this embodiment, the process of forming the isolation dielectric layer 22 further includes etching the surface regions of the N + region 17 and the P + region 16 by photolithography and etching, so as to prepare for forming the first ohmic contact subsequently.

In this embodiment, the process of depositing the first metal 18 and forming the first ohmic contact further includes: and (3) carrying out a rapid thermal annealing process under the argon atmosphere, wherein the annealing temperature is 1000 ℃, and the annealing time is 3 min. The first metal 18 is nickel.

In this embodiment, the process of forming the second ohmic contact 23 and the schottky contact 24 includes: and annealing the second metal by adopting a low-temperature rapid thermal annealing process, wherein the annealing temperature is 500 ℃, and the annealing time is 2 min. The second metal is titanium.

Then, a third metal 25 is deposited, the third metal 25 is Al, and the third metal 25 is etched by photolithography and etching processes to form an electrode pattern.

Not shown, after the third metal 25 is formed, another layer of thick metal, which may be titanium, nickel or silver, etc., may be deposited on the back side of the epitaxial wafer and on the metal 19, as a back electrode (which is part of the drain electrode).

Fig. 6 is a simulation result of blocking voltage curves of the silicon carbide MOSFET device and the conventional silicon carbide MOSFET device in this embodiment. Fig. 6 shows the simulated blocking condition of the sic MOSFET device (indicated by the dashed line New) in this embodiment and the simulated blocking condition of the existing sic MOSFET device (indicated by the dashed line Old). In contrast, in the embodiment, the silicon carbide MOSFET device has the TJBS structure (i.e., the trench junction barrier schottky diode structure), so that the device leakage current is effectively reduced, and the power consumption of the device can be reduced.

Example 2

The present embodiment provides a silicon carbide MOSFET device integrated with a trench junction barrier schottky diode, and a schematic cross-sectional structure diagram thereof is shown in fig. 7.

The device comprises, from bottom to top, a drain electrode (the drain electrode comprises metal 39 shown in fig. 7), an N + substrate 31 and an N-epitaxial layer 32; n-epitaxial layer 32 has a first P-well region 34, with P + region 36 and N + region 37 in first P-well region 34 (where first P-well region 34 is deeper than N + region 37 and P + region 36). The number of the first P-well regions 34 is more than two.

The device further comprises: a first metal 38, wherein the first metal 38 forms a first ohmic contact with the upper surface of the P + region 36 and the upper surface of a part of the N + region 37 (the first metal 38 also covers the upper surface of a part of the first P-well region 34, but the contact therebetween may be an ohmic contact or a non-ohmic contact); the back side of the N + substrate 31 also has a metal 39; a gate dielectric layer 40 on the upper surfaces of the partial N + region 37, the partial first P-well region 34 and the partial N-epitaxial layer 32; a gate 41 on the gate dielectric layer 40; an isolation dielectric layer 42 covering the side surface of the gate 41 and the upper surface of the gate 41; two second P-well regions 35 located between two adjacent first P-well regions 34, the left second P-well region 35 has a first interval with the left first P-well region 34, the right second P-well region 35 has a first interval with the right first P-well region 34, and the two second P-well regions 35 have a second interval; the second P-well region 35 encloses the trench 33 (in fig. 7, the trench 33 has been filled, as can be seen in fig. 8 to 11 of the subsequent method content); a second metal (not labeled, subsequently labeled with two contacts) covering the surface of trench 33 to form a second ohmic contact 43, the second metal simultaneously covering the first spaced upper surfaces to form a schottky contact 44; a third metal 45, the third metal 45 covering the isolation dielectric layer 42, the first metal 38 and the second metal.

The first metal 38, the second metal and the third metal 45 are all used as a part of the source electrode, or the source electrode includes the first metal 38, the second metal and the third metal 45. Specifically, the first ohmic contact is a portion of the source ohmic contact, and then the first metal 38 and the second metal are connected through the third metal 45. The first ohmic contact is connected to a second ohmic contact 43 and a schottky contact 44, which form the source electrodes of the respective MOS devices.

in the present embodiment, each second P well region 35 is formed in a two-layer shape with a wrinkle, and this shape can be realized when the width of the trench 13 is smaller than the implantation width when forming the P + region 36.

in this embodiment, the N + substrate 31 may be made of a silicon carbide material with a doping concentration of 5 × 10 ¹⁸ cm ^-3, and may have a thickness of 350 μm.

In this embodiment, the doping concentration of the N-epitaxial layer 32 may be 6 × 10 ¹⁵ cm ^-3, and the thickness may be 10 μm.

In this embodiment, the doping concentration of the first P-well region 34 and the second P-well region 35 is 3 × 10 ¹⁶ cm ^-3.

In this embodiment, the doping concentration of the N + region 37 is 5 × 10 ¹⁹ cm ^-3.

In this embodiment, the doping concentration of the P + region 36 is 5 × 10 ¹⁹ cm ^-3.

In this embodiment, the width of the first space is controlled to be 2.5 μm. The width of the trench 33 is 1 μm and the depth is 1 μm.

This embodiment further provides a method for fabricating the silicon carbide MOSFET device, please refer to fig. 8 to fig. 11 in combination, and refer back to fig. 7 for the finally formed structure.

The manufacturing method comprises the following steps:

Referring to fig. 8, an N-epitaxial layer 32 is formed on an N + substrate 31 by epitaxial growth, and the N + substrate 31 and the N-epitaxial layer 32 on which the N-epitaxial layer 32 is grown are referred to as an epitaxial wafer.

Then, with continued reference to fig. 8, on the N-epitaxial layer 32, a first mask layer (not shown) is deposited to form a first mask having a thickness of 2 μm. A first mask pattern is formed by a photolithography etching process, and two trenches 33 are formed by an ICP etching method, the width of the trench 33 being 1 μm and the depth being 0.8 μm.

Referring to fig. 9, well implantation is performed on the surface of the trench 33 and a portion of the surface of the N-epitaxial layer 32, the implanted ions are Al ions, so as to form first P-well regions 34 and second P-well regions 35, each of the two second P-well regions 35 is located between two adjacent first P-well regions 34, a first space (not labeled) is provided between each second P-well region 35 and the first P-well region 34, a second space (not labeled) is provided between the two second P-well regions 35, the width of the first space is controlled to be 2.5 μm, and the second P-well regions 35 surround the trench 33. Since the trench 33 is formed in front of and then together with the first P-well region 34 and the second P-well region 35, the depth of the second P-well region 35 is greater than the depth of the first P-well region 34. Moreover, the width of the trench 33 is smaller than the implantation width when forming the second P-well region 35, so that the second P-well region 35 has a two-layer gradient structure.

It is understood that more than two second P-well regions are formed between two adjacent first P-well regions in the present embodiment.

Referring to fig. 10, N + region 37 and P + region 36 are formed in first P-well region 34, wherein the ions implanted in N + region 37 are N ions, and the ions implanted in P + region 36 are Al ions.

Referring to fig. 11, a gate dielectric layer 40 is formed to cover the entire upper surface of the source region (including the upper surface of a portion of N + region 37, the upper surface of a portion of first P-well region 34, and the upper surface of a portion of N-epitaxial layer 32). A gate electrode 41 is formed on the upper surface of the gate dielectric layer 40. An isolation dielectric layer 42 is formed on the side and upper surfaces of the gate electrode 41.

Referring back to fig. 7, a first metal 38 is formed to cover the upper surface of the P + region 36 and a portion of the upper surface of the N + region 37 to form a first ohmic contact, and in this embodiment, the first metal 38 and a portion of the upper surface of the first P-well region 34 also form an ohmic contact (as mentioned above, the first metal and the upper surface of the first P-well region may not form an ohmic contact). At or after the formation of the first metal 38, a metal 39 is also formed on the back surface of the N + substrate 31 as part of the drain electrode.

Referring back to fig. 7, the second metal is formed to fill the trench 33 and cover the surface of the trench 33 to form a second ohmic contact 43, the second metal covers the upper surface of the first spacer to form a schottky contact 44, and the second metal covers the upper surface of the second spacer to form a schottky contact 44.

Referring back to fig. 7, a third metal 45 is formed to cover the isolation dielectric layer 42, the first metal 38 and the second metal.

in the present embodiment, forming a carbon film (not shown) on the surface of the N-epitaxial layer 32 for protection includes performing carbon film on the surface of the N-epitaxial layer 32 using a carbon film sputtering machine. Then, the implanted ions (implanted ions) were activated by high-temperature annealing at 1650 ℃ for 45min, and thereafter, the carbon film was removed by an oxidation method. Thereafter, the carbon film is removed by an oxidation method.

In this embodiment, the process of forming the gate dielectric layer 40 includes performing sacrificial oxidation on the surface of the N-epitaxial layer 32, and depositing a layer of silicon dioxide after removing the oxide layer. And then, photoetching and etching are adopted, and after the dielectric window is etched, a source region is formed. And growing a layer of silicon dioxide serving as the gate dielectric layer 40 by adopting a thermal oxidation method, and annealing in the atmosphere of nitric oxide at the annealing temperature of 1200 ℃ for 1 h.

In this embodiment, the process of forming the gate 41 includes depositing a highly doped polysilicon layer by a chemical vapor deposition method, and forming the gate 41 of polysilicon by photolithography and etching.

In this embodiment, forming the isolation dielectric layer 42 includes depositing another silicon dioxide layer and forming the isolation dielectric layer 42 by etching.

In this embodiment, the process of forming the isolation dielectric layer 42 further includes etching the surface regions of the N + region 37 and the P + region 36 by photolithography and etching, so as to prepare for forming the first ohmic contact subsequently.

In this embodiment, the process of depositing the first metal 38 and forming the first ohmic contact further includes: and (3) carrying out a rapid thermal annealing process under the argon atmosphere, wherein the annealing temperature is 1000 ℃, and the annealing time is 3 min. The first metal 38 is nickel.

In this embodiment, the process of forming the second ohmic contact 43 and the schottky contact 44 includes: and annealing the second metal by adopting a low-temperature rapid thermal annealing process, wherein the annealing temperature is 700 ℃, and the annealing time is 1 min. The second metal is titanium.

and depositing a third metal 45, wherein the third metal 45 is Al, and etching the third metal 45 by photoetching and etching processes to form an electrode pattern.

Not shown, after the third metal 45 is formed, another layer of thick metal, which may be titanium, nickel or silver, etc., may be deposited on the back side of the epitaxial wafer and on the metal 39, as a back electrode (which is part of the drain electrode).

Fig. 12 is a simulation result of blocking voltage curves of the silicon carbide MOSFET device and the conventional silicon carbide MOSFET device in this embodiment. Fig. 12 shows the simulated blocking condition of the sic MOSFET device (indicated by the dashed line New) in this embodiment and the simulated blocking condition of the existing sic MOSFET device (indicated by the dashed line Old). By contrast, in the present embodiment, the silicon carbide MOSFET device has the TJBS structure, so that the device leakage current is effectively reduced, and the device power consumption can be reduced.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present invention, and the scope of the present invention is defined by the appended claims.

Claims

1. A silicon carbide MOSFET device is characterized in that the device comprises a drain electrode, an N + substrate and an N-epitaxial layer from bottom to top; the N-epitaxial layer is provided with a first P-well region, and the first P-well region is provided with a P + region and an N + region;

Further comprising:

A first metal forming a first ohmic contact with the upper surface of the P + region and a portion of the upper surface of the N + region;

The grid dielectric layer is positioned on the upper surfaces of part of the N + region, part of the first P-well region and part of the N-epitaxial layer;

The grid electrode is positioned on the grid dielectric layer;

The isolation dielectric layer covers the side surface of the grid electrode and the upper surface of the grid electrode;

At least one second P-well region, the second P-well region being located between two adjacent first P-well regions, the second P-well region having a first spacing from the first P-well regions, the second P-well region surrounding a trench;

A second metal overlying the trench surface to form a second ohmic contact, the second metal simultaneously overlying the first spacer upper surface to form a schottky contact;

And the third metal covers the isolation medium layer, the first metal and the second metal.

2. the silicon carbide MOSFET of claim 1, wherein the second P-well region has a depth greater than the depth of the first P-well region.

3. The silicon carbide MOSFET of claim 1, wherein the trench has a depth of between 0.5 μm and 2.5 μm and a width of between 0.5 μm and 20 μm.

4. the silicon carbide MOSFET of claim 1, wherein the first P-well region and the second P-well region have a spacing between 1.5 μm and 5 μm.

5. The silicon carbide MOSFET of claim 1, wherein two or more of the second P-well regions are between adjacent ones of the first P-well regions, wherein a second space is between adjacent ones of the second P-well regions, and wherein the second metal simultaneously covers upper surfaces of the second spaces to form schottky contacts.