JP2011114028A - SiC SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SAME - Google Patents

SiC SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SAME Download PDF

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JP2011114028A
JP2011114028A JP2009266464A JP2009266464A JP2011114028A JP 2011114028 A JP2011114028 A JP 2011114028A JP 2009266464 A JP2009266464 A JP 2009266464A JP 2009266464 A JP2009266464 A JP 2009266464A JP 2011114028 A JP2011114028 A JP 2011114028A
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grooves
region
oxide film
semiconductor device
semiconductor substrate
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Masaki Konishi
正樹 小西
Hirokazu Fujiwara
広和 藤原
Takeshi Endo
剛 遠藤
Takeo Yamamoto
武雄 山本
Takashi Katsuno
高志 勝野
Yukihiko Watanabe
行彦 渡辺
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Denso Corp
Toyota Motor Corp
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Toyota Motor Corp
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    • H—ELECTRICITY
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    • H01L29/772—Field effect transistors
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    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide

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Abstract

<P>PROBLEM TO BE SOLVED: To provide an SiC semiconductor device allowing a depletion layer smooth from the inside toward the outside to be formed in an end region of a semiconductor substrate using silicon carbide as a material. <P>SOLUTION: The semiconductor device 10 includes a semiconductor substrate 25 using silicon carbide as a material. The semiconductor substrate 25 includes an element region 12 and an end region 14 surrounding the circumference of the element region. In the end region 14, a plurality of grooves 17, 19, 21, 23 taking a round outside the element region 12 are formed. Bottom faces of the plurality of grooves are formed to sequentially reduce the depth from the groove on the inner peripheral side to the groove on the outer peripheral side. On the respective lower sides of the plurality of grooves, p-type regions 16, 18, 20, 22 of which the circumferences are surrounded by a drift layer 26 are formed. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、炭化珪素（ＳｉＣ）を材料とする半導体基板を有するＳｉＣ半導体装置に関する。詳しくは、ＳｉＣ半導体装置の耐圧特性を向上するための技術に関する。   The present invention relates to a SiC semiconductor device having a semiconductor substrate made of silicon carbide (SiC). Specifically, the present invention relates to a technique for improving the breakdown voltage characteristics of an SiC semiconductor device.

近年、パワーＭＯＳＦＥＴ（Metal Oxide Semiconductor Field Effect Transistor）、パワーダイオード等の大電流を制御する半導体装置が開発されている。この種の半導体装置には、高電圧が印加されるため、半導体装置の高耐圧化が必要となる。特許文献１，２では、半導体装置の高耐圧化を実現するために、素子領域（アクティブ領域）の外周を取囲む終端領域にガードリングを形成することが提案されている。これらの文献に記載の技術では、半導体基板の終端領域に、内周側から外周側に向かって、順に浅くなる複数のガードリングが形成される。これによって、空乏層が素子領域の内側から外側に向かって滑らかに形成され、その結果、電解集中が緩和されて半導体装置の高耐圧化が図られている。   In recent years, semiconductor devices that control a large current, such as a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and a power diode, have been developed. Since a high voltage is applied to this type of semiconductor device, it is necessary to increase the breakdown voltage of the semiconductor device. In Patent Documents 1 and 2, it is proposed to form a guard ring in a termination region surrounding the outer periphery of an element region (active region) in order to achieve a high breakdown voltage of a semiconductor device. In the techniques described in these documents, a plurality of guard rings that are gradually shallower from the inner peripheral side toward the outer peripheral side are formed in the termination region of the semiconductor substrate. As a result, the depletion layer is formed smoothly from the inner side to the outer side of the element region. As a result, the concentration of electrolysis is relaxed and the high breakdown voltage of the semiconductor device is achieved.

特開平８−７８６６１JP-A-8-78661 特開２００４−９５６５９JP 2004-95659 A

近年、半導体装置の低損失化等を実現するために、炭化珪素（ＳｉＣ）を材料とする半導体基板を備えたＳｉＣ半導体装置の開発が進められている。ＳｉＣ半導体装置においても、高耐圧化が必要とされることから、上記の文献に記載された技術を適用することが望ましい。しかしながら、上記の文献に記載の技術では、シリコン基板（Ｓｉ基板）にイオン注入した不純物や、トレンチ内に埋め込んだ半導体層の不純物を熱拡散させることによってガードリングを形成している。このため、シリコン基板よりも拡散係数の小さい炭化珪素基板では、熱処理を施しても半導体基板に注入された不純物がほとんど拡散しない。従って、上記の文献に記載された方法では、深さの異なる複数のガードリングを有するＳｉＣ半導体装置を製造することができない。   2. Description of the Related Art In recent years, development of SiC semiconductor devices including semiconductor substrates made of silicon carbide (SiC) has been promoted in order to reduce the loss of semiconductor devices. Since the SiC semiconductor device is also required to have a high breakdown voltage, it is desirable to apply the technique described in the above-mentioned document. However, in the technique described in the above document, the guard ring is formed by thermally diffusing impurities implanted into the silicon substrate (Si substrate) or impurities in the semiconductor layer embedded in the trench. For this reason, in a silicon carbide substrate having a diffusion coefficient smaller than that of a silicon substrate, impurities implanted into the semiconductor substrate hardly diffuse even when heat treatment is performed. Therefore, the method described in the above literature cannot manufacture a SiC semiconductor device having a plurality of guard rings having different depths.

本明細書は上記の課題を解決する。すなわち、本明細書は、炭化珪素を材料とする半導体基板の終端領域に、内側から外側に向かって滑らかに空乏層を形成することができる技術を提供することを目的としている。   The present specification solves the above problems. That is, the present specification aims to provide a technique capable of smoothly forming a depletion layer from the inside toward the outside in a terminal region of a semiconductor substrate made of silicon carbide.

本明細書によって開示されるＳｉＣ半導体装置は、炭化珪素を材料とする半導体基板を有する。半導体基板は、素子領域と、その素子領域の周囲を取囲む終端領域を有している。終端領域には、素子領域の外側を一巡する複数の溝が形成されており、それら複数の溝の底面は、内周側の溝から外周側の溝に向かって、順に浅くなるように形成されている。そして、それら複数の溝の下方のそれぞれには、その周囲が第１導電型の第１半導体領域によって囲まれている第２導電型の第２半導体領域が形成されている。   The SiC semiconductor device disclosed by this specification has a semiconductor substrate made of silicon carbide. The semiconductor substrate has an element region and a termination region surrounding the element region. The termination region is formed with a plurality of grooves that circulate around the outside of the element region, and the bottom surfaces of the plurality of grooves are formed so as to become shallower in order from the inner circumferential groove toward the outer circumferential groove. ing. A second conductive type second semiconductor region is formed below each of the plurality of grooves, the periphery of which is surrounded by the first conductive type first semiconductor region.

上記の半導体装置では、終端領域の表面に形成された複数の溝の底面が内周側から外周側に向かって順に浅くなっている。このため、各溝の底面に第２導電型の不純物を同一の照射エネルギーで注入して第２半導体領域を形成すると、注入された不純物が熱拡散しなくても、それら第２半導体領域の深さは内周側から外周側に向かって順に浅くなる。その結果、第２半導体領域と第１半導体領域によって形成される空乏層は、内側から外側に向かって滑らかに形成されることとなる。これによって、電界集中が緩和され、高耐圧化を図ることができる。   In the above semiconductor device, the bottom surfaces of the plurality of grooves formed on the surface of the termination region become shallower in order from the inner peripheral side toward the outer peripheral side. For this reason, when the second semiconductor region is formed by implanting the second conductivity type impurity at the bottom surface of each groove with the same irradiation energy, the depth of the second semiconductor region can be increased even if the implanted impurity does not thermally diffuse. The depth becomes shallower from the inner circumference side toward the outer circumference side. As a result, the depletion layer formed by the second semiconductor region and the first semiconductor region is smoothly formed from the inside toward the outside. As a result, the electric field concentration is alleviated and a high breakdown voltage can be achieved.

上記のＳｉＣ半導体装置は、複数の溝の幅が、内周側の溝から外周側の溝に向かって、順に狭くなるように形成されていてもよい。半導体基板にエッチングによって溝を形成すると、溝の幅に応じて溝の深さが異なる。すなわち、溝の幅が広いと溝の深さが深くなり、溝の幅が狭いと溝の深さが浅くなる。したがって、終端領域に形成する複数の溝の幅を内周側から外周側に向かって順に狭くなるようにすると、同一のエッチング工程によってこれら複数の溝を形成することが可能となる。   Said SiC semiconductor device may be formed so that the width | variety of a some groove | channel may become narrow in order toward the groove | channel on the outer peripheral side from the groove | channel on the inner peripheral side. When a groove is formed in a semiconductor substrate by etching, the depth of the groove varies depending on the width of the groove. That is, if the groove width is wide, the groove depth becomes deep, and if the groove width is narrow, the groove depth becomes shallow. Therefore, if the width of the plurality of grooves formed in the termination region is reduced in order from the inner peripheral side to the outer peripheral side, the plurality of grooves can be formed by the same etching process.

上記のＳｉＣ半導体装置は、第２半導体領域のそれぞれの不純物濃度が同一であってもよい。上記の構成によれば、第２半導体領域のそれぞれの不純物濃度が変化しないため、同一の不純物注入工程で第２半導体領域を形成することができる。   In the SiC semiconductor device, the impurity concentrations of the second semiconductor regions may be the same. According to the above configuration, since the respective impurity concentrations of the second semiconductor region do not change, the second semiconductor region can be formed in the same impurity implantation step.

本明細書によって開示されるＳｉＣ半導体装置は、下記の方法で好適に製造することができる。すなわち、本明細書のＳｉＣ半導体装置の製造方法は、半導体基板上に酸化膜を形成する酸化膜形成工程と、酸化膜形成工程で形成された酸化膜のうち、複数の溝に対応する部分の酸化膜を除去する酸化膜除去工程と、酸化膜除去工程後に、半導体基板の上方から半導体基板に不純物イオンを注入する工程を備えている。そして、酸化膜除去工程では、複数の溝に対応する部分の酸化膜をオーバーエッチングすることで、半導体基板に底面の高さが内周側から外周側に向かって順に浅くなる複数の溝が形成される。   The SiC semiconductor device disclosed by this specification can be suitably manufactured by the following method. That is, the manufacturing method of the SiC semiconductor device of the present specification includes an oxide film forming step of forming an oxide film on a semiconductor substrate, and an oxide film formed in the oxide film forming step of portions corresponding to a plurality of grooves. An oxide film removing step for removing the oxide film and a step of implanting impurity ions into the semiconductor substrate from above the semiconductor substrate after the oxide film removing step are provided. Then, in the oxide film removal step, a plurality of grooves are formed in the semiconductor substrate so that the height of the bottom surface becomes shallower from the inner periphery side toward the outer periphery side by over-etching portions of the oxide film corresponding to the plurality of grooves. Is done.

上記のＳｉＣ半導体装置では、複数のガードリングの幅が内周側から外周側に向かって順に狭くされているため、半導体基板上に形成された酸化膜をオーバーエッチングすることで、半導体基板の終端領域に内周側から外周側向かって順に浅くなる複数の溝を形成することができる。したがって、深さの異なる溝を形成するために複数のエッチング工程を行う必要はなく、少ない工程で本明細書のＳｉＣ半導体装置を製造することができる。   In the SiC semiconductor device described above, since the width of the plurality of guard rings is narrowed in order from the inner peripheral side to the outer peripheral side, the oxide film formed on the semiconductor substrate is over-etched, thereby terminating the semiconductor substrate. A plurality of grooves that become shallower in order from the inner peripheral side to the outer peripheral side can be formed in the region. Therefore, it is not necessary to perform a plurality of etching steps to form grooves having different depths, and the SiC semiconductor device of this specification can be manufactured with a small number of steps.

実施例に係るＳｉＣ半導体装置の平面図。The top view of the SiC semiconductor device which concerns on an Example. 図１のII−II断面図。II-II sectional drawing of FIG. 図１のＳｉＣ半導体装置の終端領域における空乏層の形状を示す模式図。The schematic diagram which shows the shape of the depletion layer in the termination | terminus area | region of the SiC semiconductor device of FIG. 実施例に係るＳｉＣ半導体装置の製造工程の一例を示す図。The figure which shows an example of the manufacturing process of the SiC semiconductor device which concerns on an Example.

以下に説明する実施例の主要な特徴を最初に整理する。
（特徴１）終端領域には、半導体基板の表面に臨む範囲に第１導電型の第１半導体領域が形成されている。第１半導体領域の表面には、複数の溝が形成されている。各溝の下方に形成される第２半導体領域は、第１半導体領域によって囲まれている。
（特徴２）半導体基板上に形成された酸化膜上にレジスト膜を形成し、そのレジスト膜に複数の溝を形成するためのパターンを形成する。レジスト膜に形成するパターンの幅は、半導体基板の内周側から外周側に向かって狭くなるように形成されている。 The main features of the embodiments described below are first organized.
(Feature 1) In the termination region, a first semiconductor region of the first conductivity type is formed in a range facing the surface of the semiconductor substrate. A plurality of grooves are formed on the surface of the first semiconductor region. The second semiconductor region formed below each trench is surrounded by the first semiconductor region.
(Feature 2) A resist film is formed on an oxide film formed on a semiconductor substrate, and a pattern for forming a plurality of grooves is formed in the resist film. The width of the pattern formed on the resist film is formed so as to become narrower from the inner peripheral side to the outer peripheral side of the semiconductor substrate.

以下、本発明の一実施例を、図１〜４を参照して説明する。図１，２に示すように、本実施例の半導体装置１０は、ＳｉＣを材料とする半導体基板２５に形成されている。   Hereinafter, an embodiment of the present invention will be described with reference to FIGS. As shown in FIGS. 1 and 2, the semiconductor device 10 of this embodiment is formed on a semiconductor substrate 25 made of SiC.

図２に示すように、半導体基板２５は、ウェハ基板２４と、ウェハ基板２４上に積層されたドリフト層２６を備えている。ウェハ基板２４は、半導体基板２５の裏面側に配置されている。ウェハ基板２４は、例えば、ｎ型であり、その不純物濃度は１．０×１０１８ｃｍ−３〜１．０×１０２１ｃｍ−３程度の濃度とされている。ウェハ基板２４には、例えば、ｎ型の４Ｈ−ＳｉＣ基板（不純物濃度；５．０×１０１８ｃｍ−３，膜厚３５０μｍ）を用いることができる。 As shown in FIG. 2, the semiconductor substrate 25 includes a wafer substrate 24 and a drift layer 26 stacked on the wafer substrate 24. The wafer substrate 24 is disposed on the back side of the semiconductor substrate 25. The wafer substrate 24 is, for example, n-type and has an impurity concentration of about 1.0 × 10 18 cm −3 to 1.0 × 10 21 cm −3 . As the wafer substrate 24, for example, an n-type 4H—SiC substrate (impurity concentration: 5.0 × 10 18 cm −3 , film thickness 350 μm) can be used.

ドリフト層２６は、半導体基板２５の表面側に配置されている。ドリフト層２６は、ｎ型であり、その不純物濃度はウェハ基板２４よりも薄くされている。ドリフト層２６の不純物濃度は、１．０×１０１５ｃｍ−３〜５．０×１０１６ｃｍ−３程度とすることができる。ドリフト層２６は、例えば、不純物濃度を５．０×１０１５ｃｍ−３、膜厚を１３μｍとすることができる。ドリフト層２６は、ウェハ基板２４上にエピタキシャル層を成長させることで形成することができる。 The drift layer 26 is disposed on the surface side of the semiconductor substrate 25. The drift layer 26 is n-type, and its impurity concentration is thinner than that of the wafer substrate 24. The impurity concentration of the drift layer 26 can be about 1.0 × 10 15 cm −3 to 5.0 × 10 16 cm −3 . For example, the drift layer 26 may have an impurity concentration of 5.0 × 10 15 cm −3 and a film thickness of 13 μm. The drift layer 26 can be formed by growing an epitaxial layer on the wafer substrate 24.

上述した半導体基板２５の裏面（ウェハ基板２４の裏面）の全面には、裏面電極２８が形成されている。裏面電極２８は、ウェハ基板２４とオーミック接触している。裏面電極２８は、例えば、Ｔｉ，Ｍｏ，Ｎｉ（ニッケル），Ｗ（タングステン）等により形成することができる。本実施例では、裏面電極２８をＮｉによって形成している。   A back electrode 28 is formed on the entire back surface of the semiconductor substrate 25 described above (the back surface of the wafer substrate 24). The back electrode 28 is in ohmic contact with the wafer substrate 24. The back electrode 28 can be formed of, for example, Ti, Mo, Ni (nickel), W (tungsten), or the like. In this embodiment, the back electrode 28 is made of Ni.

半導体基板２５の表面（ドリフト層２６の表面）には絶縁膜３２が形成されている。絶縁膜３２は、例えば、酸化シリコン（ＳｉＯ２）で形成することができる。絶縁膜３２には開口部３２ａが形成されている。開口部３２ａには、表面電極３０が形成されている。表面電極３０は、ドリフト層２６とショットキー接合するショットキー電極と、そのショットキー電極上に形成された配線電極によって構成されている。ショットキー電極は、例えば、Ｍｏ（モリブデン）もしくはＴｉ（チタン）もしくはＮｉ（ニッケル）によって形成することができる。配線電極は、例えば、Ａｌ（アルミニウム）等で形成することができる。表面電極３０の外周部と絶縁膜３２上には、パッシベーション膜３４が形成されている。パッシベーション膜３４は、例えば、ポリイミドによって形成することができる。 An insulating film 32 is formed on the surface of the semiconductor substrate 25 (the surface of the drift layer 26). The insulating film 32 can be formed of, for example, silicon oxide (SiO 2 ). An opening 32 a is formed in the insulating film 32. A surface electrode 30 is formed in the opening 32a. The surface electrode 30 is configured by a Schottky electrode that forms a Schottky junction with the drift layer 26 and a wiring electrode formed on the Schottky electrode. The Schottky electrode can be formed of, for example, Mo (molybdenum), Ti (titanium), or Ni (nickel). The wiring electrode can be made of, for example, Al (aluminum). A passivation film 34 is formed on the outer periphery of the surface electrode 30 and the insulating film 32. The passivation film 34 can be formed of polyimide, for example.

図１に示すように、半導体基板２５には、素子領域１２と、その素子領域１２を取り囲む終端領域１４が形成されている。素子領域１２には、ショットキーバリアダイオードが形成されている。ショットキーバリアダイオードは、裏面電極２８とウェハ基板２４とドリフト層２６と表面電極３０によって構成されている（図２参照）。終端領域１４には、４つのガードリング１６，１８，２０，２２が形成されている。各ガードリング１６，１８，２０，２２は、内周側から外周側に間隔を空けて配置されており、それぞれが素子領域１２を一巡している。   As shown in FIG. 1, an element region 12 and a termination region 14 surrounding the element region 12 are formed in the semiconductor substrate 25. A Schottky barrier diode is formed in the element region 12. The Schottky barrier diode includes a back electrode 28, a wafer substrate 24, a drift layer 26, and a front electrode 30 (see FIG. 2). Four guard rings 16, 18, 20, and 22 are formed in the termination region 14. The guard rings 16, 18, 20, and 22 are arranged with an interval from the inner peripheral side to the outer peripheral side, and each makes a round of the element region 12.

図２に示すように、終端領域１４では、ドリフト層２６の表面に複数の溝１７，１９，２１，２３が形成されている。これらの溝１７，１９，２１，２３の下方には、ｐ型の半導体領域（以下、ｐ型領域という）１６，１８，２０，２２が形成されている。このｐ型領域１６，１８，２０，２２によって、ガードリングが形成されている。   As shown in FIG. 2, in the termination region 14, a plurality of grooves 17, 19, 21, and 23 are formed on the surface of the drift layer 26. Below these grooves 17, 19, 21, 23, p-type semiconductor regions (hereinafter referred to as p-type regions) 16, 18, 20, 22 are formed. The p-type regions 16, 18, 20, and 22 form a guard ring.

溝１７，１９，２１，２３は、内周側から外周側に向かって間隔を空けて配置されており、それぞれが素子領域１２を一巡している。溝１７，１９，２１，２３の深さは、内周側の溝１７から外周側の溝２３に向かって、順に浅くなるように形成されている。溝１７，１９，２１，２３の深さは、例えば、０．０〜１．０μｍの範囲で適宜設定することができる。また、溝１７，１９，２１，２３の幅は、内周側の溝１７から外周側の溝２３に向かって、順に狭くなるように形成されている。溝１７，１９，２１，２３の幅は、例えば、０．５〜１００μｍの範囲で適宜設定することができる。溝１７，１９，２１，２３の間隔、深さ及び幅は、半導体装置１０に逆方向電圧が印加されたときの空乏層が所望の形状となるように適宜設定することができる。なお、溝１９，２１，２３内には、絶縁膜３２が配置されている。溝１７には、その内周側に表面電極３０（正確には、ショットキー電極）が配置され、その外周側に絶縁膜３２が配置されている。   The grooves 17, 19, 21, and 23 are arranged at intervals from the inner peripheral side to the outer peripheral side, and each of them makes a circuit around the element region 12. The depths of the grooves 17, 19, 21, and 23 are formed so as to become shallower in order from the inner circumferential side groove 17 toward the outer circumferential side groove 23. The depth of the grooves 17, 19, 21, and 23 can be appropriately set within a range of 0.0 to 1.0 μm, for example. Further, the widths of the grooves 17, 19, 21, and 23 are formed so as to gradually decrease from the inner circumferential side groove 17 toward the outer circumferential side groove 23. The widths of the grooves 17, 19, 21, and 23 can be appropriately set within a range of 0.5 to 100 μm, for example. The interval, depth, and width of the grooves 17, 19, 21, and 23 can be appropriately set so that the depletion layer has a desired shape when a reverse voltage is applied to the semiconductor device 10. An insulating film 32 is disposed in the grooves 19, 21, 23. In the groove 17, a surface electrode 30 (precisely, a Schottky electrode) is disposed on the inner peripheral side, and an insulating film 32 is disposed on the outer peripheral side.

ｐ型領域１６，１８，２０，２２は、溝１７，１９，２１，２３のそれぞれに対応して形成されている。ｐ型領域１６，１８，２０，２２の周囲は、ドリフト層２６によって囲まれている。ｐ型領域１６，１８，２０，２２も、内周側から外周側に向かって間隔を空けて配置され、それぞれが素子領域１２を一巡している。ｐ型領域１６，１８，２０，２２は、ドリフト層２６にｐ型の不純物イオン（例えば、アルミニウムイオン）を注入することによって形成することができる。各ｐ型領域１６，１８，２０，２２の不純物濃度は同一濃度とされている。ｐ型領域１６，１８，２０，２２の不純物濃度としては、１．０×１０１７ｃｍ−３〜１．０×１０２０ｃｍ−３程度とすることができる。本実施例では、４．０×１０１７ｃｍ−３としている。ｐ型領域１６，１８，２０，２２は、対応する溝１７，１９，２１，２３の底面から同一の深さ範囲に形成されている。溝１７，１９，２１，２３の底面の深さが内周側から外周側に向かって順に浅くなるため、ｐ型領域１６，１８，２０，２２のドリフト層２６の表面からの深さ方向の位置も、内周側から外周側に向かって順に浅くなっている。また、ｐ型領域１６，１８，２０，２２の幅は、対応する溝１７，１９，２１，２３の幅と同一とされている。このため、ｐ型領域１６，１８，２０，２２の幅は、内周側から外周側に向かって順に狭くなっている。ｐ型領域１６，１８，２０，２２の不純物濃度及び深さは、半導体装置１０に逆方向の電圧が印加されたときの空乏層が所望の形状となるように適宜設定することができる。なお、ｐ型領域１６は表面電極３０に接続され、ｐ型領域１８，２０，２２は絶縁膜３２によって表面電極３０から絶縁されている。 The p-type regions 16, 18, 20, and 22 are formed corresponding to the grooves 17, 19, 21, and 23, respectively. The periphery of the p-type regions 16, 18, 20, and 22 is surrounded by the drift layer 26. The p-type regions 16, 18, 20, and 22 are also arranged at intervals from the inner peripheral side to the outer peripheral side, and each makes a round of the element region 12. The p-type regions 16, 18, 20, and 22 can be formed by implanting p-type impurity ions (for example, aluminum ions) into the drift layer 26. The impurity concentrations of the p-type regions 16, 18, 20, and 22 are the same. The impurity concentration of the p-type regions 16, 18, 20, and 22 can be about 1.0 × 10 17 cm −3 to 1.0 × 10 20 cm −3 . In this embodiment, it is 4.0 × 10 17 cm −3 . The p-type regions 16, 18, 20 and 22 are formed in the same depth range from the bottom surfaces of the corresponding grooves 17, 19, 21 and 23. Since the depths of the bottom surfaces of the grooves 17, 19, 21, and 23 gradually decrease from the inner peripheral side toward the outer peripheral side, the depth direction from the surface of the drift layer 26 of the p-type regions 16, 18, 20, and 22 The position is also shallower from the inner circumference side toward the outer circumference side. The widths of the p-type regions 16, 18, 20, 22 are the same as the widths of the corresponding grooves 17, 19, 21, 23. For this reason, the widths of the p-type regions 16, 18, 20, and 22 are gradually reduced from the inner peripheral side toward the outer peripheral side. The impurity concentration and depth of the p-type regions 16, 18, 20, and 22 can be appropriately set so that the depletion layer has a desired shape when a reverse voltage is applied to the semiconductor device 10. The p-type region 16 is connected to the surface electrode 30, and the p-type regions 18, 20, and 22 are insulated from the surface electrode 30 by the insulating film 32.

上述した半導体装置１０では、表面電極（アノード電極）３０と裏面電極（カソード電極）２８の間に順バイアスが印加される（すなわち、裏面電極２８に印加される電圧より高い電圧が表面電極３０に印加される）と、表面電極３０から裏面電極２８に電流が流れる。一方、表面電極３０と裏面電極２８の間に逆バイアスが印加される（表面電極３０に印加される電圧より高い電圧が裏面電極２８に印加される）と、表面電極３０とドリフト層２６とのショットキー障壁によって、ドリフト層２６から表面電極３０へ向かう電流は流れない。また、逆バイアス時の終端領域１４では、ｐ型領域１６，１８，２０，２２とドリフト層２６とのｐｎ接合によって空乏層３６が形成される。ここで、ｐ型領域１６，１８，２０，２２は、その深さが内周側から外周側に向かって徐々に浅くなる。このため、図３に示すように、空乏層３６の境界は、内周側から外周側に向かって徐々にドリフト層２６の表面に向かうように滑らかに形成される。これによって、電界の集中を防ぐことができ、半導体装置１０の耐圧特性を向上することができる。   In the semiconductor device 10 described above, a forward bias is applied between the front electrode (anode electrode) 30 and the back electrode (cathode electrode) 28 (that is, a voltage higher than the voltage applied to the back electrode 28 is applied to the front electrode 30. Current) flows from the front electrode 30 to the back electrode 28. On the other hand, when a reverse bias is applied between the front electrode 30 and the back electrode 28 (a voltage higher than the voltage applied to the front electrode 30 is applied to the back electrode 28), the surface electrode 30 and the drift layer 26 Due to the Schottky barrier, no current flows from the drift layer 26 to the surface electrode 30. Further, in the termination region 14 at the time of reverse bias, a depletion layer 36 is formed by a pn junction between the p-type regions 16, 18, 20, 22 and the drift layer 26. Here, the depths of the p-type regions 16, 18, 20, and 22 gradually become shallower from the inner peripheral side toward the outer peripheral side. For this reason, as shown in FIG. 3, the boundary of the depletion layer 36 is smoothly formed so as to gradually go to the surface of the drift layer 26 from the inner peripheral side toward the outer peripheral side. Thereby, concentration of the electric field can be prevented, and the breakdown voltage characteristics of the semiconductor device 10 can be improved.

次に、上述した半導体装置１０を製造する方法の一例について、図４を参照しながら説明する。まず、図４（ａ）に示すように、４Ｈ−ＳｉＣのｎ型のウェハ基板２４（厚さ３５０μｍ，不純物純度：５．０×１０１８ｃｍ−３）を準備し、そのウェハ基板２４上にエピタキシャル成長によってドリフト層２６（不純物濃度５．０×１０１５ｃｍ−３、厚さ１３μｍ）を形成する。次いで、図４（ｂ）に示すように、化学蒸着法（ＣＶＤ法）によってドリフト層２６の表面に酸化膜３８（厚さ２．０μｍ）を堆積する。次いで、図４（ｃ）に示すように、スピンコート法等によって酸化膜３８の表面にレジスト膜４０（厚さ２．０μｍ）を形成する。 Next, an example of a method for manufacturing the above-described semiconductor device 10 will be described with reference to FIG. First, as shown in FIG. 4A, a 4H—SiC n-type wafer substrate 24 (thickness 350 μm, impurity purity: 5.0 × 10 18 cm −3 ) is prepared, and the wafer substrate 24 is formed on the wafer substrate 24. A drift layer 26 (impurity concentration: 5.0 × 10 15 cm −3 , thickness: 13 μm) is formed by epitaxial growth. Next, as shown in FIG. 4B, an oxide film 38 (thickness 2.0 μm) is deposited on the surface of the drift layer 26 by chemical vapor deposition (CVD). Next, as shown in FIG. 4C, a resist film 40 (thickness 2.0 μm) is formed on the surface of the oxide film 38 by spin coating or the like.

次いで、図４（ｄ）に示すように、フォトリソグラフィによってレジスト膜４０に溝１７，１９，２１，２３に対応するパターンをパターニングする。これによって、レジスト膜４０に、溝１７，１９，２１，２３に対応する開口部４２，４４，４６，４８が形成される。溝１７，１９，２１，２３の幅が内周側から外周側に向かって順に狭くなっているため、開口部４２，４４，４６，４８の幅も内周側から外周側に向かって順に狭くなっている。   Next, as shown in FIG. 4D, patterns corresponding to the grooves 17, 19, 21, and 23 are patterned in the resist film 40 by photolithography. As a result, openings 42, 44, 46, 48 corresponding to the grooves 17, 19, 21, 23 are formed in the resist film 40. Since the widths of the grooves 17, 19, 21, and 23 are narrowed in order from the inner peripheral side to the outer peripheral side, the widths of the openings 42, 44, 46, and 48 are also narrowed in order from the inner peripheral side to the outer peripheral side. It has become.

次いで、レジスト膜４０をエッチングマスクとして、反応性イオンエッチング（ＲＩＥ）により、開口部４２，４４，４６，４８に露出している酸化膜３８を除去する。この際、酸化膜３８をオーバーエッチングすることによって、ドリフト層２６の一部も除去する。これによって、図４（ｅ）に示すように、開口部４２，４４，４６，４８に対応する溝１７，１９，２１，２３がドリフト層２６に形成される。ここで、開口部４２，４４，４６，４８の開口幅が異なるため、開口部４２，４４，４６，４８毎に反応性ガスの回り込み量が変化し、エッチングレートも変化する。具体的には、開口部の幅が大きいほどエッチングレートが大きくなるため、エッチングレートは開口部４２から開口部４８に向かって順に小さくなる。従って、開口部４２に対応する溝１７の深さが最も深くなり、以下、開口部４４に対応する溝１９、開口部４６に対応する溝２１、開口部４８に対応する溝２３と、その深さが浅くなる。なお、反応性イオンエッチングには、ＣＨＦ３あるいはＣＦ４等からなる反応性ガスを用いることができる。 Next, the oxide film 38 exposed in the openings 42, 44, 46, and 48 is removed by reactive ion etching (RIE) using the resist film 40 as an etching mask. At this time, part of the drift layer 26 is also removed by over-etching the oxide film 38. As a result, as shown in FIG. 4 (e), grooves 17, 19, 21, 23 corresponding to the openings 42, 44, 46, 48 are formed in the drift layer 26. Here, since the opening widths of the openings 42, 44, 46, and 48 are different, the amount of wraparound of the reactive gas is changed for each of the openings 42, 44, 46, and 48, and the etching rate is also changed. Specifically, since the etching rate increases as the width of the opening increases, the etching rate decreases in order from the opening 42 toward the opening 48. Accordingly, the depth of the groove 17 corresponding to the opening 42 is the deepest, and hereinafter, the groove 19 corresponding to the opening 44, the groove 21 corresponding to the opening 46, the groove 23 corresponding to the opening 48, and the depth thereof. Becomes shallower. For reactive ion etching, a reactive gas composed of CHF 3 or CF 4 can be used.

次いで、図４（ｆ）に示すように、レジスト膜４０を除去し、しかる後、酸化膜３８をマスクとして、ドリフト層２６の全面にアルミニウムイオンを一様に注入する。酸化膜３８が形成されている領域では、酸化膜３８中でアルミニウムイオンが停止し、ドリフト層２６にはアルミニウムイオンが注入されない。一方、酸化膜３８が除去された領域では、ドリフト層２６にアルミニウムイオンが注入される。したがって、ドリフト層２６に形成された溝１７，１９，２１，２３の底部にアルミニウムイオンが注入される。なお、アルミニウムイオンをドリフト層２６に照射するエネルギーは一様であるため、各溝１７，１９，２１，２３の下方に注入されるアルミニウムイオンの深さ方向の位置は同一となる。ただし、溝１７，１９，２１，２３の深さが内周側から外周側に向けて浅くなっているため、アルミニウムイオンが注入された領域も内周側から外周側に向けて浅くなる。次いで、残っている酸化膜３８をウェットエッチングで除去し、１０００℃以上の温度（例えば、１６００℃）で活性化処理を行う。これによって、アルミニウムイオンが注入された領域がｐ型の半導体領域（ｐ型領域１６，１８，２０，２２）となる。アルミニウムイオンが注入された領域の深さが内周側から外周側に向けて浅くなるため、ｐ型領域１６，１８，２０，２２の深さも内周側から外周側に向けて浅くなる。   Next, as shown in FIG. 4F, the resist film 40 is removed, and then aluminum ions are uniformly implanted into the entire surface of the drift layer 26 using the oxide film 38 as a mask. In the region where the oxide film 38 is formed, aluminum ions are stopped in the oxide film 38 and aluminum ions are not implanted into the drift layer 26. On the other hand, aluminum ions are implanted into the drift layer 26 in the region where the oxide film 38 has been removed. Accordingly, aluminum ions are implanted into the bottoms of the grooves 17, 19, 21, 23 formed in the drift layer 26. Since the energy for irradiating the drift layer 26 with aluminum ions is uniform, the positions in the depth direction of the aluminum ions implanted below the grooves 17, 19, 21, 23 are the same. However, since the depths of the grooves 17, 19, 21, and 23 are shallower from the inner peripheral side toward the outer peripheral side, the region into which the aluminum ions are implanted also decreases from the inner peripheral side toward the outer peripheral side. Next, the remaining oxide film 38 is removed by wet etching, and an activation process is performed at a temperature of 1000 ° C. or higher (for example, 1600 ° C.). Thus, the region into which the aluminum ions are implanted becomes a p-type semiconductor region (p-type regions 16, 18, 20, and 22). Since the depth of the region into which the aluminum ions are implanted becomes shallower from the inner peripheral side toward the outer peripheral side, the depths of the p-type regions 16, 18, 20, and 22 also decrease from the inner peripheral side toward the outer peripheral side.

次いで、図４（ｇ）に示すように、スパッタ装置を用いてウェハ基板２４の裏面にニッケル層を成膜し、そのＮｉ層を８００℃以上の温度（例えば、１０００℃）のアニール処理によりシリサイド化する。これによって、ウェハ基板２４の裏面に裏面電極２８を形成する。次いで、ドリフト層２６の表面全体（溝１７，１９，２１，２３の内部を含む）に絶縁膜３２を形成し、その絶縁膜３２に開口部３２ａを形成する。次いで、その開口部３２ａに露出するドリフト層２６の表面に、真空蒸着装置を用いてショットキー電極（モリブデン）を成膜し、そのショットキー電極上にアルミニウム電極を成膜する。これによって、表面電極３０が形成される。最後に、表面電極３０の外周部と絶縁膜３２の上部にポリイミドからなるパッシベーション膜３４を形成する。   Next, as shown in FIG. 4G, a nickel layer is formed on the back surface of the wafer substrate 24 using a sputtering apparatus, and the Ni layer is silicided by annealing at a temperature of 800 ° C. or higher (eg, 1000 ° C.). Turn into. Thereby, the back electrode 28 is formed on the back surface of the wafer substrate 24. Next, an insulating film 32 is formed on the entire surface of the drift layer 26 (including the inside of the grooves 17, 19, 21, and 23), and an opening 32 a is formed in the insulating film 32. Next, a Schottky electrode (molybdenum) is formed on the surface of the drift layer 26 exposed in the opening 32a by using a vacuum evaporation apparatus, and an aluminum electrode is formed on the Schottky electrode. Thereby, the surface electrode 30 is formed. Finally, a passivation film 34 made of polyimide is formed on the outer peripheral portion of the surface electrode 30 and the insulating film 32.

上述したように本実施例の半導体装置１０では、終端領域１４に溝幅の異なる複数の溝１７，１９，２１，２３を形成する。このため、１回のエッチング工程によって、溝深さが異なる複数の溝１７，１９，２１，２３を形成することができる。また、溝深さの異なる複数の溝１７，１９，２１，２３の底面にアルミニウムイオンを注入してｐ型領域１６，１８，２０，２２を形成するため、深さの異なるｐ型領域１６，１８，２０，２２を１回のイオン注入工程で形成することができる。したがって、１回のエッチング工程と１回のイオン注入工程によって、内周側から外周側に向かって順に浅くなるｐ型領域（ガードリング）１６，１８，２０，２２を形成することができる。これによって、工程を増加させることなく、半導体装置１０の耐圧特性を向上することができる。   As described above, in the semiconductor device 10 of this embodiment, the plurality of grooves 17, 19, 21, and 23 having different groove widths are formed in the termination region 14. Therefore, a plurality of grooves 17, 19, 21, and 23 having different groove depths can be formed by one etching process. Further, since the p-type regions 16, 18, 20, 22 are formed by implanting aluminum ions into the bottom surfaces of the plurality of grooves 17, 19, 21, 23 having different groove depths, the p-type regions 16, 18, 20, and 22 can be formed by one ion implantation process. Therefore, p-type regions (guard rings) 16, 18, 20, and 22 that become shallower in order from the inner peripheral side to the outer peripheral side can be formed by one etching step and one ion implantation step. As a result, the breakdown voltage characteristics of the semiconductor device 10 can be improved without increasing the number of steps.

最後に、上記の実施例の構成と請求項の対応関係を記載しておく。ウェハ基板２４とドリフト層２６が「半導体基板」に対応し、ドリフト層２６が「第１半導体領域」に対応し、ｐ型領域１６，１８，２０，２２が「第２半導体領域」に対応する。   Finally, the correspondence between the configuration of the above embodiment and the claims is described. Wafer substrate 24 and drift layer 26 correspond to “semiconductor substrate”, drift layer 26 corresponds to “first semiconductor region”, and p-type regions 16, 18, 20, and 22 correspond to “second semiconductor region”. .

以上、本発明の具体例を詳細に説明したが、これらは例示にすぎず、特許請求の範囲を限定するものではない。特許請求の範囲に記載の技術には、以上に例示した具体例を様々に変形、変更したものが含まれる。例えば、上述した実施例の半導体装置１０では、素子領域１２にショットキーバリアダイオードが形成されていたが、本願の技術はこのような例に限られない。本願の技術は、ガードリングを備えることができる種々の半導体装置に適用することができ、例えば、素子領域にはＭＯＳＦＥＴ，ＩＧＢＴ等を形成することができる。また、上述した実施例では、溝およびガードリングをそれぞれ４つ備えていたが、溝およびガードリングの数に制限はなく、半導体装置に求められる耐圧特性に応じて適宜変更することができる。   Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. For example, in the semiconductor device 10 of the above-described embodiment, the Schottky barrier diode is formed in the element region 12, but the technique of the present application is not limited to such an example. The technology of the present application can be applied to various semiconductor devices that can include a guard ring. For example, MOSFETs, IGBTs, and the like can be formed in the element region. In the above-described embodiment, four grooves and guard rings are provided. However, the number of grooves and guard rings is not limited, and can be appropriately changed according to the breakdown voltage characteristics required for the semiconductor device.

また、本明細書または図面に説明した技術要素は、単独であるいは各種の組み合わせによって技術的有用性を発揮するものであり、出願時の請求項記載の組み合わせに限定されるものではない。また、本明細書または図面に例示した技術は、複数目的を同時に達成するものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。   Further, the technical elements described in the present specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

１０ 半導体装置、１２ 素子領域、１４ 終端領域、１６，１８，２０，２２ ｐ型領域、１７，１９，２１，２３ 溝、２４ ウェハ基板、２５ 半導体基板、２６ ドリフト層、２８ 裏面電極、３０ 表面電極、３２ 絶縁膜、３２ａ 開口部、３４ パッシベーション膜、３６ 空乏層、３８ 酸化膜、４０ レジスト膜、４２，４４，４６，４８開口部   DESCRIPTION OF SYMBOLS 10 Semiconductor device, 12 Element area | region, 14 Termination area | region, 16, 18, 20, 22 p-type area | region, 17, 19, 21, 23 groove | channel, 24 wafer substrate, 25 semiconductor substrate, 26 drift layer, 28 back surface electrode, 30 surface Electrode, 32 insulating film, 32a opening, 34 passivation film, 36 depletion layer, 38 oxide film, 40 resist film, 42, 44, 46, 48 opening

Claims (4)

炭化珪素を材料とする半導体基板を有するＳｉＣ半導体装置であり、
半導体基板は、素子領域と、その素子領域の周囲を取囲む終端領域を有しており、
その終端領域には、素子領域の外側を一巡する複数の溝が形成されており、
それら複数の溝の底面は、内周側の溝から外周側の溝に向かって、順に浅くなるように形成されており、
それら複数の溝の下方のそれぞれには、その周囲が第１導電型の第１半導体領域によって囲まれている第２導電型の第２半導体領域が形成されていることを特徴とするＳｉＣ半導体装置。 A SiC semiconductor device having a semiconductor substrate made of silicon carbide,
The semiconductor substrate has an element region and a termination region surrounding the periphery of the element region.
In the termination region, there are formed a plurality of grooves that go around the outside of the element region,
The bottom surfaces of the plurality of grooves are formed so as to become shallower in order from the inner circumferential groove toward the outer circumferential groove,
A SiC semiconductor device having a second conductivity type second semiconductor region surrounded by the first conductivity type first semiconductor region is formed below each of the plurality of grooves. . 前記複数の溝の幅は、内周側の溝から外周側の溝に向かって、順に狭くなるように形成されていることを特徴とする請求項１に記載のＳｉＣ半導体装置。   2. The SiC semiconductor device according to claim 1, wherein the width of the plurality of grooves is formed so as to become narrower in order from an inner circumferential groove toward an outer circumferential groove. 前記第２半導体領域のそれぞれの不純物濃度が同一であることを特徴とする請求項２に記載のＳｉＣ半導体装置。   The SiC semiconductor device according to claim 2, wherein the impurity concentration of each of the second semiconductor regions is the same. 炭化珪素を材料とする半導体基板を有しており、その半導体基板には、素子領域と、その素子領域の周囲を取囲む終端領域が形成されており、その終端領域には、素子領域の外側を一巡する複数の溝が形成されており、その複数の溝は、その幅が内周側の溝から外周側の溝に向かって順に狭くなると共にその底面が内周側の溝から外周側の溝に向かって順に浅くなるように形成されており、それら複数の溝の下方のそれぞれには、その周囲が第１導電型の第１半導体領域によって囲まれている第２導電型の第２半導体領域が形成されているＳｉＣ半導体装置を製造する製造方法であって、
半導体基板上に酸化膜を形成する酸化膜形成工程と、
酸化膜形成工程で形成された酸化膜のうち、前記複数の溝に対応する部分の酸化膜を除去する酸化膜除去工程と、
酸化膜除去工程後、半導体基板の上方から半導体基板に不純物イオンを注入する工程と、を備えており、
前記酸化膜除去工程では、前記複数の溝に対応する部分の酸化膜をオーバーエッチングすることで、半導体基板に底面の高さが内周側から外周側に向かって順に浅くなる複数の溝が形成されることを特徴とするＳｉＣ半導体装置の製造方法。 It has a semiconductor substrate made of silicon carbide, and the semiconductor substrate is formed with an element region and a termination region surrounding the element region, and the termination region is formed outside the element region. A plurality of grooves are formed, and the width of the plurality of grooves decreases in order from the inner circumferential groove toward the outer circumferential groove, and the bottom surface of the inner circumferential groove extends from the outer circumferential groove. A second semiconductor of the second conductivity type is formed so as to become shallower in order toward the trench, and the periphery of each of the plurality of trenches is surrounded by the first semiconductor region of the first conductivity type. A manufacturing method for manufacturing a SiC semiconductor device in which a region is formed,
An oxide film forming step of forming an oxide film on the semiconductor substrate;
Of the oxide film formed in the oxide film forming step, an oxide film removing step of removing a portion of the oxide film corresponding to the plurality of grooves,
And a step of implanting impurity ions into the semiconductor substrate from above the semiconductor substrate after the oxide film removing step,
In the oxide film removing step, a plurality of grooves are formed in the semiconductor substrate so that the height of the bottom surface becomes shallower from the inner periphery side toward the outer periphery side by over-etching portions of the oxide film corresponding to the plurality of grooves. A method of manufacturing a SiC semiconductor device, wherein:
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