JPH07142713A - Semiconductor device and its production - Google Patents
Semiconductor device and its productionInfo
- Publication number
- JPH07142713A JPH07142713A JP5160874A JP16087493A JPH07142713A JP H07142713 A JPH07142713 A JP H07142713A JP 5160874 A JP5160874 A JP 5160874A JP 16087493 A JP16087493 A JP 16087493A JP H07142713 A JPH07142713 A JP H07142713A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- main surface
- semiconductor region
- electric field
- type layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 143
- 238000004519 manufacturing process Methods 0.000 title description 13
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 239000012535 impurity Substances 0.000 claims description 27
- 230000002829 reductive effect Effects 0.000 claims description 7
- 239000011810 insulating material Substances 0.000 claims 3
- 230000005684 electric field Effects 0.000 abstract description 67
- 230000000670 limiting effect Effects 0.000 abstract description 54
- 230000015556 catabolic process Effects 0.000 abstract description 26
- 150000002500 ions Chemical class 0.000 abstract description 3
- 238000010276 construction Methods 0.000 abstract 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 20
- 229910052814 silicon oxide Inorganic materials 0.000 description 20
- 230000004048 modification Effects 0.000 description 17
- 238000012986 modification Methods 0.000 description 17
- 238000000034 method Methods 0.000 description 11
- 238000005530 etching Methods 0.000 description 10
- 230000008859 change Effects 0.000 description 8
- 230000007423 decrease Effects 0.000 description 8
- 230000000694 effects Effects 0.000 description 8
- 230000002093 peripheral effect Effects 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- 238000003860 storage Methods 0.000 description 8
- 230000000903 blocking effect Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 229920001721 polyimide Polymers 0.000 description 7
- 239000009719 polyimide resin Substances 0.000 description 7
- 239000000463 material Substances 0.000 description 5
- 230000002441 reversible effect Effects 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 230000009467 reduction Effects 0.000 description 4
- 238000009826 distribution Methods 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000006698 induction Effects 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- -1 for example Chemical compound 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000013585 weight reducing agent Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、高耐圧半導体装置に係
り、特に阻止特性の経時変化に対して非常に強い耐性を
有する半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high breakdown voltage semiconductor device, and more particularly to a semiconductor device having a very strong resistance to a change in blocking characteristic over time.
【０００２】[0002]
【従来の技術】ＩＧＢＴ（Insulated Gate Bipolar Tra
nsistor），ＧＴＯ（Gate Turn OffThyristor），ＳＩ
(Static Induction）サイリスタ，サイリスタ等の高耐
圧大電力半導体素子において、阻止特性の経時変化に対
する耐性の改善への要求が強い。特にＩＧＢＴは、元来
このような要求には不向きとされている浅い接合構造を
持つ素子であるが、電源電圧が数ｋＶ級の用途への適用
も期待されており、阻止特性の高信頼化は重要な課題で
ある。2. Description of the Related Art IGBT (Insulated Gate Bipolar Tra
nsistor), GTO (Gate Turn OffThyristor), SI
(Static Induction) In high-voltage high-power semiconductor elements such as thyristors and thyristors, there is a strong demand for improvement in resistance to changes in blocking characteristics over time. In particular, the IGBT is an element having a shallow junction structure that is originally unsuitable for such requirements, but it is also expected to be applied to applications with a power supply voltage of several kV class, and the blocking characteristics are highly reliable. Is an important issue.
【０００３】一般に、ＩＧＢＴは高耐圧を得るため複数
個の電界制限リングと呼ばれる環状の領域が、チップ周
辺部に主接合を取り囲むように形成される。電界制限リ
ングは、阻止時にチップ周辺部の電界分布を均等化する
ことで、低い電圧での局部的な高電界の発生による降伏
をなくする働きをする。この技術により主接合が浅くと
もｋＶオーダの初期耐圧を得ることができる。しかしな
がら、実用化に際しては初期耐圧の達成に加えて、耐圧
の経時変化を許容範囲に抑える必要がある。この経時変
化は、長時間の高温強電界の付与条件下で、チップの封
入材のチップ近傍にまで可動イオンが侵入したり、封入
材が分極して素子外部に電荷が発生し、その電荷の作用
の結果素子内部の電界分布が変化することにより生じ
る。このような、不本意な電荷による悪影響を考慮した
従来技術が、Proceedings of Inte-rnational Symposiu
m on Power Semiconductor Devices & ICsのｐｐ８６−
ｐｐ９０に示されている。電界制限リングで挟まれた領
域の表面部に高濃度層を設け、この高濃度層により半導
体装置外部の電荷の変化が半導体基体内におよぼす影響
を小さくするものである。Generally, in order to obtain a high breakdown voltage, an IGBT is formed with a plurality of annular regions called electric field limiting rings surrounding the main junction in the peripheral portion of the chip. The electric field limiting ring functions to eliminate the breakdown due to the local generation of a high electric field at a low voltage by equalizing the electric field distribution around the chip at the time of blocking. With this technique, an initial breakdown voltage on the order of kV can be obtained even if the main junction is shallow. However, in practical use, in addition to achieving the initial withstand voltage, it is necessary to suppress the change in withstand voltage over time within an allowable range. This change with time is due to the fact that, under the condition of applying a high-temperature strong electric field for a long time, mobile ions penetrate to the vicinity of the chip of the encapsulating material of the chip, or the encapsulating material is polarized to generate electric charges outside the element. This is caused by a change in the electric field distribution inside the element as a result of the action. Proceedings of Inte-rnational Symposiu is a conventional technology that takes into consideration the adverse effects of such unwanted charges.
m on Power Semiconductor Devices & ICs pp86-
It is shown in pp90. A high-concentration layer is provided on the surface of the region sandwiched by the electric field limiting rings, and the high-concentration layer reduces the influence of changes in the charges outside the semiconductor device on the semiconductor substrate.
【０００４】[0004]
【発明が解決しようとする課題】使用条件が厳しくなる
と、外部発生電荷は多くなる。この影響で、半導体基体
の表面部に形成される蓄積層の電子濃度が初期状態の電
子濃度を大きく超える。これにより等価的に電界制限リ
ング間の間隔は大きくなり、装置の耐圧は低下する。ま
た、蓄積層の電子濃度が大きくなるに伴い、電界制限リ
ングと隣接層間の接合部における電界集中による耐圧低
下が問題となる。更に、電界制限リングの隣接層の不純
物量を多くすれば、蓄積層による電子濃度の増加割合は
小さくできるが、電界制限リングと隣接層間の接合部に
おける電界集中による耐圧低下の影響が厳しくなり、初
期耐圧を得ることが困難になる。When the conditions of use become strict, the amount of externally generated charges increases. Due to this effect, the electron concentration of the storage layer formed on the surface of the semiconductor substrate greatly exceeds the electron concentration in the initial state. This equivalently increases the distance between the electric field limiting rings and lowers the breakdown voltage of the device. Further, as the electron concentration in the storage layer increases, the breakdown voltage decreases due to electric field concentration at the junction between the electric field limiting ring and the adjacent layers. Furthermore, if the amount of impurities in the adjacent layer of the electric field limiting ring is increased, the rate of increase in electron concentration due to the storage layer can be reduced, but the influence of the breakdown voltage reduction due to the electric field concentration at the junction between the electric field limiting ring and the adjacent layer becomes severe, It becomes difficult to obtain the initial breakdown voltage.
【０００５】本発明の目的は、従来技術のレベルを超え
た更なる高信頼化を達成するための電界制限リングを有
する半導体装置を与えることである。An object of the present invention is to provide a semiconductor device having an electric field limiting ring for achieving higher reliability beyond the level of the prior art.
【０００６】[0006]
【課題を解決するための手段】上記目的を達成するため
の手段は以下の通りである。Means for achieving the above object are as follows.
【０００７】第一の手段は、隣接する電界制限リングの
間の間隔が最も小さくなる位置が、半導体基体の主表面
部以外に存在するような構造とすることである。The first means is to have a structure in which the position where the distance between the adjacent electric field limiting rings is the smallest exists outside the main surface portion of the semiconductor substrate.
【０００８】第二の手段は、電界制限リングが半導体基
体の主表面に露出しない構造とすることである。The second means is to have a structure in which the electric field limiting ring is not exposed on the main surface of the semiconductor substrate.
【０００９】第一，第二の手段の具体的な一例として
は、半導体基体の主表面部に溝を設け、その溝の底部に
電界制限リングを設け、電界制限リングが溝の開口部を
有する面、即ち主表面には露出しない構造とすることで
ある。As a concrete example of the first and second means, a groove is provided in the main surface of the semiconductor substrate, an electric field limiting ring is provided at the bottom of the groove, and the electric field limiting ring has an opening of the groove. The structure is not exposed on the surface, that is, the main surface.
【００１０】第三の手段は、第一，第二の手段に加え、
半導体基体の主表面の周辺領域に、複数個の高濃度領域
を付加することである。この高濃度領域と電界制限リン
グは、低濃度のｎ−層で隔離しておくのが好ましい。ま
た、高濃度領域の単位面積当たりの不純物量を１０13／
cm2 以上とするのが好ましく、ｎ型，ｐ型のどちらでも
良い。The third means is, in addition to the first and second means,
A plurality of high-concentration regions are added to the peripheral region of the main surface of the semiconductor substrate. The high concentration region and the electric field limiting ring are preferably separated by a low concentration n-layer. Further, the amount of impurities per unit area in the high concentration region is 10 13 /
It is preferable that the size is cm 2 or more, and either n-type or p-type may be used.
【００１１】第三の手段の具体的な一例としては、第
一，第二の手段の具体的な一例の構造に加え、周辺領域
の溝の開口部を有する面、即ち主表面に複数個の高濃度
領域を付加することである。これらの高濃度領域と電界
制限リングは、低濃度のｎ−層で隔離しておくのが好ま
しい。また、高濃度領域の単位面積当たりの不純物量を
１０13／cm2 以上とするのが好ましく、ｎ型，ｐ型のど
ちらでも良い。As a concrete example of the third means, in addition to the structure of the concrete example of the first and second means, a plurality of surfaces are provided on the surface having the opening of the groove in the peripheral region, that is, the main surface. A high-concentration region is added. It is preferable that the high concentration region and the electric field limiting ring are separated by a low concentration n-layer. Further, the amount of impurities per unit area of the high concentration region is preferably 10 13 / cm 2 or more, and either n-type or p-type may be used.
【００１２】次に上記手段を実現する製法の一つは、半
導体基体に溝を形成する工程，その溝の底部に不純物を
導入し電界制限リングを形成する工程及び溝を充填する
工程を含むものである。Next, one of the manufacturing methods for realizing the above means includes a step of forming a groove in the semiconductor substrate, a step of introducing an impurity into the bottom of the groove to form an electric field limiting ring, and a step of filling the groove. .
【００１３】他の製法としては、半導体基体内部に不純
物を導入する工程，この不純物導入層上に半導体層をエ
ピタキシャル成長させ、この不純物導入層による電界制
限リングを形成する工程を含むものである。Another manufacturing method includes a step of introducing impurities into the semiconductor substrate, a step of epitaxially growing a semiconductor layer on the impurity introduced layer, and forming an electric field limiting ring by the impurity introduced layer.
【００１４】更に他の製法としては、半導体基体内部に
高加速イオン注入法により不純物を導入する工程，この
不純物導入層による電界制限リングを形成する工程を含
むものである。Still another manufacturing method includes a step of introducing impurities into the inside of the semiconductor substrate by a highly accelerated ion implantation method, and a step of forming an electric field limiting ring by this impurity introduction layer.
【００１５】[0015]
【作用】上記の構成にすれば、隣接する電界制限リング
の間の間隔が、半導体基体の主表面部から離れた個所で
最も小さくなるような構造となっているため、半導体装
置の長期使用により半導体基体外に発生した電荷の作用
で表面部に蓄積層が形成されても、隣接する電界制限リ
ング間の間隔が最も小さい部分における電子濃度の変化
を防止することができる。このため、等価的な電界制限
リング間の間隔の増加はなくなり、耐圧の低下を防止で
きる。According to the above structure, the distance between the adjacent electric field limiting rings is such that the distance between the adjacent electric field limiting rings is the smallest at the position away from the main surface of the semiconductor substrate. Even if the storage layer is formed on the surface due to the action of the charges generated outside the semiconductor substrate, it is possible to prevent the change in the electron concentration in the portion where the distance between the adjacent electric field limiting rings is smallest. For this reason, the equivalent distance between the electric field limiting rings does not increase, and the breakdown voltage can be prevented from lowering.
【００１６】また、電界制限リングが半導体基体の主表
面に露出しない構造とすることに加えて、主表面部に形
成される蓄積層と電界制限リングを隔離することによ
り、隔離部で電圧を分担することになり、両者の接触部
付近で起きる電界集中による耐圧低下を排除することが
可能になる。In addition to the structure in which the electric field limiting ring is not exposed on the main surface of the semiconductor substrate, the electric field limiting ring is isolated from the storage layer formed on the main surface so that the isolation portion shares the voltage. As a result, it becomes possible to eliminate the decrease in breakdown voltage due to the electric field concentration that occurs in the vicinity of the contact portion between the two.
【００１７】更に、半導体基体の主表面の周辺領域に複
数個の高濃度領域を付加する構造にすれば、主表面部に
蓄積層が形成されても主表面部のキャリア濃度の変化の
割合は小さくなり、等価的な電界制限リング間の間隔の
増加は更に小さくなって、耐圧の低下を防止できる。Further, by adopting a structure in which a plurality of high-concentration regions are added to the peripheral region of the main surface of the semiconductor substrate, even if an accumulation layer is formed on the main surface part, the rate of change in carrier concentration on the main surface part is small. As a result, the increase in the distance between the equivalent electric field limiting rings becomes smaller and the breakdown voltage can be prevented from lowering.
【００１８】[0018]
【実施例】以下、本発明半導体装置を実施例として示し
た図面を用いて詳細に説明する。図１は、本発明半導体
装置の一実施例を示す平面パターン図（ａ）及び周辺領
域の断面図（ｂ）である。図において、１は一対の主表
面１１，１２を有する半導体基体で、一方の主表面１１
に隣接するｐ型層１３，ｐ型層１３及び他方の主表面１
２に隣接しそれより低不純物濃度を有するｎ型層１４，
他方の主表面１２の中央部において他方の主表面１２か
らｎ型層１４内に延びるｎ型層１４より高不純物濃度を
有するｐ型層１５，他方の主表面１２の周辺部に形成さ
れたｐ型層１５を所定間隔を有して包囲する複数個の環
状溝１２ａ，各環状溝１２ａの底部及びその近傍に隣接
してｎ型層１４内に延びる環状のｐ型層１６，ｐ型層１
５と最内周側に環状溝１２ａとの間及び環状溝１２ａ相
互間に位置し他方の主表面１２に隣接するｎ型層１４よ
り高不純物濃度を有するｎ型層１７，他方の主表面１２
の最周辺部において他方の主表面１２に隣接するｎ型層
１４より高不純物濃度を有する環状のｎ型層１８を具備
している。２はｐ型層１３にオーミックコンタクトした
第１の主電極、３はｐ型層１５にオーミックコンタクト
した第２の主電極、４は環状溝１２ａの表面に形成され
た酸化シリコン層、５は環状溝１２ａに充填されたポリ
イミド樹脂である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The semiconductor device of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 is a plane pattern view (a) and a cross-sectional view (b) of a peripheral region showing an embodiment of the semiconductor device of the present invention. In the figure, 1 is a semiconductor substrate having a pair of main surfaces 11 and 12, one main surface 11
P-type layer 13 adjacent to the p-type layer 13, the p-type layer 13 and the other main surface 1
N-type layer 14 adjacent to 2 and having a lower impurity concentration,
A p-type layer 15 having a higher impurity concentration than the n-type layer 14 extending from the other main surface 12 into the n-type layer 14 in the central portion of the other main surface 12, and a p-type layer formed in the peripheral portion of the other main surface 12 A plurality of annular grooves 12a surrounding the mold layer 15 at a predetermined interval, an annular p-type layer 16 extending in the n-type layer 14 adjacent to the bottom of each annular groove 12a and its vicinity, and a p-type layer 1
5, an n-type layer 17 having a higher impurity concentration than the n-type layer 14 located between the annular groove 12a on the innermost peripheral side and between the annular grooves 12a and adjacent to the other main surface 12, and the other main surface 12
An annular n-type layer 18 having a higher impurity concentration than that of the n-type layer 14 adjacent to the other main surface 12 is provided at the outermost peripheral portion. Reference numeral 2 is a first main electrode in ohmic contact with the p-type layer 13, 3 is a second main electrode in ohmic contact with the p-type layer 15, 4 is a silicon oxide layer formed on the surface of the annular groove 12a, and 5 is an annular shape. It is a polyimide resin filled in the groove 12a.
【００１９】この実施例において、環状溝１２ａの底部
に形成された環状のｐ型層１６は、ｎ型層１４とｐ型層
１５との間のｐｎ接合が逆バイアスされた時に形成され
る空乏層の広がりを助長する電界制限リングとして機能
する。このｐ型層１６は環状溝１２ａの底部に形成され
ているため、電界制限リング相互間の最も接近している
部分が他方の主表面１２から離れた個所に位置してい
る。このため、高温逆バイアス試験によって半導体基体
外部に可動イオンによる正電荷が発生しても、それによ
って電界制限リング相互間の最も接近している部分のｎ
型層１４のキャリア濃度には何ら影響を与えず、耐圧の
低下は殆ど生じない。また、他方の主表面１２に隣接し
て不純物量が多いｎ型層１７が存在しているため、発生
正電荷の影響でｎ型層１７に電子が誘起されても、ｎ型
層１７の電子濃度の変化の割合が非常に小さく抑えら
れ、耐圧の低下は殆ど生じない。ｎ型層１７の単位面積
当たりの不純物量は、１０13／cm2 以上である。更に、
環状溝１２ａ内は酸化シリコン層４及びポリイミド樹脂
５で充填されているため、電界制限リングが印加電圧を
分担しても環状溝１２ａにおいて絶縁破壊を生じる心配
はない。In this embodiment, the annular p-type layer 16 formed at the bottom of the annular groove 12a is depleted when the pn junction between the n-type layer 14 and the p-type layer 15 is reverse biased. It functions as an electric field limiting ring that promotes the spreading of layers. Since this p-type layer 16 is formed at the bottom of the annular groove 12a, the closest parts between the electric field limiting rings are located at positions apart from the other main surface 12. Therefore, even if positive charges due to mobile ions are generated outside the semiconductor substrate by the high temperature reverse bias test, the n of the closest parts between the electric field limiting rings are thereby generated.
The carrier concentration of the mold layer 14 is not affected at all, and the breakdown voltage hardly decreases. Further, since n-type layer 17 having a large amount of impurities exists adjacent to the other main surface 12, even if electrons are induced in n-type layer 17 due to the influence of generated positive charges, The rate of change in concentration is suppressed to a very small level, and the breakdown voltage hardly decreases. The amount of impurities per unit area of the n-type layer 17 is 10 13 / cm 2 or more. Furthermore,
Since the inside of the annular groove 12a is filled with the silicon oxide layer 4 and the polyimide resin 5, there is no fear of causing dielectric breakdown in the annular groove 12a even if the electric field limiting ring shares the applied voltage.
【００２０】図１の実施例の変形例として、ｎ型層１７
の単位面積当たりの不純物量を図１の場合より少ない１
０13／cm2 以下にしてもよい。この場合、ｎ型層１７の
キャリア濃度は多少変化が大きくなる。しかしながら、
電界制限リングの隣合う電界制限リング間が最も小さい
距離を持つ個所が他方の主表面１２から離れているた
め、この個所でのキャリア濃度は殆ど変化しない。その
ため、他方の主表面１２上に蓄積層が誘起されても、隣
合う電界制限リング間が最も小さい距離を持つ部分での
空乏層の拡がり易さは殆ど影響を受けない。即ち、等価
的電界制限リング間隔の変化は非常に小さい。従って、
図１の場合と同様に耐圧の低下は生じない。また、蓄積
層と電界効果リングとの接触部における電界集中による
耐圧低下も生じない。As a modification of the embodiment shown in FIG. 1, the n-type layer 17 is used.
The amount of impurities per unit area is less than in the case of Fig. 1 1
It may be 0 13 / cm 2 or less. In this case, the carrier concentration of the n-type layer 17 slightly changes. However,
Since the portion having the smallest distance between adjacent electric field limiting rings of the electric field limiting ring is separated from the other main surface 12, the carrier concentration at this portion hardly changes. Therefore, even if the storage layer is induced on the other main surface 12, the ease with which the depletion layer spreads in the portion where the adjacent electric field limiting rings have the smallest distance is hardly affected. That is, the change in the equivalent electric field limiting ring interval is very small. Therefore,
As in the case of FIG. 1, the breakdown voltage does not decrease. Further, the breakdown voltage does not decrease due to the electric field concentration at the contact portion between the storage layer and the field effect ring.
【００２１】図２は、本発明半導体装置の他の実施例を
示す概略断面図である。この実施例はｎ型層１７が存在
しない点で図１の実施例と相違している。図面からは確
認できないが、ｎ型層１７が存在しないことから、ｐ型
層１５と環状溝１２ａの間隔及び環状溝１２ａ相互間の
間隔等も図１の実施例の場合と異なっている。その他の
点は、図１の実施例の場合と同じである。この実施例の
場合、ｎ型層１７が無いので、発生正電荷の影響でｎ型
層１４の他方の主表面１２に隣接する個所に蓄積層が誘
起されキャリア濃度は大きく変化する。しかしながら、
電界制限リングとして機能するｐ型層１６が他方の主表
面１２から離れて形成されているので、ｎ型層１４表面
におけるキャリア濃度の変動は電界制限リングまでは及
ばず、耐圧の低下は小さくできる。FIG. 2 is a schematic sectional view showing another embodiment of the semiconductor device of the present invention. This embodiment differs from the embodiment of FIG. 1 in that the n-type layer 17 is not present. Although it cannot be confirmed from the drawing, since the n-type layer 17 does not exist, the distance between the p-type layer 15 and the annular groove 12a and the distance between the annular grooves 12a are different from those in the embodiment of FIG. The other points are the same as in the case of the embodiment of FIG. In the case of this embodiment, since the n-type layer 17 is not provided, the storage layer is induced at a portion adjacent to the other main surface 12 of the n-type layer 14 due to the influence of the generated positive charges, and the carrier concentration greatly changes. However,
Since the p-type layer 16 functioning as an electric field limiting ring is formed apart from the other main surface 12, the fluctuation of the carrier concentration on the surface of the n-type layer 14 does not reach the electric field limiting ring, and the decrease in breakdown voltage can be reduced. .
【００２２】図３は、図１の半導体装置の変形例を示す
概略断面図である。この変形例はｎ型層１７の代わりに
ｐ型層１９を用いた点で図１の実施例と相違している。
この構成によっても図１の実施例の場合と同様に耐圧の
低下を防止できる。従来技術においては、ｎ型層１７を
ｐ型層にすることは、電圧が電界制限リング間に分担さ
れなくなるため困難であった。本発明によれば、ｐ型層
１９と電界制限リングとなるｐ型層１６とが離れた構成
にすることによって、電圧を電界制限リングで挟まれた
ｎ型層１４，ｐ型層１９と電界制限リングの間及び溝１
２ａ内の酸化シリコン層４，ポリイミド樹脂５で分担で
きるので、ｐ型層１９の適用が可能になったのである。FIG. 3 is a schematic sectional view showing a modification of the semiconductor device of FIG. This modification is different from the embodiment of FIG. 1 in that a p-type layer 19 is used instead of the n-type layer 17.
With this configuration, it is possible to prevent the breakdown voltage from lowering as in the case of the embodiment of FIG. In the prior art, it was difficult to make the n-type layer 17 a p-type layer because the voltage is not shared between the electric field limiting rings. According to the present invention, the p-type layer 19 and the p-type layer 16 serving as the electric field limiting ring are separated from each other, so that the voltage is sandwiched between the n-type layer 14 and the p-type layer 19 and the electric field. Between limit rings and groove 1
Since the silicon oxide layer 4 and the polyimide resin 5 in 2a can be shared, the p-type layer 19 can be applied.
【００２３】図４は、本発明半導体装置の更に他の実施
例を示す概略断面図である。この実施例は図２の実施例
のｐ型層１６が他方の主表面１２まで延在してたものと
みることができる。この場合、溝１２ａの側壁が他方の
主表面１２に対して垂直であるため、ｐ型層１６も他方
の主表面１２に対して垂直方向に延びることになり、隣
合う電界制限リング間が最も小さい距離を持つ部分が他
方の主表面１２から内部に向かって広い範囲で存在する
ことになる。従って、ｎ型層１４表面におけるキャリア
濃度の変動によって他方の主表面１２近傍で等価的電界
制限リング間隔の変化が生じても、他方の主表面１２か
ら離れた個所で隣合う電界制限リング間が最も小さい距
離を持つ部分が依然として存在するため、耐圧の低下を
防止できる。FIG. 4 is a schematic sectional view showing still another embodiment of the semiconductor device of the present invention. This embodiment can be regarded as the p-type layer 16 of the embodiment of FIG. 2 extending to the other main surface 12. In this case, since the side wall of groove 12a is perpendicular to the other main surface 12, p-type layer 16 also extends in the direction perpendicular to the other main surface 12, and the space between adjacent electric field limiting rings is the most. A portion having a small distance exists in a wide range from the other main surface 12 toward the inside. Therefore, even if the equivalent electric field limiting ring spacing changes in the vicinity of the other main surface 12 due to the fluctuation of the carrier concentration on the surface of the n-type layer 14, the distance between the adjacent electric field limiting rings at a location distant from the other main surface 12 is increased. Since the portion having the smallest distance still exists, it is possible to prevent the breakdown voltage from decreasing.
【００２４】以上の実施例では、溝１２ａの充填にポリ
イミド樹脂が使われていたが、低不純物濃度或いはノン
ドープの多結晶シリコンを使っても良い。In the above embodiments, the polyimide resin is used to fill the groove 12a, but low impurity concentration or non-doped polycrystalline silicon may be used.
【００２５】図５は、図１に示す実施例の半導体装置の
製造方法を示す概略工程図である。まず、電界制限リン
グとなるｐ型層１６以外の拡散工程が終了した半導体基
体１を準備し、その他方の主表面１２に環状溝１２ａと
なる部分を除いて選択的に酸化シリコン膜６１を形成し
（ａ）、この酸化シリコン膜６１をマスクとして異方性
エッチングにより環状溝１２ａを形成する（ｂ）。環状
溝１２ａ内面に酸化シリコン膜６２を形成し（ｃ）、異
方性ドライエッチングを施して酸化シリコン膜６２の厚
さが薄く水平面である溝の底のみの酸化シリコン膜６２
が除去される（ｄ）。この酸化シリコン膜６２をマスク
として、ｐ型不純物を拡散させると、環状溝１２ａの底
部とその近傍にのみ位置し他方の主表面１２に露出しな
いｐ型層１６が形成される（ｅ）。次に、再び環状溝１
２ａの内面全面に酸化シリコン膜４を形成し（ｆ）、更
に環状溝１２ａをポリイミド樹脂５で充填し、エッチバ
ックして平坦化する（ｇ）。その後、電極，保護膜を形
成し、素子が完成する。工程（ｆ）において、環状溝１
２ａの内面全面に酸化シリコン膜４を形成したが、この
工程は、必須ではない。ポリイミド樹脂５の充填後、高
温熱処理をせぬような手順としたが、ポリイミド樹脂５
の代わりに多結晶シリコンを使えば、環状溝１２ａに充
填後に高温の拡散熱処理を施すことになる。工程（ｂ）
における、エッチングのマスク材は酸化シリコン以外の
物質、例えばアルミニウムでも良い。FIG. 5 is a schematic process diagram showing a method of manufacturing the semiconductor device of the embodiment shown in FIG. First, the semiconductor substrate 1 after the diffusion process other than the p-type layer 16 to be the electric field limiting ring is prepared, and the silicon oxide film 61 is selectively formed on the other main surface 12 except the portion to be the annular groove 12a. Then, (a), the annular groove 12a is formed by anisotropic etching using the silicon oxide film 61 as a mask (b). A silicon oxide film 62 is formed on the inner surface of the annular groove 12a (c), and anisotropic dry etching is performed so that the silicon oxide film 62 has a thin thickness and is a horizontal surface.
Are removed (d). When the p-type impurity is diffused using the silicon oxide film 62 as a mask, a p-type layer 16 is formed which is located only at the bottom of the annular groove 12a and in the vicinity thereof and is not exposed on the other main surface 12 (e). Then again the annular groove 1
A silicon oxide film 4 is formed on the entire inner surface of 2a (f), and further the annular groove 12a is filled with a polyimide resin 5 and flattened by etching back (g). After that, electrodes and a protective film are formed to complete the device. In step (f), the annular groove 1
Although the silicon oxide film 4 is formed on the entire inner surface of 2a, this step is not essential. After the polyimide resin 5 was filled, the procedure was such that the high temperature heat treatment was not performed.
If polycrystalline silicon is used instead of, the high temperature diffusion heat treatment is performed after filling the annular groove 12a. Process (b)
In the above, the mask material for etching may be a substance other than silicon oxide, for example, aluminum.
【００２６】この製造方法は、他の実施例にも適用でき
る。工程（ａ）で、ｎ型層１７のない半導体基体を使用
すれば図２に示す半導体装置が得られ、ｎ型層１７の代
わりにｐ型層を形成した半導体基体を使用すれば図３に
示す半導体装置が得られる。また、工程（ａ）でｎ型層
１７のない半導体基体を使用し、工程(ｃ）及び(ｄ）を
省略すると図４に示す半導体装置が得られる。この場
合、環状溝１２ａの形成に完全な異方性エッチングは必
要ない。ある程度、環状溝１２ａの側壁が主表面１２に
対する垂直性があれば、従来例の場合よりも信頼性を向
上させる効果はある。その理由は、主表面から離れたと
ころでの電界制限リング間の距離を、従来例の場合より
小さくできるからである。しかし、環状溝１２ａの形成
に異方性エッチングを使い、図４に示したように環状溝
１２ａの側壁部を垂直にする場合が、主表面から離れた
ところでの電界制限リング間の距離を小さくすることに
より効果があり、信頼性の改善効果は大きい。また、環
状溝１２ａの開口部より底部が広いような形状であれ
ば、更に効果は大きい。This manufacturing method can be applied to other embodiments. In the step (a), the semiconductor device shown in FIG. 2 is obtained by using a semiconductor substrate without the n-type layer 17, and by using a semiconductor substrate having a p-type layer formed in place of the n-type layer 17 in FIG. The semiconductor device shown is obtained. If the semiconductor substrate without the n-type layer 17 is used in step (a) and steps (c) and (d) are omitted, the semiconductor device shown in FIG. 4 is obtained. In this case, complete anisotropic etching is not required to form the annular groove 12a. If the side wall of the annular groove 12a is perpendicular to the main surface 12 to some extent, there is an effect of improving reliability as compared with the case of the conventional example. The reason is that the distance between the electric field limiting rings at a distance from the main surface can be made smaller than in the case of the conventional example. However, when anisotropic etching is used to form the annular groove 12a and the side wall portion of the annular groove 12a is made vertical as shown in FIG. 4, the distance between the electric field limiting rings at a distance from the main surface is reduced. By doing so, there is an effect, and the effect of improving reliability is great. Further, if the shape is such that the bottom portion is wider than the opening portion of the annular groove 12a, the effect is further increased.
【００２７】これまで述べた実施例では、後で述べる実
施例の場合と異なり、エピタキシャル成長を必要としな
い。そのため、工程制御面に起因するエピタキシャル成
長層の品質限界の特性への影響が無く、歩留まり良く高
い初期耐圧を得ることができる。即ち、半導体基体の不
純物濃度が低い場合も、電界制限リングで挟まれた領域
の不純物濃度を基体濃度と同じく低くできる。また、こ
の部分の欠陥密度も非常に小さくできる。The embodiments described so far do not require epitaxial growth, unlike the embodiments described later. Therefore, there is no influence of the quality limit of the epitaxial growth layer on the characteristics due to the process control surface, and it is possible to obtain a high yield and a high initial breakdown voltage. That is, even when the impurity concentration of the semiconductor substrate is low, the impurity concentration of the region sandwiched by the electric field limiting rings can be made as low as the substrate concentration. Also, the defect density in this portion can be made very small.
【００２８】図６は本発明半導体装置の異なる実施例を
示す概略断面図である。図１の実施例とは、環状溝１２
ａがないこと、環状溝１２ａがないことによりｐ型層１
６が埋込層となっていること及びｎ型層１７相互間にｎ
型層１４が露出していることにおいて相違している。こ
の構成においても図１の実施例と同じく本発明の特徴を
持っている。即ち、これらの電界制限リングでは、隣
合う電界制限リング間の距離が最も小さい部分が他方の
主表面１２から離れて存在すること、電界制限リング
が他方の主表面１２には露出していないこと、ｎ型層
１７が他方の主表面１２に形成されていること、ｎ型
層１７と電界制限リングが隔離されていることが図１と
同一であることによる。このｎ型層１７の単位面積当た
りの不純物量は１０13／cm2 以上ある。FIG. 6 is a schematic sectional view showing a different embodiment of the semiconductor device of the present invention. The embodiment of FIG. 1 differs from the annular groove 12
p-type layer 1 due to the absence of a and the absence of annular groove 12a
6 is an embedded layer, and n is provided between the n-type layers 17.
The difference is that the mold layer 14 is exposed. This configuration also has the features of the present invention as in the embodiment of FIG. That is, in these electric field limiting rings, a portion where the distance between adjacent electric field limiting rings is smallest exists apart from the other main surface 12, and the electric field limiting ring is not exposed to the other main surface 12. The fact that the n-type layer 17 is formed on the other main surface 12 and that the n-type layer 17 and the electric field limiting ring are separated is the same as in FIG. The amount of impurities per unit area of the n-type layer 17 is 10 13 / cm 2 or more.
【００２９】図７は図６の実施例の変形例を示す概略断
面図である。図６の実施例とは、ｎ型層１７の間にｐ型
層２１を付加した点で相違している。FIG. 7 is a schematic sectional view showing a modification of the embodiment shown in FIG. The embodiment is different from the embodiment of FIG. 6 in that a p-type layer 21 is added between the n-type layers 17.
【００３０】図８は図６の実施例の別の変形例を示す概
略断面図である。図６の実施例とは、ｎ型層１７の代わ
りにｐ型層２２を用いた点で相違している。FIG. 8 is a schematic sectional view showing another modification of the embodiment shown in FIG. It differs from the embodiment of FIG. 6 in that a p-type layer 22 is used instead of the n-type layer 17.
【００３１】本発明の構造面での特徴、即ち、ｐ＋層１
８と電界制限リング８が離れていることにより、電圧
を、電界制限リング８で挟まれた領域，ｐ＋層１８と電
界制限リング８で挟まれた領域及びｐ＋層１８で挟まれ
た領域で構成される領域で分担できるため、ｐ＋層１８
の適用が可能になった。The structural feature of the present invention, that is, the p + layer 1
8 and the electric field limiting ring 8 are separated from each other, the voltage is composed of a region sandwiched by the electric field limiting ring 8, a region sandwiched by the p + layer 18 and the electric field limiting ring 8 and a region sandwiched by the p + layer 18. The p + layer 18
Can be applied.
【００３２】図９は図７の変形例の更なる変形例を示す
概略断面図である。図７の実施例とは、他方の主表面１
２に絶縁層２３を介して高抵抗導電層２４を設けた点で
相違している。この高抵抗導電層２４に分路電流を流し
て装置の表面の電位分布を均一化することができる。高
抵抗導電層２４としては、多結晶Ｓｉが使われている。
この場合には、本発明の特徴である構造による効果と、
高抵抗導電層２４による高信頼化という効果を達成して
いる。この変形例では、表面に溝がない構造で平坦性が
良いため、多結晶Ｓｉによる高抵抗導電層２４を形成し
易い。FIG. 9 is a schematic sectional view showing a further modification of the modification of FIG. The other main surface 1 is different from the embodiment of FIG.
2 is different in that a high resistance conductive layer 24 is provided via an insulating layer 23. A shunt current can be passed through the high resistance conductive layer 24 to make the potential distribution on the surface of the device uniform. Polycrystalline Si is used for the high resistance conductive layer 24.
In this case, the effect of the structure, which is a feature of the present invention,
The high resistance conductive layer 24 achieves the effect of high reliability. In this modification, since the surface has no groove and the flatness is good, it is easy to form the high resistance conductive layer 24 of polycrystalline Si.
【００３３】図１０は図６の実施例の半導体装置の製造
方法の一部を示す概略工程図である。図６の半導体装置
は、半導体基体１のｎ型１４１層表面に選択的にｐ型不
純物１６１を導入し(ａ）、その上にｎ型層１４２をエ
ピタキシャル成長させる(ｂ）。その後、ｎ型層１４２
の表面付近にｐ型層１５及びｎ型層１７を形成して(ｃ)
形成される。FIG. 10 is a schematic process view showing a part of the method of manufacturing the semiconductor device of the embodiment of FIG. In the semiconductor device of FIG. 6, the p-type impurity 161 is selectively introduced into the surface of the n-type 141 layer of the semiconductor substrate 1 (a), and the n-type layer 142 is epitaxially grown thereon (b). Then, the n-type layer 142
Forming a p-type layer 15 and an n-type layer 17 near the surface of (c)
It is formed.
【００３４】図１１は本発明半導体装置の別の実施例を
示す概略断面図である。図１の実施例とは、ｐ型層１５
が環状溝１２ａと同じ深さの凹部１２ｂの底部に形成さ
れていることである。ｐ型層１５と第２の主電極との間
及び環状溝１２ａの底部の酸化シリコン膜４を除去して
ｐ型層１６とポリイミド樹脂５との間にシリサイド層２
５を介在したことにおいて相違している。FIG. 11 is a schematic sectional view showing another embodiment of the semiconductor device of the present invention. The embodiment of FIG. 1 is different from the p-type layer 15 in FIG.
Is formed at the bottom of the recess 12b having the same depth as the annular groove 12a. The silicon oxide film 4 at the bottom of the annular groove 12a is removed between the p-type layer 15 and the second main electrode to remove the silicide layer 2 between the p-type layer 16 and the polyimide resin 5.
The difference is that 5 is interposed.
【００３５】図１２は図１１の実施例の変形例を示す概
略断面図で、図１１の装置とはｐ型層１５の深さよりｐ
型層１６のそれを浅くした点において相違している。FIG. 12 is a schematic sectional view showing a modification of the embodiment shown in FIG. 11. The device shown in FIG. 11 differs from the device shown in FIG.
The difference is that the mold layer 16 is shallower.
【００３６】図１３は図１１の実施例の他の変形例を示
す概略断面図で、図１２の装置とはｐ型層１５とｐ型層
１６とを接近させた点において相違している。このよう
にすれば、ｐ型層１５の接合から延びる空乏層が電界制
限リングとしてのｐ型層１６に達し易いようになるた
め、ｐ型層１５の底部での電界集中が緩和され、図１２
の場合に比べて初期耐圧は高くできる。FIG. 13 is a schematic sectional view showing another modification of the embodiment shown in FIG. 11, which is different from the device shown in FIG. 12 in that the p-type layer 15 and the p-type layer 16 are brought close to each other. By doing so, the depletion layer extending from the junction of the p-type layer 15 easily reaches the p-type layer 16 as the electric field limiting ring, so that the electric field concentration at the bottom of the p-type layer 15 is relaxed, and the depletion layer is reduced.
The initial breakdown voltage can be made higher than in the case of.
【００３７】図１４は図１１の実施例の更に他の変形例
を示す概略断面図で、図１２の装置とは、環状溝１２ａ
の深さと幅をｐ型層１５から遠ざかるに従って浅くかつ
狭くした点で相違している。この構成によれば、ｐ型層
１５の底部での電界集中が緩和され、図１２の場合に比
べ初期耐圧は高くできる。FIG. 14 is a schematic sectional view showing still another modification of the embodiment shown in FIG. 11. The apparatus shown in FIG. 12 differs from the annular groove 12a.
The difference is that the depth and the width are made shallower and narrower with increasing distance from the p-type layer 15. According to this structure, the electric field concentration at the bottom of the p-type layer 15 is relaxed, and the initial breakdown voltage can be increased as compared with the case of FIG.
【００３８】図１５は図１１の実施例の別の変形例を示
す概略断面図で、図１１の実施例とは環状溝１２ａの深
さをｐ型層１５から離れるに従って順次浅くするととも
に幅を狭くした点で相違している。この構造によると、
他の実施例ではもっとも厳しかったｐ型層１５の底部で
の電界集中は緩和され、初期耐圧は他の実施例より向上
できる。FIG. 15 is a schematic cross-sectional view showing another modification of the embodiment of FIG. 11, in which the depth of the annular groove 12a is gradually reduced as the distance from the p-type layer 15 is increased and the width thereof is made smaller. The difference is that it is narrowed. According to this structure,
The electric field concentration at the bottom of the p-type layer 15 which is the most severe in the other examples is relaxed, and the initial breakdown voltage can be improved as compared with the other examples.
【００３９】図１６は図１５の実施例における環状溝１
２ａの製造方法を示す概略工程図で、異方性エッチング
においては開口部の幅によって深さが自動的に決められ
るという性質を利用した製造方法である。工程（ａ）は
環状溝１２ａを形成する前の半導体基体１の他方の主表
面１２上にマスクとしての酸化シリコン膜３０を、ｐ型
層１５が形成される個所は薄い酸化シリコン膜３０ａ、
環状溝１２ａが形成される個所は開口３０ｂ、他の個所
は厚い酸化シリコン膜３０ｃとなるように形成する工程
である。この状態で、半導体基体１の他方の主表面１２
に異方性エッチングを施すと、酸化シリコン膜３０の開
口３０ｂの部分ではその幅の相違により深さの異なる環
状溝１２ａが形成され、薄い酸化シリコン膜３０ａの部
分では開口３０ｂの部分に比較して酸化シリコン膜３０
ａのエッチングに要する時間だけ半導体基体１のエッチ
ング時間が短くなり開口部の幅の割には浅い凹部が形成
される（ｂ）。ここで、エッチングのマスク材は、酸化
シリコン以外の物質、例えばアルミニウム他でも良い。FIG. 16 shows an annular groove 1 in the embodiment of FIG.
2a is a schematic process diagram showing the manufacturing method of 2a, which is a manufacturing method utilizing the property that the depth is automatically determined by the width of the opening in anisotropic etching. In the step (a), the silicon oxide film 30 as a mask is formed on the other main surface 12 of the semiconductor substrate 1 before the formation of the annular groove 12a, and the thin silicon oxide film 30a is formed on the p-type layer 15.
The process for forming the annular groove 12a is such that the place where the annular groove 12a is formed is the opening 30b and the other place is the thick silicon oxide film 30c. In this state, the other main surface 12 of the semiconductor substrate 1
When anisotropic etching is performed on the silicon oxide film 30, an annular groove 12a having a different depth is formed in the opening 30b portion of the silicon oxide film 30 due to the difference in width, and the thin silicon oxide film 30a portion is different from the opening 30b portion. Silicon oxide film 30
The etching time of the semiconductor substrate 1 is shortened by the time required for etching a, and a shallow recess is formed for the width of the opening (b). Here, the etching mask material may be a material other than silicon oxide, such as aluminum.
【００４０】以上は本発明を代表的な実施例をベースに
説明したが、本発明はこれら実施例に限定されるもので
はなく、本発明の思想を逸脱しない範囲で種々の変形が
可能である。Although the present invention has been described above based on typical embodiments, the present invention is not limited to these embodiments, and various modifications can be made without departing from the spirit of the present invention. .
【００４１】図１７は、本発明半導体装置を適用したＩ
ＧＢＴ及びダイオードを用いて電動機駆動用インバータ
装置を構成した一例を示したものである。六個のＩＧＢ
Ｔ，ＳＷ１１，ＳＷ１２，ＳＷ２１，ＳＷ２２，ＳＷ３
１，ＳＷ３３により、三相誘導電動機を制御する例であ
る。ＩＧＢＴは、スイッチング速度の大きい素子であ
り、これに本発明を適用することにより逆阻止電圧が高
くされたＩＧＢＴ及びダイオードは長期に渡り使用して
も耐圧の低下がないので、インバータ装置の小型，軽
量，低損失化及び低雑音化等に効果があり、インバータ
装置を用いたシステムの低コスト，高効率化が達成でき
る。FIG. 17 shows an I to which the semiconductor device of the present invention is applied.
1 is a diagram showing an example in which a motor driving inverter device is configured using a GBT and a diode. 6 IGB
T, SW11, SW12, SW21, SW22, SW3
1 is an example of controlling a three-phase induction motor by SW33. The IGBT is an element having a high switching speed, and since the IGBT and the diode whose reverse blocking voltage is increased by applying the present invention thereto does not lower the withstand voltage even if they are used for a long period of time, the size of the inverter device can be reduced. It is effective in weight reduction, loss reduction, and noise reduction, and can achieve low cost and high efficiency of a system using an inverter device.
【００４２】[0042]
【発明の効果】本発明によれば、逆阻止電圧の低下が無
く素子を使用できる期間を大幅に長くできる。或いは、
事実上逆阻止電圧の低下の問題を根絶できるとも言え
る。また、素子の非常に過酷な環境での使用，低コスト
での実装にも道を開く。このような超高信頼化が、高い
初期耐圧を容易に達成しつつ実現できる。製造方法も容
易である。According to the present invention, the period in which the device can be used can be greatly extended without a decrease in the reverse blocking voltage. Alternatively,
It can be said that the problem of the reduction of the reverse blocking voltage can be virtually eliminated. It also opens the way to the use of the device in extremely harsh environments and low-cost mounting. Such ultra-high reliability can be realized while easily achieving a high initial breakdown voltage. The manufacturing method is also easy.
【図１】本発明半導体装置の一実施例を示す概略平面図
及び断面図である。FIG. 1 is a schematic plan view and a sectional view showing an embodiment of a semiconductor device of the present invention.
【図２】本発明半導体装置の他の実施例を示す概略断面
図である。FIG. 2 is a schematic sectional view showing another embodiment of the semiconductor device of the present invention.
【図３】図１の半導体装置の変形例を示す概略断面図で
ある。FIG. 3 is a schematic cross-sectional view showing a modified example of the semiconductor device of FIG.
【図４】本発明半導体装置の更に他の実施例を示す概略
断面図である。FIG. 4 is a schematic sectional view showing still another embodiment of the semiconductor device of the present invention.
【図５】図１の半導体装置の製造方法を示す概略工程図
である。5A to 5C are schematic process diagrams showing a method of manufacturing the semiconductor device of FIG.
【図６】本発明半導体装置の更に他の実施例を示す概略
断面図である。FIG. 6 is a schematic sectional view showing still another embodiment of the semiconductor device of the present invention.
【図７】図６の半導体装置の変形例を示す概略断面図で
ある。FIG. 7 is a schematic cross-sectional view showing a modified example of the semiconductor device of FIG.
【図８】図６の半導体装置の別の変形例を示す概略断面
図である。8 is a schematic cross-sectional view showing another modification of the semiconductor device of FIG.
【図９】図７の変形例の更に別の変形例を示す概略断面
図である。9 is a schematic cross-sectional view showing still another modification of the modification of FIG.
【図１０】図６の半導体装置の製造方法を示す概略工程
図である。10A to 10D are schematic process diagrams showing a method of manufacturing the semiconductor device of FIG.
【図１１】本発明半導体装置の別の実施例を示す概略断
面図である。FIG. 11 is a schematic sectional view showing another embodiment of the semiconductor device of the present invention.
【図１２】図１１の半導体装置の別の変形例を示す概略
断面図である。12 is a schematic cross-sectional view showing another modified example of the semiconductor device of FIG.
【図１３】図１１の半導体装置の他の変形例を示す概略
断面図である。13 is a schematic cross-sectional view showing another modified example of the semiconductor device of FIG.
【図１４】図１１の半導体装置の更に他の変形例を示す
概略断面図である。FIG. 14 is a schematic sectional view showing still another modification of the semiconductor device of FIG.
【図１５】図１１の半導体装置の異なる変形例を示す概
略断面図である。15 is a schematic cross-sectional view showing another modified example of the semiconductor device of FIG.
【図１６】図１５の半導体装置の製造方法を示す概略工
程図である。16 is a schematic process diagram showing the method of manufacturing the semiconductor device of FIG.
【図１７】本発明半導体装置を使った電動機駆動用イン
バータ装置の回路図である。FIG. 17 is a circuit diagram of an electric motor driving inverter device using the semiconductor device of the present invention.
１…半導体基体、１１，１２…主表面、１２ａ…環状
溝、１６…ｐ型層（電界制限リング）、１７…ｎ型層。1 ... Semiconductor substrate, 11, 12 ... Main surface, 12a ... Annular groove, 16 ... P-type layer (electric field limiting ring), 17 ... N-type layer.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 八尾 勉 茨城県日立市大みか町七丁目１番１号 株 式会社日立製作所日立研究所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tsutomu Yao 7-1 Omika-cho, Hitachi-shi, Ibaraki Hitachi Ltd. Hitachi Research Laboratory
Claims (11)
半導体領域と、主表面から第１の半導体領域内に延びる
他方導電型の第２の半導体領域と、主表面及び第２の半
導体領域から離れた位置において第２の半導体領域から
順次遠ざかるように配置された第２の半導体領域を包囲
する複数個の他方導電型の第３の半導体領域と、主表面
において第２の半導体領域に設けられた電極とを具備す
ることを特徴とする半導体装置。1. A first semiconductor region of one conductivity type on a main surface of a semiconductor substrate, a second semiconductor region of the other conductivity type extending from the main surface into the first semiconductor region, a main surface and a second surface. A plurality of third conductivity type third semiconductor regions surrounding the second semiconductor region, which are arranged so as to be distant from the second semiconductor region at positions distant from the semiconductor region, and the second semiconductor region on the main surface. And an electrode provided on the semiconductor device.
ら第３の半導体領域に達する凹部が設けられ、この凹部
は絶縁物によって充填されていることを特徴とする半導
体装置。2. A semiconductor device according to claim 1, wherein a recess reaching from the main surface of the semiconductor substrate to the third semiconductor region is provided, and the recess is filled with an insulating material.
主表面の第２の半導体領域と第３の半導体領域との間及
び第３の半導体領域相互間に対応する個所に第１の半導
体領域より高不純物濃度を有する一方導電型または他方
導電型の複数個の第４の半導体領域を設けたことを特徴
とする半導体装置。3. The first semiconductor region according to claim 1, wherein the first semiconductor region is provided on the main surface of the semiconductor substrate at a position corresponding to between the second semiconductor region and the third semiconductor region and between the third semiconductor regions. A semiconductor device comprising a plurality of fourth semiconductor regions of one conductivity type or the other conductivity type having a higher impurity concentration.
第２の半導体領域と第３の半導体領域との間及び第３の
半導体領域相互間に対応する個所に第１の半導体領域よ
り高不純物濃度を有する一方導電型の複数個の第４の半
導体領域を設け、半導体基体の主表面の第３の半導体領
域相互間に対応する個所に第１の半導体領域より高不純
物濃度を有する他方導電型の複数個の第４の半導体領域
を設けたことを特徴とする半導体装置。4. The semiconductor device according to claim 1, wherein a portion of the main surface of the semiconductor substrate that is located between the second semiconductor region and the third semiconductor region and between the third semiconductor regions is higher than the first semiconductor region. A plurality of one-conductivity-type fourth semiconductor regions having an impurity concentration are provided, and the other conductivity having a higher impurity concentration than the first semiconductor region is provided on the main surface of the semiconductor substrate at a position corresponding to each other between the third semiconductor regions. A semiconductor device comprising a plurality of fourth semiconductor regions of a mold.
半導体領域と、主表面から第１の半導体領域内に延びる
他方導電型の第２の半導体領域と、第２の半導体領域か
ら順次遠ざかるように離れた位置において主表面から第
１の半導体領域内に延びる第２の半導体領域を包囲する
複数個の他方導電型の第３の半導体領域と、主表面にお
いて第２の半導体領域に設けられた電極とを具備し、第
３の半導体領域相互間の最小間隔個所が主表面から離れ
ていることを特徴とする半導体装置。5. A first semiconductor region of one conductivity type on the main surface of a semiconductor substrate, a second semiconductor region of the other conductivity type extending from the main surface into the first semiconductor region, and a second semiconductor region. A plurality of third semiconductor regions of the other conductivity type surrounding a second semiconductor region extending from the main surface into the first semiconductor region at positions spaced apart from each other in sequence, and a second semiconductor region on the main surface. A semiconductor device comprising: an electrode provided, wherein a minimum distance between the third semiconductor regions is away from the main surface.
第２の半導体領域と第３の半導体領域との間及び第３の
半導体領域相互間に対応する個所に第１の半導体領域よ
り高不純物濃度を有する一方導電型または他方導電型の
複数個の第４の半導体領域を設けたことを特徴とする半
導体装置。6. The semiconductor device according to claim 5, wherein a portion of the main surface of the semiconductor substrate which is located between the second semiconductor region and the third semiconductor region and between the third semiconductor regions is higher than the first semiconductor region. A semiconductor device comprising a plurality of one conductivity type or other conductivity type fourth semiconductor regions having an impurity concentration.
主表面から第３の半導体領域に達する凹部が設けられ、
この凹部は絶縁物によって充填されていることを特徴と
する半導体装置。7. The recess according to claim 5 or 6, wherein a recess reaching from the main surface of the semiconductor substrate to the third semiconductor region is provided.
A semiconductor device, wherein the recess is filled with an insulating material.
半導体領域と、主表面から第１の半導体領域内に延びる
他方導電型の第２の半導体領域と、主表面及び第２の半
導体領域から離れた位置において第２の半導体領域から
順次遠ざかるように、かつ遠ざかるように従って深さが
浅くなるように配置された第２の半導体領域を包囲する
複数個の他方導電型の第３の半導体領域と、主表面にお
いて第２の半導体領域に設けられた電極とを具備するこ
とを特徴とする半導体装置。8. A first semiconductor region of one conductivity type on a main surface of a semiconductor substrate, a second semiconductor region of the other conductivity type extending from the main surface into the first semiconductor region, a main surface and a second surface. A plurality of third conductivity type thirds surrounding the second semiconductor region arranged so as to be gradually separated from the second semiconductor region at a position distant from the semiconductor region and to become shallower as the distance increases. A semiconductor device comprising: a semiconductor region; and an electrode provided in the second semiconductor region on the main surface.
ら第３の半導体領域に達する凹部が設けられ、この凹部
は絶縁物によって充填されていることを特徴とする半導
体装置。9. A semiconductor device according to claim 8, wherein a recess reaching from the main surface of the semiconductor substrate to the third semiconductor region is provided, and the recess is filled with an insulating material.
ら遠ざかるように従って凹部の幅が小さくなるようにさ
れていることを特徴とする半導体装置。10. A semiconductor device according to claim 9, wherein the width of the recess is reduced as the distance from the second semiconductor region increases.
体基体の主表面の第２の半導体領域と第３の半導体領域
との間及び第３の半導体領域相互間に対応する個所に第
１の半導体領域より高不純物濃度を有する一方導電型ま
たは他方導電型の複数個の第４の半導体領域を設けたこ
とを特徴とする半導体装置。11. The semiconductor device according to claim 8, 9 or 10, wherein the first surface is provided on the main surface of the semiconductor substrate at a position corresponding to between the second semiconductor region and the third semiconductor region and between the third semiconductor regions. A semiconductor device comprising a plurality of fourth semiconductor regions of one conductivity type or the other conductivity type having a higher impurity concentration than that of the semiconductor region.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16087493A JP3211490B2 (en) | 1993-06-30 | 1993-06-30 | Semiconductor device and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16087493A JP3211490B2 (en) | 1993-06-30 | 1993-06-30 | Semiconductor device and manufacturing method thereof |
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| Publication Number | Publication Date |
|---|---|
| JPH07142713A true JPH07142713A (en) | 1995-06-02 |
| JP3211490B2 JP3211490B2 (en) | 2001-09-25 |
Family
ID=15724242
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|---|---|---|---|
| JP16087493A Expired - Fee Related JP3211490B2 (en) | 1993-06-30 | 1993-06-30 | Semiconductor device and manufacturing method thereof |
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| Country | Link |
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| EP0813250A2 (en) * | 1996-06-13 | 1997-12-17 | Plessey Semiconductors Limited | Trench semiconductor device |
| WO2005076362A3 (en) * | 2004-02-02 | 2005-10-06 | Hamza Yilmaz | Semiconductor device containing dielectrically isolated doped field shield region |
| US7323386B2 (en) | 2004-02-02 | 2008-01-29 | Hamza Yilmaz | Method of fabricating semiconductor device containing dielectrically isolated PN junction for enhanced breakdown characteristics |
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| US7427800B2 (en) | 2004-02-02 | 2008-09-23 | Hamza Yilmaz | Semiconductor device containing dielectrically isolated PN junction for enhanced breakdown characteristics |
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| JP3211490B2 (en) | 2001-09-25 |
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