KR101949511B1 - Power semiconductor device and method of fabricating the same - Google Patents

Abstract

The present invention relates to a semiconductor device having a first conductivity type in which a first region having a higher vertical breakdown voltage than a horizontal breakdown voltage and a second region having a higher withstand voltage than the vertical breakdown voltage and having a higher withstand voltage than the first region, A power semiconductor device in which an oxide pattern is embedded to prevent diffusion of impurities is provided.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor device,

The present invention relates to a power semiconductor device and a manufacturing method thereof, and more particularly, to an insulated gate bipolar transistor (IGBT) device and a manufacturing method thereof.

Insulated Gate Bipolar Transistor (IGBT) is a crystalline material of MOS (Metal Oxide Silicon) and bipolar technology. It is characterized by low forward loss and high speed. It is applicable to applications that can not be realized with thyristors, bipolar transistors and MOSFETs. And is a next generation power semiconductor device which is used in a high efficiency and high speed power system widely used in a voltage range of 300V or more. Since the development of power MOSFETs in the 1970s, MOSFETs have been used for switching devices requiring high-speed switching, and bipolar transistors, thyristors, and GTOs have been used in a range where a large amount of current conduction is required at middle to high voltage . The IGBT developed in the early 1980s has a current capability of more than a bipolar transistor in terms of output characteristics and has a gate driving characteristic like a MOSFET in terms of input characteristics, so that switching at a high speed of about 100 KHz is possible. As a result, IGBTs are being used not only for replacement of MOSFETs, bipolar transistors, and thyristors, but also for new application systems.

A related prior art is Korean Laid-Open Publication No. 20140057630 (published on May 13, 2014, entitled IGBT and its manufacturing method).

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device and a manufacturing method thereof that can firmly maintain a vertical withstand voltage and a horizontal withstand voltage characteristic in an IGBT on / off state as well as a switching state. However, these problems are exemplary and do not limit the scope of the present invention.

A power semiconductor device according to one aspect of the present invention for solving the above problems is provided. The power semiconductor device comprising: an active cell region formed in one region of a substrate; A ring termination region formed in another region of the substrate and adjacent to the active cell region; And an isolation region electrically isolating the active cell region and the ring termination region from each other; Wherein the insulating region comprises an oxide pattern embedded in the substrate. Here, the oxide pattern is not formed by a deposition process for filling a trench, but is implemented by depositing an oxide layer, patterning the oxide layer, and then filling the oxide layer with an epi layer, thereby overcoming various problems of the gapfil process.

The power semiconductor device comprising a floating region of a first conductive type formed at the edge of the active cell region with the insulating region interposed therebetween and a first conductive type edge doped region formed in the ring termination region, The oxide pattern formed in the insulating region includes an oxide pattern that prevents diffusion of the first conductive impurity between the floating region of the first conductive type and the edge doped region of the first conductive type.

The power semiconductor device may further include an edge region of a second conductivity type between the floating region of the first conductivity type and the edge doping region of the first conductivity type.

In the power semiconductor device, the ring termination region may have a shape surrounding the rim of the active cell region.

In the power semiconductor device, the first conductivity type and the second conductivity type may have a conductivity type opposite to that of the p-type or n-type, respectively.

A power semiconductor device according to another aspect of the present invention for solving the above problems is provided. Wherein the power semiconductor element is disposed between a first region having a higher vertical breakdown voltage than a horizontal breakdown voltage and a second region having a higher withstand voltage and a higher horizontal breakdown voltage than the first region and a second conductivity type floating region formed in the first region, And an oxide pattern for preventing diffusion of the first conductive impurity between the edge-doped regions of the first conductivity type formed in the region.

A method of manufacturing a power semiconductor device according to another aspect of the present invention for solving the above problems is provided. A method of fabricating a power semiconductor device includes: a first step of implanting a first conductive impurity and a second conductive impurity on predetermined regions on a wafer; A second step of forming an oxide pattern on any one region for implanting the impurity of the second conductivity type; A third step of forming a substrate composed of the wafer and the epi layer by forming an epitaxial layer on the wafer so as to cover the wafer and the oxide pattern; A fourth step of implanting a first conductive impurity through the surface of the epi layer to correspond to a region where the first conductive impurity is implanted in the first step; And a fifth step of forming a first conductive type floating region and a first conductive type edge doped region spaced apart from each other on both sides with reference to the oxide pattern in the substrate by diffusing the impurities. Here, the oxide pattern is not formed by a deposition process for filling a trench, but is implemented by depositing an oxide layer, patterning the oxide layer, and then filling the oxide layer with an epi layer, thereby overcoming various problems of the gapfil process.

The concentration of the impurity of the second conductivity type injected in the first step of the method of manufacturing the power semiconductor device is higher than the concentration of the second conductivity type contained in the wafer and the third step and the fifth step An edge region of the second conductivity type may be formed between the floating region of the first conductivity type and the edge doped region of the first conductivity type.

A method of manufacturing a power semiconductor device according to another aspect of the present invention for solving the above problems is provided. The method of manufacturing a power semiconductor device includes a first region of a first conductivity type disposed in a first region and a second region of a second conductivity type having a higher internal breakdown voltage than the first region, An oxide pattern is formed to prevent diffusion of the first conductive impurity between the first conductive type edge doped regions formed in the second region, and the oxide pattern is formed not by the tapping process of filling the trench but by depositing the oxide layer And then embedding the resultant into an epi layer after patterning.

According to the embodiment of the present invention as described above, it is possible to realize a semiconductor device and a manufacturing method thereof which can firmly maintain the vertical withstand voltage and the withstand voltage characteristics even in the switching state as well as the IGBT on / off state. Of course, the scope of the present invention is not limited by these effects.

FIG. 1 is a view showing a doping profile in a power semiconductor device according to a comparative example of the present invention, and FIG. 2 is a view showing an electric potential profile of an AA 'line in the power semiconductor device shown in FIG. 1 And FIG. 3 is a view showing an electric field profile pattern centered on the line AA 'in the power semiconductor device shown in FIG.
FIG. 4 is a graph showing an electric field measured in a direction of an end of the AA 'line in the power semiconductor device shown in FIG. 1. FIG.
5 is a diagram illustrating a cross section of an area E1 including a boundary between an active cell region and a ring termination region in the power semiconductor device shown in FIG.
6 is a cross-sectional view of a region including a boundary between an active cell region and a ring termination region in a power semiconductor device according to an embodiment of the present invention.
7 is a plan view schematically illustrating a configuration of a region including a boundary between an active cell region and a ring termination region in a power semiconductor device according to an embodiment of the present invention.
8 to 15 are views sequentially illustrating a method of manufacturing a power semiconductor device according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be understood, however, that the invention is not limited to the disclosed embodiments, but may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, Is provided to fully inform the user. Also, at least some of the components may be exaggerated or reduced in size for convenience of explanation. Like numbers refer to like elements throughout the drawings.

In this specification, the first conductive type and the second conductive type have opposite conductivity types, and may be any of n-type and p-type, respectively. For example, the first conductivity type may be p-type and the second conductivity type may be n-type, and the conductivity type configuration is exemplarily illustrated in the accompanying drawings. However, the technical idea of the present invention is not limited thereto. For example, the first conductivity type may be n-type and the second conductivity type may be p-type.

FIG. 1 is a view showing a doping profile in a power semiconductor device according to a comparative example of the present invention, and FIG. 2 is a view showing an electric potential profile of an AA 'line in the power semiconductor device shown in FIG. 1 And FIG. 3 is a view showing an electric field profile pattern centered on the line AA 'in the power semiconductor device shown in FIG.

Power semiconductor devices must be of high voltage and high current for use and development purposes and should be robust. In order to form a strong breakdown voltage among the characteristics of a power semiconductor device, it is necessary to withstand a strong electric field not only in the vertical breakdown voltage but also in the horizontal direction. The active cell region takes a large internal pressure in the vertical direction in the semiconductor section, and the ring termination region takes a large internal pressure in the horizontal direction in the semiconductor section.

1 to 3, in a boundary region between an active cell region and a ring termination region, an isolation interval is narrow, and as a breakdown voltage is applied, a junction or a depletion region on both sides of the floating region, ) May cause an anomaly in current or voltage characteristics.

FIG. 4 is a graph showing the results of electric field measurements in the cross-sectional direction of line A-A 'in the power semiconductor device shown in FIG.

Referring to FIG. 4, in an area where electrons are not supplied in an on-state, the space charge balance is broken at the time of hole injection, and the electric field is increased by the hole charge . This is about 130000 V / cm level, and avalanche phenomenon is possible according to the three-dimensional curvature effect.

5 is a diagram illustrating a cross section of an area E1 including a boundary between an active cell region and a ring termination region in the power semiconductor device shown in FIG. In the structure shown in Fig. 5, the left side corresponds to the active cell region and the right side corresponds to the ring termination region.

Referring to FIG. 5, the power semiconductor device includes a gate electrode 50 disposed in a trench 20 of a substrate 1. In FIG. The power semiconductor device further includes a first conductive type body region 42 disposed on one side of the gate electrode 50 in the substrate 1 and a second conductive type body region 42 disposed on the gate electrode 50 in the first conductive type body region 42. [ And a source region 44 of a second conductivity type arranged adjacently.

The power semiconductor element includes a floating region 30b of the first conductivity type disposed on the other side of the gate electrode 50 in the substrate 1 and a floating region 30b of the first conductivity type in the substrate 1, An edge doped region 30c of the first conductivity type electrically connected to the source region 44 and a floating region 30b of the first conductivity type in the substrate 1 and an edge doped region 30c of the first conductivity type, And an edge junction isolation region 17 of a second conductivity type interposed between the source and drain regions.

Further, the power semiconductor device is disposed in the substrate 1 under the floating region 30b of the first conductivity type, the edge-doped region 30c of the first conductivity type, and the edge region 17 of the second conductivity type And a drift region 10 of the second conductivity type.

An edge doped region 30c of the first conductivity type is disposed in the ring termination region of the power semiconductor device. The edge doped region 30c of the first conductivity type is electrically connected to the source region 44 by the wiring pattern 68 disposed on the substrate 1. [ Thus, the edge doped region 30c is maintained at the source potential. An edge structure such as a field plate or a channel stopper may be provided between the edge doped region 30c and the edge of the substrate 1 although not shown in the figure.

A conductive pattern 64 electrically connected to the gate electrode 50 and a conductive pattern 69a electrically connected to the source region 44 and the body region 42 are formed on the substrate 1. [ The conductive pattern 69a serves as a contact, and can be electrically insulated with the insulating patterns 62 and 66 interposed therebetween. A collector electrode 76 is disposed under the substrate 1 and a buffer layer of a second conductivity type and / or a second conductivity type of the first conductivity type are formed before forming the collector electrode 76, Can be formed first.

Referring to FIG. 5, the floating region 30b, which is a P-type junction, and the edge doped region 30c are isolated by an N-type junction. However, as the density of the power semiconductor device increases, the width of the separated N-type junction becomes narrow and both junctions or depletion layers are brought into contact with each other, resulting in anomalies in current / voltage characteristics.

6 is a cross-sectional view of a region including a boundary between an active cell region and a ring termination region in a power semiconductor device according to an embodiment of the present invention. In the structure shown in Fig. 6, the left side corresponds to the active cell region and the right side corresponds to the ring termination region.

Referring to FIG. 6, the power semiconductor device includes a gate electrode 50 disposed in the trench 20 of the substrate 1. The gate electrode 50 may have a closed-type structure when viewed in plan view. For example, the element shown in Fig. 6 is a power semiconductor element of a closed cell type, and has a trench 20 structure closed on a section parallel to the upper surface 1s of the substrate 1, (50) may be implemented by filling the trench (20). The substrate 1 can be understood to mean a wafer and an epitaxially grown epitaxial layer on the wafer.

The power semiconductor device further includes a body region 42 of a first conductivity type disposed inside the gate electrode 50 constituting a closed cell in the substrate 1 and a body region 42 of a first conductivity type, And a source region 44 of a second conductivity type disposed adjacent to the gate electrode 50 in the second region 42.

The power semiconductor device includes a floating region 30b of a first conductivity type disposed outside the gate electrode 50 constituting a closed cell in the substrate 1, An edge doped region 30c of a first conductivity type electrically connected to the floating region 30b and electrically connected to the source region 44, a floating region 30b of the first conductivity type in the substrate 1, And an edge junction isolation region 17 of a second conductivity type interposed between the edge-doped regions 30c of the first conductivity type. Further, the power semiconductor device is disposed in the substrate 1 under the floating region 30b of the first conductivity type, the edge-doped region 30c of the first conductivity type, and the edge region 17 of the second conductivity type And a drift region 10 of the second conductivity type.

An edge doped region 30c of the first conductivity type is disposed in the ring termination region of the power semiconductor device. The edge doped region 30c of the first conductivity type is electrically connected to the source region 44 by the wiring pattern 68 disposed on the substrate 1. [ Thus, the edge doped region 30c is maintained at the source potential. An edge structure such as a field plate or a channel stopper may be provided between the edge doped region 30c and the edge of the substrate 1 although not shown in the figure.

A conductive pattern 64 electrically connected to the gate electrode 50 and a conductive pattern 69a electrically connected to the source region 44 and the body region 42 are formed on the substrate 1. [ The conductive pattern 69a serves as a contact, and can be electrically insulated with the insulating patterns 62 and 66 interposed therebetween. A collector electrode 76 is disposed under the substrate 1 and a buffer layer of a second conductivity type and / or a second conductivity type of the first conductivity type are formed before forming the collector electrode 76, Can be formed first.

Referring to FIG. 6, the floating region 30b, which is a P-type junction, and the edge doped region 30c are isolated by an N-type junction. The second conductivity type doping concentration N2 of the edge junction region 17 formed between the first conductivity type floating region 30b and the first conductivity type edge doping region 30c is greater than the second conductivity type doping concentration N2 of the drift region 10. [ 2 < / RTI > conductivity type doping concentration. According to this structure, the maximum electric field can be formed below the center depth of the thickness in the vertical direction of the first-conductivity-type floating region 30b and the edge doped region 30c. The charge balance may be adjusted such that the maximum electric field falls to the bottom of the floating region 30b and the edge doped region 30c.

In this case, in the power semiconductor device having this configuration, the maximum electric field is not formed on the upper surface 1s of the substrate 1 but is formed in the floating region 30b and the lower end portion of the edge doped region 30c, It is possible to improve the internal pressure reduction phenomenon of the separation region due to the dynamic electric field change caused by the change of the electric field. That is, the conventional isolation structure has a structure in which the dynamic breakdown voltage due to the Hall current is lowered in the IGBT switching state, whereas the isolation structure of the present invention uses the junction using the charge sharing effect to improve robustness and space efficiency It is possible to obtain an advantageous effect that can be secured.

On the other hand, in the present invention, the oxide pattern 77 is buried in the substrate of the insulating region for electrically separating the active cell region and the ring termination region from the above-described structure, It is possible to prevent the occurrence of an anomaly in the current / voltage characteristic since both junctions or depletion layers are brought into contact with each other in a situation where the width is narrowed. That is, by introducing the oxide pattern 77 between the floating region 30b of the first conductivity type and the edge doped region 30c of the first conductivity type, the floating region 30b of the first conductivity type and the floating region 30b of the first conductivity type, The diffusion of the first conductive impurity can be prevented between the edge doped region 30c.

Power semiconductor devices must be of high voltage and high current for use and development purposes and should be robust. In order to form a strong breakdown voltage among the characteristics of a power semiconductor device, it is necessary to withstand a strong electric field not only in the vertical breakdown voltage but also in the horizontal direction. The active cell region takes a large internal pressure in the vertical direction in the semiconductor section, and the ring termination region can take a large internal pressure in the horizontal direction in the semiconductor section. In order to accomplish this, the present invention is characterized in that a floating region 30b of a first conductivity type and a floating region 30b of a first conductivity type are formed in order to reinforce the insulation portion. The oxide pattern 77 is inserted between the edge-doped regions 30c of the first conductivity type to prevent the diffusion of both the first conductivity-type regions.

According to another aspect of the present invention, there is provided a power semiconductor device including: a power semiconductor device having a first region having a higher vertical breakdown voltage than a horizontal breakdown voltage and a second region having a higher horizontal breakdown voltage than the vertical breakdown voltage, And an oxide pattern 77 for preventing the diffusion of the first conductive impurity between the first conductive type regions arranged apart from each other.

Meanwhile, the above-mentioned oxide pattern 77 is not implemented as a gap filling process for filling a trench, but is implemented as a process of first depositing and patterning an oxide layer and then filling an oxide pattern with an epilayer, thereby overcoming various problems of the gapfil process A detailed description thereof will be given later.

7 is a plan view schematically illustrating a configuration of a region including a boundary between an active cell region and a ring termination region in a power semiconductor device according to an embodiment of the present invention. In the structure shown in Fig. 7, the left side corresponds to the active cell region and the right side corresponds to the ring termination region.

Referring to FIGS. 6 and 7, a plurality of closed cells are arrayed in the left active cell area. In each of the closed cells, a gate electrode 50 is formed, and a first contact pattern 69a is disposed in the gate electrode 50. And a second contact pattern 69b electrically connected to the edge doped region 30c of the first conductivity type is disposed in the ring termination region on the right side. An oxide pattern (77) is disposed in an insulating region for electrically separating the active cell region and the ring termination region. The ring termination region has a shape surrounding the rim of the active cell region, and the oxide pattern 77 may also have a shape surrounding the rim of the active cell region. Only a part of the oxide pattern 77 surrounding the rim of the active cell region is shown in Fig.

8 to 15 are views sequentially illustrating a method of manufacturing a power semiconductor device according to an embodiment of the present invention.

First, referring to FIG. 8, a first conductive impurity and a second conductive impurity are implanted on predetermined regions on the wafer. For example, a first conductivity type barrier (PBL) 31 is formed by implanting an impurity of the first conductivity type into the region I, the region III and the region V, The impurity of the second conductivity type is injected to form the second conductivity type barrier (NBL) 11. The concentration of the impurity of the second conductivity type injected into the region (II) and the region (IV) may be higher than the concentration of the second conductivity type dopant contained in the wafer.

Subsequently, referring to FIG. 9, an oxide pattern 77 is formed on the region IV into which the impurity of the second conductivity type is implanted. The oxide pattern 77 may be implemented by a deposition process and a patterning process. The oxide pattern 77 may be made of, for example, silicon oxide (SiO ₂ ).

Referring to FIG. 10, an epitaxial layer B is formed on the wafer so as to cover the wafer (A) and the oxide pattern 977). An epitaxial layer B is formed on the wafer A to form the substrate 1 made of the wafer A and the epitaxial layer B. [ The oxide pattern 77 is first embedded and the epitaxial layer B is formed so that the oxide pattern 77 is embedded in the substrate 1. [ If the trench pattern is formed in the substrate 1 and the trench pattern is filled with oxide, the chamber may be contaminated in the process of etching the trench pattern. In this case, the process of tapping the trench pattern into oxide Voids may be generated in the insulating layer, resulting in insufficient insulation. The present invention overcomes these problems by first implementing the oxide pattern 77 and forming the epilayer (B).

11, after grinding the plane of the epi-layer B protruded by the oxide pattern 77, an additional first conductive type doping region RING 33 is formed by implanting an impurity of the first conductivity type And an impurity of the second conductivity type is injected to form an additional second conductive type doped region (JFET) 13. [

Referring to FIG. 12, a trench 20 is formed in the active cell region and the gate electrode 50 is formed by filling the electrode material. Subsequently, an impurity of the first conductivity type is self-aligned to form a first conductive type doped region (Pbase) 35.

Referring to FIG. 13, after polysilicon is deposited, a predetermined region is etched to form a gate wiring 64, and further, an ion implantation process is performed to form a source region 44 or the like.

Referring to FIG. 14, an activation process through heat treatment is performed to diffuse impurities to complete the doping region. For example, the first conductive type doped region (Pbase) 35 and the first conductive type doped region (PBL) 31 constitute the floating region 30a of the first conductive type in FIG. 6, The doping region RING 33 of the first conductivity type and the doping region PBL 31 of the first conductivity type are the same as the floating region 30b of the first conductivity type and the edge doping region 30c of the first conductivity type, .

15, contact patterns 69a and 69b may be formed, a wiring pattern 68 may be formed, and a collector electrode 76 may be formed below the substrate 1. In this case, Although not shown in the drawing, a buffer layer of a second conductive type and / or a collector layer of a first conductive type may be formed before the collector electrode 76 is formed.

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the invention. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

1: substrate
10: drift region
20: trench
30a, 30b: Floating area
30c: edge doped region
42: Body area
44: source region
50: gate electrode
17: Edge junction separation area
77: oxide pattern

Claims (9)

An active cell region formed in one region of the substrate;
A ring termination region formed in another region of the substrate and adjacent to the active cell region; And
And an insulation region electrically isolating the active cell region and the ring termination region from each other,
Wherein the insulating region comprises an oxide pattern embedded in the substrate,
Further comprising a floating region of a first conductive type formed at the edge of the active cell region with the insulating region interposed therebetween and a first conductive type edge doped region formed in the ring termination region,
Further comprising an edge region of a second conductivity type between the floating region of the first conductivity type and the edge doping region of the first conductivity type,
Wherein the insulating region region is formed between the floating region of the first conductivity type and the edge doping region of the first conductivity type and is buried and spaced apart from the substrate surface by a predetermined distance below the edge region of the second conductivity type, Semiconductor device. The method according to claim 1,
Wherein the oxide pattern formed in the insulating region includes an oxide pattern that prevents diffusion of the first conductive impurity between the floating region of the first conductive type and the edge doped region of the first conductive type. delete The method according to claim 1,
Wherein the ring termination region has a shape surrounding the rim of the active cell region. The method according to claim 1,
Wherein the first conductivity type and the second conductivity type are opposite to each other and are either p-type or n-type. A first region of the power semiconductor element having a higher vertical breakdown voltage than a horizontal breakdown voltage and a second region having a higher horizontal breakdown voltage than the vertical breakdown voltage, the floating region of the first conductivity type formed in the first region, And an oxide pattern for preventing diffusion of the first conductivity type impurity between the edge-doped regions of the first conductivity type formed in the first-
Further comprising an edge region of a second conductivity type between the floating region of the first conductivity type and the edge doping region of the first conductivity type,
Wherein the oxide pattern is buried and spaced apart from the substrate surface by a predetermined distance below the edge region of the second conductivity type between the floating region of the first conductivity type and the edge doping region of the first conductivity type,
Power semiconductor device. A first step of implanting impurities of a first conductivity type and a second conductivity type on predetermined regions on the wafer;
A second step of forming an oxide pattern on any one region for implanting the impurity of the second conductivity type;
A third step of forming a substrate composed of the wafer and the epi layer by forming an epitaxial layer on the wafer so as to cover the wafer and the oxide pattern;
A fourth step of implanting a first conductive impurity through the surface of the epi layer to correspond to a region where the first conductive impurity is implanted in the first step; And
A fifth step of forming a floating region of a first conductive type and a first conductive type edge doped region spaced apart from each other on both sides with reference to the oxide pattern in the substrate by diffusing the impurity;
, ≪ / RTI &
And the second step includes forming the oxide pattern so as to be located in an insulating region region electrically separating between the active cell region and the ring termination region of the power semiconductor element. 8. The method of claim 7,
The concentration of the impurity of the second conductivity type injected in the first step is higher than the concentration of the second conductivity type contained in the wafer,
Forming an edge region of a second conductivity type between the floating region of the first conductivity type and the edge doping region of the first conductivity type by performing the third step and the fifth step, Gt; A first region of the power semiconductor element having a higher vertical breakdown voltage than a horizontal breakdown voltage and a second region having a higher horizontal breakdown voltage than the vertical breakdown voltage, the floating region of the first conductivity type formed in the first region, Doped regions of the first conductivity type formed between the first conductive type impurity region and the second conductive type impurity region. The oxide pattern is formed not by the capping process of filling the trench, but by depositing and patterning the oxide layer, Wherein the step of forming the semiconductor layer is embodied as a step of embedding the semiconductor layer into the semiconductor layer.

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