KR101870826B1 - Power semiconductor device and method of fabricating the same - Google Patents

Abstract

The present invention provides a semiconductor device comprising: a pair of gate electrodes disposed in a first trench and a second trench, respectively, spaced apart from each other in a substrate; A pair of first conductivity type floating regions spaced from each other and surrounding the bottom surface and at least one side surface of the first trench and the second trench in the substrate, respectively; A pair of switching loss prevention planar electrodes formed on the upper surface of the substrate, the pair of switching loss prevention planar electrodes formed on the pair of first conductivity type floating regions, respectively, and isolated from the gate electrode; And an insulating film interposed between the sidewall of the trench and the gate electrode and between the floating electrode and the floating electrode for preventing switching loss, respectively.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor device,

The present invention relates to a power semiconductor device and a manufacturing method thereof, and more particularly, to an insulated gate bipolar transistor (IGBT) device and a manufacturing method thereof.

Insulated Gate Bipolar Transistor (IGBT) is a crystalline material of MOS (Metal Oxide Silicon) and bipolar technology. It is characterized by low forward loss and high speed. It is applicable to applications that can not be realized with thyristors, bipolar transistors and MOSFETs. And is a next generation power semiconductor device which is used in a high efficiency and high speed power system widely used in a voltage range of 300V or more. Since the development of power MOSFETs in the 1970s, MOSFETs have been used for switching devices requiring high-speed switching, and bipolar transistors, thyristors, and GTOs have been used in a range where a large amount of current conduction is required at medium to high voltages Has come. The IGBT developed in the early 1980s has a current capability of more than a bipolar transistor in terms of output characteristics and has a gate driving characteristic like a MOSFET in terms of input characteristics, so that switching at a high speed of about 100 KHz is possible. As a result, IGBTs are being used not only for replacement of MOSFETs, bipolar transistors, and thyristors, but also for new application systems.

A related prior art is Korean Laid-Open Publication No. 20140057630 (published on May 13, 2014, entitled IGBT and its manufacturing method).

It is an object of the present invention to provide a power semiconductor device capable of reducing switching loss and a method of manufacturing the same. However, these problems are exemplary and do not limit the scope of the present invention.

A power semiconductor device according to one aspect of the present invention for solving the above problems is provided. The power semiconductor device comprising: a pair of gate electrodes each disposed in a first trench and a second trench spaced apart from each other in a substrate; A pair of first conductivity type floating regions spaced from each other and surrounding the bottom surface and at least one side surface of the first trench and the second trench in the substrate, respectively; A pair of switching loss prevention planar electrodes formed on the upper surface of the substrate, the pair of switching loss prevention planar electrodes formed on the pair of first conductivity type floating regions, respectively, and isolated from the gate electrode; And an insulating film interposed between the sidewall of the trench and the gate electrode, and between the floating electrode for preventing switching loss and the floating region, respectively.

The power semiconductor device may further include an emitter metal pattern disposed on the gate electrode and the switching loss prevention planar electrode, wherein one end of the switching loss prevention planar electrode is connected to the emitter metal pattern Can be bonded.

The power semiconductor device may further include an insulating pattern interposed between the other end of the switching loss prevention flat electrode and the emitter metal pattern and between the gate electrode and the emitter metal pattern, And may be extended to reach the floating region while filling a gap between the planar electrode for preventing the switching loss and the gate electrode.

In the power semiconductor device, the insulating film interposed between the sidewall of the trench and the gate electrode and the insulating film interposed between the floating electrode and the floating electrode are made of the same material and may have the same thickness.

The power semiconductor device comprising: a body region of a first conductivity type disposed between the first trench and the second trench in the substrate; And a second conductivity type drift region extending from the pair of first conductivity type floating regions in the substrate to the body region of the first conductivity type through the pair of first conductivity type floating regions, Area. ≪ / RTI >

In the power semiconductor device, the capacitance formed between the floating region and the floating region by the capacitance formed between the floating electrode and the floating region reduces the ratio of the capacitance formed between the floating region and the drift region to the gate channel capacitance Cgc have.

In the power semiconductor device, the switching loss prevention planar electrode may include polysilicon.

In the power semiconductor device, a maximum doping depth of the first conductive type body region is shallower than a depth of the first trench and the second trench, and a maximum doping depth of the first conductive type floating region And may be deeper than the depth of the trench and the second trench.

In the power semiconductor device, the second conductivity type and the first conductivity type have opposite conductivity types, and may be any one of n-type and p-type.

A method for manufacturing a power semiconductor device according to another aspect of the present invention for solving the above problems is provided. The method for manufacturing a power semiconductor device includes the steps of implanting a first conductivity type impurity into a first region of a wafer and implanting a second conductivity type impurity at a concentration higher than a second conductivity type doping concentration contained in the wafer in a second region of the wafer, ; Forming an epilayer on the wafer; Forming a first trench and a second trench spaced apart from each other in a region including a boundary of the first region and the second region while removing a portion of the epilayer; Forming a pair of first conductivity type floating regions spaced apart from each other by surrounding the bottom surface and at least one side surface of the first trench and the second trench by diffusing the impurities, Forming at least a portion of a drift region of a second conductivity type from below the floating region to the region between the pair of first conductivity type floating regions; Lining the inner walls of the first trench and the second trench with an insulating film and filling the gate electrode material to form a gate electrode; Forming a pair of switching loss prevention planar electrodes formed on the pair of first conductivity type floating regions and spaced apart from and spaced apart from the gate electrode through an insulating film on an upper surface of the substrate; .

The method for manufacturing a power semiconductor device according to claim 1, further comprising forming an emitter metal pattern disposed on the gate electrode and the switching loss prevention flat electrode, wherein one end of the switching loss prevention flat electrode And can be bonded to the emitter metal pattern.

The manufacturing method of the power semiconductor device may further include forming an insulating pattern interposed between the other end of the switching loss prevention flat electrode and the emitter metal pattern and between the gate electrode and the emitter metal pattern And the insulating pattern may be extended to reach the floating region while filling the space between the planar electrode for preventing switching loss and the gate electrode.

In the above method of manufacturing a power semiconductor device, the insulating film interposed between the sidewall of the trench and the gate electrode and the insulating film interposed between the floating electrode and the floating region are made of the same material and have the same thickness . In this case, the capacitance formed between the floating region and the floating region can reduce the ratio of the capacitance formed between the floating region and the drift region to the gate channel capacitance Cgc.

In the method of manufacturing the power semiconductor device, the step of forming the planar electrode for preventing switching loss may include forming a planar electrode for preventing switching loss, the planar electrode being made of polysilicon.

In the method of manufacturing the power semiconductor device, the second conductivity type and the first conductivity type may have any conductivity type opposite to that of the n type and the p type, respectively.

According to one embodiment of the present invention as described above, a power semiconductor device capable of reducing a switching loss and a manufacturing method thereof can be implemented. Of course, the scope of the present invention is not limited by these effects.

1 is a cross-sectional view illustrating a cell structure of a power semiconductor device according to an embodiment of the present invention.
2 is a plan view illustrating a cell structure layout of a power semiconductor device according to an embodiment of the present invention.
3 is a diagram illustrating an aspect of a capacitance formed in a power semiconductor device according to an embodiment of the present invention.
4 to 10 are cross-sectional views illustrating a method of manufacturing a power semiconductor device according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The embodiments of the present invention are described in order to more fully explain the present invention to those skilled in the art, and the following embodiments may be modified into various other forms, It is not limited to the embodiment. Rather, these embodiments are provided so that this disclosure will be more thorough and complete, and will fully convey the concept of the invention to those skilled in the art. In the drawings, the thickness and size of each layer are exaggerated for convenience and clarity of explanation.

It is to be understood that throughout the specification, when an element such as a film, region or substrate is referred to as being "on", "connected to", "laminated" or "coupled to" another element, It is to be understood that elements may be directly "on", "connected", "laminated" or "coupled" to another element, or there may be other elements intervening therebetween. On the other hand, when one element is referred to as being "directly on", "directly connected", or "directly coupled" to another element, it is interpreted that there are no other components intervening therebetween do. Like numbers refer to like elements. As used herein, the term "and / or" includes any and all combinations of one or more of the listed items.

Although the terms first, second, etc. are used herein to describe various elements, components, regions, layers and / or portions, these members, components, regions, layers and / It is obvious that no. These terms are only used to distinguish one member, component, region, layer or section from another region, layer or section. Thus, a first member, component, region, layer or section described below may refer to a second member, component, region, layer or section without departing from the teachings of the present invention.

Also, relative terms such as "top" or "above" and "under" or "below" can be used herein to describe the relationship of certain elements to other elements as illustrated in the Figures. Relative terms are intended to include different orientations of the device in addition to those depicted in the Figures. For example, in the figures the elements are turned over so that the elements depicted as being on the top surface of the other elements are oriented on the bottom surface of the other elements. Thus, the example "top" may include both "under" and "top" directions depending on the particular orientation of the figure. If the elements are oriented in different directions (rotated 90 degrees with respect to the other direction), the relative descriptions used herein can be interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the" include singular forms unless the context clearly dictates otherwise. Also, " comprise "and / or" comprising "when used herein should be interpreted as specifying the presence of stated shapes, numbers, steps, operations, elements, elements, and / And does not preclude the presence or addition of one or more other features, integers, operations, elements, elements, and / or groups.

Hereinafter, embodiments of the present invention will be described with reference to the drawings schematically showing ideal embodiments of the present invention. In the figures, for example, variations in the shape shown may be expected, depending on manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention should not be construed as limited to the particular shapes of the regions shown herein, but should include, for example, changes in shape resulting from manufacturing.

FIG. 1 is a cross-sectional view illustrating a cell structure of a power semiconductor device according to an embodiment of the present invention, and FIG. 2 is a plan view illustrating a cell structure layout of a power semiconductor device according to an embodiment of the present invention.

The cell structure of the power semiconductor device according to an embodiment of the present invention shown in FIG. 1 corresponds to a cross-sectional structure taken along the line A-A 'shown in FIG.

Referring to FIGS. 1 and 2, a power semiconductor device 100 according to an embodiment of the present invention includes a first trench 20a and a second trench 20b, which are disposed in a first trench 20a and a second trench 20b, And a pair of gate electrodes 50a and 50b.

Here, the substrate 1 can be understood as meaning a wafer and an epitaxial layer epitaxially grown on the wafer. The substrate 10 may be classified as a silicon (Si), a silicon carbide (SiC), a gallium nitride (GaN), a diamond, a gallium oxide or the like. However, It is not.

A power semiconductor device 100 according to an embodiment of the present invention includes a body region 42 of a first conductive type disposed between a first trench 20a and a second trench 20b in a substrate 1, And a pair of source regions 44a and 44b of a second conductivity type disposed adjacent to and spaced from each other in the first trench 20a and the second trench 20b in the body region 42 of the first conductive type.

The power semiconductor device 100 according to an embodiment of the present invention includes a floating region 30a of the first conductivity type surrounding the bottom surface and at least one side surface of the first trench 20a in the substrate 1 And a pair of first conductivity type floating regions (30a, 30b) are formed on the surface of the first trench (20b), and the floating region (30b) of the first conductivity type surrounding the bottom surface and at least one side surface of the first trench (1).

The depth to the bottom surface of the floating regions 30a and 30b with respect to the top surface 1s of the substrate 1 is deeper than the depth to the bottom surface of the first trench 20a and the second trench 20b. That is, the maximum doping depth of the floating regions 30a and 30b of the first conductivity type may be deeper than the depth of the first trench 20a and the second trench 20b.

The power semiconductor device 100 according to an embodiment of the present invention includes a pair of first conductivity type floating regions 30a and 30b from a pair of first conductivity type floating regions 30a and 30b in the substrate 1, And a second conductivity type drift region 10 that extends between the regions 30a and 30b and extends to the body region 42 of the first conductivity type.

On the other hand, for example, in the drift region 10, the second conductivity type doping concentration N1 between the pair of the first conductivity type floating regions 30a and 30b is a pair of the first conductivity type floating regions 30a, 30b) of the second conductivity type doping concentration (N2).

On the other hand, the maximum doping depth of the body region 42 of the first conductive type is shallower than the depth of the first trench 20a and the second trench 20b, and the depth of the floating regions 30a and 30b of the first conductivity type The maximum doping depth may be deeper than the depth of the first trench 20a and the second trench 20b. Here, the second conductivity type doping concentration between the pair of the first conductivity type floating regions 30a and 30b in the drift region 10 and between the first trench 20a and the second trench 20b is a pair May be relatively higher than the second conductivity type doping concentration below the floating regions 30a and 30b of the first conductivity type.

A pair of switching loss preventing planar electrodes 52a and 52b formed on the upper surface 1s of the substrate 1 and formed on the floating regions 30a and 30b of the first conductivity type are connected to the gate electrodes 50a and 50b And is electrically insulated.

For example, the switching loss preventing planar electrode 52a is spatially separated by the spacing space 51 from the gate electrode 50a, and covers a part of the switching loss preventing flat electrode 52a and the gate electrode 50a The planar electrode 52a for preventing the switching loss and the gate electrode 50a are electrically insulated from each other by extending the insulation pattern 66 formed so as to reach the floating region 30a while filling the space 51. [

Likewise, the switching loss preventing planar electrode 52b is spatially separated by the spacing space 51 from the gate electrode 50b and is formed so as to cover a part of the switching loss preventing flat electrode 52b and the gate electrode 50b The insulating pattern 66 is extended to reach the floating region 30b while filling the spacing space 51 so that the switching loss preventing flat electrode 52b and the gate electrode 50b are electrically insulated.

The switching loss preventing planar electrodes 52a and 52b may include polysilicon. Unlike the trench gate electrodes 50a and 50b extending in the direction perpendicular to the upper surface 1s of the substrate 1, the planar electrodes extend in a direction parallel to the upper surface 1s of the substrate 1 .

An emitter metal pattern 68 is disposed on the gate electrodes 50a and 50b and the switching loss preventing planar electrodes 52a and 52b. The emitter metal pattern 68 may form at least a portion of the emitter electrode and / or emitter wiring pattern, the contact pattern. The emitter metal pattern 68 is bonded to one end of the switching loss preventing planar electrodes 52a and 52b. In this case, the other ends of the switching loss preventing planar electrodes 52a and 52b are spatially separated from the gate electrode 50b by the spacing space 51. [

2 corresponds to a part of the emitter metal pattern 68, and the first point P1 shown in FIG. 2 corresponds to a part of the emitter metal pattern 68 shown in FIG. The sixth point P6 corresponds to a portion to be bonded to the planar electrodes 52a and 52b and the sixth point P6 corresponds to a portion to be bonded to the body region 42 of the first conductivity type among the emitter metal patterns 68 shown in Fig. .

The red region shown in Fig. 2 corresponds to a part of the conductive pattern in contact with the insulating film 40 disposed on the upper surface 1s of the substrate 1, and the second point P2 shown in Fig. 2 The fourth point P4 corresponds to the switching loss preventing planar electrodes 52a and 52b shown in FIG. 1 and is connected to the gate electrodes 50a and 50b shown in FIG. 1 to correspond to the upper surfaces 1s ) Of the conductive pattern.

The black region shown in FIG. 2 corresponds to a region for electrically insulating between the switching loss preventing planar electrodes 52a and 52b and the gate electrodes 50a and 50b, and the third point P3 shown in FIG. May correspond to the insulation pattern 66 filling the spacing space 51 to the spacing space 51 shown in FIG.

The gray regions shown in Fig. 2 correspond to the gate electrodes 50a and 50b formed in the trenches 20a and 20b.

An insulating film 40 is interposed between the side walls of the trenches 20a and 20b and the gate electrodes 50a and 50b and between the switching loss preventing planar electrodes 52a and 52b and the first conductivity type floating regions 30a and 30b .

The insulating film 40 interposed between the sidewalls of the trenches 20a and 20b and the gate electrodes 50a and 50b and the switching loss preventing flat electrodes 52a and 52b and the floating regions 30a and 30b of the first conductivity type The insulating layer 40 may be made of the same material and may have the same thickness.

A collector electrode 72 is disposed under the substrate 1 and a buffer layer of a second conductivity type and / or a first conductive type layer of a second conductivity type are formed before forming the collector electrode 72, Can be formed first.

3 is a diagram illustrating an aspect of a capacitance formed in a power semiconductor device according to an embodiment of the present invention.

1 to 3 together show the capacitance formed between the switching loss preventing planar electrodes 52a and 52b and the first conductivity type floating regions 30a and 30b in the power semiconductor device 100 having the above- The ratio of the capacitance formed between the first conductivity type floating regions 30a and 30b and the second conductivity type drift region 10 to the gate channel capacitance Cgc can be reduced.

The thickness of the insulating film 40 under the switching loss preventing planar electrodes 52a and 52b is made equal to the thickness of the insulating film 40 interposed between the side walls of the trenches 20a and 20b and the gate electrodes 50a and 50b A third capacitance C _C is formed between the switching loss prevention flat electrodes 52a and 52b and the first conductivity type floating regions 30a and 30b.

A second capacitance C _B is formed between the floating regions 30a and 30b of the first conductivity type and the gate electrodes 50a and 50b and the gate electrodes 50a and 50b A first capacitance C _A is formed between the drift region 10 of the first conductivity type and the drift region 10 of the second conductivity type and a first capacitance C _A is formed between the drift region 10 of the second conductivity type and the floating region 30a, A fourth capacitance C _D may be formed.

In this case, the value of the gate channel capacitance Cgc forming the Miller capacitance is the sum of the value of the capacitor due to the series connection of the second capacitance C _B and the fourth capacitance C _D and the value of the first capacitance C _A , . On the other hand, the third capacitance (C _C) formed by the third capacitance (C _C) and a fourth capacitance (C _D) is connected in series with the second capacitance, the fourth capacitance connected in series with the (C _B) (C _D) Only the gate channel capacitance Cgc may be included in the entire gate capacitance Cgc, thereby reducing the value of the total gate channel capacitance Cgc. As the value of the gate channel capacitance (Cgc) decreases, E _on (turn on transition switching loss) can be reduced. The larger the third capacitance (C _C ) is, the smaller the E _on (turn on transition switching loss) is.

Since the conventional power semiconductor device having no structure as described above causes injection enhancement, E _on (turn on transition switching loss) is increased due to an increase of the gate channel capacitance Cgc due to the formation of the blocking region .

On the other hand, as another issue, in the power semiconductor device 100 according to the embodiment of the present invention, the second conductivity type doping concentration (concentration) distributed in the space 14 between the pair of first conductivity type floating regions 30a and 30b The doping concentration N1 is relatively higher than the second conductivity type doping concentration N2 distributed below the first conductivity type floating regions 30a and 30b so that the distance between the trenches 20a and 20b It is possible to enhance the robustness by forming a balance of N1 and P1 so that a base current supply path is formed and a rich base current is supplied and a maximum electric field is formed on the E side.

That is, when the distance between the trenches in the G direction MOSFET for supplying the base current of the IGBT is reduced, the phenomenon that the first conduction type impurities of the floating regions 30a and 30b are diffused and the base current path is limited is formed by forming the N1 region Can be improved. Further, according to the configuration of the power semiconductor device 100 according to an embodiment of the present invention, when assuming the same transconductance, a high cell density is formed with a narrower distance to reduce the current density in the G section at the same total current The short circuit characteristic can be improved by mitigating the local temperature rise.

The IGBT resistance and the short circuit characteristics are improved by this principle and the total amount of charges of the second conductivity type impurity concentration N1 of the region 14 and the first conductivity type impurity concentration P1 of the floating regions 30a and 30b So that the maximum electric field is formed on the E-plane, so that the robustness can be improved. Here, E plane on which the maximum electric field G2 is formed is lower than the bottom surface of the trenches 20a and 20b. On the other hand, in the modified embodiment, the surface on which the maximum electric field G3 is formed may have the same height as the bottom surface of the floating regions 30a and 30b.

When the relationship between the electric field and the charge amount in the static state in the N-type depletion at the time of voltage application is simplified to one dimension in the C direction, it can be regarded as a function of only N doping with dE / dx = (1 / When the carrier is injected during operation, the charge is changed by dE / dx = (1 / ε) * (n + he) due to the amount of charge injected. When the hole density in the turn- In the structure of the present invention, the electric field change rate between the bottom surface of the trenches 20a and 20b and the bottom surface of the body region 42 is lower than the electric field change rate between the bottom surface of the trenches 20a and 20b and the bottom surface of the body region 42. However, By making the negative interval, the decrease of the dynamic breakdown voltage is alleviated by the increase of the electric field area when the slope of the electric field increases.

4 to 10 are cross-sectional views illustrating a method of manufacturing a power semiconductor device according to an embodiment of the present invention.

4 and 5, a first conductivity type impurity is implanted (P1 implant) into a first region I on a wafer A and the wafer A is implanted into a second region II of the wafer A (N1 Implant) a second conductivity type impurity at a concentration higher than that of the second conductivity type doping concentration.

Referring to FIG. 6, an epitaxial layer B is formed on the wafer A. The substrate 1 may be understood to include a wafer A and an epitaxial layer B epitaxially grown on the wafer. It is possible to perform a doping process in which an additional impurity is implanted through the upper surface of the epi layer B after the epi layer B is grown.

7, a part of the epi-layer B is removed, and a first trench 20a and a second trench 20b, which are spaced apart from each other in an area including a boundary of the first area I and the second area II, (20b) can be formed.

Referring to FIG. 8, the first and second trenches 20a and 20b are doped with impurities of a first conductivity type and a second conductivity type, respectively, through a diffusion process such as heat treatment. A pair of first conductivity type floating regions 30a and 30b which are spaced apart from each other and surround the side surfaces can be formed. The drift region 10 of the second conductivity type extending from below the pair of first conductivity type floating regions 30a and 30b to the region between the pair of first conductivity type floating regions 30a and 30b At least a part of which can be formed. In this case, the lower part of the floating regions 30a and 30b of the first conductivity type may include the interface F between the wafer A and the epi layer B. [

Referring to FIG. 9, impurities are implanted into the region between the first trench 20a and the second trench 20b to form a first conductive type body region 42 and a first conductive type body region 42 A pair of source regions 44a and 44b of a second conductivity type disposed adjacent to and spaced apart from the first trench 20a and the second trench 20b may be formed. Subsequently, the inner walls of the first trench 20a and the second trench 20b may be lined with an insulating film and filled with a gate electrode material to form the gate electrodes 50a and 50b. The insulating layer may extend not only to the inner walls of the first trench 20a and the second trench 20b but also to the upper surface of the substrate 1. [ The gate electrode material filling the first trench 20a and the second trench 20b to form the gate electrodes 50a and 50b may be formed to extend not only to the space in the trench but also to the top surface of the substrate 1 .

Referring to FIG. 10, a space 51 is formed by etching a part of the insulating film and the gate electrode material on the upper surface of the substrate 1. The floating regions 30a and 30b of the first conductivity type can be exposed through the spacing space 51. [ The gate electrodes 50a and 50b and the switching loss prevention flat electrodes 52a and 52b are spatially separated by the formed spacing space 51. [

11, an insulating pattern 66 is formed so as to fill the spacing spaces 51 while covering the switching electrodes 52a and 52b and the gate electrodes 50a and 50b. The insulating pattern 66 may be formed such that one end of the switching loss prevention flat electrodes 52a and 52b is exposed and the body region 42 is exposed.

Subsequently, by forming the emitter metal pattern 68 on one end of the exposed planar electrodes 52a and 52b, the insulating pattern 66, and the exposed body region 42, Thereby realizing the power semiconductor device 100 according to one embodiment of the present invention.

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the invention. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

1: substrate
10: drift region
20a and 20b: trenches
30a, 30b: Floating area
40: Insulating film
42: Body area
44: source region
50a, 50b: gate electrode
51: Spacing space
52a and 52b: planar electrodes for preventing switching loss
66: Insulation pattern
68: Emitter metal pattern

Claims (11)

A pair of gate electrodes respectively disposed in the first trench and the second trench spaced apart from each other in the substrate;
A pair of first conductivity type floating regions spaced from each other and surrounding the bottom surface and at least one side of the first trench and the second trench in the substrate, respectively;
A pair of switching loss prevention planar electrodes formed on the upper surface of the substrate, the pair of switching loss prevention planar electrodes formed on the pair of first conductivity type floating regions, respectively, and isolated from the gate electrode;
An insulating film interposed between the sidewalls of the first trench and the second trench and the gate electrode and between the floating electrode for preventing switching loss and the floating region, respectively;
A body region of a first conductivity type disposed between the first trench and the second trench in the substrate; And a second conductivity type drift region extending from the pair of first conductivity type floating regions in the substrate to the body region of the first conductivity type through the pair of first conductivity type floating regions, domain;
/ RTI >
And a second conductivity type doping concentration (N1) between the pair of first conductivity type floating regions in the drift region and between the first trench and the second trench, And a surface on which a maximum electric field is formed in a cross section perpendicular to a path (G) passing between the pair of first conductivity type floating regions up and down ( E) is lower than the bottom surface of the first trench and the bottom surface of the second trench.
Power semiconductor device. The method according to claim 1,
And an emitter metal pattern disposed on the gate electrode and the switching loss prevention planar electrode,
And one end of the switching loss prevention flat electrode is bonded to the emitter metal pattern. 3. The method of claim 2,
And an insulating pattern interposed between the other end of the switching loss prevention flat electrode and the emitter metal pattern and between the gate electrode and the emitter metal pattern,
Wherein the insulating pattern is elongated to reach the floating region while filling a spacing space between the planar electrode for preventing switching loss and the gate electrode. The method according to claim 1,
The insulating film interposed between the first trench and the sidewall of the second trench and the gate electrode and the insulating film interposed between the floating electrode and the floating electrode are made of the same material and have the same thickness To the power semiconductor device. delete The method according to claim 1,
Characterized in that the capacitance formed between the floating region and the floating region by the capacitance formed between the floating electrode and the floating region reduces the ratio of the capacitance formed between the floating region and the drift region to the gate channel capacitance Cgc. device. The method according to claim 1,
Wherein the switching loss prevention planar electrode comprises polysilicon. The method according to claim 1,
Wherein a maximum doping depth of the first conductive type body region is shallower than a depth of the first trench and the second trench and a maximum doping depth of the first conductive type floating region is greater than a doping maximum depth of the first trench and the second trench, Deeper than the depth of the power semiconductor device. The method according to claim 1,
Wherein the second conductivity type and the first conductivity type are of opposite conductivity types and are any one of an n type and a p type. Implanting a first conductivity type impurity into a first region on a wafer and implanting a second conductivity type impurity at a concentration higher than a second conductivity type doping concentration contained in the wafer in a second region of the wafer;
Forming an epitaxial layer on the wafer, thereby forming a substrate including the wafer and the epitaxial layer;
Forming a first trench and a second trench spaced apart from each other in a region including a boundary of the first region and the second region while removing a portion of the epilayer;
Forming a pair of first conductivity type floating regions spaced apart from each other by surrounding the bottom surface and at least one side surface of the first trench and the second trench by diffusing the impurities, Forming at least a portion of a drift region of a second conductivity type from below the floating region to the region between the pair of first conductivity type floating regions;
Lining the inner walls of the first trench and the second trench with an insulating film and filling the gate electrode material to form a gate electrode;
Forming a pair of switching loss prevention planar electrodes formed on the pair of first conductivity type floating regions and spaced apart from and spaced apart from the gate electrode through an insulating film on an upper surface of the substrate;
Gt; wherein < / RTI > 11. The method of claim 10,
And forming an emitter metal pattern disposed on the gate electrode and the switching loss prevention planar electrode,
And one end of the switching loss prevention flat electrode is bonded to the emitter metal pattern.

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