KR102019852B1 - Power semiconductor device and method of fabricating the same - Google Patents

Abstract

The present invention relates to a power semiconductor device capable of securing switching stability and short circuit robustness and a manufacturing method thereof. A power semiconductor device according to the present invention comprises: a trench type gate electrode disposed in a substrate; a first conductive type body region disposed on one side of the gate electrode in the substrate; an oxide pattern disposed on the other side of the gate electrode in the substrate; a first conductive type floating region disposed under the oxide pattern to be in contact with the oxide pattern and extended to the bottom of the gate electrode; a second conductive type drift region extended from the lower part of the floating region to the lower part of the body region in the substrate; and a collector electrode disposed under the substrate.

Description

Power semiconductor device and method of fabricating the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor device and a method of manufacturing the same, and more particularly, to an insulated gate bipolar transistor (IGBT) device and a method of manufacturing the same.

Insulated Gate Bipolar Transistors (IGBTs) are crystals of MOS (Metal Oxide Silicon) and bipolar technologies that feature low forward loss and high speed, making them ideal for applications such as thyristors, bipolar transistors and MOSFETs. This is a next generation power semiconductor device that is widely used and is essential for high efficiency, high speed power system widely used in the voltage range of 300V or higher. Since the development of power MOSFETs in the 1970s, switching devices have used MOSFETs in a range requiring high-speed switching, and bipolar transistors, thyristors, GTO, etc. have been used in a range requiring large current conduction at medium to high voltages. . Developed in the early 1980s, IGBTs have more current capability than bipolar transistors in terms of output characteristics, and gate drive characteristics like MOSFETs in terms of input characteristics, enabling fast switching at around 100KHz. As a result, IGBTs are creating new application systems as well as replacements for MOSFETs, bipolar transistors, and thyristors, and are therefore increasingly used in industrial and home electronics.

Related prior arts are Republic of Korea Publication No. 20140057630 (2014.05.13. Publication, the name of the invention: IGBT and its manufacturing method).

An object of the present invention is to provide a power semiconductor device capable of securing switching stability and securing short circuit robustness and a method of manufacturing the same. However, these problems are exemplary, and the scope of the present invention is not limited thereby.

A power semiconductor device according to one aspect of the present invention for solving the above problems is provided. The power semiconductor device may include a trench type gate electrode disposed in a substrate; A body region of a first conductivity type disposed on one side of the gate electrode in the substrate; An oxide pattern disposed on the other side of the gate electrode in the substrate; A floating region of a first conductivity type disposed under the oxide pattern to be in contact with the oxide pattern and extending to the bottom of the gate electrode; A drift region of a second conductivity type extending from the floating region to below the body region in the substrate; And a collector electrode disposed under the substrate.

In the power semiconductor device, the gate electrode, the body region, the oxide pattern, the floating region, and the drift region may be disposed in an active cell region.

In the power semiconductor device, a height of the oxide pattern may be equal to a height of the gate electrode.

The power semiconductor device may further include a conductive pattern electrically connected to the gate electrode, wherein an upper surface of the oxide pattern may directly contact the conductive pattern, and a lower surface of the oxide pattern may directly contact the floating region.

In the power semiconductor device, a maximum doping depth of the body region of the first conductivity type is shallower than a depth of the gate electrode, and a maximum doping depth of the floating region of the first conductivity type is deeper than a depth of the gate electrode, The second conductivity type doping concentration at the side of the floating region of the drift region is configured to be relatively higher than the second conductivity type doping concentration at the bottom of the floating region, so that the maximum electric field in the bottom region of the floating region is This can be formed.

In the power semiconductor device, the substrate may include a wafer and an epitaxial layer grown on the wafer, and a boundary region between the floating region and the oxide pattern may include an interface between the wafer and the epitaxial layer.

In the power semiconductor device, the second conductivity type and the first conductivity type may have opposite conductivity types, but may be any one of n type and p type.

According to another aspect of the present invention for solving the above problems there is provided a method of manufacturing a power semiconductor device. In the method of manufacturing the power semiconductor device, a first conductivity type impurity is implanted into a first region on a wafer, and a second conductivity type impurity is higher than a second conductivity type doping concentration contained in the wafer in a second region of the wafer. Injecting; Forming an epitaxial layer on the wafer; Removing a portion of the epi layer; Injecting a second conductivity type impurity having a concentration higher than a second conductivity type doping concentration contained in the wafer to the remaining epitaxial layer after removing the partial region; Removing the partial region and then filling the removed region with an oxide pattern; Injecting a second conductivity type impurity at a concentration higher than the second conductivity type doping concentration contained in the wafer into the remaining epitaxial layer; Etching along the boundary between the remaining epitaxial layer and the oxide pattern to form a trench to expose the wafer; Lining the inner wall of the trench with an insulating film and filling the gate electrode material to form a gate electrode; And forming a first conductivity type floating region extending under the oxide pattern so as to contact the oxide pattern and extending to the bottom of the gate electrode by diffusing the impurities, the second extending from the lower portion of the floating region to the side. And forming a conductive type drift region.

In the method of manufacturing the power semiconductor device, removing a portion of the epi layer may include removing a portion of the epi layer so that the width of the epi layer remaining after the removal is the same as the width of the second region. And forming the trench may include etching a portion of the oxide pattern.

In the method of manufacturing the power semiconductor device, removing a portion of the epi layer may include removing a portion of the epi layer so that the width of the epi layer remaining after the removal is greater than the width of the second region. And forming the trench may include etching a portion of the remaining epitaxial layer.

According to one embodiment of the present invention made as described above, the power semiconductor device that can ensure the switching stability and short circuit robustness by suppressing the generation of the negative capacitor by removing the space in which holes are introduced into the floating mesa during switching And the manufacturing method can be implemented. Of course, the scope of the present invention is not limited by these effects.

1 is a cross-sectional view illustrating a cell structure of a power semiconductor device according to a comparative example of the present invention.
2 is a diagram illustrating a movement path of electrons and holes in an operation process of a power semiconductor device according to a comparative example of the present invention.
3 is a measurement graph showing switching operation instability in a power semiconductor device according to a comparative example of the present invention.
4 is a cross-sectional view illustrating a cell structure of a power semiconductor device according to an embodiment of the present invention.
5A to 7E are views illustrating a process of manufacturing a power semiconductor device according to an embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms, and the following embodiments are intended to complete the disclosure of the present invention, to those skilled in the art It is provided to inform you completely. In addition, in the drawings, at least some of the components may be exaggerated or reduced in size. Like numbers in the drawings refer to like elements.

In the present specification, the first conductivity type and the second conductivity type may have opposite conductivity types, and may be either of n-type and p-type. For example, the first conductivity type may be p-type and the second conductivity type may be n-type, and the accompanying drawings exemplify such a conductivity type configuration. However, the technical idea of the present invention is not limited thereto. For example, the first conductivity type may be n type and the second conductivity type may be p type.

1 is a cross-sectional view illustrating a cell structure of a power semiconductor device according to a comparative example of the present invention.

Referring to FIG. 1, a power semiconductor device according to a comparative example of the present invention includes a pair of gate electrodes 50a disposed in the first trenches 20a and the second trenches 20b spaced apart from each other in the substrate 1. 50b).

The power semiconductor device is formed in the first conductive type body region 42 and the first conductive type body region 42 disposed between the first trench 20a and the second trench 20b in the substrate 1. And a pair of second conductivity type source regions 44a and 44b which are spaced apart from each other adjacent to the first trench 20a and the second trench 20b, respectively. In the body region 42 of the first conductivity type, a region 43 doped with a relatively higher concentration of the first conductivity type impurity may be disposed.

The power semiconductor device according to the comparative example of the present invention includes a floating region 30a of the first conductivity type that surrounds both the bottom surface and at least one side surface of the first trench 20a in the substrate 1, and A first conductivity type floating region 30b that surrounds both the bottom and at least one side surface of the first trench 20b, wherein the pair of first conductivity type floating regions 30a, 30b are formed of the substrate 1. ) Are spaced apart from each other within. The depth to the bottom surfaces of the floating regions 30a and 30b with respect to the top surface 1s of the substrate 1 is deeper than the depth to the bottom surfaces of the first trenches 20a and the second trenches 20b. That is, the maximum depth of doping of the floating regions 30a and 30b of the first conductivity type may be deeper than that of the first trench 20a and the second trench 20b.

In the power semiconductor device according to the comparative example of the present invention, a pair of the first conductive type floating region 30a, which is formed from the bottom 12 of the pair of first conductive type floating regions 30a and 30b in the substrate 1. 30b) and a second conductivity type drift region 10 that extends through the gap 14 to the body region 42 of the first conductivity type. In particular, the second conductivity type doping concentration between the pair of first conductivity type floating regions 30a, 30b in the drift region 10 is lower than the second conductivity type doping concentration 30a, 30b below the pair of first conductivity type floating regions. It can be relatively higher than the two conductivity doping concentration.

Meanwhile, the maximum doping depth of the first conductive type body region 42 is shallower than that of the first trench 20a and the second trench 20b, and the doping of the first conductive type floating regions 30a and 30b is performed. The maximum depth may be deeper than the depths of the first trenches 20a and the second trenches 20b. Here, in the drift region 10, the second conductivity type doping concentration between the pair of floating regions 30a and 30b of the first conductivity type and between the first trench 20a and the second trench 20b is a pair. It can be relatively higher than the second conductivity type doping concentration below the first conductivity type floating region (30a, 30b) of.

A conductive pattern 64 electrically connected to the gate electrodes 50a and 50b and a conductive pattern 68 electrically connected to the source regions 44a and 44b and the body region 42 are formed on the substrate 1. The conductive patterns 64 and 68 may serve as electrodes or contacts, and may be electrically insulated through the insulating patterns 62 and 66. Meanwhile, a collector electrode 72 is disposed below the substrate 1, and although not shown in the drawing, before forming the collector electrode 72, a buffer layer and / or a first conductivity type of the second conductivity type are formed. The collector layer of can be formed first.

2 is a diagram illustrating a path of movement of electrons and holes in an operation process of an IGBT according to a comparative example of the present invention, and FIG. 3 is a measurement showing switching instability in a power semiconductor element according to a comparative example of the present invention. It is a graph.

Referring to FIG. 2, a mesa portion through which electrons flow and a floating region for forming a breakdown voltage exist in the active unit cell. In FIG. 2, the upward blue solid line arrow indicates the flow of holes and the downward red dashed arrow indicates the flow of electrons. The floating region inevitably acts as a gate-collector capacitor of the entire chip, which affects the switching characteristics. In addition, when electrons are injected after turn-on, holes flow from the collector and current flows through the mesa region and the floating region, and these holes cross the gate oxide surface, changing the electric field and causing a negative capacitor when switching. To become an element. Induction of such a negative capacitor becomes an unstable element in switching operation as shown in Z of FIG. 3.

4 is a cross-sectional view illustrating a cell structure of a power semiconductor device according to an embodiment of the present invention.

Referring to FIG. 4, the power semiconductor device according to the embodiment of the present invention includes trench type gate electrodes 50a and 50b disposed in the substrate 1; A body region 42 of a first conductivity type disposed on one side of the gate electrodes 50a and 50b in the substrate 1; Oxide patterns 35a and 35b disposed on the other side of the gate electrodes 50a and 50b in the substrate 1; Floating regions 30a and 30b of a first conductivity type disposed under the oxide patterns 35a and 35b so as to contact the oxide patterns 35a and 35b and extending to the bottoms of the gate electrodes 50a and 50b; A second conductivity type drift region (10) extending from the floating region (30a, 30b) down to the body region (42) in the substrate (1); And a collector electrode 72 disposed under the substrate 1.

The second conductivity type and the first conductivity type may have opposite conductivity types, but may be any one of n-type and p-type.

The gate electrodes 50a and 50b, the body region 42, the oxide patterns 35a and 35b, the floating regions 30a and 30b and the drift region 10 may be disposed in the active cell region.

The oxide patterns 35a and 35b are disposed on the other side of the gate electrodes 50a and 50b, but the heights of the oxide patterns 35a and 35b may not be lower than the heights of the gate electrodes 50a and 50b. The heights of the patterns 35a and 35b may be about the same as or higher than the heights of the gate electrodes 50a and 50b.

The power semiconductor device further includes a conductive pattern 64 electrically connected to the gate electrodes 50a and 50b. The conductive pattern 64 is disposed on the upper surface of the substrate 1. Upper surfaces of the oxide patterns 35a and 35b may directly contact the conductive patterns 64, and lower surfaces of the oxide patterns 35a and 35b may directly contact the floating regions 30a and 30b.

The substrate 1 may include a wafer and an epitaxial layer grown on the wafer, and a boundary area between the floating regions 30a and 30b and the oxide patterns 35a and 35b may include an interface between the wafer and the epitaxial layer. .

The power semiconductor device having the above-described configuration can reduce the gate-collector capacitor of the power semiconductor. That is, by filling oxide patterns 35a and 35b in the floating mesa, the amount of gate-collector capacitance is reduced, and the generation of a negative capacitor can be suppressed by eliminating a space in which holes flow into the floating mesa during switching. The reduced gate-collector capacitance reduces chip drive current and speeds up switching. Eventually, suppression of negative capacitors results in switching stability and short circuit robustness.

Referring to the power semiconductor device having the above-described configuration from another viewpoint, the power semiconductor uses high voltage, high current for use and development purposes and must ensure the corresponding robustness. In order to form a strong withstand voltage characteristic of the power semiconductor, it must withstand a strong electric field not only in the vertical withstand voltage but also horizontally in the semiconductor cross-section, and has an insulating portion separating the vertical withstand voltage (active cell) and the horizontal withstand voltage (ring termination). In the active region, there are a mesa portion through which electrons flow and a floating portion for forming gate protection and breakdown voltage. The present invention provides a design method for minimizing a capacitor component generated in a floating portion.

The active cell of the power semiconductor device is composed of a mesa portion and a floating portion through which electrons flow, and the mesa portion is a portion where a channel is turned on and electrons flow into the collector, and the floating portion protects the lower portion of the gate and forms a breakdown voltage. Deeply downwards. Furthermore, the floating portion fills and insulates the gate inner region except for the doped region for forming breakdown voltage with oxide patterns 35a and 35b. The structures of the oxide patterns 35a and 35b are different from the comparative examples of the present invention shown in FIG.

On the other hand, in the power semiconductor device according to the embodiment of the present invention, the maximum doping depth of the body region 42 of the first conductivity type is shallower than the depths of the gate electrodes 50a and 50b, and the floating region of the first conductivity type ( The maximum doping depths of 30a and 30b are deeper than the depths of the gate electrodes 50a and 50b, and the second conductivity type doping concentration at the side portions 14 and 15 of the floating region of the drift region 10 is the lower portion of the floating region. It is configured to be relatively higher than the second conductivity type doping concentration in (12), so that a maximum electric field can be formed in the bottom region of the floating regions 30a, 30b.

That is, the second conductivity type doping concentration distributed between the pair 14 of the first conductivity type floating regions 30a and 30b is distributed below the first conductivity type floating regions 30a and 30b. Since it is relatively higher than the second conductivity type doping concentration, even if the separation distance between the trenches 20a and 20b becomes narrow, a base current supply path is formed and abundant base current is supplied, and the bottom of the floating regions 30a and 30b is provided. Robustness can be enhanced by forming a balance between the doping concentrations of the floating regions 30a and 30b and the doping concentrations 14 between the floating regions 30a and 30b so that a maximum electric field is formed in the surface region.

That is, when the separation distance between the trenches is reduced in the MOSFET supplying the base current of the IGBT, the first conductive type impurities in the floating regions 30a and 30b are diffused to limit the base current path. This can be improved by forming a doped region 14 between). In addition, according to the configuration of the power semiconductor device according to an embodiment of the present invention, assuming a same transconductance, a high cell density is formed at a narrower separation distance, thereby lowering the current density at the same total current and mitigating local temperature rise. Thus, short circuit characteristics can be improved.

This principle improves the IGBT resistance and the short circuit characteristics, and at the same time, the total charge of the second conductivity type impurity concentration N1 in the region 14 and the first conductivity type impurity concentration P1 in the floating regions 30a and 30b. Robustness may be improved by controlling the maximum electric field to be formed in the bottom area of the floating areas 30a and 30b.

Since the description of other components has already been described in the comparative example of the present invention with reference to FIG. 1, duplicate description thereof will be omitted.

5A to 7E are views illustrating a process of manufacturing a power semiconductor device according to an embodiment of the present invention.

Referring to FIGS. 5A and 5B, a first conductivity type impurity is implanted into the first region I on the wafer A (P1 Implant) and the wafer A is formed in the second region II of the wafer A. FIG. A second conductivity type impurity of higher concentration than the second conductivity type doping concentration contained is implanted (N1 Implant). The mask patterns 2 and 3 may be used on the wafer A in the process of implanting impurities. When the heat treatment is performed in a subsequent process, the first region I on the wafer A into which the first conductivity type impurity is implanted (P1 implanted) is transferred to the floating regions 30a and 30b of the first conductivity type shown in FIG. 4. Correspondingly, the second region II of the wafer A in which the second conductivity type impurity is implanted (N1 Implant) is an area between the pair of first conductivity type floating regions 30a and 30b shown in FIG. 4. Corresponds to (14).

Referring to FIG. 5C, an epitaxial layer B is formed on the wafer A. FIG. The substrate 1 may be understood as including a wafer A and an epitaxially grown layer B on the wafer. After the epi layer B is grown, a doping process may be performed to inject impurities additionally through the top surface of the epi layer B. FIG.

Subsequently, subsequent manufacturing methods can be divided into a first method (FIGS. 6A-6D) and a second method (FIGS. 7A-7E).

First, the first method will be described. Referring to FIG. 6A, a portion of the epi layer (B of FIG. 5C) is removed to form the first trenches T1. In the removing process, the mask pattern PR1 having the first width W1 may be used. The first width W1 may be adjusted such that the width of the epi layer (B of FIG. 6A) remaining after removal is equal to the width of the second region (II of FIG. 5B).

Subsequently, a second conductivity type impurity having a higher concentration than the second conductivity type doping concentration contained in the wafer may be injected into the epi layer (B of FIG. 6A) remaining after the removal. When the heat treatment is performed in a subsequent process, the region into which the second conductivity type impurity is implanted may correspond to the region 15 illustrated in FIG. 4.

Referring to FIG. 6B, after removing a portion of the epi layer (B of FIG. 5C), the removed region is filled with oxide patterns 35a and 35b. Subsequently, a mask pattern PR2 having a second trench T2 is formed on the remaining epitaxial layers B in FIG. 6B and the oxide patterns 35a and 35b. The second trench T2 is formed so that the boundary between the remaining epitaxial layer (B of FIG. 6B) and the oxide patterns 35a and 35b is exposed, and preferably, a portion of the upper surface of the oxide patterns 35a and 35b is exposed. It is composed.

Referring to FIG. 6C, oxide patterns 35a and 35b are formed along a boundary between the epi layer (B of FIG. 6B) and the oxide patterns 35a and 35b remaining using the mask pattern PR2 having the second trench T2. ) Is etched to form a third trench T3 through which the wafer is exposed.

Referring to FIG. 6D, after removing the mask pattern PR2, the inner wall of the third trench T3 is lined with an insulating film, and the gate electrode material (for example, polysilicon) is filled to fill the gate electrodes 50a and 50b. ). Subsequently, a conductive pattern 64 electrically connected to the gate electrodes 50a and 50b is formed on the substrate 1.

On the other hand, by diffusing the above-mentioned impurities, the first conductivity type of the first conductive type extending under the oxide patterns (35a, 35b) to extend to the bottom of the gate electrode (50a, 50b) to contact the oxide patterns (35a, 35b) Floating regions 30a and 30b of the first conductivity type are formed, and drift regions 10 of the second conductivity type extending from the lower side of the floating regions 30a and 30b of the first conductivity type are formed.

Furthermore, the first trenches in the first conductive body region 42 and the first conductive body region 42 disposed between the first trenches 20a and the second trenches 20b in the substrate 1. The power semiconductor device illustrated in FIG. 4 may be implemented by forming a pair of second conductivity type source regions 44a and 44b which are spaced apart from each other adjacent to 20a and the second trench 20b, respectively.

Unlike the first method described above, the second method will be described next to FIG. 5C.

Referring to FIG. 7A, a portion of the epi layer (B of FIG. 5C) is removed to form the fourth trench T4. In the removing process, the mask pattern PR3 having the second width W2 may be used. The second width W2 may be adjusted such that the width of the epi layer (B of FIG. 7A) remaining after removal is greater than the width of the second region (II of FIG. 5B).

Subsequently, a second conductivity type impurity having a higher concentration than the second conductivity type doping concentration contained in the wafer may be injected into the epi layer (B of FIG. 7A) remaining after the removal. When the heat treatment is performed in a subsequent process, the region into which the second conductivity type impurity is implanted may correspond to the region 15 illustrated in FIG. 4.

Referring to FIG. 7B, after removing a portion of the epi layer (B of FIG. 5C), the removed region is filled with oxide patterns 35a and 35b. Subsequently, a mask pattern PR4 covering the nitride film 61 covering the oxide patterns 35a and 35b and the remaining epitaxial layer (B in FIG. 7A) is formed.

Referring to FIG. 7C, a mask pattern PR4 having a fifth trench T5 is formed on the remaining epitaxial layer (B of FIG. 7C). The fifth trench T5 is formed such that the boundary between the remaining epitaxial layer (B of FIG. 7C) and the oxide patterns 35a and 35b is exposed. Preferably, a portion of the upper surface of the remaining epitaxial layer (B of FIG. 7C) is exposed. Is configured to be exposed.

Referring to FIG. 7D, the epi layer (B of FIG. 7C) and the epitaxial layer (B of FIG. 7C) remaining along with the remaining epi layer (B of FIG. 7C) using the mask pattern PR4 having the fifth trench T5 may be formed. B) is etched to form a sixth trench T6 through which the wafer is exposed.

Referring to FIG. 7E, after removing the mask pattern PR4, the inner walls of the sixth trenches T6 are lined with an insulating film, and the gate electrode materials are filled to form the gate electrodes 50a and 50b. Subsequently, a conductive pattern 64 electrically connected to the gate electrodes 50a and 50b is formed on the substrate 1.

On the other hand, by diffusing the above-mentioned impurities, the first conductivity type of the first conductive type extending under the oxide patterns (35a, 35b) to extend to the bottom of the gate electrode (50a, 50b) to contact the oxide patterns (35a, 35b) Floating regions 30a and 30b of the first conductivity type are formed, and drift regions 10 of the second conductivity type extending from the lower side of the floating regions 30a and 30b of the first conductivity type are formed.

Furthermore, the first trenches in the first conductive body region 42 and the first conductive body region 42 disposed between the first trenches 20a and the second trenches 20b in the substrate 1. The power semiconductor device illustrated in FIG. 4 may be implemented by forming a pair of second conductivity type source regions 44a and 44b which are spaced apart from each other adjacent to 20a and the second trench 20b, respectively.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

1: substrate
10: drift region
20a, 20b: trench
30a, 30b: floating area
35a, 35b: oxide pattern
42: body area
44: source region
50a, 50b: gate electrode

Claims (10)

A trench type gate electrode disposed in the substrate;
A body region of a first conductivity type disposed on one side of the gate electrode in the substrate;
An oxide pattern disposed directly in contact with the other side of the gate electrode in the substrate;
A floating region of a first conductivity type disposed under the oxide pattern to be in contact with the oxide pattern and extending to the bottom of the gate electrode;
A drift region of a second conductivity type in the substrate, extending from below the floating region to below the body region;
A conductive pattern electrically connected to the gate electrode; And
And a collector electrode disposed under the substrate.
The upper surface of the oxide pattern is in direct contact with the conductive pattern and the lower surface of the oxide pattern is in direct contact with the floating region,
Power semiconductor devices. In claim 1,
The gate electrode, the body region, the oxide pattern, the floating region, and the drift region are disposed in an active cell region.
Power semiconductor devices. In claim 1,
The height of the oxide pattern is characterized in that the same as the height of the gate electrode,
Power semiconductor devices. delete The method of claim 1,
The maximum doping depth of the body region of the first conductivity type is shallower than the depth of the gate electrode, the maximum depth of doping of the floating region of the first conductivity type is deeper than the depth of the gate electrode, the floating of the drift region The second conductivity type doping concentration at the side of the region is configured to be relatively higher than the second conductivity type doping concentration at the bottom of the floating region, such that a maximum electric field can be formed in the bottom region of the floating region. Characterized by
Power semiconductor devices. The method of claim 1,
And the substrate includes a wafer and an epitaxial layer grown on the wafer, wherein a boundary region of the floating region and the oxide pattern includes an interface of the wafer and the epilayer. The method according to any one of claims 1 to 3,
The second conductive type and the first conductive type has a conductive type opposite to each other, each of the n-type and p-type, the power semiconductor device. delete delete delete

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