KR102042833B1 - Power semiconductor device and method of fabricating the same - Google Patents

Abstract

According to the present invention, a power semiconductor device comprises: a first trench gate and a second trench gate spaced apart from each other in a substrate; a capacitance tuning pattern disposed over an area between the first trench gate and the second trench gate and made of metal; first conductive floating regions extending downward while surrounding the bottom surfaces of the first trench gate, the second trench gate, and the capacitance tuning pattern; first conductive body regions disposed on the lateral surfaces of the first trench gate and the second trench gate, respectively, in the direction opposite to the capacitance tuning pattern; second conductive source regions disposed adjacent to the first trench gate and the second trench gate in the first conductive body regions, respectively; and a second conductive drift region disposed in a region including a region between the first conductive floating regions and the first conductive body regions in the substrate. Thus, a stable device operation can be implemented.

Description

Power semiconductor device and method of fabricating the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor device and a method of manufacturing the same, and more particularly, to an insulated gate bipolar transistor (IGBT) device and a method of manufacturing the same.

Insulated Gate Bipolar Transistors (IGBTs) are crystals of MOS (Metal Oxide Silicon) and bipolar technologies that feature low forward loss and high speed, making them ideal for applications such as thyristors, bipolar transistors and MOSFETs. This is a next generation power semiconductor device that is widely used and is essential for high efficiency, high speed power system widely used in the voltage range of 300V or higher. Since the development of power MOSFETs in the 1970s, switching devices have been used in the range where high speed switching is required, and bipolar transistors, thyristors, GTO, etc. are used in the range where large current conduction is required from medium to high voltage. Has been. Developed in the early 1980s, IGBTs have more current capability than bipolar transistors in terms of output characteristics, and gate drive characteristics like MOSFETs in terms of input characteristics, enabling fast switching at around 100KHz. As a result, IGBTs are creating new application systems as well as replacements for MOSFETs, bipolar transistors, and thyristors, and are therefore increasingly used in industrial and home electronics.

Related prior arts are Republic of Korea Publication No. 20140057630 (2014.05.13. Publication, the name of the invention: IGBT and its manufacturing method).

An object of the present invention is to provide a power semiconductor device capable of realizing stable device operation by minimizing the influence of negative capacitance. However, these problems are exemplary, and the scope of the present invention is not limited thereby.

A power semiconductor device according to one aspect of the present invention for solving the above problems is provided. The power semiconductor device may include a first trench gate and a second trench gate spaced apart from each other in a substrate; A capacitance tuning pattern disposed over an area between the first trench gate and the second trench gate, the capacitance tuning pattern being made of metal; A first conductivity type floating region extending downward while surrounding a bottom surface of the first trench gate, the second trench gate, and the capacitance tuning pattern; A body region of a first conductivity type disposed in a direction opposite to the capacitance tuning pattern among side surfaces of the first trench gate and the second trench gate; A source region of a second conductivity type disposed in the body region of the first conductivity type adjacent to the first trench gate and the second trench gate, respectively; And a second conductivity type drift region disposed in the substrate, the region including between the floating region of the first conductivity type and the body region of the first conductivity type.

The power semiconductor device may further include an emitter contact pattern contacting the source region of the second conductivity type, wherein the capacitance tuning pattern and the emitter contact pattern may be electrically connected to form a coin phase.

In the power semiconductor device, the capacitance tuning pattern may include a pattern for tuning the capacitance between the gate and the emitter.

In the power semiconductor device, the value of the gate-emitter capacitance caused by the presence of the capacitance tuning pattern may be increased so that the floating region of the first conductivity type extends to the region where the capacitance tuning pattern is located instead of the capacitance tuning pattern. If located, it can be greater than the value of the gate-emitter capacitance that occurs.

In the power semiconductor device, the capacitance tuning pattern may have one side of the left and right sides in contact with the first trench gate, the other side in contact with the second trench gate, and the bottom surface thereof in contact with the floating region of the first conductivity type.

In the power semiconductor device, a height of the capacitance tuning pattern may be a height of the first trench gate and the second trench gate.

In the power semiconductor device, the second conductivity type and the first conductivity type may have opposite conductivity types, but may be any one of n type and p type.

Provided is a method of manufacturing a power semiconductor device according to one aspect of the present invention for solving the above problems. The method of manufacturing a power semiconductor device may include forming a floating region of a first conductivity type and a drift region of a second conductivity type by doping an impurity of a first conductivity type and an impurity of a second conductivity type in a substrate; Etching a portion of the substrate to form a first trench having a first width to expose the floating region; Filling the first trenches with metal to form a capacitance tuning prepattern; Etching left and right side regions of the capacitance tuning preliminary pattern by a second width smaller than the first width to form a pair of second trenches, and forming a capacitance tuning pattern made of metal between the pair of second trenches ; Filling a gate material into the pair of second trenches to form a first trench gate and a second trench gate; It includes.

The method of manufacturing the power semiconductor device may include forming a first conductive body region disposed on opposite sides of the capacitance tuning pattern of the first trench gate and the second trench gate, respectively; And forming a source region of a second conductivity type disposed adjacent to the first trench gate and the second trench gate, respectively, in the body region of the first conductivity type.

The method of manufacturing the power semiconductor device may include forming an emitter contact pattern in contact with the source region of the second conductivity type; Further comprising, the capacitance tuning pattern and the emitter contact pattern may be electrically connected to form a coin.

According to one embodiment of the present invention made as described above, it is possible to provide a power semiconductor device that can implement a stable device operation by minimizing the influence of negative capacitance. Of course, the scope of the present invention is not limited by these effects.

1 is a vertical cross-sectional view illustrating a structure of a power semiconductor device according to a comparative example of the present invention, illustrating a charge inflow by current as a negative capacitance is formed.
FIG. 2 is a diagram illustrating a circuit of a power semiconductor device of the present invention and illustrating a mode in which capacitance is generated by a gate current.
3 is a diagram illustrating a circuit of a power semiconductor device of the present invention and illustrates a charge inflow pattern caused by current as a negative capacitance is formed.
4 is a view illustrating an unstable waveform is formed during operation under the influence of the charge due to negative capacitance in the power semiconductor device according to a comparative example of the present invention.
5 is a longitudinal cross-sectional view illustrating a structure of a power semiconductor device according to an embodiment of the present invention.
6 to 10 are views illustrating a method of manufacturing the power semiconductor device 200 according to an embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms, and the following embodiments are intended to complete the disclosure of the present invention, the scope of the invention to those skilled in the art It is provided to inform you completely. In addition, in the drawings, at least some of the components may be exaggerated or reduced in size. Like numbers in the drawings refer to like elements.

In the present specification, the longitudinal section refers to a cross section perpendicular to the upper surface of the substrate, unlike a cross section representing a cross section in a direction parallel to the upper surface of the substrate.

In the present specification, the first conductivity type and the second conductivity type may have opposite conductivity types, and may be either of n-type and p-type. For example, the first conductivity type may be p-type and the second conductivity type may be n-type, and the accompanying drawings exemplify such a conductivity type configuration. However, the technical idea of the present invention is not limited thereto. For example, the first conductivity type may be n type and the second conductivity type may be p type.

1 is a longitudinal sectional view conceptually illustrating a cell structure of a power semiconductor device according to a comparative example of the present invention.

Referring to FIG. 1, a power semiconductor device 100 according to a comparative example of the present invention includes a pair of gate electrodes disposed in the first trenches 20a and the second trenches 20b spaced apart from each other in the substrate 1, respectively. (50a, 50b). Here, the substrate 1 may be understood as including a wafer and an epitaxially grown epitaxial layer on the wafer.

The power semiconductor device 100 according to the comparative example of the present invention includes a body region 42 and a first conductivity type disposed between the first trench 20a and the second trench 20b in the substrate 1. The conductive body region 42 includes a pair of second conductive source regions 44a and 44b which are spaced apart from each other adjacent to the first trench 20a and the second trench 20b, respectively.

The power semiconductor device 100 according to the comparative example of the present invention surrounds the bottom surface and at least one side of the first trench 20a in the substrate 1 and at least one bottom surface of the first trench 20b. And a floating region 30 of a first conductivity type surrounding each side. The depth to the bottom surface of the floating region 30 based on the top surface 1s of the substrate 1 is deeper than the depth to the bottom surfaces of the first trenches 20a and the second trenches 20b. That is, the maximum doping depth of the first conductivity type floating region 30 may be deeper than that of the first trench 20a and the second trench 20b.

The power semiconductor device 100 according to the comparative example of the present invention is arranged between the bottom 12 of the first conductive type floating region 30 and the space 14 between the first conductive type floating region 30 in the substrate 1. And a drift region 10 of the second conductivity type, passing through to the body region 42 of the first conductivity type. In particular, the second conductivity type doping concentration N1 between the drift region 10 and the floating region 30 of the first conductivity type is the second conductivity type doping concentration N2 below the floating region 30 of the first conductivity type. Relatively higher than).

On the other hand, the maximum doping depth of the first conductive type body region 42 is shallower than the depth of the first trench 20a and the second trench 20b, and the maximum doping depth of the first conductive type floating region 30 is shown. May be deeper than the depth of the first trenches 20a and the second trenches 20b. Here, the second conductivity type doping concentration between the drift region 10 between the first conductivity type floating region 30 and between the first trench 20a and the second trench 20b is a floating region of the first conductivity type. 30 may be relatively higher than the second conductivity type doping concentration below.

A conductive pattern 68 is formed on the substrate 1 to be electrically connected to the source regions 44a and 44b and the body region 42. The conductive pattern 68 may serve as an emitter electrode or a contact. In addition, an insulation pattern 66 may be provided to implement electrical insulation.

A field stop region 72 may be provided on the bottom surface opposite to the top surface of the substrate 10. The field stop region 72 may be a region in which the second conductivity type impurities are heavily doped. For example, the second conductivity type impurity concentration of the field stop region 72 may be higher than the second conductivity type impurity concentration of the drift region 10 of the second conductivity type. The collector region 74 may be provided below the field stop region 72. The collector region 74 may be a region doped with a second conductivity type impurity. The collector electrode 76 may be provided below the collector region 74.

If the floating area 30 does not exist to the bottom of the trenches 20a and 20b, there is a problem in that an electric field increases at the bottom of the trenches 20a and 20b, and the floating area 30 is formed in the trenches 20a and 20b. When only the bottom of the transistor is present, when the separation distance of the trenches 20a and 20b is reduced in the MOSFET supplying the base current of the IGBT, the base current path is limited by the diffusion of the first conductivity type impurities, thereby reducing the cell pitch to a predetermined distance or less. There is a problem that can not be reduced.

In the power semiconductor device 100 illustrated in FIG. 1, the second conductivity type doping concentration N1 distributed between the pair 14 of first conductivity type floating regions 30 is the first conductivity type floating region 30. Since it is relatively higher than the second conductivity type doping concentration (N2) distributed below (12) below, the base current supply path is formed even if the separation distance between the trenches 20a and 20b becomes narrow, In addition, a balance between N1 and P1 may be formed so as to form a maximum electric field on the bottom surface of the floating region 30, thereby improving robustness.

That is, when reducing the separation distance F between trenches in the MOSFET supplying the base current of the IGBT, the first conductivity type impurities of the floating region 30 are diffused to form a N1 region in which the base current path is limited. It can be improved. In addition, according to the above-described configuration of the power semiconductor device 100, a short cell characteristic can be improved by forming a high cell density with a narrower separation distance F, assuming the same transconductance, to mitigate local temperature rise. have.

This principle improves the IGBT resistance and short circuit characteristics, and simultaneously adjusts the total amount of charges in the second conductivity type impurity concentration N1 in the region 14 and the first conductivity type impurity concentration P1 in the floating region 30. As a result, a maximum electric field is formed on the bottom surface of the floating region 30, thereby improving robustness. The bottom surface of the floating region 30 in which the maximum electric field is formed is lower than the bottom surfaces of the trenches 20a and 20b.

Simplifying the relationship between the static electric field and the amount of charge in one dimension in the C direction at N type depletion when voltage is applied can be seen as a function of N doping only with dE / dx = (1 / ε) * n, but IGBT In operation, when carrier is injected, it is changed by dE / dx = (1 / ε) * (n + he) under the influence of injected charge.In the general structure, when the hole density is excessive in the G section in the turn-off state Although the electric field area decreases at the same maximum electric field due to the increase of the electric field change rate due to the concentration change, the drop in internal pressure suddenly occurs, but in the structure of the present invention, the electric field change rate between the bottom surfaces of the trenches 20a and 20b and the bottom of the body region 42 is increased. When the electric field is tilted by making a negative section, the area of the electric field increases, which reduces the dynamic breakdown.

FIG. 2 is a diagram illustrating a circuit of a power semiconductor device of the present invention and illustrating a mode in which capacitance is generated by a gate current.

Referring to FIG. 2, when power is applied to the gate, the gate-emitter capacitance Cgc and the gate-collector capacitance Cgc are generated by the gate current Ig. The gate charging pattern varies according to the charging order of the capacitor and the capacitance value.

3 is a diagram illustrating a circuit of a power semiconductor device of the present invention and illustrating a charge inflow pattern caused by a current as a negative capacitance is formed.

Referring to FIG. 3 together with FIG. 1, when a potential is reversed to form a negative capacitance, charge flows into the gate. In other words, when a negative capacitance is formed, charge is introduced due to displacement current. The exemplary dashed arrow shown in FIG. 1 means current due to negative capacitance. This current satisfies the relationship I = Cgc x (dV _CE / dt).

4 is a view illustrating an unstable waveform is formed during operation under the influence of the charge due to negative capacitance in the power semiconductor device according to a comparative example of the present invention.

Referring to FIG. 4, when the negative capacitance occurs, the capacitance Cge of the gate-emitter is increased by the displacement current, and an ice peak is generated by the increased gate-emitter voltage Vge.

Currently, the development direction of IGBT is focused on making the epi layer thin for better efficiency and reducing the chip size for performance and price competitiveness. Reducing the chip size with the same size and structure of the same active cell would result in a lot of performance loss, although it is advantageous in terms of price due to damage to the active area. Therefore, the design rule of IGBT development is required to reduce the chip size and to improve the performance of the active cell. The cell pitch of the products currently on the market and those under development are made in less than about 10 um. In addition, the chip thickness is shortened to improve the static characteristics, and the cell pitch is reduced to increase the current density per unit area. This development direction has caused problems due to capacitors such as negative capacitance (Negative Capacitance). In the device's Turn On operation, the formation of negative capacitance in the capacitor between the gate and the collector causes current to flow from the collector to the gate, resulting in overshooting of the gate, oscillation of unwanted current, and non-ideal rise. Cause. This phenomenon causes device destruction when a situation such as a short circuit occurs, and causes a malfunction even in a normal switching operation. For example, the IGBT, which is being developed by the applicant, operates at a speed of 5 GV / s or more during a switching operation. This abrupt change in voltage creates a current in the capacitor between the gate and the collector, which causes the problem of turning the device on again in the turn off operation.Increasing the peak of the voltage leads to malfunction of the system. This can cause element breakdown. For stable device operation, the effects of negative capacitance must be minimized.

Therefore, in the power semiconductor device according to the embodiment of the present invention, the gate-to-collector capacitance Cgc, which causes a problem with negative capacitance at turn-on, is reduced and a stable gate-emitter voltage Vge is reduced. To maintain, we want to design a large gate-to-emitter capacitance (Cge).

5 is a longitudinal cross-sectional view illustrating a structure of a power semiconductor device according to an embodiment of the present invention.

Referring to FIG. 5, a power semiconductor device 200 according to an embodiment of the present invention may include a first trench gate 50a and a second trench gate 50b spaced apart from each other in a substrate 1; A capacitance tuning pattern 35 disposed over a region between the first trench gate 50a and the second trench gate 50b and made of metal; A first conductivity type floating region 30 extending downward while enclosing a bottom surface of the first trench gate 50a, the second trench gate 50b, and the capacitance tuning pattern 35; A body region 42 of a first conductivity type disposed in a direction opposite to the capacitance tuning pattern 35 among the side surfaces of the first trench gate 50a and the second trench gate 50b; Source regions 44a and 44b of the second conductivity type disposed in the region of the first conductivity type body 42 adjacent to the first trench gate 50a and the second trench gate 50b, respectively; And a second conductivity type drift region 10 disposed in the substrate including a region between the floating region 30 of the first conductivity type and the body region 42 of the first conductivity type.

Further, the power semiconductor device 200 further includes an emitter contact pattern 68-1 contacting the source regions 44a and 44b of the second conductivity type, but includes the capacitance tuning pattern 35 and the emi. The contact contact pattern 68-1 may be electrically connected to form a coin place.

In the power semiconductor device 200 according to an embodiment of the present invention, the capacitance tuning pattern 35 has one side of the left and right sides contacting the first trench gate 50a and the other side of the second trench gate 50b. And the bottom surface may contact the floating region 30 of the first conductivity type. In addition, the height of the capacitance tuning pattern 35 may be the height of the first trench gate 50a and the second trench gate 50b.

The capacitance tuning pattern 35 may include a pattern for tuning the capacitance between the gate and the emitter. The value of the gate-emitter capacitance caused by the presence of the capacitance tuning pattern 35 is that the floating region of the first conductivity type extends to an area where the capacitance tuning pattern is located instead of the capacitance tuning pattern. It may be larger than the value of the gate-emitter capacitance that occurs.

According to the structure of the power semiconductor device 200 according to the embodiment of the present invention described above, when the trench structure is used, the space between the floating region or the gate trench between the active cells is utilized. By increasing the gate-emitter capacitance (Cge) to the maximum, the device can be operated stably. In the power semiconductor device according to the comparative example of the present invention, the region located between the trench gates in the floating region 30 acted as a gate-collector capacitance (Cgc) component. On the contrary, in the power semiconductor device 200 according to an embodiment of the present invention, the device is stably operated by replacing the space between the gate trenches with a capacitance tuning pattern 35 made of metal, rather than forming a floating region. Do it.

That is, the power semiconductor device 200 according to an embodiment of the present invention has a large gate-emitter capacitance Cge as compared to the gate-emitter capacitance Cge of the conventional trench structure, thereby providing stable operation. This is possible. A device having a small gate-emitter capacitance (Cge) is a phenomenon in which the gate-emitter voltage (Vge) is lowered or reversed by holes stacked in the trenches, resulting in unstable operation such as oscillation. However, in the power semiconductor device 200 according to an embodiment of the present invention, by increasing the gate-emitter capacitance Cge in the existing structure, the influence of holes accumulated near the trench is reduced, thereby achieving more stable operation. Do it.

6 to 10 are views illustrating a method of manufacturing the power semiconductor device 200 according to an embodiment of the present invention.

Referring to FIG. 6, the first conductive type floating region 30 is formed by doping the substrate 1 with impurities of the first conductive type. In addition, the second conductive type drift region 10 is formed by doping the substrate 1 with impurities of the second conductive type. The substrate 1 may be understood as including a wafer and an epitaxially grown epitaxial layer on the wafer.

7 and 8, a first trench 33 having a first width is formed to etch a portion of the substrate 1 to expose the floating region 30. Subsequently, the first trench 33 is filled with metal to form a capacitance tuning preliminary pattern 35a.

9, left and right side regions of the capacitance tuning preliminary pattern 35a are etched by a second width smaller than the first width to form a pair of second trenches 20a and 20b and the pair of first A capacitance tuning pattern 35 made of metal is formed between the two trenches 20a and 20b. Therefore, the width of the capacitance tuning pattern 35 is smaller than the first width, which is the width of the first trench 33.

Referring to FIG. 10, a gate material is filled in the pair of second trenches 20a and 20b to form a first trench gate 50a and a second trench gate 50b. The process of forming the first trench gate 50a and the second trench gate 50b may include, for example, forming a gate oxide film by thermal oxidation and then depositing a polysilicon material to form a gate electrode. have.

According to the process illustrated in FIGS. 7 to 10, the gate oxide films of the first trench gate 50a and the second trench gate 50b are implemented after the capacitance tuning pattern 35 is formed, so that the capacitance tuning pattern 35 is formed. The problem that the gate oxide film is deteriorated or lost during the process of forming the oxide can be blocked at the source. In addition, the misalignment burden of the photolithography process in which the first trench gate 50a and the second trench gate 50b are first formed and then the space therebetween is precisely etched can be prevented.

Meanwhile, according to the method of manufacturing the power semiconductor device according to the modified embodiment of the present invention, the pair of second trenches 20a in the structure of FIG. 6 without forming the capacitance tuning preliminary pattern 35a as described above. The first trench gate 50a and the second trench gate 50b may be formed by first forming a 20b and then filling a gate material in the pair of second trenches 20a and 20b. Subsequently, in the space between the first trench gate 50a and the second trench gate 50b, silicon forming the substrate 1 is etched to form a trench, and then a metal is charged to implement the capacitance tuning pattern 35. have. In this case, a part of the capacitance tuning preliminary pattern 35a made of metal may be etched to prevent a burden on the process of forming the pair of second trenches 20a and 20b, and the capacitance tuning pattern 35 is formed first. Then, in the process of forming the gate oxide layer by thermal oxidation, it is possible to prevent the contamination of the equipment by the metal material.

Subsequently, subsequent steps may be performed to implement the power semiconductor device 200 shown in FIG. 5.

For example, a body region 42 of a first conductivity type, which is disposed in a direction opposite to the capacitance tuning pattern 35, is formed among side surfaces of the first trench gate 50a and the second trench gate 50b. can do. Further, second conductive source regions 44a and 44b are formed in the first conductive body region 42 adjacent to the first trench gate 50a and the second trench gate 50b, respectively. can do.

Meanwhile, an emitter contact pattern 68-1 may be formed to contact the second conductive source regions 44a and 44b, and the capacitance tuning pattern 35 and the emitter contact pattern 68-1 may be formed. May be electrically connected to form a coin place.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

1: substrate
10: drift region
30: floating area
35: capacitance tuning pattern
42: body area
44: source region
50a, 50b: trench gate
68-1: Emitter Contact Pattern
72: field stop area
74: collector area
76: collector electrode

Claims (10)

A first trench gate and a second trench gate spaced apart from each other in the substrate;
A capacitance tuning pattern disposed over an area between the first trench gate and the second trench gate, the capacitance tuning pattern being made of metal;
A first conductivity type floating region extending downward while surrounding a bottom surface of the first trench gate, the second trench gate, and the capacitance tuning pattern;
A body region of a first conductivity type disposed in a direction opposite to the capacitance tuning pattern among side surfaces of the first trench gate and the second trench gate;
A source region of a second conductivity type disposed in the body region of the first conductivity type adjacent to the first trench gate and the second trench gate, respectively; And
A second conductivity type drift region disposed in the substrate, the region including between the floating region of the first conductivity type and the body region of the first conductivity type;
Comprising a power semiconductor device. The method of claim 1,
And an emitter contact pattern in contact with the source region of the second conductivity type.
And the capacitance tuning pattern and the emitter contact pattern are electrically connected to form a coincidence. The method of claim 2,
The capacitance tuning pattern includes a pattern for tuning the gate-emitter capacitance. The method of claim 2,
The gate-emitter capacitance value generated by the presence of the capacitance tuning pattern is a gate generated when the floating region of the first conductivity type extends to a region where the capacitance tuning pattern is located instead of the capacitance tuning pattern. A power semiconductor device, characterized in that greater than the value of the inter-emitter capacitance. The method of claim 1,
The capacitance tuning pattern is a power semiconductor device, characterized in that one side of the left and right sides in contact with the first trench gate, the other side in contact with the second trench gate, the bottom surface in contact with the floating region of the first conductivity type. The method of claim 5,
And the height of the capacitance tuning pattern is the height of the first trench gate and the second trench gate. The method according to any one of claims 1 to 6,
Wherein the second conductivity type and the first conductivity type has a conductivity type opposite to each other, each of n-type and p-type,
Power semiconductor devices. Doping an impurity of a first conductivity type and an impurity of a second conductivity type in the substrate to form floating regions of the first conductivity type and drift regions of the second conductivity type, respectively;
Etching a portion of the substrate to form a first trench having a first width to expose the floating region;
Filling the first trenches with metal to form a capacitance tuning prepattern;
Etching left and right side regions of the capacitance tuning preliminary pattern by a second width smaller than the first width to form a pair of second trenches, and forming a capacitance tuning pattern made of metal between the pair of second trenches ; And
Filling gate material into the pair of second trenches to form a first trench gate and a second trench gate; Including,
Method for manufacturing a power semiconductor device. The method of claim 8,
Forming a body region of a first conductivity type in a side of the first trench gate and the second trench gate opposite to the capacitance tuning pattern; And
Forming a source region of a second conductivity type disposed adjacent to the first trench gate and the second trench gate, respectively, in the body region of the first conductivity type;
Method for manufacturing a power semiconductor device. The method of claim 9,
Forming an emitter contact pattern in contact with the second conductivity type source region; Further comprising, wherein the capacitance tuning pattern and the emitter contact pattern is electrically connected to form a coin phase,
Method for manufacturing a power semiconductor device.

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