JP2005032941A - Insulated gate type semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an insulated gate type semiconductor device which reduces gate-collector capacitance without hindering an on-voltage caused by an injection enhancement effect. <P>SOLUTION: An insulation film 31 with a thickness equal to or larger than that of a gate-insulated film 13 and thinner than an interlayer insulation film covering a gate electrode 14 is formed on the surface of a floating p-region 7, and an emitter potential region 32 with emitter potential applied is formed on it, thereby forming a relatively large capacitor between the region 7 and an emitter electrode 11. This capacitor converts a major part of the gate-collector capacitance into collector-emitter capacitance and gate-emitter capacitance, thereby reducing effective gate-collector capacitance. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an insulated gate semiconductor device such as an IGBT (insulated gate bipolar transistor) used for a semiconductor switching device or the like.
[0002]
[Prior art]
FIG. 9 is a cross-sectional view showing a configuration of an IGBT having a conventional trench gate structure. As shown in FIG. 9, the p layer 5 is formed on the surface of the n ⁻ layer 4 serving as a drift layer. The p layer 5 is divided into a p base region 6 and a floating p region 7 by a plurality of trenches 8 and 9 reaching the n ⁻ layer 4 from the surface thereof.
[0003]
The p base region 6 is a region sandwiched between adjacent first trenches 8 in the p layer 5. The n ⁺ emitter region 10 is provided on the side surface of the first trench 8 in the p base region 6. The emitter electrode 11 is electrically connected to the n ⁺ emitter region 10 and the p base region 6. The gate region 12 made of polysilicon that contributes to actual channel formation is provided in the first trench 8 via the gate insulating film 13 and is electrically connected to the gate electrode 14.
[0004]
The floating p region 7 includes a region sandwiched between adjacent second trenches 9 in the p layer 5 or a side surface of the first trench 8 on the side where the n ⁺ emitter region 10 is not present and the second trench. 9 is an area sandwiched between the two. The floating p region 7 is insulated from the n ⁻ layer 4 by a pn junction, and is insulated from the gate region 12 by the gate insulating film 13. That is, the floating p region 7 is in a so-called floating state.
[0005]
The dummy gate region 15 made of polysilicon that does not contribute to actual channel formation is provided in the second trench 9 via the insulating film 16 and is electrically connected to the electrode 17. This electrode 17 is electrically connected to the gate electrode 14. On the other hand, n buffer layer 3 and p collector layer 2 are provided on the back side of n ⁻ layer 4. The collector electrode 1 is electrically connected to the collector layer 2.
[0006]
In the IGBT having the configuration shown in FIG. 9, an inversion layer is formed in the p base region 6 near the gate insulating film 13 with respect to the emitter electrode 11 in a state where a positive voltage is applied to the collector electrode 1 with respect to the emitter electrode 11. When a positive voltage as generated is applied to the gate electrode 14, electrons are injected from the n ⁺ emitter region 10 into the n ⁻ layer 4 through the inversion layer. The electrons injected into the n ⁺ emitter region 10 reach the n buffer layer 3 and cause injection of holes from the p collector layer 2. Such a so-called conductivity modulation reduces the on-voltage.
[0007]
Holes injected into the n ⁻ layer 4 through the n buffer layer 3 cannot pass through the floating p region 7 in the floating state, and flow out to the emitter electrode 11 through the p base region 6. Therefore, in the n ⁻ layer 4, the hole density in the vicinity of the p base region 6 is increased, and electron injection is increased accordingly. Such a so-called IE (injection enhancement) effect further reduces the on-voltage. An IGBT having such a floating p region is sometimes called an IEGT (Injection Enhanced Insulated Gate Bipolar Transistor) (see, for example, Patent Document 1).
[0008]
However, in the above-described IEGT, since there are many dummy gates that do not contribute to channel formation, the gate-collector capacitance is increased, the switching loss is large, the gate driving energy is large, and the gate defect is caused. There are drawbacks such as a high defect rate. As shown in FIG. 10, if the emitter potential is applied to the dummy gate region 15 (see, for example, Patent Document 2 and Patent Document 3), the gate-collector capacitance is reduced, so that switching loss and gate Driving energy is reduced.
[0009]
However, the IGBT having the configuration shown in FIG. 10 is the same as the IGBT having the configuration shown in FIG. 9 in that the number of dummy gates is large, so that the defect due to the gate defect cannot be solved. In order to reduce gate defects, it is effective to use a structure without a dummy gate as shown in FIG. 11 (see, for example, Patent Document 1).
[0010]
FIG. 12 is a cross-sectional view of an essential part schematically showing the capacitance of the IGBT having the configuration shown in FIG. In FIG. 12, Cge is a gate-emitter capacitance, and Cgc is a gate-collector capacitance. Cgf is a gate-floating p region capacitance, and Ccf is a collector-floating p region capacitance. In each of these capacitors, a depletion layer capacitor extending in each semiconductor region is also considered.
[0011]
As shown in FIG. 12, a capacitance in which a gate-floating p region capacitance Cgf and a collector-floating p region capacitance Ccf are connected in series is added in parallel to the gate-collector capacitance Cgc. Therefore, the effective gate-collector capacitance C is expressed by the following equation (1).
[0012]
C = Cgc + Cgf · Ccf / (Cgf + Ccf) (1)
[0013]
In general, the amount by which the trench 8 protrudes into the p layer 5 in order to obtain a good breakdown voltage is smaller than the depth of the p layer 5. Further, since the width of the trench 8 is also small, the gate-collector capacitance Cgc is smaller than the gate-floating p region capacitance Cgf. On the other hand, since the width of the floating p region 7 is large in order to enhance the IE effect, the collector-floating p region capacitance Ccf becomes very large.
[0014]
Therefore, in the configuration without the dummy gate, the effective gate-collector capacitance C becomes very large. Therefore, the switching loss increases due to the feedback capacitance between the gate and the collector, or the feedback via the feedback capacitance between the gate and the collector at the time of reverse recovery of the FWD (freewheeling diode) connected in parallel with the IGBT in the application circuit such as an inverter. There are problems such as oscillation phenomenon.
[0015]
Therefore, as shown in FIG. 13, an IGBT having a configuration in which an emitter potential is applied to the floating p region 7 via an electrode 18 is known. In this way, the gate-floating p region capacitance Cgf and the collector-floating p region capacitance Ccf shown in FIG. 12 are converted into a gate-emitter capacitance and a collector-emitter capacitance, respectively. As a result, the effective gate-collector capacitance is only Cgc shown in FIG. 12, and is suppressed to a low value.
[0016]
FIG. 14 schematically shows a result of comparison of output characteristics between the IGBT having the configuration shown in FIG. 11 (with the IE effect) and the IGBT having the configuration shown in FIG. 13 (without the IE effect). In FIG. 14, the solid line is the output characteristic of the IGBT shown in FIG. 11, and the broken line is the output characteristic of the IGBT shown in FIG.
[0017]
[Patent Document 1]
JP 2001-332728 A [Patent Document 2]
Japanese Patent Laid-Open No. 11-330466 [Patent Document 3]
Japanese Patent Laid-Open No. 2001-308327
[Problems to be solved by the invention]
However, when the floating p region 7 is connected to the emitter electrode 11 as in the IGBT having the configuration shown in FIG. 13, holes are extracted from the p collector layer 2, so that the IE effect described above is obtained as shown in FIG. 14. It will not be possible. Therefore, there is a problem that the on-voltage increases.
[0019]
The present invention has been made in view of the above problems, and provides an insulated gate semiconductor device capable of reducing the gate-collector capacitance without hindering the low on-voltage due to the IE effect. Objective.
[0020]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides an insulated gate semiconductor device having a trench structure in which an emitter region is provided only on one side surface of a trench, on the surface of the semiconductor region on the other side surface of the trench, An emitter potential region is provided through an insulating film that is the same as or thicker than the gate insulating film and thinner than the interlayer insulating film covering the gate electrode, or in the semiconductor region on the other side of the trench A second trench that is shallower than the trench and has an emitter potential region on the inner side through an insulating film, or in the semiconductor region on the other side surface of the trench than the semiconductor region. A second trench is provided which is shallow and has an emitter potential region inside through an insulating film.
[0021]
According to the present invention, since a relatively large capacitor is formed between the semiconductor region on the side of the trench where the emitter region is not provided and the emitter electrode, most of the gate-collector capacitance is between the collector and the emitter. Capacitance and gate-emitter capacitance are converted. Moreover, since the semiconductor region on the side where the emitter region is not provided on the side surface of the trench is in a floating state in terms of direct current, it is effective to reduce the on-state voltage by the IE effect. Therefore, the effective gate-collector capacitance can be reduced without hindering the low on-voltage due to the IE effect.
[0022]
In order to achieve the above object, according to the present invention, in an insulated gate semiconductor device having a portion having a narrow interval between trenches and a portion having a wide interval, the surface of the portion having a wide interval between trenches is the same as or equal to the gate insulating film. The emitter potential region is provided through an insulating film that is thicker than the interlayer insulating film that covers the gate electrode, or is shallower than the trench and insulates in a portion where the interval between the trenches is wide A second trench having a region of emitter potential is provided through the film, or the emitter is shallower than the semiconductor region in the part of the semiconductor region where the interval between the trenches is wide and through the insulating film inside A second trench having a potential region is provided.
[0023]
According to the present invention, since a relatively large capacitor is formed between the semiconductor region and the emitter electrode in a portion where the trench interval is wide, most of the gate-collector capacitance is the collector-emitter capacitance and the gate-emitter. It is converted into capacity. In addition, since the semiconductor region in a portion where the interval between the trenches is wide is in a floating state in terms of direct current, it is effective to reduce the on-state voltage by the IE effect. Therefore, the effective gate-collector capacitance can be reduced without hindering the low on-voltage due to the IE effect.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings, the same components are denoted by the same reference numerals, and redundant description will be omitted, and only different components will be described.
[0025]
Embodiment 1 FIG.
1 is a cross-sectional view showing a configuration of an insulated gate semiconductor device according to a first embodiment of the present invention. As shown in FIG. 1, in the IGBT according to the first embodiment, the p layer 5 is divided into a p base region 6 and a floating p region 7 by a plurality of trenches 8 reaching the n ⁻ layer 4 from the surface thereof. In FIG. 1, a region partitioned by a one-dot chain line represents one cell region (the same applies to other drawings).
[0026]
The p base region 6 is a region sandwiched between the side surfaces of the adjacent trenches 8 on the side where the n ⁺ emitter region 10 is provided in the p layer 5. The floating p region 7 is a region sandwiched between the side surfaces of the adjacent trenches 8 on the side where the n ⁺ emitter region 10 does not exist in the p layer 5. Usually, the portion where the interval between the trenches 8 is narrow becomes the p base region 6, and the portion where the interval between the trenches 8 is wide becomes the floating p region 7.
[0027]
Part or all of the surface of the floating p region 7 is covered with an insulating film 31 such as an oxide film. A region 32 made of, for example, polysilicon is provided on the insulating film 31. The polysilicon region 32 is electrically connected to the emitter electrode 11 via the electrode 33, and always has an emitter potential. Hereinafter, this region 32 is referred to as an emitter potential region. The emitter potential region 32, the floating p region 7, and the insulating film 31 constitute a capacitor that sandwiches the insulating film 31 between the emitter potential region 32 and the floating p region 7.
[0028]
Here, the thickness of the insulating film 31 constituting the capacitor is equal to or greater than the thickness of the gate insulating film 13. The reason is that when the thickness is smaller than that of the gate insulating film, there is a high possibility that the required reliability of the oxide film cannot be ensured. The insulating film 31 is thinner than an interlayer insulating film (not shown) that covers the gate electrode 14. The reason is that there is almost no difference in capacitance between the floating p region 7 and the polysilicon region 32 and the emitter electrode on the interlayer insulating film (not shown) and the floating p region 7 in the case of the same as the interlayer insulating film. This is because does not appear. In addition, since the thickness of the insulating film 31 is the same as that of the gate insulating film, this structure can be conveniently formed without adding a special process.
[0029]
FIG. 2 is a main part sectional view schematically showing the capacitance of the IGBT having the configuration shown in FIG. In FIG. 2, Cge, Cgc, Cgf, and Ccf are a gate-emitter capacitance, a gate-collector capacitance, a gate-floating p region capacitance, and a collector-floating p region capacitance, respectively. Cfe is a floating p region-emitter capacitance. In each of these capacitors, a depletion layer capacitor extending in each semiconductor region is also considered.
[0030]
As shown in FIG. 2, an equivalent circuit in which a floating p region-emitter capacitance Cfe is connected between a connection node between a gate-floating p region capacitance Cgf and a collector-floating p region capacitance Ccf and the emitter electrode 11 is shown. Become. Therefore, the effective gate-collector capacitance C is expressed by the following equation (2).
[0031]
C = Cgc + Cgf · Ccf / (Cgf + Ccf + Cfe) (2)
[0032]
Here, the floating p region-emitter capacitance Cfe is larger than the sum (Cgf + Ccf) of the gate-floating p region capacitance Cgf and the collector-floating p region capacitance Ccf. Therefore, [Cgf · Ccf / (Cgf + Ccf + Cfe)] is a value close to zero and the effective gate-collector capacitance C is about Cgc, so that the effective gate-collector capacitance is greatly reduced.
[0033]
On the other hand, since the floating p region 7 is in a floating state in terms of direct current, there is no adverse effect on the low on-voltage due to the IE effect. Therefore, the on-voltage of the IGBT having the configuration shown in FIG. 1 has a low value equivalent to that of the IGBT having the conventional configuration shown in FIG. In addition, since there is no dummy gate, an improvement in the yield rate is expected. Even if the floating p region 7 and the emitter potential region 32 are short-circuited, there is almost no characteristic influence as long as the resistance value of the short-circuited portion is sufficiently large. When the resistance at the short-circuited portion is low, the configuration is equivalent to the conventional configuration shown in FIG. 11, and the on-voltage is only the same as that of the conventional device.
[0034]
Next, the manufacturing process of the element of the first embodiment will be briefly described with reference to FIGS. 3-5 is a figure which shows the cross-sectional structure (for 1 cell) of the element surface part in the middle of manufacture in order of a process.
[0035]
First, the p layer 5 is formed on the n ⁻ layer 4 by a known method (FIG. 3A). Then, a well-known photo process and trench etching are performed to form a plurality of trenches 8 so as to reach the n ⁻ layer 4 from the surface of the p layer 5. As a result, the p layer 5 is divided into the p base region 6 and the floating p region 7 (FIG. 3B).
[0036]
Next, an oxide film is formed on the side and bottom surfaces of the trench 8 and the surface of the p layer 5. This oxide film becomes the gate insulating film 13 in the trench 8, while it becomes the insulating film 31 constituting the capacitor on the surface of the floating p region 7 (FIG. 3C). Next, a polysilicon film 41 is stacked, and the trench 8 is filled with polysilicon. Then, a resist 42 is applied and patterned to leave the resist 42 only on the formation region of the emitter potential region 32 (FIG. 4D).
[0037]
Using the remaining resist 42 as a mask, the polysilicon film 41 is etched to form a gate region 12 having a trench gate structure and an emitter potential region 32. Then, the resist 42 is removed (FIG. 4E). The resist 43 is applied again and patterned to open the formation region of the emitter region 10. Then, for example, an impurity for forming an n-type semiconductor is introduced into the formation region of the emitter region 10 in the p base region 6 by ion implantation. (FIG. 4 (f)).
[0038]
After removing the resist 43, heat treatment is performed to form the n ⁺ emitter region 10 (FIG. 5G). Next, an interlayer insulating film 44 is laminated, and a contact region with the p base region 6 and the n ⁺ emitter region 10 and a contact region with the emitter potential region 32 of the interlayer insulating film 44 are removed by etching (FIG. 5 ( h)). Subsequently, the metal 45 is laminated | stacked and the emitter electrode 11 and the electrode 33 are formed (FIG.5 (i)).
[0039]
In FIG. 5I, the contact portion between the gate region 12 and the gate electrode 14 is not shown. Also, since the fabrication of the back side structure of the element is conventional, description and illustration are omitted. By the way, in the manufacturing process described above, the gate insulating film 13 and the insulating film 31 on the floating p region 7 may be formed separately. In that case, the floating p region-emitter capacitance Cfe can be adjusted by forming the insulating film 31 thicker than the gate insulating film 13, for example. Further, the gate region 12 and the emitter potential region 32 may be formed separately.
[0040]
According to the first embodiment described above, since most of the gate-collector capacitance is converted into the collector-emitter capacitance and the gate-emitter capacitance, the effective gate-collector capacitance can be reduced. . Therefore, since the collector potential can be reduced from being fed back to the gate via the gate-collector feedback capacitor, the oscillation phenomenon at the time of turn-on can be prevented. Further, the on-state voltage can be reduced by the IE effect.
[0041]
Embodiment 2. FIG.
FIG. 6 is a cross-sectional view showing a configuration of an insulated gate semiconductor device according to the second embodiment of the present invention. As shown in FIG. 6, in the second embodiment, an insulating film 31, an emitter potential region 32, and an electrode 33 are provided on each floating region 7 near each gate region 12. It is. That is, the second embodiment has a configuration in which the insulating film 31, the emitter potential region 32, and the electrode 33 of the first embodiment are divided for each gate region 12. Other configurations are the same as those of the first embodiment.
[0042]
According to the second embodiment, as in the first embodiment, an effective gate-collector capacitance reduction effect and an on-voltage reduction effect due to the IE effect can be obtained. Further, compared to the first embodiment, an increase in the collector-emitter capacitance due to the resistance of the floating p region 7 can be suppressed, so that an increase in loss at turn-on can be suppressed.
[0043]
Embodiment 3 FIG.
FIG. 7 is a cross-sectional view showing a configuration of an insulated gate semiconductor device according to the third embodiment of the present invention. In the third embodiment, a second trench 19 shallower than the floating p region 7 is formed in the floating p region 7, an insulating film 26 is provided on the inner surface of the second trench 19, and the inner side of the insulating film 26 is further provided. Is buried with polysilicon to form an emitter potential region 25, thereby providing a trench-structure capacitor serving as a floating p region-emitter capacitance Cfe. The emitter potential region 25 is electrically connected to the emitter electrode 11 through the electrode 27. Other configurations are the same as those of the first embodiment.
[0044]
According to the third embodiment, as in the first embodiment, an effective gate-collector capacitance reduction effect and an on-voltage reduction effect due to the IE effect can be obtained. Even if the floating p region 7 is a relatively narrow region, a large capacitance can be obtained. Desirably, the second trench 19 is formed near the gate region 12. Then, as in the second embodiment, an increase in loss at turn-on can be suppressed.
[0045]
Embodiment 4 FIG.
FIG. 8 is a sectional view showing a configuration of an insulated gate semiconductor device according to the fourth embodiment of the present invention. In the fourth embodiment, the second trench 19 has the same depth as the trench 8 and the depth of the floating p region 7 is deeper than the second trench 19 in the third embodiment. Other configurations are the same as those in the third embodiment or the first embodiment.
[0046]
In the fourth embodiment, the p base region 6 and the floating p region 7 have different depths, and the floating p region 7 is deeper. In order to form such p regions 6 and 7 having different depths, the trench 8 and its neighboring regions are covered with a resist so that p-type impurities are not introduced near the surface of the trench 8 to be the gate region 12. A p-type impurity may be ion-implanted. If this step is shared with the step of forming the p region necessary for the peripheral breakdown voltage structure, the number of manufacturing steps will not increase.
[0047]
According to the fourth embodiment, as in the first embodiment, an effective gate-collector capacitance reduction effect and an on-voltage reduction effect due to the IE effect can be obtained. Further, since it is not necessary to form trenches having different depths, the process can be simplified as compared with the third embodiment. Furthermore, since the depletion layer extending from the p base region 6 and the floating p region 7 is close to that of the planar junction, the breakdown voltage can be increased.
[0048]
In the above, this invention is not restricted to each embodiment mentioned above, A various change is possible. In addition, the present invention is similarly established even with a conductivity type opposite to that of the above-described embodiments.
[0049]
【The invention's effect】
According to the present invention, most of the gate-collector capacitance is converted into the collector-emitter capacitance and the gate-emitter capacitance, and the low on-voltage due to the IE effect remains effective. The effective gate-collector capacitance can be reduced without hindering the on-voltage.
[Brief description of the drawings]
1 is a cross-sectional view showing a configuration of an insulated gate semiconductor device according to a first embodiment of the present invention;
2 is a cross-sectional view of the principal part schematically showing the capacitance of the insulated gate semiconductor device having the configuration shown in FIG. 1;
3 is a cross-sectional view sequentially illustrating a part of the manufacturing process of the insulated gate semiconductor device having the configuration shown in FIG. 1;
4 is a cross-sectional view sequentially illustrating a part of the manufacturing process of the insulated gate semiconductor device having the configuration shown in FIG. 1;
5 is a cross-sectional view sequentially showing a part of the manufacturing process of the insulated gate semiconductor device having the configuration shown in FIG. 1; FIG.
FIG. 6 is a cross-sectional view showing a configuration of an insulated gate semiconductor device according to a second embodiment of the present invention;
FIG. 7 is a cross-sectional view showing a configuration of an insulated gate semiconductor device according to a third embodiment of the present invention;
FIG. 8 is a cross-sectional view showing a configuration of an insulated gate semiconductor device according to a fourth embodiment of the present invention;
FIG. 9 is a cross-sectional view showing a configuration of a conventional trench gate type IGBT.
FIG. 10 is a cross-sectional view showing a configuration of a conventional trench gate type IGBT.
FIG. 11 is a cross-sectional view showing a configuration of a conventional trench gate type IGBT.
12 is a cross-sectional view of a principal part schematically showing the capacitance of the IGBT having the configuration shown in FIG.
FIG. 13 is a cross-sectional view showing a configuration of a conventional trench gate type IGBT.
FIG. 14 is a characteristic diagram schematically showing a result of comparing output characteristics of an IGBT having an IE effect and an IGBT having no IE effect.
[Explanation of symbols]
7 Semiconductor region (floating p region) on the side surface without the emitter region of the trench or where the trench spacing is wide
8 Trench 10 n ⁺ Emitter region 13 Gate insulating film 19 Second trench 25, 32 Emitter potential region 26, 31 Insulating film

Claims (6)

In an insulated gate semiconductor device having a trench structure in which an emitter region is provided only on one side surface of the trench,
On the surface of the semiconductor region on the other side of the trench, an emitter potential region is provided via an insulating film that is the same as or thicker than the gate insulating film and thinner than the interlayer insulating film covering the gate electrode. An insulated gate semiconductor device comprising: In an insulated gate semiconductor device having a trench structure in which an emitter region is provided only on one side surface of the trench,
An insulated gate type characterized in that a second trench having a region of an emitter potential is provided inside the semiconductor region on the other side surface of the trench, which is shallower than the trench and is disposed inside through an insulating film. Semiconductor device. In an insulated gate semiconductor device having a trench structure in which an emitter region is provided only on one side surface of the trench,
An insulated gate, characterized in that a second trench having a region of an emitter potential is provided inside the semiconductor region on the other side surface of the trench, which is shallower than the semiconductor region and has an emitter potential region inside through an insulating film. Type semiconductor device. In an insulated gate semiconductor device having a narrow portion and a wide portion between trenches,
An emitter potential region is provided on the surface of the portion where the interval between the trenches is wide via an insulating film which is the same as or thicker than the gate insulating film and thinner than the interlayer insulating film covering the gate electrode. A feature of an insulated gate semiconductor device. In an insulated gate semiconductor device having a narrow portion and a wide portion between trenches,
2. An insulated gate semiconductor device, wherein a second trench having a region of an emitter potential that is shallower than the trench and has an insulating film inside is provided in a portion where the interval between the trenches is wide. In an insulated gate semiconductor device having a narrow portion and a wide portion between trenches,
An insulated gate comprising a second trench having a region of an emitter potential shallower than the semiconductor region and having an emitter potential inside through an insulating film in the semiconductor region in a portion where the interval between the trenches is wide. Type semiconductor device.

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