JP2007266570A - Insulated gate bipolar transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce on-voltage by suppressing a lowering of a breakdown voltage of a cell of an IGBT having a thinning-out part to obtain an IE effect. <P>SOLUTION: There are provided a substrate; a drift layer formed on the surface of the substrate; a base area formed on the surface of this layer; a gate trench that penetrates this area so as to reach the drift layer from the surface of this area, and is formed to protrude to the drift layer; a channel area formed in the base area between the gate trench and the adjacent gate trench; an emitter area formed in a part of the area in an internal surface of the channel area; a dummy trench formed to protrude in a direction from the base area to the drift area, between the channel area and another channel area; a gate insulating film formed on the surfaces of inner walls of the gate trench and the dummy trench; a gate electrode formed on the gate insulating film inside of the gate trench; a first electrode connected to the channel area; and a second electrode connected to the substrate. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a trench gate type insulated gate bipolar transistor (hereinafter referred to as IGBT).

  Along with the progress of lower power consumption of power converters, there are great expectations for lower power consumption of power devices that play a central role. In particular, due to the conductivity modulation effect, an insulated gate bipolar transistor (hereinafter referred to as IGBT), which can achieve a lower on-voltage than a power MOSFET and can be driven by a gate, greatly contributes to lower power consumption, and its use has become established. Have been doing. Further, compared with a normal so-called planar type IGBT in which a gate electrode is provided on the surface of a semiconductor substrate, a trench type IGBT in which a stripe-shaped trench is dug from the surface of the substrate and a gate electrode is embedded in the trench is provided on the surface of the substrate. In recent years, a large number of channels are formed that are substantially perpendicular to each other and parallel to the direction of current flow.

  One of the important characteristics for the trench IGBT is an on-voltage, and a smaller one is preferable. In order to realize this, a so-called thinned-out IGBT has been proposed. FIG. 20 is a cross-sectional view of the conventional full trench IGBT, and FIG. 21 is a cross-sectional view of the thinned IGBT that is cut across the trench. The thinned-out IGBT has a structure in which cell regions are periodically thinned out from a plurality of continuous cell regions in contrast to an IGBT having a structure in which a plurality of cell regions functioning as elements are continuously arranged in order to reduce the on-voltage. is there. This element is the same as the full trench type IGBT, but since the thinned region is not in contact with the emitter electrode, the holes under the P base layer are not easily discharged to the emitter electrode, and are accumulated here. Since the carrier concentration distribution of the type drift layer is close to that of the diode, it becomes lower than the ON voltage of the IE normal trench type IGBT (see, for example, Patent Document 1). This effect is generally called the IE effect.

  Specifically, the IGBT includes a P + type emitter layer 1, an N− type drift layer 3, a P type base region 4 on the surface of the N− type drift layer 3, and an inner surface side of the P type base region 4. An N + type emitter region 5 located in the region, and a trench 7 having a depth reaching the N− type drift layer 3 from the surface of the P type base region 4 through the N + type emitter region 5 and the P type base region 4, A gate oxide film 6 formed on the inner wall of the trench 7, a gate electrode 8 formed on the gate oxide film 6 inside the trench 7, and a surface of the P-type base region 4, An emitter electrode 9 electrically connected to a part of the P-type base region 4 and the N + -type emitter region 5 is disposed in contact with the back surface of the P + -type emitter layer 1 and is electrically connected to the P + -type emitter layer 1. Collector electrode 10.

  The P-type base region 4 has two regions 4a and 4b that are electrically separated by the trench 7. Of the two regions 4a and 4b, only the region 4a on the left side of FIG. 20 and FIG. N + type emitter region 5 and P type body region 11 are formed. The left region 4 a is electrically connected to the emitter electrode 9 via the P-type body region 11. The N + type emitter region 5 is partially disposed in a region in the vicinity of the trench 7 in the left region 4a. In addition, a channel is formed in a portion in contact with the trench 7 in the left region 4a. This left region 4a is the cell region described above.

  On the other hand, of the two regions 4a and 4b, the region 4b on the right side of the trench 7 in FIG. 21 is electrically insulated from the emitter electrode 9 and other electrodes by the insulating film 12, and is in a floating state. . The left region 4b is a region obtained by thinning a cell region from a plurality of continuous cell regions.

  Hereinafter, an operation for turning on the trench IGBT will be described.

  When the emitter electrode 9 is connected to the ground between the emitter electrode 9 and the collector electrode 10 in the off state, and a voltage higher than this is applied to the collector electrode 10, between the N − type drift layer 2 and the P type base layer 3. The reverse bias junction results in a blocking state below the reverse withstand voltage, but when a voltage higher than the threshold voltage is applied to the gate electrode 7 in this state, the gate electrode 7 is connected to the gate electrode 7 via a gate resistance from a gate drive circuit (not shown). Charge begins to accumulate. At the same time, the channel region which is between the N + emitter region 4 on the inner wall of the first trench 7a and the n-type drift layer 2 and which is in contact with the gate electrode 7 through the gate oxide film 6 is inverted to the n-type. (Not shown) is formed. When the channel region is formed, the reverse bias junction disappears in the path passing through the channel region, so that electrons pass from the emitter electrode 9 through the N + channel region of the N + emitter region 4 and the P base layer 4 to form an N− type. It is injected into the drift layer 3. When electrons are injected into the N − type drift layer 3, the PN junction between the P + type collector layer silicon substrate (collector layer) 1 and the N − type drift layer 3 is forward-biased, and the P type collector layer silicon substrate Holes that are minority carriers are injected from the (collector layer) 1 to the N-type buffer layer 2 and the N-type drift layer. When holes are injected into the N-drift layer 3, so-called conductivity modulation occurs in which the concentration of electrons as majority carriers increases in order to maintain neutral conditions for carriers in the drift layer, so that the resistance of the drift layer decreases. Become. It is ideal that the voltage drop due to the current flowing between the collector electrode 10 and the emitter electrode 9 of the IGBT at this time is approximately the same as the ON voltage of the diode composed of the P + type collector layer 1 and the N− drift layer 2. ON voltage.

Next, the IGBT is turned from the on state to the off state by setting the voltage between the emitter electrode 9 and the gate electrode 8 to be equal to or lower than a threshold value. Then, the charge accumulated in the gate electrode 8 is discharged to the gate drive circuit via the gate resistance, the channel region that has been inverted to the N-type returns to the P-type, and the channel region disappears, so the supply of electrons stops. At the same time, the injection of holes from the collector electrode 10 is also eliminated. However, the current flows until the electrons and holes accumulated in the N − type drift layer 3 are discharged to the collector electrode 10 and the emitter electrode 9 or disappear by recombination with each other. And the current is turned off after the hole disappears.
JP 2001-308327 A

  In the conventional device, in order to suppress the saturation current in the DC operation and reduce the on-voltage, the size of the trench portion for channel operation is, for example, 4 [μm], whereas the accumulation of hole concentration by the IE effect is promoted. Therefore, it is necessary to increase the thinning portion size to 20 [μm]. However, when the relationship between the thinning dimension and the element breakdown voltage is obtained by simulation, it is clear that the element breakdown voltage decreases when the thinning dimension is increased. This relationship is shown in FIG. It was found that when the thinning dimension is 20 [μm] with respect to 4 [μm], the breakdown voltage is reduced by about 350 [V]. In order to prevent a decrease in withstand voltage, the size of the screen should be as small as 4 [μm]. However, since the channel size is large in this size, the saturation current increases, for example, a large current flows when the load is short-circuited. There is a problem that leads to destruction. Therefore, the channel portion is thinned out to suppress the saturation current, and in order to achieve a low Von due to the IE effect, the blinking interval is set to 20 [μm], and the optimum design is performed from the tradeoff between the saturation current and Von. In view of this, the breakdown voltage reduced by increasing the thinning dimension to 20 [μm] is compensated by increasing the element thickness. As a result, even if the on-voltage was reduced by thinning out, the on-voltage increased to increase the element thickness, the on-voltage reduction effect was reduced as a whole, and the on-voltage could not be lowered sufficiently. .

  The present invention proposes an IGBT element structure in which the withstand voltage is not reduced by the thinning-out portion, and an IE effect equivalent to that of the conventional one is obtained and a low voltage is possible.

  In order to achieve the above object, the invention according to claim 1 is a first conductivity type first semiconductor layer, a second conductivity type second semiconductor layer formed on a surface of the first semiconductor layer, and A third semiconductor layer of a first conductivity type formed on a surface of the second semiconductor layer, and penetrating through the third semiconductor layer so as to reach the second semiconductor layer from the surface of the third semiconductor layer; A gate trench formed so as to protrude into the two semiconductor layers, a channel region formed in the third semiconductor layer between the gate trench and the adjacent gate trench, and a part of the inner surface of the channel region The second semiconductor in a direction from the third semiconductor layer to the second semiconductor layer between the fourth semiconductor layer of the second conductivity type formed in the region, the channel region, and another channel region. Dummy formed to protrude into the layer A wrench, a gate oxide film formed on the inner wall surface of the gate trench and the dummy trench, a gate electrode formed on the gate oxide film inside the gate trench, and the channel region are electrically connected. And a second electrode electrically connected to the first semiconductor layer.

  In this manner, by providing the dummy trench protruding at least to the second semiconductor layer between the gate trench and the gate trench, the on-voltage can be reduced without lowering the breakdown voltage of the transistor.

  According to a second aspect of the present invention, the dummy trench is grounded at the emitter.

  By grounding the dummy trenches at the emitter, adverse effects on the switching characteristics when switching off and on can be suppressed.

  The invention according to claim 3 is characterized in that the potential of the dummy trench is floating.

  By making the potential of the dummy trench floating, the surge voltage when the switching state is switched from on to off can be reduced.

  The invention according to claim 4 is characterized in that the third semiconductor layer is divided by a dummy trench.

  According to a fifth aspect of the present invention, in the region divided by the dummy trench, the third semiconductor layer is not formed, and the tip end portion of the gate trench exists at the end portion of the insulated gate bipolar transistor. Is encased in a third semiconductor layer.

  By wrapping the bottom portion of the gate trench with the third semiconductor layer, the electric field at the portion where the third semiconductor layer at the end of the transistor is in contact with the gate trench in the vicinity of the end can be relaxed, and a decrease in breakdown voltage can be prevented.

  According to a sixth aspect of the present invention, at least one of the gate oxide film thickness, the trench depth, the width, and the buried electrode type of the gate trench and the dummy trench is the same, and the trench interval is also the same. It is characterized by that.

  According to a seventh aspect of the present invention, an interval between the dummy trench and another dummy trench that is closest to the dummy trench is between the gate trench and another gate trench facing each other across the channel region. Or less.

  The breakdown voltage decreases when the distance between the gate trench and the dummy trench, or between the dummy trench and the dummy trench, or between the gate trench and the gate trench is wide. For this reason, it is possible to prevent a decrease in breakdown voltage by making the distance between the dummy trench and the dummy trench equal to or narrower than the distance between the gate trench and the gate trench sandwiching the channel portion.

  The invention according to claim 8 is characterized in that the dummy trench has an annular shape with respect to the extending direction of the first semiconductor layer.

  By making the dummy trench into an annular shape without termination, an electric field relaxation effect is obtained also in a direction orthogonal to the extending direction of the first semiconductor layer, and a high breakdown voltage is obtained.

  The invention according to claim 9 is characterized in that the dummy trench has a plate-like shape parallel to the direction in which the channel regions are arranged.

  The invention described in claim 10 has a structure in which the blink P is diffused in the blink region, and is diffused to a position where the outer peripheral P diffusion termination contacts the channel portion trench.

  Hereinafter, the present invention will be described in detail using the first to fifth embodiments.

(First embodiment)
The first embodiment will be described with reference to FIGS. 1 and 2.

  FIG. 2 shows the IGBT in the present embodiment. 2 is a cross-sectional view taken along line A-A 'of the plan view shown in FIG.

  The correspondence between this embodiment and the present invention is as follows. The P type corresponds to the first conductivity type, and the N type corresponds to the second conductivity type. The P + type emitter layer 1 corresponds to the first semiconductor layer, the N− type drift layer 3 corresponds to the second semiconductor layer, the P type base region 4 corresponds to the third semiconductor layer, and the N + type emitter region 5 corresponds to the first semiconductor layer. This corresponds to 4 semiconductor layers. The emitter electrode 9 corresponds to the first electrode, and the collector electrode 10 corresponds to the second electrode.

  In the IGBT of this embodiment, for example, a silicon (Si) substrate is used as the P + type emitter layer 1, and the N + type drift layer is added to the N type buffer layer 2 and the N type buffer layer 2 on the P + type collector layer 1. The layer 3 is further laminated with a P-type base region 4 on the N − -type drift layer 3. As the gate oxide film 6, a silicon oxide film (SiO2 film) is used. In addition, polysilicon (Poly-Si) doped with phosphorus (P) at a high concentration and reduced in resistance is buried as a gate electrode 8 in the gate trench 7a. The gate trench 7a is connected to the gate electrode 8 and is electrically floating.

  The cell region is constituted by two gate trenches 7a adjacent to each other with a channel region having a MOS structure of 4 [μm]. The channel region is formed by diffusing the N + emitter region 5 in the channel P4a. The depth of the channel region, that is, the thickness of the P-type base region 4 is 4 [μm]. A body P11 is formed between the channel P4a and the emitter electrode 9 so as to be in contact with the emitter electrode 9. Further, an interlayer insulating film 12 is provided between the gate trench 7 a and the emitter electrode 9 so that the gate trench 7 a does not contact the emitter electrode 9.

  In this embodiment, the dummy trench 7b is provided in the dummy P4b region having a structure in which the distance between the cell regions in FIG. 21 is increased. The dummy trench 7b has the same shape, size, and structure as the gate trench 7a, and is embedded with polysilicon (Poly-Si) doped with phosphorus (P) at a high concentration and reduced in resistance, similar to the gate trench 7a. It is. The polysilicon electrode buried in the dummy trench 7b is grounded to the emitter, and a 1000 [Å] gate oxide film is provided on the surface of the dummy trench 7b. The interval between the adjacent dummy trenches 7b is 4 [μm].

  On the other hand, the dummy P4b is electrically insulated from the channel P4a by the gate trench 7a, and has a floating potential.

  In this way, by setting the gate trench 7a to be floating and the dummy trench 7b to be grounded on the emitter, adverse effects on the switching characteristics when switching off and on can be suppressed. For this reason, it is excellent in controllability of switching characteristics. The switching speed can be controlled by changing the gate resistance value.

  Here, the configuration of the dummy trench 7b and the gate trench 7a in the depth direction (the extending direction of the channel P4a) will be described with reference to FIG. 2 is a cross-sectional view taken along the line A-A 'of FIG. As shown in FIG. 2, the IGBT includes an element portion between a gate trench 7a located at one end and a gate trench 7a located at the other end, and a gate trench 7a located at the end. The outer peripheral portion of the element.

  The gate trench 7a of this embodiment has an annular shape as shown in FIG. An annular gate trench 7a is provided so as to enclose the dummy trench 7b, and the inner peripheral sides of the gate trench 7a face the outer peripheral sides of the dummy trench 7b substantially in parallel. The distance between the inner periphery of the gate trench 7a and the outer periphery of the dummy trench 7b facing the inner periphery, the outer periphery of the gate trench 7a, and the adjacent gate trench 7a facing the outer periphery. The distance to the outer periphery is the same distance as 4 [μm]. Further, the angle of the corner of the gate trench 7a and the corner of the dummy trench 7b is about 90 degrees.

  As shown in FIG. 1, the dummy trench 7b is formed in an annular shape having no termination, and the outer periphery of the dummy trench 7b and the inner periphery of the gate trench 7a are arranged at equal intervals, thereby making it possible to obtain a depth direction (in the case of FIG. 1). An electric field relaxation effect is also obtained in the (vertical direction), and a breakdown voltage equivalent to the point S in FIG.

  Hereinafter, the effect of this embodiment will be described with reference to FIG. In the present embodiment, the dummy trenches 7b are formed in the dummy P4b at an interval equivalent to the interval between the gate trenches 7a (the width of the cell region). As a result, the breakdown voltage of the dummy P4b can be improved.

  Furthermore, even if the floating thinned-out portion is divided by the dummy trench 7b, there is no difference in the hole concentration accumulated immediately below the gate trench 7a having a structure in which the distance between the cell regions is simply increased in FIG. An IE effect equivalent to the structure can be obtained.

  Next, switching characteristics of the IGBT of the present embodiment and the IGBT having a structure in which the distance between the conventional cell regions shown in FIG. 21 is increased will be described with reference to FIGS. FIG. 3 is a simulation circuit when the IGBT is used for the switching operation, FIG. 4 is a switching characteristic of the conventional structure (a structure in which the distance between the cell regions is simply increased), and FIG. 5 is a switching characteristic of the structure of the present embodiment. Represents.

  Further, as shown in FIGS. 4 and 5, the surge voltage Vpeak when the switch is switched from on to off is 1100 [V] in the structure of the present embodiment, whereas 1020 [V in the conventional structure. 〕Met.

  Further, FIG. 6 shows the amount of heat generated in the switch on / off state by the structure of this embodiment and the conventional structure, and the surge voltage Vpeak. As shown in FIG. 6, the structure of this embodiment can reduce the loss EON generated by switching on with the same gate resistance. In addition, the loss when the switch is off generates 0.102 [J] in the structure of the present embodiment, but the conventional structure is 0.108 [J], and the structure of the present embodiment has a loss. Few.

  As described above, the device withstand voltage can be improved by forming one or a plurality of dummy trenches 7b at the same interval as the gate trenches 7a in the conventional dummy P4b having a structure in which the distance between the cell regions is simply increased. Accordingly, the chip thickness can be reduced and the IE effect similar to that of the conventional full trench structure can be obtained, so that the on-voltage can be reduced.

  In this embodiment, the number of dummy trenches 7b is two, but the number is not limited and may be selected in consideration of the IE effect. Since the element breakdown voltage is determined by the distance between the gate trench 7a and the dummy trench 7b, or the gate trench 7a and the gate trench 7a, or the dummy trench 7b and the dummy trench 7b, the width of the dummy P4b (distance between the cell regions) is increased. However, if the number of dummy trenches 7b is increased, it is possible to suppress a decrease in breakdown voltage. Further, if the distances between the gate trench 7a and the dummy trench 7b, the gate trench 7a and the gate trench 7a, and the dummy trench 7b and the dummy trench 7b are determined to be, for example, 4 [μm], the dummy until the required IE effect is obtained. By increasing the width of P4b (distance between cell regions) and increasing the number of dummy trenches 7b, it is possible to suppress a decrease in breakdown voltage.

  Although not shown, the hole concentration directly under the gate trench 7a when the P-type base region 4 is present between the cell regions (that is, when the dummy P4b is present) and when the P-type base region 4 is not present is estimated by simulation. As a result, it was found that there was no difference in the hole concentration. That is, even if there is no P-type base region 4, the IE effect can be obtained by providing the dummy trench 7b.

[Modification of First Embodiment]
The characteristic structure of this modification is that the shape of the dummy trench 7b is not an annular shape. As shown in FIG. 7, although the dummy trench 7b exists inside the gate trench 7a, the parallel direction side of the thinned portion is cut and the depth direction (vertical direction in FIG. 7) side exists. That is, a plurality of linear dummy trenches 7b are provided in the parallel direction of the body P11 in the dummy P4b inside the gate trench 7a. As described above, even when the dummy trench 7b is not formed into an annular shape, the distance between the gate trench 7a and the dummy trench 7b, the distance between the dummy trench 7b and the dummy trench 7b, and the gate trench 7a and the gate trench 7a. Since the same electric field relaxation effect can be obtained at all points, the breakdown voltage can be improved as in the first embodiment described above.

(Second Embodiment)
The second embodiment will be described with reference to FIGS. The second embodiment is different from the first embodiment in that the dummy trench 7b is floating. In addition, about the structure equivalent to the above-mentioned 1st Embodiment, the code | symbol similar to 1st Embodiment is attached | subjected, and description in 2nd Embodiment is abbreviate | omitted.

  FIG. 8 is a cross-sectional view showing the IGBT in the second embodiment and corresponds to FIG. 2 in the first embodiment. As shown in FIG. 8, the dummy trench 7b is floating.

  FIG. 9 shows the switching characteristics of the IGBT having the dummy trench 7b in the floating state, and FIG. 10 shows the loss and surge voltage Vpeak generated in the switch on / off state. From FIG. 9, it can be seen that the structure of this embodiment is about twice as large for both Eoff and Eon, and the performance is worse than that of the conventional cell structure.

  However, the surge voltage Vpeak at the time of switch-off is 1020 [V] in the conventional structure, whereas the structure of this embodiment is 770 [V], and the surge voltage can be greatly reduced.

(Third embodiment)
The third embodiment will be described with reference to FIGS. The third embodiment is different from the first embodiment in that the dummy trench 7 b is not in contact with the P-type base region 4. In addition, about the structure equivalent to the above-mentioned 1st Embodiment, the code | symbol similar to 1st Embodiment is attached | subjected, and description in 3rd Embodiment is abbreviate | omitted.

  FIG. 12 is a cross-sectional view showing the IGBT in the third embodiment, and corresponds to FIG. 2 in the first embodiment. 11 is a cross-sectional view showing the IGBT and corresponds to FIG. 1, and FIG. 13 is a cross-sectional view taken along line C-C ′ of FIG.

  As shown in FIGS. 12 and 13, the IGBT of this embodiment does not have the outer peripheral P region 13 between the dummy trench 7b and the gate trench 7a and between the dummy trench 7b and the dummy trench 7b. That is, the dummy P4b described in each of the above embodiments does not exist. Further, as shown in FIG. 11, in the depth direction of the element (vertical direction in FIG. 11), the channel P4a including the gate trench 7a exists only before the dummy trench 7b. That is, the dummy trench 7b does not contact any P-type region.

  Thus, when there is no dummy P4b, there are the following advantages in the vicinity of the boundary between the cell region and the element outer periphery.

  As in the first embodiment described above, in an IGBT element having a dummy P4b, the outer peripheral P region 13 of the outer peripheral part of the emitter grounded is short-circuited to the floating dummy P4b beyond the outermost gate trench 7a. I can't do it. Therefore, in this case, the outermost peripheral gate trench 7 a has a structure protruding from the N − type drift layer 3. For this reason, in the structure of the first embodiment, there is a possibility that electric field concentration occurs at the portion where the P-type base region 4 and the gate trench 7a on the outer periphery of the element are in contact with each other and the breakdown voltage is lowered. However, in the structure in which there is no dummy P4b and the N− type drift layer 3 is between the cell region and other cell regions as in the present embodiment, the outer peripheral portion P region 13 covers the bottom of the outermost gate trench 7a. Can be wrapped. In other words, since there is no dummy P4b grounded at the emitter, there is no possibility of shorting to the emitter even if the P-type base region 4 in the outer periphery of the element exceeds the gate trench 7a. For this reason, there is no possibility that the IE effect is hindered by providing the dummy trench 7b. Further, in such a structure in which the dummy P4b does not exist, the depth of the outer peripheral P region 13 can be made deeper than the depth of the outermost gate trench 7a, and the bottom of the gate trench 7a is included in the outer peripheral P region 13. Therefore, the electric field at the portion where the P-type base region 4 in the outer peripheral portion of the element and the outermost gate trench 7a are in contact is relaxed, and the breakdown voltage can be prevented from being lowered. Even if the dummy trench 7b is provided to improve the breakdown voltage of the element as in the present invention, if the breakdown voltage at the portion where the outer peripheral P region 13 and the outermost peripheral gate trench 7a are in contact is low, The breakdown voltage of the entire element is reduced. For this reason, it is desirable to improve the breakdown voltage at the location where the outer peripheral P region 13 and the outermost peripheral gate trench 7a are in contact with each other as in this embodiment.

  FIG. 14 shows the distance between the trenches (the distance between the gate trench 7a and the dummy trench 7b and the distance between the dummy trench 7b and the dummy trench 7b when the distance between the gate trenches 7a forming one cell region is 4 μm. (Assuming that the distance is equal) and the breakdown voltage. The graph with “dummy P4b” and a leader line is attached to the structure of the first embodiment (with dummy P4b), and the graph with “no dummy P4b” and a leader line attached to the structure of this embodiment ( The relationship between the breakdown voltage of the dummy P4b) and the trench distance is shown. As shown in FIG. 14, even when the dummy P4b does not exist, the distance (4 [μm]) between the gate trenches 7a forming the cell region is equal to the distance between the dummy trench 7b and the gate trench 7a. In this case (distance between the dummy trench 7b and the gate trench 7a = 4 [μm]), a breakdown voltage equivalent to that when the dummy P4b is present can be obtained.

  Although not shown, as a result of estimating the hole concentration immediately below the gate trench 7a with and without the dummy P4b by simulation, it was found that there is no difference, that is, without being affected by the presence or absence of the dummy P4b. An effect can be obtained.

(Fourth embodiment)
The fourth embodiment will be described with reference to FIGS. 15 to 17. The fourth embodiment has a structure in which the dummy trench 7b is in contact with the P-type base region 4, and is the same as the first embodiment. FIG. 15 is a plan view showing an IGBT in the fourth embodiment, and corresponds to FIG. 1 in the first embodiment. 16 is a cross-sectional view taken along line DD ′ in FIG. 15, and corresponds to FIG. Here, as shown in FIG. 16, in the emitter electrode 9, the central portion of the portion in contact with the outer peripheral P region 13 is the end of the diffusion window. The distance between the side surface of the gate trench 7a located at the outermost wall and the end of the diffusion window is defined as the overlap amount.

FIG. 17 is a diagram showing the relationship between the overlap amount between the diffusion window end and the trench and the element breakdown voltage when the diffusion depth of the outer peripheral P region 13 is 8 [μm]. In FIG. 17, the overlap amount = 0 [μm] is a state where the side surface of the gate trench 7 a is located immediately below the end of the diffusion window, and the overlap amount is negative (rightward in the horizontal axis in FIG. 17). Accordingly, the distance between the end of the diffusion window and the side surface of the gate trench 7a is increased. As shown in FIG. 17, when the diffusion depth of the outer peripheral P region 13 is 8 [μm], the distance from the end of the diffusion window to the trench 7a, that is, the overlap amount is 5 [μm] or less (in FIG. 10 [μm]), the collector-emitter breakdown voltage is stable and high. This is because when the diffusion layer in the outer peripheral P region 13 comes close to contact with the gate trench 7a, the depletion layer in the outer peripheral P region extends to the bottom of the trench 7a and relaxes the electric field at the bottom of the trench. In order to improve the breakdown voltage between the collector and the emitter, a stable high value can be obtained. However, it is necessary to make the outer peripheral P diffusion layer 13 approach so as not to get over the channel trench. This is because the dummy P is short-circuited with the outer periphery P, and the IE effect cannot be obtained.
As shown in FIG. 23, even if the diffusion layer 13 on the outer periphery P passes over the channel trench, the outer periphery P diffusion layer approaches the channel portion trench as long as it does not come into contact with the channel portion trench. Even if it is short-circuited with the dummy P, the concentration of the outer peripheral P diffusion layer under the channel trench is low, so that the resistance between the dummy P and the outer peripheral P becomes sufficiently high as long as the IE effect is obtained. Does not interfere with the effect. In the embodiment, the trench depth is 5.0 μm, the trench width is 1.0 μm, the channel diffusion depth is 4.0 μm, the outer peripheral P diffusion surface concentration is 3e18 cm, the diffusion depth is 9.0 μm, and the distance from the trench to the outer peripheral diffusion layer window is 2.0 μm. This is the case. In the prototype, the on-voltage was compared between this structure and the structure where the outer peripheral P diffusion layer window and the trench had a sufficient distance and the outer peripheral P diffusion could not get over the trench P. However, there was no difference in Von and the IE effect was sufficiently obtained. It was done.

(Fifth embodiment)
A fifth embodiment will be described with reference to FIGS. 18 and 19. 18 is a plan view of the IGBT, and FIG. 19 is a cross-sectional view taken along the line BB ′ of FIG. As shown in FIG. 19, the gate trench 7a is formed to have a trench depth of 5 [μm], deeper than the channel depth 4.0 [μm] of the dummy trench 7a and shallower than the gate trench. Since the withstand voltage at the bottom of the trench is higher in the shallow dummy trench than in the deep gate trench, the withstand voltage is always determined at the bottom of the gate trench. As a result, there is an advantage that it is possible to obtain a stable cell breakdown voltage that can be obtained by the gate trench without being affected by the dummy trench.

The top view of trench gate type IGBT in a 1st embodiment is shown. A sectional view of trench gate type IGBT in a 1st embodiment is shown. It is an example of the switching circuit using IGBT in 1st Embodiment. It is a figure which shows the operation | movement waveform at the time of switching off of a conventional element. It is a figure which shows the operation | movement waveform of IGBT in 1st Embodiment. It is a table | surface which shows the switching loss (Eon, Eoff) of the conventional element and IGBT of 1st Embodiment, and the surge voltage (Vpeak) at the time of switching. The top view of the trench gate type IGBT in the modification of 1st Embodiment is shown. Sectional drawing of the trench gate type IGBT in 2nd Embodiment is shown. It is a figure which shows the operation | movement waveform of IGBT in 2nd Embodiment. It is a table | surface which shows the switching loss (Eon, Eoff) of the conventional element and IGBT of 2nd Embodiment, and the surge voltage (Vpeak) at the time of switching. The top view of the trench gate type IGBT in 3rd Embodiment is shown. Sectional drawing of the trench gate type IGBT in 3rd Embodiment is shown. The fragmentary sectional view of trench gate type IGBT in a 3rd embodiment is shown. The distance between the trenches (the distance between the gate trench and the dummy trench and the distance between the dummy trench and the dummy trench when the distance between the gate trenches forming one cell region of the trench gate type IGBT in the third embodiment is 4 μm. ) And the breakdown voltage. The top view of the trench gate type IGBT in 4th Embodiment is shown. The fragmentary sectional view of trench gate type IGBT in a 4th embodiment is shown. The relationship between the overlap amount of the diffusion window edge and trench in 4th Embodiment and an element breakdown voltage is shown. The top view of the trench gate type IGBT in 5th Embodiment is shown. The fragmentary sectional view of trench gate type IGBT in a 5th embodiment is shown. Sectional drawing of the conventional full trench type IGBT is shown. Sectional drawing of the conventional thinning type IGBT is shown. The relationship between the distance between gate trenches that form one cell region of a conventional trench gate type IGBT and the breakdown voltage is shown. The fragmentary sectional view of trench gate type IGBT in a 6th embodiment is shown.

Explanation of symbols

1 P + type emitter layer 2 N type buffer layer 3 N− type drift layer 4 P type base region 4a Channel P
4b Dummy P
5 N + emitter region 6 Gate oxide film 7a Gate trench 7b Dummy trench 8 Gate electrode 9 Emitter electrode 10 Collector electrode 11 Body P
12 Interlayer insulation film 13 Outer periphery P region

Claims (12)

A first conductivity type first semiconductor layer (1);
A second conductivity type second semiconductor layer (2, 3) formed on the surface of the first semiconductor layer (1);
A third semiconductor layer (4) of the first conductivity type formed on the surface of the second semiconductor layer (3);
Formed so as to penetrate the third semiconductor layer (4) so as to reach the second semiconductor layer (3) from the surface of the third semiconductor layer (4) and to protrude to the second semiconductor layer (3) Gate trench (7a),
A channel region (4a) formed in the third semiconductor layer (4) between the gate trench (7a) and the adjacent gate trench (7a);
A fourth semiconductor layer (5) of the second conductivity type formed in a partial region on the inner surface of the channel region (4a);
Formed between the channel region and another channel region so as to protrude from the third semiconductor layer (4) to the second semiconductor layer (3) in the direction from the third semiconductor layer (4). Dummy trench (7b) made,
A gate insulating film (6) formed on inner wall surfaces of the gate trench (7a) and the dummy trench (7b);
A gate electrode (8) formed on the gate insulating film (6) inside the gate trench (7a);
A first electrode (9) electrically connected to the channel region (4a);
An insulated gate bipolar transistor comprising a second electrode (10) electrically connected to the first semiconductor layer (1). The insulated gate bipolar transistor according to claim 1, wherein the dummy trench (7b) is grounded at the emitter. The insulated gate bipolar transistor according to claim 1, wherein the potential of the dummy trench (7b) is floating. The insulated gate bipolar transistor according to any one of claims 1 to 3, wherein the third semiconductor layer (4) is divided by a dummy trench (7b). In the region divided by the dummy trench (7b), the third semiconductor layer (4) is not formed, and the tip of the gate trench (7a) existing at the end of the insulated gate bipolar transistor. 4. The insulated gate bipolar transistor according to claim 1, wherein the insulated gate bipolar transistor is enclosed in a third semiconductor layer. 4. At least one of the gate oxide film thickness, trench depth, width, and buried electrode type of the gate trench (7a) and the dummy trench (7b) is the same, and the trench interval is also the same. An insulated gate bipolar transistor according to any one of claims 2 to 4. The distance between the dummy trench (7b) and another nearest dummy trench (7b) is another gate trench facing the gate trench (7a) and the channel region (4a). 7. The insulated gate bipolar transistor according to claim 1, wherein the insulated gate bipolar transistor is equal to or less than an interval between (7 a). The insulated gate type according to any one of claims 1 to 7, wherein the dummy trench (7b) has an annular shape with respect to an extending direction of the first semiconductor layer (1). Bipolar transistor. The insulated gate bipolar transistor according to any one of claims 1 to 7, wherein the dummy trench (7b) has a plate shape parallel to a direction in which the channel regions (4a) are arranged. In the structure in which the blink P is diffused in the blink region, the outer peripheral P diffusion end is brought into contact with the channel portion trench more than the contact, and the outer peripheral P diffusion layer is brought close to the position where the channel portion trench is not short-circuited with the dummy P. The insulated gate bipolar transistor according to any one of claims 1 to 7, wherein a diffusion layer is formed. With a structure in which the blink P is diffused in the blink region, the outer peripheral P diffusion layer approaches the channel trench in a range where it does not come in contact, and diffuses to a position where the outer peripheral P diffusion layer passes over the channel trench and shorts with the dummy P 8. The insulated gate bipolar transistor according to claim 1, wherein a layer is formed. 8. The insulated gate bipolar transistor according to claim 1, wherein the dummy trench has a shallower depth than the channel trench.

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