JP2006049455A - Trench type insulated gate semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a trench type insulated gate semiconductor device which obtains a high element breakdown voltage, makes switching loss low also and reduces total generating loss in the state where ON-state voltage of a trench type IGBT is maintained at the same low state as an ordinary IEGT. <P>SOLUTION: The trench type insulated gate semiconductor device comprises respectively a first gap wherein two or more first trenches sandwiches the base layer, and a second gap larger than the first gap. The base layer of the first gap is provided with the source region of the first conductivity type; an emitter electrode is brought into common contact with both the surfaces of the base layer and the source region; and it is provided with a flattening means common to the equipotential line of the depletion layer, which spreads in the drift layer under the second gap and the equipotential line of the depletion layer which spreads in the drift layer under the first gap, when the forward voltage is impressed at the time of OFF in the base layer of the second gap. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a trench type insulated gate semiconductor device such as a trench type IGBT.

Along with the progress of lower power consumption of power converters, there are great expectations for lower power consumption of power devices that play a central role. In particular, due to the conductivity modulation effect, an insulated gate bipolar transistor (hereinafter referred to as IGBT), which can achieve a lower on-voltage than a power MOSFET and can be driven by a gate, greatly contributes to lower power consumption, and its use has become established. Have been doing. In addition, compared with a normal so-called planar type IGBT in which a gate electrode is provided on the surface of a semiconductor substrate, a trench type IGBT in which a striped trench is dug from the surface of the substrate and a gate electrode is embedded in the trench is provided on the surface of the substrate. In recent years, a large number of channels are formed that are substantially perpendicular to each other and parallel to the direction of current flow.
The structure of this trench IGBT will be described with reference to FIG. FIG. 2 is a cross-sectional view of an n-channel IGBT having a trench gate having a stripe pattern on the surface of the silicon substrate, cut in a direction perpendicular to the silicon substrate surface and across the trench gate. In this figure, a p base layer 3 is formed on the surface of a drift layer 2 of a silicon wafer comprising a stack of a p-type high-concentration silicon substrate 1 and an n-type low-concentration drift layer 2. An n + source region 4 is selectively formed in the layer. In addition, a first trench 5 is formed which reaches the n-type drift layer 2 through the p base layer 3 from the surface on the n + source region 4 side. However, as a manufacturing method, the first trench 5 is first formed from the surface of the p base layer 3, and the first trench 5 is filled with conductive polycrystalline silicon serving as the gate insulating film and the gate electrode 7. , N + source region 4 is formed. An interlayer insulating film 8 is formed on the gate electrode 7 so as to cover it, and an emitter electrode 9 made of a metal film is in contact with the n + source region 4 and the p base layer 3 in common thereover. It is provided as follows. Further, a nitride film or an amorphous silicon film may be formed as a passivation film on the upper portion, but is omitted in FIG. A collector electrode 10 made of a metal film is provided on the surface (back surface) of the p-type silicon substrate (collector layer) 1 opposite to the drift layer 2.

Hereinafter, an operation for turning on the trench IGBT will be described.
When the emitter electrode 9 is connected to the ground between the emitter electrode 9 and the collector electrode 10 in the off state, and a voltage higher than this is applied to the collector electrode 10, the reverse bias junction between the n drift layer 2 and the p base layer 3 is applied. However, when the voltage is higher than the threshold voltage in this state, the gate electrode 7 is charged by the gate drive circuit (not shown) via the gate resistance. Begins to accumulate. At the same time, the channel region which is between the n + source region 4 and the n-type drift layer 2 on the inner wall of the first trench 5 and which is in contact with the gate electrode 7 through the gate oxide film 6 is inverted to the n-type. (Not shown) is formed. When this channel region is formed, the reverse bias junction disappears in the path passing through the channel region, so that electrons pass from the emitter electrode 9 through the n channel region of the n + source region 4 and the p base layer 3 and the n type drift. Implanted into layer 2. When electrons are injected into the n-type drift layer 2, the pn junction between the p-type silicon substrate (collector layer) 1 and the n-type drift layer 2 is forward-biased, and the p-type silicon substrate (collector layer) 1 Holes that are minority carriers are injected into the n-type drift layer 2. When holes are injected into the drift layer 2, so-called conductivity modulation occurs in which the concentration of electrons as majority carriers increases in order to maintain neutral conditions for carriers in the drift layer, and the resistance of the drift layer decreases. At this time, the ideal voltage drop due to the current flowing between the collector electrode 10 and the emitter electrode 9 of the IGBT is approximately the same as the diode ON voltage of the p collector layer 1 and the n drift layer 2. It is.

Next, the IGBT is turned from the on state to the off state by setting the voltage between the emitter electrode 9 and the gate electrode 7 to a threshold value or less. Then, the charge accumulated in the gate electrode 7 is discharged to the gate drive circuit through the gate resistance, the channel region that has been inverted to the n-type returns to the p-type, and the channel region disappears, so that the supply of electrons stops. At the same time, the injection of holes from the collector electrode 10 is also eliminated. However, current flows until electrons and holes accumulated in the n-type drift layer 2 are discharged to the collector electrode 10 and the emitter electrode 9, respectively, or disappear by recombination with each other. After the hole disappears, the current is turned off.
Various improvement methods have been proposed to further reduce the on-voltage of the trench IGBT. For example, IEGT (INJECTION ENHANCED GATE BIPOLOR TRANSISTOR) can produce a limit characteristic close to the ON voltage of the diode. In this IEGT, the n + source region of the cell and a part of the substrate surface of the p base layer are covered with an insulating layer so that these regions and the emitter electrode do not contact each other. This operation is basically the same as that of the trench IGBT, but the holes under the p base layer where the n + source region and the p base layer are not in contact with the emitter electrode are difficult to be discharged to the emitter electrode. Since it accumulates here and the carrier concentration distribution of the n-type drift layer is close to that of the diode, it becomes lower than the on-voltage of a normal trench IGBT (Patent Document 1). Furthermore, power devices are always required to have high-speed switching characteristics in addition to a low on-voltage, and improvement thereof is an important issue. However, since the trench IGBT and the IEGT have a trench structure formed at a high density in order to obtain a low on-voltage as described above, the capacitance between the gate electrode and the emitter electrode also increases. As the capacity increases, the high-speed switching characteristics deteriorate and the switching loss increases. In other words, there is a trade-off between low on-voltage and reduced switching loss or high-speed switching characteristics, where the other worsens, so it is usually difficult to improve both the low on-voltage and high-speed switching characteristics. is there. However, it is also an important issue that must be solved.

A trench IGBT that improves the trade-off characteristics between the on-voltage and the switching characteristics by increasing the concentration of accumulated carriers on the emitter electrode side is known as an improvement in the trade-off characteristics between the on-voltage and the switching characteristics. (Patent Document 2-0020 paragraph).
As described in the above-mentioned IGBT operation, when switching to ON / OFF operation, it is necessary to charge / discharge the capacitance between the gate electrode and the emitter electrode. Not only does the loss increase, but a larger gate drive circuit is also required. Since the generated loss of the power device is the sum of the steady loss determined by the on-voltage and the switching loss during the on / off operation, the switching loss is reduced along with the reduction of the on-voltage, that is, the capacitance between the gate electrode and the emitter electrode is reduced. It is also important to reduce. For example, an insulated gate semiconductor device having an IEGT structure as shown in FIG. 2 has been proposed as a semiconductor device in which the on-voltage is reduced and the capacitance between the gate electrode and the emitter electrode is reduced (Patent Document 3). Furthermore, an invention relating to a power semiconductor device that can simplify the control circuit and has low on-state voltage and steady loss is also known (Patent Document 4).
JP-A-5-243561 (FIG. 101) Japanese Unexamined Patent Publication No. 2000-228519 (FIG. 7) JP 2001-308327 A (FIG. 1) JP-A-9-139510 (FIG. 1)

However, the IEGT structure described in Patent Document 3 has a problem that it is difficult to obtain a high element breakdown voltage. The reason is that the electric field distribution in the silicon substrate tends to be non-uniform when off (when the applied voltage is blocked), and the breakdown is likely to occur at a voltage lower than the design withstand voltage due to electric field concentration below the trench gate. It is.
The present invention has been made in view of such problems. The on-state voltage of the trench IGBT remains as low as IEGT, the switching loss is reduced, the total generation loss is reduced, and the high An object of the present invention is to provide a trench type insulated gate semiconductor device capable of obtaining an element breakdown voltage.

  According to the present invention, the drift layer of the first conductivity type, the base layer of the second conductivity type formed in one surface of the drift layer, the base layer In the trench type insulated gate semiconductor device comprising a plurality of first trenches having a gate electrode embedded in a gate oxide film with a depth reaching the drift layer and reaching the drift layer, the plurality of first trenches Has a first interval sandwiching the base layer and a second interval (between bc) wider than the first interval, and the base layer of the first interval is selective from the surface of the base layer to the inner wall surface of the first trench. A source region of the first conductivity type formed on the base layer, the emitter electrode is in common contact with both surfaces of the base layer and the source region, and the base layer of the second interval (between bc) During forward voltage application, the second interval (Between bc) Trench-type insulated gate provided with a common flattening means for the equipotential line of the depletion layer extending to the drift layer below and the equipotential line of the depletion layer extending to the drift layer under the first interval By using a semiconductor device, the object of the present invention is achieved.

According to the second aspect of the present invention, the equipotential line common flattening means is formed on the surface of the second conductivity type base layer at the second interval (between bc), and the conductor is formed inside. The total volume inside the second trench is larger than the total volume inside the first trench, and the conductor formed inside the second trench is made up of the emitter, collector, and gate electrode. Preferably, the trench type insulated gate semiconductor device according to claim 1 is not connected to any of the above.
According to the third aspect of the present invention, the conductor filled in the second trench has a gate oxide film interposed between the inner surface of the second trench and the trench. It is more preferable to use a type insulated gate semiconductor device.
According to the present invention as set forth in claim 4, the trench type insulation according to claim 2 or 3, wherein the depth of the second trench is equal to or deeper than the depth of the first trench. A gate semiconductor device is also preferable.

  According to the present invention as set forth in claim 5, the conductor is installed on the surface of the second conductivity type base layer at the second interval (between bc) through an insulating film of 500 nm or less. The trench-type insulated gate semiconductor device described in 1 is also desirable.

  According to the present invention, there is provided a trench type insulated gate semiconductor device in which the on-voltage of the trench IGBT is kept as low as IEGT, the switching loss is reduced, the total generation loss is reduced, and a high element breakdown voltage is obtained. Can be provided.

FIG. 1 is a longitudinal sectional view of a trench type insulated gate semiconductor device according to the present invention, cut in a direction perpendicular to a silicon wafer surface in a direction crossing a trench gate having a stripe-like planar pattern.
On the surfaces of the n-type drift layer 2 and the n-type drift layer 2 which are the second conductivity type layers having a low impurity concentration formed on one surface of the p-type silicon substrate which is the collector layer 1 of the first conductivity type. The p base layers 3 and 4, which are disposed and are first conductivity type layers having a higher impurity concentration than the n type drift layer 2, are second conductivity type layers selectively formed on the surface of the p base layer 3. An n + source region 5 is a first trench having a shape reaching the n-type drift layer 2 through the p base layer 3 from the surface of the n + source region 4, and 6 is an insulating film coated on the inner surface of the first trench 5. A gate oxide film, 7 is a gate electrode as a control electrode filled in the trench through the gate oxide film 5, 8 is an interlayer insulating film, 9 is straddling the surfaces of the p base layer 3 and the n + source region 4. The coated emitter electrode, 10 is a collection of silicon substrates. A collector electrode which is coated on the surface of the layer 1. Further, 11 is an oxide film which is an insulating film disposed inside the second trench 13 having a depth reaching the n-type drift layer 2 through the p base layer 3 not connected to the emitter electrode 9, and 12 is an oxide film. A conductor formed of the same material as the gate electrode 7 filled in the second trench 13 through the film 11. Further, in the first trench, when the interval between the trench a and the trench b is the first interval and the interval between the trench b and the trench c is the second interval (b-c), the surface of the p base layer with the first interval The n + source layer 4 is formed, and the second trench 13 is formed in the p base layer 3 having the second interval (b-c). In the following description, the same reference numerals represent the same configuration.

  An embodiment of a method of manufacturing a trench type insulated gate semiconductor device according to the present invention will be described. A step of forming a wafer in which a low-concentration epitaxial layer to be an n-type drift layer 2 is laminated on a high-concentration p-type silicon substrate 1 and a low concentration to form a base layer 3 from the surface on the drift layer 2 side of the wafer. A step of forming a p-type diffusion layer by ion implantation and thermal diffusion over the entire surface and simultaneously oxidizing the wafer surface; selectively etching the trench window by patterning the oxide film with a resist; and A step of forming first and second trenches 5 and 13 reaching the n-type drift layer 2 through the p base layer 3 from the surface of the silicon substrate using the oxide film as a mask, and inner surfaces of these trenches 5 and 13 by thermal oxidation Forming a gate oxide film on the silicon substrate, and depositing polysilicon on the surface of the silicon substrate including the first and second trenches 5 and 13, and then etching back. The step of removing polysilicon on the inside of the trenches 5 and 13 and the surface other than the interconnection of the second trench 13 and the n + source layer 4 which is shallower than the p base layer 3 and has a high concentration are arranged at the first interval (a A step (b) between the P base layer 3 and the oxide film such as PSG to be the interlayer insulating film 8 is formed by CVD, and is selectively etched by patterning with a resist. A step of depositing aluminum to be the emitter electrode 9 thereon by vapor deposition or the like, and patterning and etching with a resist so as to form a necessary electrical wiring, and a nitride film to be a passivation film if necessary Or an amorphous Si film formed by CVD, etc., patterned and etched with resist, and on the opposite surface of the p-type silicon substrate By sequentially executing the steps of forming a gold or silver as a collector electrode 10 deposited by such, the trench-type insulated gate semiconductor device according to the present invention is manufactured.

FIG. 3 shows the breakdown voltage waveforms (a) and (b) between the emitter and the collector of the trench type insulated gate semiconductor device of the 1200 V breakdown voltage class for the prior art and the present invention. From this result, with respect to 1345V which is the withstand voltage value of the conventional structure, except that the second trench structure is provided in the floating mesa region made of the p base layer at the second interval (b-c) of the first trench. The device breakdown voltage of the present invention produced with the same structure is 1608 V, an improvement of about 20%. On the other hand, there is no significant change in other element characteristics such as on-voltage and switching characteristics.
It was initially considered that the same breakdown voltage improvement effect could be obtained by conductively connecting the conductor inside the second trench structure to the emitter electrode. However, in this method, it has been found that the switching speed slows down as the gate-emitter capacitance increases. Therefore, it was found that a trench type insulated gate semiconductor device capable of obtaining a high breakdown voltage while maintaining a fast switching characteristic was obtained when a structure in which the conductor inside the second trench structure was not connected to the emitter electrode. Invented.

  Furthermore, it was also found that when the plurality of second trenches are not conductively connected to each other, such an effect of improving the breakdown voltage cannot be obtained. As a result of device simulation, by connecting the second trenches to each other, it is possible to flatten the equipotential lines extending to the drift layer under the second trenches by applying a forward voltage when turning off. It turned out to be important. The principle by which these effects can be obtained is shown by the equipotential lines (dotted lines) by forward voltage application in the OFF state shown in FIGS. 4 and 5 showing the sectional views of the respective trench type insulated gate bipolar transistors of the conventional and the present invention. explain. In the trench type insulated gate bipolar transistor having the conventional structure shown in FIG. 4, in the p base layer (p base layer 3 not connected to the emitter) at the second interval (b-c) of the first trench, Since the equipotential line that spreads by voltage application spreads so as to bend into the p base layer 3, the dotted line indicates that the radius of curvature near the symbol A is smaller than the others. For this reason, the electric field strength tends to increase due to the electric field concentration in the area of the symbol A. Since the element breakdown voltage is determined by the applied voltage when this part reaches the critical electric field strength at which the avalanche breakdown of silicon occurs, the element breakdown voltage decreases.

  On the other hand, in the present invention, as shown by the dotted line in FIG. 5, by obtaining a substantially flat equipotential line, the electric field strength at the point A is greatly weakened and the electric field concentration is relaxed. It can be realized. The reason why the electric field concentration is reduced at the point A as described above by the present invention is that the second trenches 12 are conductively connected to each other as shown in FIG. The equipotential lines that have been bent so as to be curved inside the layer 3 are pushed downward to the second interval (b-c) of the first trench to form a constant equipotential line, and the first interval of the first trench ( This is considered to be because the equipotential lines located in the lower part of (between a and b) acted so as to make the spreading method almost common and flat. Further, the effect of increasing the withstand voltage can be obtained by making the volume of the second trench larger than that of the first trench. Further, as in the equipotential lines shown in FIG. 5, the equipotential lines spread below the first interval (between bc) of the first trench with respect to the lower portion of the first interval (between a and b) of the first trench. If there is still a small level difference, the second trench can be made deeper than that shown in FIG. Preferred for.

The effect of obtaining a high device breakdown voltage by realizing the substantially flat equipotential surface as described above can be similarly obtained by the second trench structure shown in FIG.
In FIG. 6, 1 is a p-type collector layer, 2 is an n-type drift layer, 3 is a p base layer disposed on the surface of the n-type drift layer 2, and 4 is a first interval (a N + source region 5 selectively formed on the surface of the p base layer 3 (between -b) is formed so as to penetrate the p base layer 3 from the surface of the n + source region 4 and reach the n type drift layer 2. One trench, 6 is a gate oxide film which is an insulating film disposed inside the first trench 5, and 7 is a control disposed in the trench facing the p base layer 3 through the gate oxide film 5. The gate electrode is an electrode, 8 is an interlayer insulating film, 9 is an emitter electrode conductively connected to the surfaces of the p base layer 3 and the n + source region 4, and 10 is a collector electrode formed on the surface of the collector layer 1 of the silicon substrate. . Further, 13 is a second trench having a depth reaching the n-type drift layer 2 through the p base layer 3 from the surface of the p base layer 3 at the second interval (b-c) of the first trench 5. In addition, a conductor 12 (shaded portion in FIG. 6) filled directly without an insulating film is provided inside, and is electrically connected to the second trench 13 but is not connected to the emitter electrode 9, etc. This is a common flattening means for potential lines. In the following embodiments, the same reference numerals mean the same configuration.

The feature of this structure is that the manufacturing process is complicated as compared with the structure described above, but the potential of the second trench portion is kept more uniform by being directly conductively connected without passing through the insulating film. Therefore, a higher breakdown voltage can be obtained.
The trench insulated gate semiconductor device according to the present invention can be basically manufactured by the same method as in the first embodiment. That is, by selectively removing only the second trench portion from the gate oxide film inside the trench, a trench type insulated gate semiconductor device can be manufactured.

Further, as shown in FIG. 7, the conductive thin layer 15 is covered with a thin insulating film 14 on the upper portion of the p base layer 3 at the second interval (b-c) of the first trench not connected to the emitter electrode 9. Also, by electrically shielding, the device breakdown voltage can be improved by flattening the equipotential line when the forward voltage is applied in the off state. In the case of the above-described first and second embodiments, since the second trench is provided in the p base layer 3 at the second interval (b-c) of the first trench, the equipotential line is extended to the lower portion of the second trench. In the third embodiment, since there is no second trench, only the effect of planarization on the surface of the p base layer 3 at the second interval (b-c) of the first trench is obtained. However, the effect of improving the breakdown voltage is inferior to that of Examples 1 and 2. However, since there is no need to form a trench structure, there is an advantage that the manufacturing process becomes very easy.
FIG. 8 shows the relationship between the thickness of the insulating film 13 and the element breakdown voltage in the above case. When the insulating film is 1000 nm, a difference in device breakdown voltage from the conventional structure is not recognized and the effect is not obtained. However, the insulating film becomes thinner, and the device breakdown voltage is improved, for example, about 30 V at 500 nm and about 100 V at 50 nm. The thickness of the insulating film is desirably 500 nm or less as a range where an improvement of 3% or more of the element breakdown voltage can be expected.

  Moreover, as a manufacturing method of the trench type insulated gate semiconductor device according to the invention of the third embodiment, it can be basically manufactured by the same method as the first embodiment. That is, an oxide film pattern is formed on the p base layer 3 at the second interval (b-c) of the first trench, and the polysilicon is selectively etched to form an oxide film on the p base layer 3. It can be manufactured in the same manner as in Example 1 except that a polysilicon layer is formed as a conductive thin layer through the step.

1 is a cross-sectional view of a trench type insulated gate semiconductor device described in Example 1 according to the present invention, cut in a direction perpendicular to a silicon substrate and across a trench gate. It is sectional drawing cut | disconnected in the direction perpendicular | vertical to a silicon substrate and crossing a trench gate about the conventional trench type insulated gate semiconductor device. It is a figure which shows the comparison of the element breakdown voltage in each trench type insulated gate semiconductor device of this invention and the conventional. It is sectional drawing which shows the equipotential line at the time of the forward voltage application at the time of OFF about the conventional trench type insulated gate semiconductor device with a dotted line. BRIEF DESCRIPTION OF THE DRAWINGS It is sectional drawing which shows the equipotential line at the time of the forward voltage application at the time of OFF about the trench type insulated gate semiconductor device concerning Example 1 of this invention with a dotted line. It is sectional drawing cut | disconnected in the direction perpendicular | vertical to a silicon substrate and crossing a trench gate about the trench type insulated gate semiconductor device concerning Example 2 of this invention. It is sectional drawing cut | disconnected in the direction perpendicular | vertical to a silicon substrate and crossing a trench gate about the trench type insulated gate semiconductor device concerning Example 3 of this invention. It is a figure which shows the relationship between the thickness of the oxide film of the surface of the p base layer between 2nd trenches, and element breakdown voltage about the trench type insulated gate semiconductor device concerning Example 3 of this invention.

Explanation of symbols

1 collector layer of the first conductivity type,
2 n-type drift layer,
3 p base layer,
4 n + source region,
5, a, b, c trench,
6 Gate oxide film,
7 Gate electrode,
8 Interlayer insulation film,
9 Emitter electrode,
10 collector electrode,
11 Second trench inner insulating film 12 Conductor in second trench 13 Oxide film,
14 p base layer between second trenches, floating mesa region,
15 Conductor.

Claims (5)

A drift layer of a first conductivity type, a base layer of a second conductivity type formed in one surface of the drift layer, and a depth formed from the surface of the base layer and reaching the drift layer inside. In a trench type insulated gate semiconductor device comprising a plurality of first trenches having a gate electrode embedded via a gate oxide film, the plurality of first trenches are wider than the first interval and the first interval sandwiching the base layer And a base layer of the first interval includes a source region of a first conductivity type that is selectively formed from the surface of the base layer to the inner wall surface of the first trench, and an emitter electrode and the base layer The base layer in contact with both surfaces of the source region in common and the second interval is the first interval between the equipotential line of the depletion layer extending to the drift layer under the second interval when the forward voltage is applied in the off state. Lower Trench-type insulated gate semiconductor device characterized in that it comprises a common flattening means with the equipotential line of a depletion layer spreads in the shift layer. The common flattening means for equipotential lines is a second trench formed on the surface of the second conductivity type base layer with the second interval and filled with a conductor, and the total volume inside the second trench is the first trench. 2. The trench type insulated gate according to claim 1, wherein the conductor formed inside the second trench is larger than the total internal volume and is not conductively connected to any of the emitter, collector and gate electrode. Semiconductor device. 3. The trench type insulated gate semiconductor device according to claim 2, wherein a gate oxide film is interposed between the conductor filled in the second trench and the inner wall surface of the second trench. 4. The trench type insulated gate semiconductor device according to claim 2, wherein the depth of the second trench is equal to or deeper than the depth of the first trench. 2. The trench type insulated gate semiconductor device according to claim 1, wherein a conductor is provided on the surface of the second conductivity type base layer at the second interval via an insulating film of 500 nm or less.

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