JP2010050211A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device for appropriately performing a screening inspection step for a gate insulating film of a dummy gate electrode. <P>SOLUTION: A first float wiring 12 has a double layer structure. At a lower layer part 12a, a portion which is electrically connected to a doped Poly-Si10b connected to a dummy gate electrode 8b is separated by a predetermined distance from a portion that is electrically connected to a first float layer 3b. Prior to formation of an upper layer part 12b, a screening inspection step is performed. By this arrangement, whether a gate insulating film 7 of the dummy gate electrode 8b is provided with a desired breakdown voltage is properly determined. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a semiconductor device having a trench gate structure such as an insulated gate transistor (hereinafter referred to as IGBT) having a trench gate structure.

  2. Description of the Related Art Conventionally, as a high breakdown voltage insulated gate semiconductor element such as an IGBT having a trench gate structure, for example, a semiconductor device having an IGBT shown in Patent Document 1 is generally known.

In the IGBT shown here, an n ⁺ -type emitter region to be contacted with the emitter electrode is selectively formed in the p-type base region, and a dummy trench is formed in a portion without the n ⁺ -type emitter region. Thus, the structure has a trench gate structure with a uniform distribution. That is, the n ⁺ -type emitter region is not formed over the entire p-type base region, but is formed by thinning, and the dummy region is not a trench in which a gate electrode for applying a gate voltage is formed in the thinned region. A dummy trench provided with a dummy gate electrode is arranged.

In this way, by selectively forming the n ⁺ -type emitter region, the conductivity modulation of the high-resistance p-type base region can be promoted to further reduce the conduction loss. By forming the dummy trench, the breakdown voltage can be reduced. Can be improved.

In the IGBT having such a structure, in order to stabilize the potential of the dummy gate electrode, the dummy gate electrode is formed into a floating p-type base region (hereinafter referred to as a float layer) in which an n ⁺ -type emitter region is not formed. By adopting a structure connected to the gate electrode or the emitter electrode, the effect of improving the breakdown voltage can be exhibited. However, since connecting the dummy gate electrode to the gate electrode increases the gate capacitance and deteriorates the switching characteristics, it is preferable to connect the dummy gate electrode to the float layer or the emitter electrode.
JP 2006-49455 A

  When the gate oxide film of the dummy gate electrode is destroyed, a leak occurs through the destroyed gate oxide film. Therefore, a voltage is applied to the dummy trench electrode before product shipment, and a potential difference is generated between the p-type base region and a potential stress is applied to the gate oxide film, whereby the gate oxide film can obtain a desired breakdown voltage. It is necessary to conduct screening tests. However, if the dummy gate electrode is electrically connected to the float layer or the emitter electrode, an appropriate potential stress cannot be applied to the gate oxide film, and the screening test cannot be performed.

  An object of the present invention is to provide a method for manufacturing a semiconductor device in which a screening inspection process for a gate insulating film of a dummy gate electrode can be appropriately performed.

  In order to achieve the above object, according to the first aspect of the present invention, the dummy gate electrode (8b) is electrically connected to at least a part of the float layers (3b, 3c) and the dummy gate electrode (8b). It is characterized in that a screening test is performed by applying a voltage to.

  Thus, the screening inspection process is performed before electrically connecting at least a part of the float layers (3b, 3c) and the dummy gate electrode (8b). This makes it possible to appropriately determine whether or not the gate insulating film (7) of the dummy gate electrode (8b) can obtain a desired breakdown voltage.

  For example, as in the invention described in claim 2, the step of forming the float wiring (12), the emitter electrode (13) and the gate wiring (11) includes the step of forming the float wiring (12) in the lower layer portion (12a) and the upper layer portion. (12b) formed as a structure having two layers, a portion electrically connected to at least a part of the float layer (3b, 3c) in the lower layer portion (12a), a dummy gate electrode (8b), and an electric Forming a lower layer portion (12a) so that the portion to be electrically connected is electrically isolated, and after forming the lower layer portion (12a), a dummy gate in the lower layer portion (12a) A step of performing a screening test by applying a voltage to a portion electrically connected to the electrode (8b), and after performing the screening test, an upper layer part (12b) is formed on the lower layer part (12a). By doing so, the dummy gate electrode (8b) is electrically connected to at least a part of the float layer (3b, 3c) in the lower layer part (12a) via the upper layer part (12b). And a step of electrically connecting the connected parts to each other.

  In this way, the float wiring (12) has a structure including two layers of the lower layer portion (12a) and the upper layer portion (12b). In the lower layer portion (12a), a portion connected to the dummy gate electrode (8b) and a float layer ( 3b and 3c) are electrically separated from at least a portion electrically connected to the portion. Prior to the formation of the upper layer portion (12b), a screening inspection process is performed. This makes it possible to appropriately determine whether or not the gate insulating film (7) of the dummy gate electrode (8b) can obtain a desired breakdown voltage.

  The invention according to claim 3 is characterized in that a screening test is performed by applying a voltage to the dummy gate electrode (8b) before electrically connecting the emitter region (5) and the dummy gate electrode (8b). It is said.

  Thus, even when the dummy gate electrode (8b) is electrically connected to the emitter electrode (13), a screening test is performed before the emitter region (5) and the dummy gate electrode (8b) are electrically connected. By doing so, an effect similar to that of the first aspect can be obtained.

  For example, as in the invention described in claim 4, the step of forming the emitter electrode (13) and the gate wiring (11) includes the step of forming the emitter electrode (13) into two layers of a lower layer portion (13a) and an upper layer portion (13b). In the lower layer portion (13a), a portion electrically connected to the emitter region (5) and a portion electrically connected to the dummy gate electrode (8b) are electrically separated. Forming the lower layer portion (13a) so as to have the structure described above, and a portion of the lower layer portion (13a) that is electrically connected to the dummy gate electrode (8b) after the lower layer portion (13a) is formed. A step of performing a screening test by applying a voltage to the substrate, and after performing the screening test, an upper layer part (13b) is formed on the lower layer part (13a), thereby passing through the upper layer part (13b). Lower layer And 13a) a step of electrically connecting a portion electrically connected to the emitter region (5) and a portion electrically connected to the dummy gate electrode (8b). Can be adopted.

  Thus, even when the dummy gate electrode (8b) is electrically connected to the emitter electrode (13), the emitter electrode (13) has a structure having two layers of a lower layer portion (13a) and an upper layer portion (13b). The lower layer portion (13a) has a structure in which a portion connected to the dummy gate electrode (8b) and a portion electrically connected to the emitter region (5) are electrically separated. 1 can be obtained.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
A first embodiment of the present invention will be described. FIG. 1 is a top surface layout diagram of an IGBT according to the present embodiment. 2 is a cross-sectional view taken along line AA of the semiconductor device shown in FIG. 1, and FIG. 3 is a cross-sectional view taken along line BB of the semiconductor device shown in FIG. Although FIG. 1 is not a cross-sectional view, hatching is partially shown for easy understanding of the drawing. Further, in FIGS. 2 and 3, a portion indicated by a one-dot chain line corresponds to a bent portion on the AA line or the BB line in FIG. Hereinafter, the semiconductor device having the IGBT according to the present embodiment will be described with reference to these drawings.

As shown in FIG. 2, the IGBT is formed using a semiconductor substrate provided with a p ⁺ -type layer (semiconductor layer) 1 and an n ⁻ -type drift layer 2 having a main surface on one side.
For example, an n ⁻ type substrate constituting the n ⁻ type drift layer 2 is prepared, and after the n ⁻ type substrate is thinned, p type impurities are ion-implanted to form a p ⁺ type layer 1 to form a semiconductor substrate. can do. The step of thinning the n ⁻ -type substrate and the step of forming the p ⁺ -type layer 1 can be performed in the middle or at the end of the steps described below, as well as in this step. A semiconductor substrate can also be formed by preparing a p ⁺ type substrate constituting the p ⁺ type layer 1 and epitaxially growing the n ⁻ type drift layer 2 on the surface of the p ⁺ type substrate.

A p-type base region 3 having a predetermined thickness is formed in the surface layer portion of the n ⁻ -type drift layer 2. Further, a plurality of trenches 4 are formed so as to penetrate the p-type base region 3 and reach the n ⁻ -type drift layer 2, and the p-type base region 3 is separated into a plurality of trenches 4. Specifically, as shown in FIG. 1, a plurality of trenches 4 are formed at equal intervals, and after the trenches 4 are extended in parallel in the depth direction of FIG. As shown, an annular structure is formed by being routed at the tip. Each of the trenches 4 constitutes a multiple ring structure with a plurality of annular structures (two in this embodiment) as a set so that the longitudinal directions of adjacent multiple ring structures are parallel to each other. Is arranged. Hereinafter, among the plurality of trenches 4, the one disposed on the outermost periphery is referred to as the outermost periphery trench 4 a, and the inner one is referred to as the inner periphery trench 4 b.

The p-type base region 3 disposed between the outermost peripheral trenches 4a of adjacent multiple ring structures is a channel p layer 3a constituting a channel region, and an n ⁺ type is formed on the surface layer portion of the channel p layer 3a. An emitter region 5 is formed.

The n ⁺ -type emitter region 5 has a higher impurity concentration than the n ⁻ -type drift layer 2, terminates in the p-type base region 3, and is disposed so as to be in contact with the side surface of the outermost peripheral trench 4 a. Yes. More specifically, a structure is provided that extends in a rod shape along the longitudinal direction of the outermost peripheral trench 4a and terminates inside the front end of the outermost peripheral trench 4a. For this reason, among the plurality of trenches 4, the outermost peripheral trench 4 a disposed on both sides of the n ⁺ -type emitter region 5 is used for forming the gate electrode, and the other inner peripheral trench 4 b is used for the dummy trench. .

Adjacent n ⁺ -type emitter regions 5 are spaced apart from each other by a predetermined distance, and a p ⁺ -type body layer 6 having a higher concentration than the p-type base region 3 is formed therebetween. The p ⁺ type body layer 6 is also extended in a rod shape in the same direction as the n ⁺ type emitter region 5 and has a structure terminated on the inner side of the tip of the outermost peripheral trench 4a.

In each trench 4, gate electrodes 8 a, 8 b configured by a gate insulating film 7 formed so as to cover the inner wall surface of each trench 4 and doped Poly-Si formed on the surface of the gate insulating film 7. And embedded by. As shown in FIG. 2, of the gate electrodes 8a and 8b, the gate electrode 8a formed in the outermost periphery trench 4a arranged on both sides of the n ⁺ -type emitter region 5 is a gate to which a gate voltage is applied. A dummy gate electrode 8b electrically connected to a wiring (not shown) and formed in the inner peripheral trench 4b is a p-type base region sandwiched between the outermost peripheral trench 4a and the inner peripheral trench 4b inside thereof. 3 is electrically connected to the first float layer 3b. Electrical connection between the dummy gate electrode 8b and the first float layer 3b is made by the first float wiring 12.

  Further, the p-type base region 3 located in the inner peripheral trench 4b is a second float layer 3c, and is not connected to any part or a portion not shown in FIG. 2 (for example, omitted in FIG. 1). The trench 4 is connected to the second float wiring at the lower end portion of the trench 4 in the drawing.

Further, the n ⁺ -type emitter region 5 and the p ⁺ -type body layer 6 are electrically connected to the emitter electrode 13 and the gate electrode 8a is electrically connected to the gate wiring 14 (see FIG. 1). . The first float wiring 12, the second float wiring, the emitter electrode 13 and the gate wiring 14 have a two-layer structure. For example, as shown in FIG. 1, the first float wiring 12 and the emitter electrode 13 are composed of lower layer portions 12a and 13a and upper layer portions 12b and 13b, and the lower layer portions 12a and 13a are made of a metal such as Al, the upper layer portion 12b, 13b is constituted by metal plating such as Au.

  Here, the case where the dummy gate electrode 8b is electrically connected to the first float layer 3b as at least a part of the first and second float layers 3b and 3c will be described. However, the first and second float layers 3b are described. 3c, or connected to the second float layer 3c.

  And as shown in FIG. 3, the 1st float wiring 12 is electrically connected to the part electrically connected with doped Poly-Si10b connected with the dummy gate electrode 8b in the lower layer part 12a, and the 1st float layer 3b. The parts are separated from each other by a predetermined distance, and these parts are electrically connected through the upper layer part 12b disposed on the lower layer part 12a.

  As for the layout of the first float wiring 12, the second float wiring, the emitter electrode 13 and the gate wiring 14, as long as these parts are electrically connected as described above and the wirings are not short-circuited. In this embodiment, the structure shown in FIG. 1 is used.

  Specifically, as shown in FIG. 2, the surface of each float layer 3b, 3c is covered with an insulating film 9, and then doped Poly-Si 10a electrically connected to the gate electrode 8a as shown in FIG. Is extended over the outermost peripheral trench 4a, and the doped Poly-Si 10b electrically connected to the dummy gate electrode 8b is extended over the inner peripheral trench 4b and the second float layer 3c. Yes. The gate electrode 8a is electrically connected to the doped Poly-Si 10a, and the dummy gate electrode 8b is electrically connected to the doped Poly-Si 10b.

  Further, each part is insulated by the interlayer insulating film 11 as shown in FIG. 2, and a part of the doped Poly-Si 10b and the first float layer through the contact holes 11a and 11b formed in the interlayer insulating film 11 as shown in FIG. A part of 3b is exposed. Then, by arranging the lower layer portion 12a of the first float wiring 12 thereon, a part of the lower layer portion 12a is electrically connected to the doped Poly-Si 10b, and the remaining portion is connected to the first float layer 3b. The structure is electrically connected. Further, the upper layer portion 12b is disposed on the lower layer portion 12a, whereby the lower layer portion 12a is electrically connected through the upper layer portion 12b.

Similarly, a part of doped Poly-Si 10a is exposed through a contact hole 11c formed in the interlayer insulating film 11. The doped poly-Si 10a and the lower layer portion of the gate wiring 14 are electrically connected through the contact hole 11c, and the upper wiring layer is disposed on the lower layer portion, whereby the gate wiring 14 is configured. Further, the lower layer portion 13a is electrically connected to the n ⁺ type emitter region 5 and the p ⁺ type body layer 6 through the contact hole 11d formed in the interlayer insulating film 11, and the upper layer portion 13b is disposed on the lower layer portion 13a. Thus, the emitter electrode 13 is configured.

  A protective film 15 is provided on the surface of the lower layer portion 12a of the first float wiring 12, the lower layer portion 13a of the emitter electrode 13, the gate wiring 14 and the lower layer portion of the second float wiring. The upper layer portion 12b of the first float wiring 12, the upper layer portion 13b of the emitter electrode 13, the upper layer portion of the gate wiring 14 and the second float wiring are arranged. The protective film 15 insulates the first float wiring 12, the second float wiring, the emitter electrode 13, and the gate wiring 14.

  Specifically, as shown in FIG. 1, the protective film 15 is arranged in stripes so as to be parallel to the longitudinal direction and the vertical direction of each trench 4. Since the upper layer portion 12b of the first float wiring 12, the upper layer portion 13b of the emitter electrode 13, the gate wiring 14 and the upper layer portion of the second float wiring are disposed in the portion where the protective film 15 is not disposed. The first float wiring 12, the second float wiring, the emitter electrode 13, and the gate wiring 14 are also arranged so as to be parallel to the longitudinal direction and the vertical direction of each trench 4. The emitter electrode 13 is arranged so as to cover the inside of the cell with a large area, and the first float wiring 12 and the gate wiring 14 are arranged in a straight line parallel to each other at the tip position of the trench 4.

A collector electrode 16 is formed in contact with the p ⁺ type layer 1. In this manner, a semiconductor device including the IGBT according to the present embodiment is configured.

  The electrical connection between the second float wiring and the second float layer 3c and the electrical connection between the gate electrode 8a and the gate wiring 14 are not shown in FIG. 11 is electrically connected through a contact hole formed in 11.

  In the semiconductor device according to the present embodiment described above, the gate electrode 8a is electrically connected to the gate wiring 14 to which the gate voltage is applied, and the dummy gate electrode 8b is electrically connected to the first float layer 3b. The second float layer 3 c is electrically connected to the second float wiring while being connected to the first float wiring 12. As described above, the dummy gate electrode 8b is electrically connected to the first float layer 3b and is not electrically connected to the gate wiring 14, so that the switching surge and the switching loss are improved while exhibiting the effect of improving the breakdown voltage. A balanced structure can be obtained.

  Next, a manufacturing method of the semiconductor device according to the present embodiment will be described, and a screening inspection process performed during the manufacturing process will be described. 4 and 5 are diagrams showing the manufacturing process of the semiconductor device according to the present embodiment, in which the left figure shows the top layout, the right figure shows the cross-sectional layout, and corresponds to FIG. It is sectional drawing (on the AA line of FIG. 1).

[Steps shown in FIGS. 4A and 4A]
First, a semiconductor substrate including a p ⁺ type layer 1 and an n ⁻ type drift layer 2 is prepared, and a collector electrode 16 is formed so as to be in contact with the p ⁺ type layer 1. For example, an n ⁻ type substrate constituting the n ⁻ type drift layer 2 is prepared, and after the n ⁻ type substrate is thinned, p type impurities are ion-implanted to form a p ⁺ type layer 1 to form a semiconductor substrate. can do. The step of thinning the n ⁻ -type substrate and the step of forming the p ⁺ -type layer 1 can be performed in the middle or at the end of the steps described below, as well as in this step. A semiconductor substrate can also be formed by preparing a p ⁺ type substrate constituting the p ⁺ type layer 1 and epitaxially growing the n ⁻ type drift layer 2 on the surface of the p ⁺ type substrate.

Further, the p-type base region 3 is formed by ion-implanting p-type impurities into the surface of the n ⁻ -type drift layer 2 or epitaxially growing the p-type layer. Then, after a mask (not shown) having an opening in which the trench 4 is to be formed is disposed on the p-type base region 3, etching is performed using the mask to penetrate the p-type base region 3. A plurality of trenches 4 are formed so as to reach the n ⁻ type drift layer 2. Thereafter, the mask is removed, and the gate insulating film 7 and the insulating film 9 are formed by thermal oxidation or the like.

[Steps shown in FIGS. 4B and 4B]
Next, after doping Poly-Si is formed on the surfaces of the gate insulating film 7 and the insulating film 9 so as to fill the trench 4, it is patterned. Thereby, the gate electrode 8a and the dummy gate electrode 8b are formed, and the Poly-Si 10b is left on the dummy gate electrode 8b. At this time, Poly-Si 10a is left on the gate electrode 8a as shown in the left figure.

[Steps shown in FIGS. 4C and 4C]
Subsequently, after arranging a mask (not shown) in which a region where the n ⁺ -type emitter region 5 is to be formed is opened, ion implantation of n-type impurities is performed using the mask. In addition, after removing the previously used mask, a mask (not shown) in which a region where the p ⁺ -type body layer 6 is to be formed is opened is arranged, and ion implantation of p-type impurities is performed using the mask. . Then, after removing the mask again, the impurity implanted by the heat treatment is activated to form the n ⁺ -type emitter region 5 and the p ⁺ -type body layer 6.

[Steps shown in FIGS. 5A and 5A]
After the interlayer insulating film 11 is formed on the entire surface of the substrate, a mask (not shown) having openings in the regions where the contact holes 11a to 11d are to be formed is disposed, and etching is performed using this mask, whereby the contact holes 11a To 11d.

[Steps shown in FIGS. 5B and 5B]
After depositing a metal such as Al on the entire surface of the substrate, patterning is performed to form the lower layer portion 12a of the first float wiring 12, the lower layer portion 13a of the emitter electrode 13, the gate wiring 14 and the lower layer portion of the second float wiring. The patterning at this time may be performed by dry etching, but it is preferable that the end surface of the portion removed by patterning by wet etching is tapered. With such a tapered shape, it is possible to facilitate plating growth when the upper layer portion is formed on the lower layer portion by plating.

  At this time, the first float wiring 12 includes a portion electrically connected to the doped Poly-Si 10b connected to the dummy gate electrode 8b in the lower layer portion 12a, and a portion electrically connected to the first float layer 3b. Becomes a structure separated by a predetermined interval.

[Steps shown in FIGS. 5C and 5C]
The protective film 15 is formed on the entire surface and then patterned to leave the protective film 15 only in necessary portions. Specifically, the protective film 15 is removed in the regions where the first float wiring 12 and the upper layer portions 12b and 13b of the emitter electrode 13 are to be formed and the regions where the gate wiring 14 and the second float wiring are to be formed. To do.

  Even in the state in which the protective film 15 is thus formed, the first float wiring 12 is electrically connected to the doped Poly-Si 10b connected to the dummy gate electrode 8b in the lower layer portion 12a as described above. A portion electrically connected to the first float layer 3b is separated from the first float layer 3b by a predetermined distance. For this reason, a screening inspection process is performed after patterning of the protective film 15.

  That is, a potential for screening is applied to a portion of the lower layer 12a that is electrically connected to the doped Poly-Si 10b connected to the dummy gate electrode 8b, and potential stress is applied to the gate insulating film 7 of the dummy gate electrode 8b. Add At this time, as described above, the first float wiring 12 is electrically connected to the portion of the lower layer portion 12a that is electrically connected to the doped Poly-Si 10b connected to the dummy gate electrode 8b and the first float layer 3b. Therefore, a potential stress can be applied to the gate insulating film 7 in a state where the dummy gate electrode 8b is not connected to the first float layer 3b or the like. This makes it possible to determine whether or not the gate insulating film 7 of the dummy gate electrode 8b can obtain a desired breakdown voltage.

  The screening inspection process may be performed after the above-described process shown in FIG. 5B and before the formation of the protective film 15, but in consideration of the influence of particles and the like, the protective film It is preferable to carry out after forming 15.

  Thereafter, although not shown, upper layer portions 12b and 13b are formed on the surface of the lower layer portion 12a of the first float wiring 12 and the lower layer portion 13a of the emitter electrode 13, and the surface of the lower layer portion of the gate wiring 14 and the second float wiring. Also, the upper layer portion is formed. For example, when Au or the like is plated, a portion where the protective film 15 is not formed can be plated to form each upper layer portion. Thereby, the semiconductor device as shown in FIG. 2 is completed.

  In addition, when forming an upper layer part by plating, it is preferable to perform the patterning of the lower layer part mentioned above as follows. That is, by patterning, the first float wiring 12 includes a portion electrically connected to the doped Poly-Si 10b connected to the dummy gate electrode 8b in the lower layer portion 12a, and a portion electrically connected to the first float layer 3b. However, if the interval between the separated parts is set to ½ or less of the thickness of the upper layer part, the plating formed on the separated parts can be easily connected. Here, the interval between the separated parts corresponds to the mask width when etching is performed, and in the case of wet etching, is the width of the lower end part.

  As described above, according to the manufacturing method of the semiconductor device according to the present embodiment, the first float wiring 12 has a two-layer structure, and the lower layer portion 12a is electrically connected to the doped Poly-Si 10b connected to the dummy gate electrode 8b. The part that is electrically connected to the first float layer 3b is separated from the first float layer 3b by a predetermined distance. Then, prior to the formation of the upper layer portion 12b, a screening inspection process is performed. This makes it possible to appropriately determine whether or not the gate insulating film 7 of the dummy gate electrode 8b can obtain a desired breakdown voltage.

(Second Embodiment)
A second embodiment of the present invention will be described. In the semiconductor device of this embodiment, the dummy gate electrode 8b is not electrically connected to the first float layer 3b as in the first embodiment, but is electrically connected to the emitter electrode 13. However, other aspects are the same as those in the first embodiment, and therefore only the parts different from the first embodiment will be described.

  FIG. 6 is a top surface layout diagram of the IGBT according to the present embodiment. 7 is a cross-sectional view taken along the line CC of the semiconductor device shown in FIG. 6, and FIG. 8 is a cross-sectional view taken along the line DD of the semiconductor device shown in FIG. Although FIG. 6 is not a cross-sectional view, hatching is partially shown for easy understanding of the drawing. Further, in FIGS. 7 and 8, a portion indicated by a one-dot chain line corresponds to a bent portion on the CC line or the DD line in FIG. Hereinafter, the semiconductor device having the IGBT according to the present embodiment will be described with reference to these drawings.

  As shown in FIG. 7, in the present embodiment, the dummy gate electrode 8 b is not connected to the first float layer 3 b by covering the first float layer 3 b with the interlayer insulating film 11. Then, as shown in FIG. 8, a part of the lower layer portion 13a of the emitter electrode 13 and the doped Poly-Si 10b connected to the dummy gate electrode 8b are electrically connected through a contact hole 11a formed in the interlayer insulating film 11. Thus, the dummy gate electrode 8b is electrically connected to the emitter electrode 13.

In addition, as shown in FIG. 8, the emitter electrode 13 includes a lower layer portion 13a electrically connected to doped Poly-Si 10b connected to the dummy gate electrode 8b, an n ⁺ type emitter region 5 and a p ⁺ type body layer. 6 is a structure in which a portion electrically connected to 6 is spaced apart by a predetermined interval, and each part is electrically connected through an upper layer portion 13b disposed on the lower layer portion 13a.

  Thus, even if the dummy gate electrode 8b is electrically connected to the emitter electrode 13, it is possible to achieve a structure in which switching surge and switching loss are balanced while exhibiting the effect of improving the breakdown voltage.

Even in such a structure, after the lower layer portion 13a is formed and before the upper layer portion 13b is formed, a portion electrically connected to the doped Poly-Si 10b connected to the dummy gate electrode 8b Since the n ⁺ -type emitter region 5 and the portion electrically connected to the p ⁺ -type body layer 6 are separated from each other by a predetermined distance, a screening inspection process can be performed. That is, a potential for screening is applied to a portion of the lower layer portion 13a that is electrically connected to the doped Poly-Si 10b connected to the dummy gate electrode 8b, and potential stress is applied to the gate insulating film 7 of the dummy gate electrode 8b. Add As a result, as in the first embodiment, it is possible to determine whether or not the gate insulating film 7 of the dummy gate electrode 8b can obtain a desired breakdown voltage.

  In the structure of this embodiment, the formation positions of the contact holes 11a to 11d formed in the interlayer insulating film 11 are changed, and the lower layer portion 12a of the first float wiring 12, the lower layer portion 13a of the emitter electrode 13, and the gate wiring 14 are changed. The pattern of the lower layer of the first float wiring 12, the upper layer 12b of the first float wiring 12, the upper layer 13b of the emitter electrode 13, the pattern of the upper layer of the gate wiring 14 and the second float wiring, and the pattern of the protective film 15 Need only be changed with respect to the first embodiment.

(Other embodiments)
In the first embodiment, the case where the upper layer portion 12b of the first float wiring 12, the upper layer portion 13b of the emitter electrode 13, the gate wiring 14 and the upper layer portion of the second float wiring are formed by plating has been described. It may be.

  For example, the materials of the upper layer part and the protective film 15 are selected so that the metal constituting the upper layer part is easily peeled off from the protective film 15, and after the metal constituting the upper layer part is formed, The upper layer part can also be patterned by peeling off the part formed in the adhesive sheet (see, for example, JP 2001-35854 A).

  Further, after arranging a metal mask or the like that opens only a portion where the upper layer portion is desired, a metal for forming the upper layer portion may be deposited. Moreover, you may make it apply | coat the metal for forming an upper layer part only to the part which wants to arrange | position an upper layer part by an inkjet system. Furthermore, the upper layer portion may be composed of solder, solder paste or the like or a bonding wire. In the case where solder paste or the like is used, it may be structured to be connected to the lower layer portion by reflow after being disposed.

  In addition, the upper layer portion has a structure in which a metal block such as a copper block or a lead frame is joined via solder or the like, so that the lower layer portion 12a of the first embodiment or the lower layer portion of the second embodiment separated by a predetermined distance. 13a may be electrically connected. In this case, even if the solder or the like is disposed in each separated part of the lower layer part 12a of the first embodiment or the lower layer part 13a of the second embodiment, that is, the solder or the like is not connected, It only needs to be electrically connected via a metal block or a lead frame.

In each of the above embodiments, the case where the first conductivity type is n-type and the second conductivity type is p-type, that is, the case where the IGBT is an n-channel type is described as an example. May be of the p-channel type and the second conductivity type may be the n-type. In each of the above embodiments, the IGBT is described as an example of the semiconductor device having a trench gate structure. However, the same effects can be obtained by adopting the same manufacturing method for the MOSFET. In the case of a MOSFET, the p ⁺ type layer 1 is an n ⁺ type layer.

Also, a charge storage type trench gate bipolar transistor (CSTBT (registered trademark)) in which an n type charge storage layer is formed between the n ⁻ type drift layer 2 and the p type base region 3. The present invention can also be applied to.

It is a top surface layout diagram of IGBT concerning a 1st embodiment of the present invention. It is AA sectional drawing of the semiconductor device shown in FIG. FIG. 2 is a cross-sectional view of the semiconductor device shown in FIG. It is a figure which shows the manufacturing process of the semiconductor device shown in FIGS. FIG. 5 is a diagram showing a manufacturing step of the semiconductor device following that of FIG. 4; It is a top surface layout figure of IGBT concerning a 2nd embodiment of the present invention. It is CC sectional drawing of the semiconductor device shown in FIG. It is DD sectional drawing of the semiconductor device shown in FIG.

Explanation of symbols

1 p ⁺ type substrate 2 n ⁻ type drift layer 3 p type base region 3a channel p layer 3b first float layer 3c second float layer 4 trench 4a outermost periphery trench 4b inner periphery trench 5 n ⁺ type emitter region 6 p ⁺ type Body layer 7 Gate insulating film 8a Gate electrode 8b Dummy gate electrode 9 Insulating film 11 Interlayer insulating film 12 First float wiring 12a Lower layer 12b Upper layer 13 Emitter electrode 13 Float wiring 13a Lower layer 13b Upper layer 14 Gate wiring 15 Protective film 16 Collector electrode

Claims (4)

A semiconductor substrate having a semiconductor layer (1) of a first conductivity type or a second conductivity type and a drift layer (2) of a second conductivity type disposed on one surface side of the semiconductor layer (1);
A first conductivity type base region (3) formed on the drift layer (2);
A trench (4) that penetrates the base region (3) and reaches the drift layer (2) to separate the base region (3) into a plurality of parts;
A second conductivity type emitter region (5) selectively formed so as to be in contact with the side surface of the trench (4) in a part of the base region (3) separated into a plurality;
A gate electrode (8a) disposed through a gate insulating film (7) in a trench (4a) in contact with the emitter region (5) of the trench (4);
A dummy gate electrode (8b) disposed through a gate insulating film (7) in a trench (4b) not in contact with the emitter region (5);
Of the base region (3), the one provided with the emitter region (5) is the channel layer (3a), the one not provided with the emitter region is the float layer (3b, 3c), and the dummy gate electrode ( 8b) and a float wiring (12) electrically connecting at least a part of the float layer (3b, 3c);
An emitter electrode (13) electrically connected to the emitter region (5);
A gate wiring (14) electrically connected to the gate electrode (8a);
In a method for manufacturing a semiconductor device, comprising a collector electrode (16) electrically connected to the semiconductor layer (1) in the semiconductor substrate,
A screening test is performed by applying a voltage to the dummy gate electrode (8b) before electrically connecting at least a part of the float layers (3b, 3c) and the dummy gate electrode (8b). A method of manufacturing a semiconductor device. Preparing a semiconductor substrate having a semiconductor layer (1) of the first conductivity type or the second conductivity type and a drift layer (2) of the second conductivity type disposed on one surface side of the semiconductor layer (1);
Forming a first conductivity type base region (3) on a surface layer portion of the drift layer (2) or on the drift layer (2);
Forming a trench (4) that penetrates the base region (3) and reaches the drift layer (2) to separate the base region (3) into a plurality of parts;
Forming a gate insulating film (7) in the trench (4);
Filling the trench (4) with doped Poly-Si on the gate insulating film (7) in the trench (4);
A second conductivity type emitter region (5) is selectively applied to a part of the base region (3) separated into a plurality of portions so as to contact a side surface of the trench (4) in the base region (3). Forming, and
Forming an interlayer insulating film (11) on the substrate surface including the emitter region (5) and the base region (3), and forming contact holes (11a to 11d) in the interlayer insulating film (11); When,
Of the trench (4), the doped poly-Si disposed in the trench (4a) in contact with the emitter region (5) is used as the gate electrode (8a), and the trench (not in contact with the emitter region (5) ( 4b) the doped poly-Si disposed as a dummy gate electrode (8b), and the base region (3) provided with the emitter region (5) is a channel layer (3a), A layer without the emitter region (5) is defined as a float layer (3b, 3c), and at least one of the dummy gate electrode (8b) and the float layer (3b, 3c) through the contact holes (11a to 11d). Float wiring (12) for electrically connecting the part, emitter electrode (13) electrically connected to the emitter region (5), and the Forming over gate electrode (8a) and electrically connected to the gate lines (14),
Forming a collector electrode (16) in contact with the semiconductor layer (1),
Forming the float wiring (12), the emitter electrode (13) and the gate wiring (14),
The float wiring (12) is formed as a structure having two layers of a lower layer portion (12a) and an upper layer portion (12b), and at least a part of the float layers (3b, 3c) in the lower layer portion (12a) Forming the lower layer portion (12a) so that the electrically connected portion and the electrically connected portion with the dummy gate electrode (8b) are electrically separated;
After forming the lower layer portion (12a), performing a screening test by applying a voltage to a portion of the lower layer portion (12a) electrically connected to the dummy gate electrode (8b);
After the screening test, the upper layer portion (12b) is formed on the lower layer portion (12a), whereby the float layer (3b) in the lower layer portion (12a) is formed via the upper layer portion (12b). 3c), and a step of electrically connecting a portion electrically connected to at least a part and a portion electrically connected to the dummy gate electrode (8b). A method for manufacturing a semiconductor device, comprising: A semiconductor substrate having a semiconductor layer (1) of a first conductivity type or a second conductivity type and a drift layer (2) of a second conductivity type disposed on one surface side of the semiconductor layer (1);
A first conductivity type base region (3) formed on the drift layer (2);
A trench (4) that penetrates the base region (3) and reaches the drift layer (2) to separate the base region (3) into a plurality of parts;
A second conductivity type emitter region (5) selectively formed so as to be in contact with the side surface of the trench (4) in a part of the base region (3) separated into a plurality;
A gate electrode (8a) disposed through a gate insulating film (7) in a trench (4a) in contact with the emitter region (5) of the trench (4);
A dummy gate electrode (8b) disposed through a gate insulating film (7) in a trench (4b) not in contact with the emitter region (5);
Of the base region (3), the one provided with the emitter region (5) is defined as a channel layer (3a), and the one not provided with the emitter region is defined as a float layer (3b, 3c). And an emitter electrode (13) electrically connected to the dummy gate electrode (8b),
A gate wiring (14) electrically connected to the gate electrode (8a);
In a method for manufacturing a semiconductor device, comprising a collector electrode (16) electrically connected to the semiconductor layer (1) in the semiconductor substrate,
A semiconductor device is manufactured by performing a screening test by applying a voltage to the dummy gate electrode (8b) before electrically connecting the emitter region (5) and the dummy gate electrode (8b). Method. Preparing a semiconductor substrate having a semiconductor layer (1) of the first conductivity type or the second conductivity type and a drift layer (2) of the second conductivity type disposed on one surface side of the semiconductor layer (1);
Forming a first conductivity type base region (3) on a surface layer portion of the drift layer (2) or on the drift layer (2);
Forming a trench (4) that penetrates the base region (3) and reaches the drift layer (2) to separate the base region (3) into a plurality of parts;
Forming a gate insulating film (7) in the trench (4);
Filling the trench (4) with doped Poly-Si on the gate insulating film (7) in the trench (4);
A second conductivity type emitter region (5) is selectively applied to a part of the base region (3) separated into a plurality of portions so as to contact a side surface of the trench (4) in the base region (3). Forming, and
Forming an interlayer insulating film (11) on the substrate surface including the emitter region (5) and the base region (3), and forming contact holes (11a to 11d) in the interlayer insulating film (11); When,
Of the trench (4), the doped poly-Si disposed in the trench (4a) in contact with the emitter region (5) is used as the gate electrode (8a), and the trench (not in contact with the emitter region (5) ( 4b) the doped poly-Si disposed as a dummy gate electrode (8b), and the base region (3) provided with the emitter region (5) is a channel layer (3a), A layer without the emitter region (5) is used as a float layer (3b, 3c), and the emitter region (5) and the dummy gate electrode (8b) are electrically connected through the contact holes (11a, 11c, 11d). Forming an electrically connected emitter electrode (13) and a gate wiring (14) electrically connected to the gate electrode (8a);
Forming a collector electrode (16) in contact with the semiconductor layer (1),
The step of forming the emitter electrode (13) and the gate wiring (14) includes:
The emitter electrode (13) is formed as a structure having two layers of a lower layer portion (13a) and an upper layer portion (13b), and is electrically connected to the emitter region (5) in the lower layer portion (13a). Forming the lower layer portion (13a) so that the portion and the portion electrically connected to the dummy gate electrode (8b) are electrically separated;
After forming the lower layer portion (13a), performing a screening test by applying a voltage to a portion of the lower layer portion (13a) electrically connected to the dummy gate electrode (8b);
After the screening test, the upper layer portion (13b) is formed on the lower layer portion (13a), whereby the emitter region (5) in the lower layer portion (13a) is formed via the upper layer portion (13b). And a step of electrically connecting a portion electrically connected to the dummy gate electrode (8b) and a portion electrically connected to the dummy gate electrode (8b). Device manufacturing method.

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