JP7176978B2 - Semiconductor device and its manufacturing method - Google Patents

Description

The present invention relates to a semiconductor device and its manufacturing method, and is particularly applicable to a semiconductor device having an insulated gate bipolar transistor (IGBT).

Trench gate type IGBTs are widely used as IGBTs with low on-resistance. By alternately arranging an active cell region having a gate electrode connected to a gate potential electrode, an emitter region and a body region, and an inactive cell region including a p-type floating region, an IE (Injection Enhancement) effect is achieved. An available IE type IGBT has been developed. The IE effect increases the concentration of charges accumulated in the drift region by making it difficult for holes to be discharged from the emitter potential electrode side when the IGBT is in the ON state.

For example, Patent Document 1 discloses, as an IE type IGBT, a GG (gate-gate) structure in which two adjacent trench gates are connected to a gate potential, and a GG (gate-gate) structure in which two adjacent trench gates are each connected to an emitter potential. A GGEE (gate-gate-emitter-emitter) structure, in which an EE (emitter-emitter) structure coexists, and the like are disclosed. The GGEE structure forms a parasitic p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with a trench gate connected to the emitter potential. By discharging holes by this parasitic p-type MOSFET, it is possible to suppress the potential fluctuation of the floating region between the GG structure and the EE structure, so that the noise during the switching operation of the IE-type IGBT can be reduced.

The GG structure includes two trenches, a gate electrode connected to a gate potential buried in each trench through a gate insulating film, a body region provided between the two trenches, and a body region provided in the body region. and an emitter potential electrode connected to the body region and the emitter region. The EE structure includes two trenches, a gate electrode connected to an emitter potential buried in each trench through a gate insulating film, a body region provided between the two trenches, and a body region connected to the body region. an emitter potential electrode;

JP 2017-157733 A

The inventor of the present application is studying how to improve the reliability of an IE type IGBT having a GGEE structure. A gate insulating film having a GG structure can be screened for initial defective products by applying a reference potential (0 [V]) to the emitter potential electrode and applying a pulse voltage of, for example, ±40 to 60 [V] to the gate electrode. However, gate dielectric films in EE structures cannot be screened in a similar manner. This is because in the EE structure, the gate electrode and body region are connected to the emitter potential electrode.

Screening can be performed by transiently applying a high electric field to the gate insulating film of the EE structure using an L-load circuit. The IGBT may melt due to the heat generated from the test equipment, and the maintenance of the test equipment was difficult.

Therefore, there is a need for a technology that can screen the gate insulating film of the EE structure by a relatively simple test method, as in the case of the GG structure, and improve the reliability of the semiconductor device.

Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

Among the embodiments disclosed in the present application, a brief outline of representative ones is as follows.
It is as follows.

A semiconductor device according to one embodiment has an active cell region and a hole collector cell region. In the hole collector cell region, a gate electrode serves as a gate finger, a body region serves as an emitter potential electrode, and a floating region serves as a floating region. The gate fingers are connected to the emitter potential electrode by shunt wires formed over the gate fingers and the emitter fingers. By applying a positive voltage or a negative voltage to the gate electrode of the body region and the floating region before forming the shunt wiring, screening of the gate insulating film in the hole collector cell region is made possible.

According to one embodiment, reliability of a semiconductor device can be improved.

1 is a plan view of a semiconductor chip, which is the semiconductor device of Embodiment 1; FIG. 1 is a plan view of a semiconductor chip, which is the semiconductor device of Embodiment 1; FIG. 2 is a plan view of a main part of the semiconductor device of FIG. 1; FIG. 3 is a plan view of a main part of the semiconductor device of FIG. 2; FIG. FIG. 5 is a cross-sectional view taken along line AA of FIG. 4; FIG. 5 is a cross-sectional view taken along line BB of FIG. 4; 5 is a cross-sectional view taken along line CC of FIG. 4; FIG. FIG. 2 is a process flow diagram showing a method for manufacturing the semiconductor device of Embodiment 1; FIG. 4 is a plan view showing a manufacturing process of the semiconductor device of Embodiment 1; FIG. 9 is a process flow diagram showing a modification of FIG. 8; 2 is a plan view of a semiconductor device that is a modification of FIG. 1; FIG. 4 is a plan view of a semiconductor device that is a modification of FIG. 3; FIG. 6 is a plan view of a semiconductor device that is a modification of FIG. 5; FIG. FIG. 11 is a plan view of a main part of a semiconductor chip which is a semiconductor device according to a second embodiment; FIG. 15 is a cross-sectional view taken along line DD of FIG. 14; FIG. 15 is a fragmentary plan view of a semiconductor device that is a modification of FIG. 14; FIG. 16 is a fragmentary plan view of a semiconductor device that is a modification of FIG. 15;

For the sake of convenience, the following embodiments are divided into a plurality of sections or embodiments when necessary, but unless otherwise specified, they are not independent of each other, and one There is a relationship of part or all of the modification, details, supplementary explanation, etc. In addition, in the following embodiments, when referring to the number of elements (including the number, numerical value, amount, range, etc.), when it is particularly specified, when it is clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Furthermore, in the following embodiments, the constituent elements (including element steps, etc.) are not necessarily essential, unless otherwise specified or clearly considered essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., unless otherwise specified or in principle clearly considered otherwise, the shape is substantially the same. It shall include things that are similar or similar to, etc. This also applies to the above numerical values and ranges.

Hereinafter, embodiments will be described in detail based on the drawings. In addition, in all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted. Also, in the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary. In addition, in the drawings used in the embodiments, hatching may be omitted to make the drawings easier to see.

In the present specification, the fact that the conductivity type of the semiconductor is p-type means that only holes may be charge carriers, or both electrons and holes may be charge carriers. is higher than that of electrons, meaning that holes are the major charge carriers. In the present specification, the n-type conductivity of a semiconductor means that only electrons are charge carriers or both electrons and holes are charge carriers. is higher than the concentration of holes, meaning that electrons are the predominant charge carriers.

(Embodiment 1)
The semiconductor device of this embodiment will be described in detail below with reference to the drawings. The semiconductor device of the first embodiment is a semiconductor device including an IE-type IGBT having a GGEE structure.

<Structure of semiconductor device>
FIG. 1 is a plan view of a semiconductor chip CHP, which is a semiconductor device of this embodiment. Although FIG. 1 is a plan view, the gate potential electrode GE, the emitter potential electrode EE, the gate finger GF1, the emitter finger EF and the guard ring GR are hatched for easy viewing of the drawing. Note that FIG. 1 is a plan view of an intermediate structural body before forming a metal layer ML2 and a protective film PV, which will be described later.

As shown in FIG. 1, a large-area emitter potential electrode EE and a large-area gate potential electrode GE are arranged in the central portion of the semiconductor chip CHP, and a guard ring GR is formed around the periphery thereof. The semiconductor chip CHP is, for example, rectangular, and for the sake of convenience, the long side direction is called the X direction, and the short side direction is called the Y direction. In the Y direction, a gate potential electrode GE is arranged in the center of the semiconductor chip CHP, and the gate potential electrode GE has a plurality of (for example, five) electrodes extending in the X direction at predetermined intervals in the Y direction. Gate finger GF1 is connected.

An emitter potential electrode EE is arranged between adjacent gate fingers GF1, and an emitter finger EF extending in the X direction is connected to the emitter potential electrode EE. A gate finger GF2 extending in the X direction is arranged between the gate finger GF1 and the emitter finger EF, and a floating finger extending in the X direction is arranged between the emitter potential electrode EE and the emitter finger EF. FF is arranged. The width of emitter potential electrode EE in the Y direction is wider than the width of gate fingers GF1 and GF2, emitter finger EF and floating finger FF in Y direction.

For convenience, regions sandwiched between gate fingers GF1 adjacent in the Y direction are defined as blocks BK1 to BK4. Each block BK1-BK4 includes gate fingers GF1 and GF2, emitter fingers EF, floating fingers FF and an emitter potential electrode EE. In each block BK1-BK4, the emitter potential electrode EE and emitter finger EF are connected to each other, and between each block BK1-BK4, the emitter potential electrode EE and emitter finger EF are connected to each other. The gate potential electrode GE, gate fingers GF1 and GF2, emitter finger EF, floating finger FF, and emitter potential electrode EE are formed by patterning a metal layer ML1, which will be described later. Gate fingers GF1 and GF2 and floating finger FF are spaced apart from each other and electrically isolated from integrally formed emitter finger EF and emitter potential electrode EE.

Further, as shown in FIG. 1, a gate finger pad GFP is provided at the end of the gate finger GF2, and a floating finger pad FFP is provided at the end of the floating finger FF. In the Y direction, the width of the gate finger pad GFP is wider than the width of the gate finger GF2, and the width of the floating finger pad FFP is wider than the width of the floating finger FF.

Most of the semiconductor chip CHP is covered with an emitter potential electrode EE extending in the X direction, and semiconductor elements such as IGBTs are formed below the emitter potential electrode EE. The emitter potential electrodes EE of the blocks BK1 to BK4 have the same length in the X direction, and the emitter potential electrodes EE of the blocks GK2 and BK3 are separated from the gate potential electrode GE without overlapping the gate potential electrode GE. are placed. That is, in the Y direction, on both sides of the gate potential electrode GE, there is an empty space where no emitter potential electrode EE is provided. A finger pad FFP is arranged. Thus, by arranging the gate finger pads GFP and the floating finger pads FFP on the same side as the gate potential electrode GE with respect to the emitter potential electrode EE in the X direction, an increase in the area of the semiconductor chip CHP is suppressed. ing. The temperature sensitive diode Di and the sense IGBT are semiconductor elements for temperature detection and current detection of the IE type IGBT.

FIG. 2 is a plan view of a semiconductor chip CHP, which is the semiconductor device of the present embodiment, and shows a state in which a metal layer ML2 and a protective film PV are formed on the intermediate structure of FIG. To make the drawing easier to see, the metal layer ML2 is hatched. As shown in FIG. 2, a shunt line SL extending in the X direction is arranged to overlap the gate finger GF2 and the emitter finger EF, the shunt line SL is in contact with the gate finger GF2 and the emitter finger EF, Both are electrically connected. Since emitter finger EF is connected to emitter potential electrode EE, gate finger GF2 is connected to emitter potential electrode EE via shunt line SL and emitter finger EF.

An emitter pad EP is arranged on the emitter potential electrode EE, and a gate pad GP is arranged on the gate potential electrode GE. The emitter pad EP is in contact with the emitter potential electrode EE and electrically connected to the emitter potential electrode EE. Similarly, the gate pad GP is in contact with the gate potential electrode GE and is electrically connected to the gate potential electrode GE.

Shunt line SL, emitter pad EP and gate pad GP are formed of metal layer ML2 above metal layer ML1. The shunt wiring SL, the emitter pad EP and the gate pad GP are formed, for example, by electroless plating using the protective film PV having a desired pattern as a mask. A protective film PV is arranged in the region. External connection terminals such as bonding wires or clips (copper plates) are connected on the emitter pad EP and the gate pad GP to electrically connect the semiconductor chip CHP to another chip or a wiring board. can be done.

3 is a plan view of the P1 portion of FIG. 1, and FIG. 4 is a plan view of the P1 portion of FIG. 3 shows the intermediate structure before forming the metal layer ML2 and the protective film PV, and FIG. 4 shows the structure after forming the metal layer ML2 and the protective film PV. 3 and 4, the gate electrodes G1 and G2 are hatched. 5 is a cross-sectional view along line AA in FIG. 4, FIG. 6 is a cross-sectional view along line BB in FIG. 4, and FIG. 7 is a cross-sectional view along line CC in FIG.

As shown in FIG. 3, block BK2 includes cell region CR and peripheral region PER. Active cell areas AC and inactive cell areas IAC are alternately arranged in the X direction in the cell area CR. The inactive cell region IAC includes a hole collector cell region HCC and a floating region PF which is a p-type semiconductor region. The active cell area AC and the inactive cell area IAC are covered with an emitter potential electrode EE. Also, the cell region CR includes floating fingers FF electrically connected to the floating region PF. In the aforementioned IE-type IGBT having the GGEE structure, the active region AC corresponds to the GG structure, and the hole collector cell region HCC corresponds to the EE structure.

Peripheral region PER includes gate fingers GF1 and GF2 and emitter finger EF. Gate fingers GF1 and GF2 and emitter fingers EF extend in the X direction and are spaced apart in the Y direction. A well region PW, which is a p-type semiconductor region, is formed in the semiconductor substrate SB below the gate fingers GF1 and GF2 and the emitter finger EF. Well region PW is electrically connected to emitter finger EF. Peripheral region PER includes an n-type semiconductor region NF at the boundary with cell region CR. The n-type semiconductor region NF is a region for electrically separating the floating region PF of the cell region CR and the well region PW of the peripheral region PER.

A pair of gate electrodes G1 extending in the Y direction are arranged in the active cell region AC, and a pair of gate electrodes G2 extending in the Y direction are arranged in the hole collector cell region HCC. A pair of gate electrodes G1 continuously extend from the cell region CR to the peripheral region PER and are connected to the gate fingers FG1 in the peripheral region PER. A pair of gate electrodes G1 extends continuously over four blocks BK1 to BK4. A pair of gate electrodes G2 continuously extend from the cell region CR to the peripheral region PER and are connected to the gate fingers FG2 in the peripheral region PER. A pair of gate electrodes G2 extends continuously over the four blocks BK1 to BK4. As explained in FIG. 1, the gate finger FG1 is connected to the gate potential electrode GE. Also, as described with reference to FIGS. 1 and 2, the gate finger FG2 is connected to the emitter potential electrode EE. Therefore, the pair of gate electrodes G1 are connected to the gate potential electrode GE, and the pair of gate electrodes G2 are connected to the emitter potential electrode EE.

As shown in FIG. 4, in peripheral region PER, shunt line SL is arranged to partially overlap gate finger GF2 and emitter finger EF. The shunt wiring SL extends in the X direction and electrically connects the gate finger GF2 and the emitter finger EF. In the cell region CR, an emitter pad EP is arranged on the emitter potential electrode EE, and the emitter pad EP is electrically connected to the emitter potential electrode EE.

Moreover, in the cell region CR and the peripheral region PER, a protective film PV is arranged in a region where the shunt line SL and the emitter pad EP are not arranged.

As shown in FIG. 5, the semiconductor device of this embodiment has an active cell region AC and an inactive cell region IAC, and the inactive cell region IAC includes a hole collector cell region HCC and a floating region PF. Floating region PF including body region PB on its surface is in contact with hole collector cell region HCC and active cell region AC.

The semiconductor device is formed on a semiconductor substrate SB, and a drift region NV, which is a low-concentration n-type semiconductor region, is formed on the semiconductor substrate SB. On the back surface SBb side of the semiconductor substrate SB, there are a field stop region NS which is an n-type semiconductor region having an impurity concentration higher than that of the drift region NV, a collector region PC which is a p-type semiconductor region, and a collector potential electrode made of a metal film. CE is formed. During operation of the IGBT, a collector potential is applied to the collector region PC via the collector potential electrode CE.

The active cell area AC is an area that becomes a current path of the IE type IGBT. The active cell area AC includes two gate electrodes G1 connected to the gate potential electrode GE, a hole barrier area NHB, a body area PB and an emitter area NE. Two trenches T1 extend from main surface SBa of semiconductor substrate SB toward back surface SBb, and two trenches T1 are formed at a predetermined interval in the X direction. A gate electrode G1 is buried in the two trenches T1 via a gate insulating film GI. A hole barrier region NHB, which is an n-type semiconductor region having a concentration higher than that of the drift region NV, is formed in the semiconductor substrate SB in a region sandwiched between the two trenches T1. A body region PB that is a p-type semiconductor region is formed, and an emitter region NE that is an n-type semiconductor region is formed on the surface of the body region PB. Body region PB and emitter region NE are in contact with gate insulating film GI formed in two trenches T1. The hole barrier region NHB is provided mainly to improve the hole accumulation effect, thereby improving the IE effect.

Emitter region NE and body region PB are in contact with contact hole CH1 extending in the Y direction, and emitter potential electrode EE is embedded in contact hole CH1. A body contact region PR, which is a p-type semiconductor region having an impurity concentration higher than that of the body region PB, is formed in the semiconductor substrate SB under the contact hole CH1. Therefore, an emitter potential is applied to the emitter region NE, body region PB and body contact region PR during operation of the IGBT.

In the Y direction, the emitter regions NE are not formed over the entire surface of the body regions PB, but are arranged at regular intervals. That is, the plurality of emitter regions NE are formed so as to be separated from each other in the Y direction by the body regions PB.

The inactive cell region IAC is a region other than the active cell region AC. Most of the inactive cell region IAC is the floating region PF having the body region PB formed on its surface. A hole collector cell region HCC is formed in a part thereof. That is, a floating region PF is formed between the active cell region AC and the hole collector cell region HCC adjacent in the X direction.

In the hole collector cell region HCC, as shown in FIG.
The two trenches T2 are arranged adjacent to each other in the X-direction perpendicular to the Y-direction. Further, as shown in FIG. 5, the trench T2 is filled with the gate electrode G2 via the gate insulating film GI.

A p-type body region PB is formed on the surface of the semiconductor substrate SB in the region sandwiched between the two trenches T2. , the n-type emitter region NE is not formed.

The body region PB is in contact with a contact hole CH1 extending in the Y direction, and an emitter potential electrode EE is embedded in the contact hole CH1. A body contact region PR, which is a p-type semiconductor region having an impurity concentration higher than that of the body region PB, is formed in the semiconductor substrate SB under the contact hole CH1. Therefore, in the hole collector cell region HCC, an emitter potential is applied to the gate electrode G2, body region PB and body contact region PR during operation of the IGBT.

An emitter potential electrode EE is formed over the main surface SBa of the semiconductor substrate SB via an interlayer insulating film IL2, and the emitter potential electrode EE is embedded in a contact hole CH1 formed in the interlayer insulating film IL2. . The contact hole CH1 extends from the main surface SBa of the semiconductor substrate SB to the interior thereof, and in the active cell region AC, penetrates the emitter region NE to reach the interior of the body region SB, and the hole collector cell region HCC. , it reaches the inside of the body region SB.

In addition, in the semiconductor device of the present embodiment, an emitter pad EP is formed on the emitter potential electrode EE so as to be in contact with the emitter potential electrode EE.

Trench T1 and T2 have a depth of 2 to 5 μm, eg, 3 μm, from main surface SBa of semiconductor substrate SB. The gate electrodes G1 and G2 are, for example, polycrystalline silicon films into which n-type impurities are introduced, and the gate insulating film GI and the interlayer insulating film IL2 are, for example, silicon oxide films. The metal layer ML1 forming the emitter potential electrode EE and others is, for example, an aluminum film, but may be a laminated film of a barrier metal film made of, for example, a titanium nitride film and an aluminum film thereon. The metal layer ML2 forming the emitter pad EP and others is, for example, a laminated film of a nickel film and a gold film formed on the nickel film.

As shown in FIG. 6, the semiconductor substrate SB includes a drift region NV. In the peripheral region, a well region PW and a body region PB on the surface of the well region PW are formed in the drift region NV. In the cell region CR, a floating region PF and a body region PB on the surface of the floating region PF are formed in the drift region NV. An n-type semiconductor region NF is further formed in the drift region NV of the peripheral region PER, and the n-type semiconductor region NF is formed between the well region PW and the floating region PF. and the floating region PF. The impurity concentration of the n-type semiconductor region NF is higher than that of the drift region NV, and punch-through between the well region PW and the floating region PF is suppressed. That is, compared to the case where the n-type semiconductor region NF is not provided, the distance between the well region PW and the floating region PF can be narrowed, so that the size of the peripheral region PER can be reduced. Note that the n-type semiconductor region NF does not necessarily have to be provided, but if provided, it may be formed with an impurity concentration equal to that of the hole barrier region NHB in the step of forming the hole barrier region NHB in FIG.

Further, as shown in FIG. 6, over the main surface SBa of the semiconductor substrate SB, gate fingers GF1 and GF2, emitter fingers EF, and wirings formed of a metal layer ML1 are formed via interlayer insulating films IL1 and IL2. A floating finger FF and an emitter potential electrode EE are formed apart from each other. However, as described with reference to FIG. 1, emitter finger EF and emitter potential electrode EE are electrically connected in another region. Emitter fingers EF are also formed in contact holes CH1 formed in interlayer insulating films IL1 and IL2, and are electrically connected to body contact regions (p-type semiconductor regions) PR formed in well regions PW and body regions PB. properly connected. That is, the emitter finger EF is provided to supply the emitter potential to the well region PW. Floating fingers FF are also formed in contact holes CH1 formed in interlayer insulating films IL1 and IL2, and body contact regions (p-type semiconductor regions) PR formed in floating regions PF and body regions PB. is electrically connected to That is, the floating finger FF is provided to supply desired potentials to the floating region PF and the body region PB.

Further, as shown in FIG. 6, the protective film PV formed so as to cover the side surface and the upper surface of the metal layer ML1 has an opening OP. A wiring SL and an emitter pad EP are formed. The shunt wiring SL is in contact with the gate finger GF2 and the emitter finger EF and electrically connects the gate finger GF2 and the emitter finger EF. The shunt wiring SL covers the side surfaces and part of the upper surfaces of the gate finger GF2 and the emitter finger EF. Also, the emitter pad EP is formed on the emitter potential electrode EE and is in contact with the upper surface of the emitter potential electrode EE. Note that the interlayer insulating film IL1 can be made of, for example, a silicon oxide film, and the protective film PV can be made of, for example, an organic film such as a polyimide film.

As shown in FIG. 7, gate electrode G1 is electrically connected to gate finger GF1, and gate electrode G2 is electrically connected to gate finger GF2. As shown in FIG. 5, gate electrodes G1 and G2 are formed in trenches T1 and T2 in semiconductor substrate SB in cell region CR. It is formed on the substrate SB. Gate electrodes G1 and G2 are formed over main surface SBa of semiconductor substrate SB with interlayer insulating film IL1 interposed therebetween, and are covered with interlayer insulating film IL2. As shown in FIGS. 3 and 4, two adjacent gate electrodes G1 extend parallel to each other in the Y direction, and the peripheral region PER has a gate connection portion G1c connecting the two gate electrodes G1. is provided. Similarly, two adjacent gate electrodes G2 extend parallel to each other in the Y direction, and the peripheral region PER is provided with a gate connection portion G2c that connects the two gate electrodes G2. Then, as shown in FIG. 7, the gate finger GF1 is formed on the interlayer insulating film IL2 and in the contact hole CH1 provided in the interlayer insulating film IL2. is electrically connected to Similarly, the gate finger GF2 is formed on the interlayer insulating film IL2 and in the contact hole CH1 provided in the interlayer insulating film IL2, and is electrically connected to the two gate electrodes G2 and the gate connecting portion G2c. ing. Note that the gate connection portions G1c and G2c are not essential, and the gate fingers GF1 or GF2 need only be connected to the two gate electrodes G1 or G2.

Next, an inspection process called screening will be described. The screening of the present embodiment is a process of detecting and removing initial defects in the gate insulating films GI of the active cell region AC and the hole collector region HCC. It is directed to the detection of early GI failures. FIG. 8 is a process flow chart showing the method of manufacturing the semiconductor device of this embodiment, and FIG. 9 is a plan view showing the manufacturing process of the semiconductor device of this embodiment. showing. In FIG. 9, the same regions as in FIG. 1 are hatched.

As shown in FIG. 8, the method of manufacturing a semiconductor device according to the present embodiment includes, in order, preparation of an intermediate structure (S1), formation of a protective film PV (S2), screening (S3), formation of a metal layer ML2 (S4), It includes each step of polishing the back surface (S5) and forming the collector potential electrode CE (S6).

First, the step of intermediate structure preparation (S1) is performed. Here, the intermediate structure is a semiconductor device before forming the metal layer ML2 and the protective film PV, and has the structure shown in FIGS. 1 and 3. In FIGS. is removed.

Next, the step of forming the protective film PV (S2) is performed. As described with reference to FIGS. 2, 4, 6 and 7, a protective film PV having an opening OP is formed over the semiconductor substrate SB. As described with reference to FIG. 6, the protective film PV is formed so as to entirely or partially cover the gate fingers GF1 and GF2, the emitter fingers EF, the floating fingers FF and the emitter potential electrode EE, which are made up of the metal layer ML1. .

Next, a screening (S3) step is performed. FIG. 9 shows a state in which probe needles (inspection terminals) PN are brought into contact with the intermediate structure of FIG. Although not shown, the semiconductor chip CHP is mounted on the stage of the inspection apparatus. As shown in FIG. 9, gate fingers GF1 and GF2, emitter fingers EF, floating fingers FF, emitter potential electrode EE and gate potential A probe needle (terminal for inspection) PN is in contact with the electrode GE. In the gate finger GF2 and the floating finger FF, the probe needle PN is in contact with the gate finger pad GFP and the floating finger pad FFP. Then, a desired potential is applied to each part of the intermediate structure to screen (inspect) the gate insulating films GI of the active cell region AC and the hole collector region HCC.

Screening includes “Vg+screening” in which a positive screening voltage is applied to the gate finger GF2 and the gate potential electrode GE, and “Vg−screening” in which a negative screening voltage is applied. In both cases, a reference potential of 0 [V] is applied to floating finger FF, emitter finger EF and emitter to electrode EE, and to the stage. In "Vg+ screening", a pulse voltage of +40 to +60 [V] for 1 second or less is applied to the gate finger GF2 and the gate potential electrode GE. A pulse voltage of -40 to -60 [V] for 1 second or less is applied. Either “Vg+ screening” or “Vg− screening” may be performed, or both may be performed. Screening of the gate insulating films GI of the active cell region AC and the hole collector region HCC may be performed simultaneously or separately.

Further, FIG. 9 shows an example in which the screening of the gate insulating films GI of the hole collector regions HCC is performed simultaneously in the blocks BK1 to BK4. That is, the probe needles PN are brought into contact with the gate finger pads GFP, the floating finger pads FFP, and the emitter potential electrodes EE of the respective blocks BK1 to BK4, and the aforementioned voltages are applied.

Next, a metal layer ML2 formation (S4) step is performed. After the screening (S3) step is completed, a metal film ML2 is selectively formed on the regions exposed from the protective film PV, and as shown in FIGS. to form The metal film ML2 is formed on the upper and side surfaces of the gate finger GF2, the emitter finger EF, the emitter potential electrode EE and the gate potential electrode GE exposed from the protective film PV using an electroless plating method. Therefore, as shown in FIG. 6, the shunt wiring SL is formed on the upper and side surfaces of the gate finger GF2 and the emitter finger EF exposed from the protective film PV, and the gate finger GF2 and the emitter finger EF are electrically connected by the shunt wiring SL. connected to

Next, the rear surface polishing (S5) step and the collector potential electrode CE formation (S6) step are performed in order. The thickness of the semiconductor substrate SB is reduced by polishing the back surface SBb side of the semiconductor substrate SB. Next, ion implantation is performed from the back surface SBb side of the semiconductor substrate SB. This ion implantation forms an n-type field stop region NS and a p-type collector region PC. Field stop region NS is an impurity region having a higher impurity concentration than drift region NV. Next, a collector potential electrode CE is formed on the surface of the collector region PC exposed on the back surface SBb side of the semiconductor substrate SB by, for example, sputtering.

As described above, the semiconductor device of the present embodiment is manufactured.

As described above, in the intermediate structure, in plan view, the gate finger GF2 connected to the gate electrode G2 and the emitter potential electrode EE are separated from each other and electrically independent of each other. Therefore, the gate insulating film GI of the hole collector region HCC can be screened without using an L-load circuit or the like, the screening inspection process can be simplified, the cost can be reduced, and the reliability of the semiconductor device can be improved. can. Further, since the gate finger GF2 is electrically connected to the emitter finger EF connected to the emitter potential electrode EE by the shunt wiring SL formed after the screening, the hole collector region HCC is formed during the operation of the IGBT. Since holes can be discharged by the parasitic p-type MOSFET, the potential fluctuation of the floating region PF can be suppressed.

Furthermore, in the intermediate structure, the floating finger FF connected to the floating region PF and the emitter potential electrode EE are separated from each other and electrically independent from each other in plan view. Therefore, in screening the gate insulating film GI of the hole collector region HCC, it becomes possible to screen the gate insulating film GI positioned between the gate electrode G2 and the floating region PF, thereby further improving the reliability of the semiconductor device. Furthermore, screening of the gate insulating film GI in the active cell region AC also enables screening of the gate insulating film GI between the gate electrode G1 and the floating region PF, thereby further improving the reliability of the semiconductor device.

Since emitter fingers EF connected to the emitter potential electrode EE are provided in the peripheral region PER and connected to the well region PW, holes in the peripheral region PER can be drawn out and thermal destruction of the IGBT can be suppressed. For example, in the study example, the emitter potential electrode EE was extended from the cell region CR to the peripheral region PER and connected to the well region PW. However, in the present embodiment, since the floating finger FF is provided at the end of the cell region CR, it becomes difficult to extend the emitter potential electrode EE to the peripheral region PER as in the study example. Therefore, as shown in FIG. 1, an emitter finger EF connected to the emitter potential electrode EE and extending in the X direction is formed in the peripheral region PER, bypassing the floating finger FF, and connected to the well region PW. Thus, thermal destruction of the IE type IGBT can be suppressed.

Further, as shown in FIG. 1, the emitter finger pad EFP provided at the end of the emitter finger EF and the floating finger pad FFP provided at the end of the floating finger FF are arranged with respect to the emitter potential electrode EE in the X direction. By arranging it in the empty space on the same side as the gate potential electrode GE, an increase in the area of the semiconductor chip CHP is suppressed.

Further, as shown in FIG. 6, by providing an n-type semiconductor region NF having an impurity concentration higher than that of the drift region NV between the well region PW and the floating region PF, the well region PW and the floating region PF Since punch-through between the regions PF can be suppressed and the gap between the well region PW and the floating region PF can be narrowed, the size of the peripheral region PER can be reduced.

Further, as described in the step of forming the metal layer ML2 (S4) in FIG. 8, the shunt wiring SL is formed using the step of forming the emitter pad EP and the gate pad GP. A simple and low-cost screening can be realized.

Further, as shown in FIG. 8, since the back surface polishing (S5) is performed after the screening (S3) step and the metal film ML2 forming (S4) step, in the screening (S3) step and the metal film ML2 forming (S4) step, Since it is not necessary to form a protective film on the back surface SBb of the semiconductor substrate SB, an increase in manufacturing steps can be suppressed.

FIG. 10 is a process flow diagram showing a modification of FIG. As shown in FIG. 10, the screening (S3) step and the metal film ML2 formation (S4) step may be performed after performing the back surface polishing (S5) and the collector potential electrode CE (S6) step. With such an order, defects in the gate insulating film GI caused by the back surface polishing (S5) and collector potential electrode CE (S6) steps can be detected by screening.

11 is a plan view of a semiconductor device that is a modification of FIG. 1. FIG. In FIG. 11, the same regions as in FIG. 1 are hatched. The emitter finger pad EFP and the floating finger pad FFP are arranged on the side opposite to the gate potential electrode GE with respect to the emitter potential electrode EE in the X direction. Floating finger pads FFP connected to floating fingers FF provided in blocks BK1 and BK2 can be shared. The same is true for blocks BK1 and BK2.

12 is a plan view of a semiconductor device that is a modification of FIG. 3. FIG. In FIG. 12, the gate electrodes G1 and G2 are hatched. Although the two gate electrodes G2 extend continuously in the blocks BK1 to BK4 in FIG. 3, the two gate electrodes G2 are independent in each of the blocks BK1 to BK4 in FIG. As shown in FIG. 12, the two gate electrodes G2 provided in the block BK2 are separated from the two gate electrodes G2 provided in the block BK1. Two gate electrodes G2 provided in the block BK2 are connected to gate fingers GF2 provided in the block BK2. The same applies to other blocks BK1, BK3 and BK4.

Unlike the above embodiment, this is effective when screening the gate insulating film GI of the hole collector region HCC for each block. For example, when screening the gate insulating film GI of the hole collector region HCC of the block BK2 shown in FIG. 12, the screening potential is applied only to the gate finger GF2 of the block BK2, and the gate fingers GF2 of the other blocks BK1, BK3 and BK4 are applied. No screening potential is applied to This is because if the screening potential is applied to the gate fingers GF2 of the other blocks BK1, BK3 and BK4, the gate insulating films GI of the hole collector regions HCC provided in the blocks BK1, BK3 and BK4 are deteriorated. It's for.

Then, when the screening of block BK2 is completed, the screening of the next block is performed, and so on.

When screening the gate insulating film GI of the hole collector region HCC of the block BK2, the probe needle PN should be in contact with the gate finger pad GFP, the floating finger pad FFP and the emitter potential electrode EE of the block BK2. (See FIG. 9). The same is true when screening blocks BK1, BK3 and BK4. However, it suffices if the screening pulse voltage is applied only to the gate finger pads GF2 of the blocks to be screened, and as shown in FIG. It's okay to be there.

13 is a plan view of a semiconductor device that is a modification of FIG. 5. FIG. Although FIG. 13 shows the hole collector cell region HCC, the other regions are the same as in FIG. 5 and will be described with reference to FIG. FIG. 13 shows an example in which the distance between two trenches T2a and T2b is narrowed in the hole collector cell region HCC. That is, the interval between two adjacent trenches T2a and T2b is narrower than the interval between two adjacent trenches T1 in the active cell area AC. A contact hole CH2 provided in the interlayer insulating film IL2 and the semiconductor substrate SB is formed across the body region PB and the trench T2a, and an emitter potential electrode EE is formed in the contact hole CH2.

In this embodiment, in order to screen the gate insulating film GI of the hole collector cell region HCC, it is necessary to electrically separate the gate electrode G2a and the emitter potential electrode EE in the intermediate structure. Therefore, the height of the gate electrode G2a formed in the trench T2a is lower than the height of the gate electrode G2b formed in the adjacent trench T2b, and the insulating film IF is formed on the gate electrode G2a. . Also, in other words, the height of the gate electrode G2a is lower than the height of two adjacent trenches T1 in the active cell area AC. Here, the height of the gate electrode is the length from the lower end of the gate electrode positioned at the bottom of the trench to the upper end of the gate electrode positioned above the trench.

(Embodiment 2)
The semiconductor device of the second embodiment is a semiconductor device having an IE-type IGBT with an EGE (emitter-gate-emitter) structure. Here, only parts different from the first embodiment will be described. 14 is a fragmentary plan view of a semiconductor chip, which is the semiconductor device of the second embodiment, and FIG. 15 is a cross-sectional view taken along line DD of FIG. 14 and 15 correspond to FIGS. 3 and 5 of the first embodiment, and show the intermediate structure before the formation of the metal layer ML2 and the protective film PV. Incidentally, in FIG. 14, the gate electrodes G1 and G2 are hatched. Also in the second embodiment, the state after the formation of the metal layer ML2 and the protective film PV is the same as in FIGS.

As shown in FIG. 14, the EGE structure consists of an active cell region AC and two hole collector cell regions HCC arranged on both sides thereof. A gate electrode G1 extending in the Y direction is arranged in the active cell region AC, and a gate electrode G2 extending in the Y direction is arranged in the hole collector cell region HCC. That is, the EGE structure includes one gate electrode G1 and two gate electrodes G2.

The gate electrode G1 continuously extends from the cell region CR to the peripheral region PER and is connected to the gate finger FG1 in the peripheral region PER. Also, the gate electrode G1 continuously extends over the four blocks BK1 to BK4. The gate electrode G2 continuously extends from the cell region CR to the peripheral region PER and is connected to the gate finger FG2 in the peripheral region PER. Also, the gate electrode G2 continuously extends over the four blocks BK1 to BK4.

As described in the first embodiment, after forming the metal layer ML2 and the protective film PV on the intermediate structure, the gate finger FG1 is connected to the gate potential electrode GE, and the gate finger FG2 is connected to the emitter potential. It is connected to electrode EE. Therefore, the gate electrode G1 is connected to the gate potential electrode GE, and the gate electrode G2 is connected to the emitter potential electrode EE.

As shown in FIG. 15, active cell areas AC and inactive cell areas IAC are alternately arranged in the X direction in the cell area CR. The inactive cell region IAC includes a hole collector cell region HCC and a floating region PF. Floating regions PF are formed on both sides.

The active cell region AC includes a gate electrode G1 formed in the trench T1 via the gate insulating film GI and connected to the gate potential electrode GE, and the hole collector cell region HCC includes the gate insulating film GI in the trench T2. It includes a gate electrode G2 formed through. A hole barrier region NHB, which is an n-type semiconductor region having a higher concentration than the drift region NV, is formed in the semiconductor substrate SB in a region sandwiched between the trenches T1 and T2. , a body region PB, which is a p-type semiconductor region, is formed.

An emitter region NE, which is an n-type semiconductor region, is formed on the surface of the body region PB. The emitter region NE is in contact with the trench T1 (in other words, the gate insulating film GI in the trench T1) It is separated from the trench T2 and does not contact the trench T2 (in other words, the gate insulating film GI in the trench T2). Emitter region NE and body region PB are in contact with contact hole CH1 extending in the Y direction, and emitter potential electrode EE is embedded in contact hole CH1. A body contact region PR, which is a p-type semiconductor region having an impurity concentration higher than that of the body region PB, is formed in the semiconductor substrate SB under the contact hole CH1.

By screening the intermediate structures shown in FIGS. 14 and 15 in the same manner as in the first embodiment, the reliability of the semiconductor device can be improved.

FIG. 16 is a plan view of a semiconductor device that is a modification of FIG. 14, and corresponds to FIG. 12 of the first embodiment. In FIG. 16, the gate electrodes G1 and G2 are hatched. In FIG. 14, the gate electrode G2 extends continuously in the blocks BK1-BK4, but in FIG. 16 the gate electrode G2 is independent in each of the blocks BK1-BK4. As shown in FIG. 16, the gate electrode G2 provided in the block BK2 is separated from the gate electrode G2 provided in the block BK1. A gate electrode G2 provided in the block BK2 is connected to a gate finger GF2 provided in the block BK2. The same applies to other blocks BK1, BK3 and BK4. Screening is performed for each of the blocks BK1 to BK4 in order, and the method is as described with reference to FIG. 12 of the first embodiment.

FIG. 17 is a cross-sectional view of a semiconductor device that is a modification of FIG. 15, and corresponds to FIG. 13 of the first embodiment, but is a cross-sectional view of an intermediate structure. This is effective when the distance between adjacent trenches T1 and T2 is narrow. A contact hole CH3 provided in the interlayer insulating film IL2 and the semiconductor substrate SB is formed across the body region PB and the trench T2, and an emitter potential electrode EE is formed in the contact hole CH3.

In this embodiment, in order to screen the gate insulating film GI of the hole collector cell region HCC, it is necessary to electrically separate the gate electrode G2 and the emitter potential electrode EE in the intermediate structure. Therefore, the height of the gate electrode G2 formed in the trench T2 is lower than the height of the gate electrode G1 formed in the adjacent trench T1, and the insulating film IF is formed on the gate electrode G2. .

Although the invention made by the inventor of the present application has been specifically described above based on the embodiment, the invention is not limited to the above embodiment, and can be variously modified without departing from the scope of the invention. A part of the content described in the above embodiment will be described below.

[Appendix 1]
(a) providing an intermediate structure;
the intermediate structure includes a first block and a second block;
each of the first block and the second block,
a first trench and a second trench which are formed in a semiconductor substrate, extend in a first direction in plan view, and are formed with a predetermined spacing in a second direction intersecting the first direction;
a first gate electrode formed in the first trench via a first gate insulating film;
a second gate electrode formed in the second trench via a second gate insulating film;
a first body region of a first conductivity type formed in the semiconductor substrate and in contact with the first trench;
a second body region of the first conductivity type formed in the semiconductor substrate in contact with the second trench;
an emitter region of a second conductivity type opposite to the first conductivity type formed on the first body region in contact with the first trench;
a first contact hole formed in contact with the emitter region and the first body region;
a second contact hole formed in contact with the second body region;
an emitter potential electrode in contact with the emitter region and the first body region in the first contact hole, and in contact with the second body region in the second contact hole;
a first wiring extending in the second direction on the semiconductor substrate and connected to the second gate electrode;
with
(b) in the first block, after a first terminal is brought into contact with the emitter potential electrode and a second terminal is brought into contact with the first wiring, a desired voltage is applied between the first terminal and the second terminal; a first inspection step of applying;
(c) in the second block, after a third terminal is brought into contact with the emitter potential electrode and a fourth terminal is brought into contact with the first wiring, a desired voltage is applied between the third terminal and the fourth terminal; a second inspection step of applying;
(d) forming a shunt wiring electrically connecting the first wiring and the emitter potential electrode in the first block and the second block after the steps (b) and (c);
has
The method of manufacturing a semiconductor device, wherein the second gate electrodes of the first block and the second block are separated from each other.

[Appendix 2]
In the method for manufacturing a semiconductor device according to Supplementary Note 1,
The method of manufacturing a semiconductor device, wherein the first gate electrodes of the first block and the second block are separated from each other.

AC active cell regions BK1 to BK4 block CE collector potential electrodes CH1, CH2, CH3 contact holes CHP, CHP1 semiconductor chip CR cell region Di temperature sensitive diode EE emitter potential electrode EF emitter finger (metal wiring, wiring)
EP Emitter pad FF Floating finger (metal wiring, wiring)
FLP floating pads G1, G2 gate electrodes G1c, G2c gate connecting portion GE gate potential electrodes GF1, GF2 gate fingers (metal wiring, wiring)
GFP gate finger pad GI gate insulating film GP gate pad GR guard ring HCC hole collector cell region IAC inactive cell region IF insulating films IL1, IL2 interlayer insulating films ML1, ML2 metal layer NE emitter region (n-type semiconductor region)
NF n-type semiconductor region NHB hole barrier region (n-type semiconductor region)
NS field stop region (n-type semiconductor region)
NV drift region (n-type semiconductor region)
OP opening PB body region (p-type semiconductor region)
PC collector region (p-type semiconductor region)
PER Peripheral area PF Floating area PN Probe needle (inspection terminal)
PR body contact region (p-type semiconductor region)
PV protective film PW well region (p-type semiconductor region)
SB Semiconductor substrate SBa main surface (first surface)
SBb back side (second side)
SE Sense IGBT
SL Shunt wiring (shunt layer)
T1, T2, T2a, T2b Trench

Claims (15)

a first trench and a second trench which are formed in a semiconductor substrate, extend in a first direction in plan view, and are formed with a predetermined spacing in a second direction intersecting the first direction;
a first gate electrode formed in the first trench via a first gate insulating film;
a second gate electrode formed in the second trench via a second gate insulating film;
a first body region of a first conductivity type formed in the semiconductor substrate and in contact with the first trench;
a second body region of the first conductivity type formed in the semiconductor substrate in contact with the second trench;
a first emitter region of a second conductivity type opposite to the first conductivity type formed on the first body region in contact with the first trench;
a floating region of the first conductivity type formed on a side opposite to the second body region with respect to the second trench in the second direction and in contact with the second trench;
a first contact hole formed in contact with the first emitter region and the first body region;
a second contact hole formed in contact with the second body region;
an emitter potential electrode in contact with the first emitter region and the first body region in the first contact hole, and in contact with the second body region in the second contact hole;
a first wiring extending in the second direction on the semiconductor substrate and connected to the second gate electrode;
a second wiring extending in the second direction on the semiconductor substrate and connected to the floating region;
has
the first wiring and the emitter potential electrode are separated from each other in plan view,
the first wiring and the emitter potential electrode are electrically connected via a shunt wiring ,
The semiconductor device , wherein the second wiring is separated from the emitter potential electrode and the first wiring in plan view . The semiconductor device according to claim 1 ,
moreover,
a well region of the first conductivity type formed in the semiconductor substrate spaced apart from the floating region in the first direction;
a third wiring extending in the second direction on the semiconductor substrate and connected to the well region;
has
The semiconductor device, wherein the third wiring is connected to the emitter potential electrode. 3. The semiconductor device according to claim 2 ,
moreover,
a first semiconductor region of the second conductivity type formed between the floating region and the well region in the first direction;
has
the semiconductor substrate is of the second conductivity type;
The semiconductor device, wherein the impurity concentration of the first semiconductor region is higher than the impurity concentration of the semiconductor substrate. The semiconductor device according to claim 1 ,
moreover,
a fourth wiring extending in the second direction on the semiconductor substrate and connected to the first gate electrode;
a gate potential electrode formed on the semiconductor substrate and connected to the fourth wiring;
A semiconductor device having 5. The semiconductor device according to claim 4 ,
the first wiring, the second wiring, the fourth wiring, the gate potential electrode and the emitter potential electrode are made of a first metal layer;
The semiconductor device according to claim 1, wherein the shunt wiring is formed of a second metal layer above the first metal layer. 5. The semiconductor device according to claim 4 ,
moreover,
a third trench formed in the semiconductor substrate, extending in the first direction in plan view, and in contact with the first body region;
a second emitter region of the second conductivity type formed on the first body region in contact with the third trench;
a fourth trench formed in the semiconductor substrate, extending in the first direction in plan view, and in contact with the second body region;
a third gate electrode formed in the third trench via a third gate insulating film;
a fourth gate electrode formed in the fourth trench via a fourth gate insulating film;
has
the third gate electrode is connected to the fourth wiring,
The semiconductor device, wherein the fourth gate electrode is connected to the first wiring. The semiconductor device according to claim 1,
moreover,
an insulating film formed on the second gate electrode in the second trench;
has
a portion of the second contact hole overlaps the second trench;
The semiconductor device according to claim 1, wherein the emitter potential electrode formed in the second contact hole is electrically separated from the second gate electrode by the insulating film. 8. The semiconductor device according to claim 7 ,
the depth of the first trench is equal to the depth of the second trench;
The semiconductor device, wherein the height of the second gate electrode is lower than the height of the first gate electrode. (a) providing an intermediate structure;
The intermediate structure is
a first trench and a second trench which are formed in a semiconductor substrate, extend in a first direction in plan view, and are formed with a predetermined spacing in a second direction intersecting the first direction;
a first gate electrode formed in the first trench via a first gate insulating film;
a second gate electrode formed in the second trench via a second gate insulating film;
a first body region of a first conductivity type formed in the semiconductor substrate and in contact with the first trench;
a second body region of the first conductivity type formed in the semiconductor substrate in contact with the second trench;
an emitter region of a second conductivity type opposite to the first conductivity type formed on the first body region in contact with the first trench;
a floating region of the first conductivity type formed on a side opposite to the second body region with respect to the second trench in the second direction and in contact with the second trench;
a first contact hole formed in contact with the emitter region and the first body region;
a second contact hole formed in contact with the second body region;
an emitter potential electrode in contact with the emitter region and the first body region in the first contact hole, and in contact with the second body region in the second contact hole;
a first wiring extending in the second direction on the semiconductor substrate and connected to the second gate electrode;
a second wiring extending in the second direction on the semiconductor substrate and connected to the floating region;
with
(b) an inspection step of applying a desired voltage between the first terminal and the second terminal after the first terminal is brought into contact with the emitter potential electrode and the second terminal is brought into contact with the first wiring;
(c) forming a shunt wiring electrically connecting the first wiring and the emitter potential electrode after the step (b);
has
In the step (b),
A third terminal is brought into contact with the second wiring,
A method of manufacturing a semiconductor device , wherein a reference potential is applied to the first terminal and the third terminal, and a positive or negative potential is applied to the second terminal . In the method for manufacturing a semiconductor device according to claim 9 ,
The method of manufacturing a semiconductor device, wherein in the step (b), a reference potential is applied to the semiconductor substrate. In the method for manufacturing a semiconductor device according to claim 9 ,
The intermediate structure further comprises:
a fourth wiring extending in the second direction on the semiconductor substrate and connected to the first gate electrode;
a gate potential electrode formed on the semiconductor substrate and connected to the fourth wiring;
with
In the step (b),
affixing a fourth terminal to the second wiring;
A method of manufacturing a semiconductor device, wherein the positive or negative potential is applied to the fourth terminal. In the method for manufacturing a semiconductor device according to claim 9 ,
The method of manufacturing a semiconductor device, wherein the shunt wiring is formed by an electroless plating method. In the method for manufacturing a semiconductor device according to claim 9 ,
moreover,
(d) polishing the back surface of the semiconductor substrate;
(e) forming a collector potential electrode on the back surface of the semiconductor substrate;
A method of manufacturing a semiconductor device, comprising: In the method of manufacturing a semiconductor device according to claim 13 ,
A method of manufacturing a semiconductor device, wherein the steps (d) and (e) are performed after the step (c). In the method of manufacturing a semiconductor device according to claim 13 ,
A method of manufacturing a semiconductor device, wherein the steps (d) and (e) are performed between the steps (a) and (b).

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