JP6956247B2 - Semiconductor device - Google Patents

Description

The present invention relates to a SiC semiconductor device.

Conventionally, various proposals have been made in order to prevent defects from occurring when testing the characteristics of a semiconductor device. For example, Patent Document 1 proposes measures to prevent an electric discharge from occurring in the atmosphere during an electrical property test. Specifically, in Patent Document 1, a base region and an emitter region are formed on a semiconductor wafer, the base electrode and the emitter electrode are patterned, and then a polyimide film is adhered to the surface of the base electrode and the emitter electrode to pattern the semiconductor wafer. A method for manufacturing a semiconductor device including a step of covering a region other than an electrode bonding portion is disclosed.

Japanese Unexamined Patent Publication No. 60-50937 JP-A-54-45570 Japanese Unexamined Patent Publication No. 2011-2438337 Japanese Unexamined Patent Publication No. 2001-176876 Republished Patent WO2009 / 101668

By the way, high temperature, high humidity and high voltage tests have begun to be adopted as tests for semiconductor devices. In this test, the semiconductor device is continuously exposed to, for example, 85 ° C., 85% RH and 960 V application for 1000 hours (about 40 days). Conventionally, measures that can individually withstand the above-mentioned temperature, humidity, and voltage conditions have been taken, but measures that satisfy all of these three conditions have not yet been proposed.

Therefore, an object of the present invention is to provide a SiC semiconductor device capable of preventing electric discharge during an electrical characteristic test carried out in a wafer state and capable of withstanding a high temperature, high humidity and high voltage test.

The semiconductor device according to one aspect of the present invention has a first conductive type SiC layer having an active region in which a plurality of transistor elements are formed on the surface and an outer peripheral region which is a peripheral portion thereof, and on the SiC layer. The insulation comprises an electrode selectively formed and electrically connected to the transistor element, and an insulator formed on the SiC layer so as to extend toward a dicing region at the end of the SiC layer. The body includes an insulating film formed below the electrode and a surface insulating film covering the insulating film and a part of the electrode, and the surface insulating film is formed so as to reach the dicing region. The surface insulating film has a first region formed so as to overlap the insulating film, and the surface insulating film comes into contact with the SiC layer and extends toward the end of the SiC layer outside the first region. It has a second region formed so as to.

FIG. 1 is a schematic plan view of the semiconductor device according to the first embodiment of the present invention. FIG. 2 is an enlarged view of the region surrounded by the alternate long and short dash line II of FIG. FIG. 3 is an enlarged view of the region surrounded by the alternate long and short dash line III of FIG. FIG. 4 is a cross-sectional view when the semiconductor device is cut along the cutting lines IV-IV of FIG. FIG. 5 is an enlarged view of the region surrounded by the alternate long and short dash line V in FIG. FIG. 6 is a cross-sectional view when the semiconductor device is cut along the cutting line VI-VI of FIG. FIG. 7A is a cross-sectional view for explaining a process related to cutting the wafer. FIG. 7B is a cross-sectional view showing the state of the wafer after cutting. FIG. 8 is a schematic cross-sectional view of the semiconductor device according to the second embodiment of the present invention. FIG. 9 is a schematic cross-sectional view of the semiconductor device according to the third embodiment of the present invention. FIG. 10 is a schematic cross-sectional view of the semiconductor device according to the fourth embodiment of the present invention. FIG. 11 is a schematic cross-sectional view of the semiconductor device according to the fifth embodiment of the present invention. FIG. 12 is a schematic cross-sectional view of the semiconductor device according to the sixth embodiment of the present invention. FIG. 13 is a schematic cross-sectional view of the semiconductor device according to the seventh embodiment of the present invention. FIG. 14 is a schematic cross-sectional view of the semiconductor device according to the eighth embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic plan view of the semiconductor device 1 according to the first embodiment of the present invention. In FIG. 1, for clarity, some of the elements that are not exposed on the outermost surface of the semiconductor device 1 in an actual plan view are shown by solid lines.
The semiconductor device 1 is a semiconductor device in which SiC is adopted. For example, the semiconductor device 1 is formed in a rectangular chip shape in a plan view (hereinafter, simply referred to as "plan view") when the outermost surface thereof is viewed from the normal direction. Has been done.

The semiconductor device 1 is set with an active region 2 and an outer peripheral region 3 surrounding the active region 2. In this embodiment, the active region 2 is formed in a substantially square shape in a plan view in the inner region of the semiconductor device 1, but the shape thereof is not particularly limited.
A gate metal 44, a source metal 43 as an example of the electrode of the present invention, and a gate finger 5 are formed in the active region 2. A passivation film 40 is formed on the outermost surface of the semiconductor device 1 so as to cover them. The passivation film 40 is formed with openings 41 and 42 that expose a part of the gate metal 44 and a part of the source metal 43 as the gate pad 4 and the source pad 6, respectively. On the other hand, the entire gate finger 5 is covered with the passivation film 40. In FIG. 1, for clarity, the gate finger 5 is shown by a solid line and hatched.

The gate metal 44, the gate finger 5, and the source metal 43 are made of metal wiring such as Al (aluminum), AlCu (aluminum-copper alloy), and Cu (copper), for example. Preferably, as described in the description of FIG. 6, it has a laminated structure represented by Ti / TiN / Al—Cu.
By configuring the gate finger 5 with metal wiring having a lower resistance than polysilicon, the gate current can be applied to the transistor cell 18 (see FIG. 2) at a position relatively far (far away) from the gate metal 44. It can be supplied in a short time. Further, if it is Al, its workability is good (because it is easy to process), so that the process of forming these wirings can be simplified. On the other hand, AlCu can improve the power cycle resistance and humidity resistance of the semiconductor device 1 as compared with the case where Al is used, and can also improve the bonding strength of the bonding wire with respect to the gate pad 4. When Cu is used, there is an advantage that the resistivity can be reduced as compared with the case of Al and AlCu.

The gate metal 44 is selectively formed in a part of the peripheral edge portion (near the boundary with the outer peripheral region 3) of the active region 2. The gate finger 5 extends from the formation position of the gate pad 4 in a direction along the peripheral edge of the active region 2 and in a direction toward the inside of the active region 2. As a result, in the active region 2, cell regions 7 and 45 are formed in a portion partitioned by a plurality of gate fingers 5 extending in different directions with the gate metal 44 interposed therebetween and in an outer region of the gate fingers 5. ..

More specifically, in this embodiment, the gate metal 44 is formed in a rectangular shape in a plan view and is selectively arranged in the central portion of one side 8 of the active region 2. The sides other than one side 8 (the side on which the gate metal 44 is arranged) of the active region 2 are the opposite side 9 of the one side 8 and the sides 10 and 11 continuous to both ends of these sides 8 and 9, respectively.
The gate finger 5 has a pad peripheral portion 12 that surrounds the gate metal 44 at intervals, a direction along the one side 8 of the active region 2 and a direction orthogonal to the one side 8 from the pad peripheral portion 12, respectively. Includes a first finger 13 and a second finger 14 extending in.

The pad peripheral portion 12 is formed in a square ring in a plan view along the periphery of the gate metal 44.
A pair of first fingers 13 are formed along the side 8 in the direction toward the side 10 and the opposite side 11 with respect to the pad peripheral portion 12.
The second finger 14 is integrally connected to the linear main portion 15 that crosses the active region 2 up to the side 9 in the direction orthogonal to the first finger 13, and the first finger 13 from the connection portion. Includes a plurality of branches 16 extending along. In this embodiment, the branch portions 16 are connected to two locations, the tip portion of the main portion 15 and the middle portion of the main portion 15, to form a total of two pairs, but the number is not particularly limited.

Thus, in the active region 2, the cell regions 7 and 45 are partitioned by the first finger 13 and the second finger 14 (main portion 15 and branch portion 16). In this embodiment, a total of four inner cell regions 7 are formed, one at each corner of the intersection formed by the main portion 15 of the second finger 14 and the central branch portion 16. Further, between the peripheral edge of the active region 2 and the gate finger 5, an annular outer cell region 45 is formed along the peripheral edge of the active region 2.

The source metal 43 is formed so as to cover substantially the entire inner cell region 7 and outer cell region 45. The passivation film 40 is formed with a total of four openings 42 so that one source pad 6 is arranged in each inner cell region 7.
Further, the source metal 43 is formed with a recess 17 corresponding to the shape of the gate metal 44. The recess 17 is a recess formed in order to avoid the gate metal 44 in which the gate metal 44 is set back to the inner side of the active region 2 with respect to the first finger 14.

FIG. 2 is an enlarged view of the region surrounded by the alternate long and short dash line II of FIG. That is, it is an enlarged view showing the gate pad 4 of the semiconductor device 1 and the region around it. In FIG. 2, for clarity, a part of the elements not exposed on the outermost surface of the semiconductor device 1 in an actual plan view is shown by a solid line.
As shown in FIG. 2, a plurality of transistor cells 18 are arranged in the inner cell region 7 and the outer cell region 45 partitioned by the gate fingers 5 (pad peripheral portion 12, the first finger 13 and the second finger 14). ing.

In this embodiment, the plurality of transistor cells 18 are arranged in a matrix in a plan view in each of the inner cell region 7 and the outer cell region 45. In the vicinity of the gate finger 5, the plurality of transistor cells 18 are aligned according to the shape of the gate finger 5. For example, the plurality of transistor cells 18 are bent and aligned according to the shape of the corner portion of the pad peripheral portion 12, and are linearly aligned according to the shape of the main portion 15 of the linear second finger 14. .. The source metal 43 is formed so as to cover the plurality of transistor cells 18.

Note that FIG. 2 shows only a part of the plurality of transistor cells 18 covered with the source metal 43 for the sake of clarity. Further, the arrangement form of the plurality of transistor cells 18 is not limited to the matrix shape, and may be, for example, a striped shape, a staggered shape, or the like. Further, the planar shape of each transistor cell 18 is not limited to a quadrangular shape, and may be, for example, a circular shape, a triangular shape, a hexagonal shape, or the like.

A gate electrode 19 is formed between the transistor cells 18 adjacent to each other. The gate electrodes 19 are arranged between each of the matrix-shaped transistor cells 18 in the inner cell region 7 and the outer cell region 45, and are formed in a planar grid shape as a whole. On the other hand, the gate electrode 19 is formed not only in the inner cell region 7 and the outer cell region 45 but also in the region where the gate finger 5 is arranged, and the lower portion of the gate finger 5 contacts the gate finger 5. doing.

In this embodiment, a part of the gate electrode 19 is formed in the lower region of the first finger 13 and the second finger 14, and faces the first finger 13 and the second finger 14 as a contact portion. In FIG. 2, for clarity, the portion formed in the lower region of the gate electrode 19 is represented by a hatched region. As a result, the gate electrodes 19 of the inner cell regions 7 adjacent to each other are continuous via the gate electrodes 19 that cross the second finger 14 downward. The continuous form of the gate electrode 19 is the same with respect to the space between the inner cell region 7 and the outer cell region 45 adjacent to the gate metal 44. That is, the gate electrodes 19 in these regions are continuous via the gate electrodes 19 that cross the first finger 13 downward.

The first finger 13 and the second finger 14 are each connected to the gate electrode 19 arranged in the lower region thereof by the gate contact 20. The gate contact 20 is formed linearly along the respective longitudinal directions at the central portion of the finger spaced from each side edge of the first finger 13 and the second finger 14.

Further, in this embodiment, a plurality of built-in resistances 21 are arranged below the gate metal 44. It is preferable that the plurality of built-in resistors 21 are arranged at positions substantially equidistant from the position of the center of gravity of the planar shape of the gate metal 44 so as to have symmetry with respect to the arrangement of the plurality of built-in resistors 21. In this embodiment, a plurality of built-in resistances 21 are arranged one by one at each corner of the gate metal 44 equidistant from the center of gravity G of the rectangular gate metal 44 in a plan view. This gives symmetry to the four built-in resistances 21.

Various patterns of such symmetry can be considered. For example, two built-in resistances 21 may be arranged one by one at two corners of the diagonal gate metal 44, or may be arranged in a diagonal relationship. It may be arranged so as to face each other one by one on two sides of a certain gate metal 44. Further, for example, when the gate metal 44 has a circular shape in a plan view, two built-in resistances 21 may be arranged at both ends of the diameter of the gate metal 44, and the gate metal 44 may be arranged in a plan view. In the case of a triangular shape, three built-in resistors 21 may be arranged one by one at the three corners of the gate metal 44.

Each built-in resistance 21 is formed so as to cross and straddle the annular gap region 26 between the gate metal 44 and the gate finger 5 (pad peripheral portion 12). As a result, the built-in resistance 21 faces each of the gate metal 44 and the gate finger 5. The gate metal 44 and the gate finger 5 (pad peripheral portion 12) are connected to the built-in resistance 21 arranged in the lower region thereof by the pad side contact 22 and the cell side contact 23, respectively.

In this embodiment, the four built-in resistances 21 extend from the lower side of each peripheral edge portion 24 of the two sides of the gate metal 44 having a side-to-side relationship to the outer side orthogonal to the side, and reach below the pad peripheral portion 12. There is. Each built-in resistance 21 is formed in a rectangular shape in a plan view, and has a size of, for example, 200 μm □ or less (200 μm × 200 μm or less). Practically, if the size of each built-in resistance 21 is 200 μm □ or less, the area of the region on the SiC epitaxial layer 28 (see FIG. 4) that is sacrificed by the built-in resistance 21 can be reduced. Space can be saved.

Further, the pad-side contact 22 and the cell-side contact 23 are formed in a straight line parallel to each other along the sides of the gate metal 44 and the pad peripheral portion 12, respectively.
By arranging the built-in resistance 21 below the peripheral edge portion 24 avoiding the central portion of the gate metal 44 and further covering the upper region of the region where the built-in resistance 21 is arranged with the passivation film 40, the central portion of the gate metal 44 A gate pad 4 is secured as a wire region surrounded by a built-in resistance 21. The gate pad 4 is an area to which the bonding wire is connected.

That is, in this embodiment, each corner of the gate metal 44 on which the built-in resistance 21 is arranged is selectively covered with the passivation film 40, and the other parts of the gate metal 44 are exposed from the opening 41. As a result, on the outermost surface of the semiconductor device 1, a gate pad 4 having a rectangular shape in a plan view in which each corner portion is recessed inward is exposed. By covering the upper region of the region where the built-in resistance 21 is arranged with the passivation film 40 in this way, the bonding wire is erroneously joined to the portion of the gate metal 44 that overlaps with the built-in resistance 21 when the bonding wire is joined. Can be prevented. As a result, it is possible to prevent the built-in resistance 21 from being damaged or destroyed by an impact such as ultrasonic waves when the bonding wire is bonded.

FIG. 3 is an enlarged view of the region surrounded by the alternate long and short dash line III of FIG. FIG. 4 is a cross-sectional view when the semiconductor device 1 is cut along the cutting lines IV-IV of FIG. In addition, in FIGS. 3 and 4, the scale of each component may be different from that of FIGS. 1 and 2 for the sake of clarity, and the scale of each component may be different between FIGS. 3 and 4. be. Further, in FIGS. 3 and 4, for clarity, a part of the elements not exposed on the outermost surface of the semiconductor device 1 in an actual plan view is shown by a solid line.

Next, a more detailed configuration of the built-in resistance 21 and a region in the vicinity thereof will be described together with the cross-sectional structure of the semiconductor device 1.
The semiconductor device 1 includes a SiC substrate 27 and a SiC epitaxial layer 28. The SiC epitaxial layer 28 is laminated on the SiC substrate 27, and this laminated structure is shown as an example of the SiC layer of the present invention.

The SiC substrate 27 and the SiC epitaxial layer 28 are n ⁺ type and n ⁻ type SiC, respectively. The impurity concentration of the n ⁺ type SiC substrate 27 is, for example, 1 × 10 ¹⁷ cm ^-3 to 1 × 10 ²¹ cm ^-3 . On the other hand, ^{the impurity concentration of the n-} type SiC epitaxial layer 28 is, for example, 1 × 10 ¹⁴ cm ^-3 to 1 × 10 ¹⁶ cm ^-3 . Further, as the n-type impurity, for example, N (nitrogen), P (phosphorus), As (arsenic) and the like can be used (hereinafter, the same applies).

The thickness of the SiC substrate 27 is, for example, 50 μm to 1000 μm, and the thickness of the SiC epitaxial layer 28 is, for example, 5 μm or more (specifically, 5 μm to 100 μm).
In the inner cell region 7, a plurality of transistor cells 18 are formed on the surface portion of the SiC epitaxial layer 28. The plurality of transistor cells 18 have a p ^- type body region 29, ^{an n +} -type source region 30 selectively formed in an inner region spaced from the periphery of the ^{p- type body region 29, and an n +} -type source. ^{It includes a p +} type body contact region 31 selectively formed in an inner region spaced from the peripheral edge of the region 30. ^{Further, the n-} type portion of the SiC epitaxial layer 28 is a common drain region of the plurality of transistor cells 18.

^{As shown in FIG. 3, in a plan view, an n +} type source region 30 is formed ^{so as to surround the p +} type body contact region 31 except for the transistor cell 18 along the pad peripheral portion 12 (gate finger 5). Further, a ^p- type body region 29 is formed so as to surround ^{the n + -type source region 30.} In the p ^- type body region 29, the ^{annular region surrounding the n +} -type source region 30 is the channel region 32 in which the channel is formed when the semiconductor device 1 is turned on.

On the other hand, in the transistor cell 18 along the pad peripheral portion 12 (gate finger 5), the p ^- type body region 29 and the p ⁺ -type body contact region 31 are divided into the p ^- type region 34 and the p ⁺ -type region 33, which will be described later, respectively. It is electrically connected.
The impurity concentration of the p ^- type body region 29 is, for example, 1 × 10 ¹⁴ cm ^-3 to 1 × 10 ¹⁹ cm ^-3 , and ^{the impurity concentration of the n +} type source region 30 is, for example, 1 × 10 ¹⁷ cm ^{−. It is 3} to 1 × 10 ²¹ cm ^-3 , and ^{the impurity concentration of the p +} type body contact region 31 is, for example, 1 × 10 ¹⁹ cm ^-3 to 1 × 10 ²¹ cm ^-3 .

To form these regions 29 to 31, for example, a p ^- type body region 29 is formed on the surface of the SiC epitaxial layer 28 by ion implantation. After that, ^{the n +} type source region 30 and the p ⁺ type body contact region 31 are formed by ion-implanting the n-type impurities and the p-type impurities into the surface portion of ^{the p-type body region 29 in order.} As a result, the transistor cell 18 composed of the regions 29 to 31 is formed. As the p-type impurity, for example, B (boron), Al (aluminum) and the like can be used (hereinafter, the same applies).

In the active region 2, in regions other than the inner cell region 7 and the outer cell region 45, specifically, in the region below the gate metal 44, the gate finger 5 and the gap region 26, a p ^- type region is formed on the surface of the SiC epitaxial layer 28. 34 is formed. A p ⁺ type region 33 is formed on the surface of the ^{p − type region 34.}
The p ^{+ type region 33 selectively exposes the p − type portion of the p −} type region 34 to the SiC surface in the region facing the built-in resistance 21 of the SiC epitaxial layer 28, and in the other regions, it is its own. It is formed over almost the entire lower region of the gate metal 44 or the like so that the p ^{+ type portion is selectively exposed on the SiC surface.} That is, the gate metal 44 and the gate finger 5 ^{face the p − type portion in the region where the built-in resistance 21 is arranged, but face the p +} type portion in most of the other regions. There is. Further, the p ⁺ type region 33 and the p ⁻ type region 34 are formed so as to extend below the source metal 43, respectively, and are formed of the source metal 43 (in this embodiment, an outer portion from the source pad 6). Below, it is integrally connected to ^{the p +} type body contact region 31 and the p ^{− type body region 29. In FIG. 3, the p +} type body contact region 31 and the p ⁺ type region 33 of the transistor cell 18 along the pad peripheral portion 12 (gate finger 5) are represented by hatched regions. Practically, the p ⁺ type body contact region 31 is fixed to the ground potential together with the source metal 43, whereby the p ⁺ type region 33 is stabilized at 0 V. Therefore, as in this embodiment, it is preferable that most of the gate metal 44 and the gate finger 5 face the p ^{+ type region 33.}

The p ⁺ type region 33 and the p ⁻ type region 34 are ^{formed in the same process as the p +} type body contact region 31 and the p ⁻ type body region 29, respectively, and their impurity concentrations and depths are also the same.
A gate insulating film 35 is formed on the surface of the SiC epitaxial layer 28. The gate insulating film 35 is made of an insulating material such as silicon oxide and has a thickness of, for example, 0.001 μm to 1 μm. The gate insulating film 35 is a common insulating film for insulating the gate electrode 19 and the built-in resistance 21 from the SiC epitaxial layer 28.

A gate electrode 19 and a built-in resistance 21 are formed on the gate insulating film 35. The gate electrode 19 is formed so as to face the channel region 32 of each transistor cell 18 with the gate insulating film 35 interposed therebetween. On the other hand, internal resistors 21, p ^- exposed p type region 34 ^- the mold portion, is formed so as to face each other across the gate insulating film 35.
Both the gate electrode 19 and the built-in resistance 21 are made of p-type polysilicon and may be formed in the same process. In this embodiment, the gate electrode 19 and the built-in resistance 21 contain B (boron) as a p-type impurity. The B (boron) -containing polysilicon has a large specific resistance value with respect to the phosphorus (P) -containing polysilicon generally used in Si semiconductor devices. Therefore, the boron-containing polysilicon (built-in resistance 21) requires a smaller area than the phosphorus-containing polysilicon even when achieving the same resistance value. Therefore, the area occupied by the built-in resistance 21 on the SiC epitaxial layer 28 can be reduced, so that the space can be effectively used.

The concentration of p-type impurities contained in polysilicon can be appropriately changed according to the design resistance values of the gate electrode 19 and the built-in resistance 21. In this embodiment, the concentration is set so that the sheet resistance of the built-in resistor 21 is 10 Ω / □ or more. Practically, if the sheet resistance of the built-in resistor 21 is 10 Ω / □ or more, the resistance value of the entire built-in resistor 21 can be varied among the plurality of semiconductor devices 1 without increasing the area of the built-in resistor 21. Can be made larger more easily than. For example, when the variation of the resistance value is 0.1Ω to 20Ω, the resistance value of the built-in resistance 21 can be set to 2Ω to 40Ω in a small area. As a result, the area of the region on the SiC epitaxial layer 28 that is sacrificed due to the built-in resistance 21 can be reduced, so that the influence on the layout of other elements can be reduced. Further, in this case, the total resistance value of the resistance value of the gate electrode 19 and the resistance value of the built-in resistance 21 is preferably 4Ω to 50Ω.

The thickness of the gate electrode 19 and the built-in resistance 21 is preferably 2 μm or less. By reducing the thickness of the built-in resistor 21 to 2 μm or less, the resistance value of the entire built-in resistor 21 can be easily increased more than the variation in the resistance value among the plurality of semiconductor devices 1. On the contrary, if the built-in resistance 21 is too thick, the resistance value becomes too low, which is not preferable.
An insulating film 47 is further formed on the SiC epitaxial layer 28. The insulating film 47 is made of _{an insulating material such as silicon oxide (SiO 2} ) and silicon nitride (SiN), and has a thickness of, for example, 1 μm to 5 μm. In particular, it is preferable to use a BPSG (Boron Phosphorus Silicon Glass) film having a thickness of 1 μm or more.

The insulating film 47 includes an interlayer film 36 formed so as to cover the gate electrode 19 and the built-in resistance 21. The interlayer film 36 is formed so as to enter a region (first region) in which the gate electrode 19 and the built-in resistance 21 are not arranged in the region on the gate insulating film 35. As a result, the distance between the SiC epitaxial layer 28 and the gate metal 44 (thickness T of the insulating film) can be increased in the region where the built-in resistance 21 is not arranged, so that the capacitance between them can be reduced.

A pad-side contact 22 and a cell-side contact 23 are formed so as to penetrate the interlayer film 36. The pad-side contact 22 and the cell-side contact 23 are each composed of a metal via formed integrally with the gate metal 44 and the gate finger 5 (pad peripheral portion 12).
Further, the interlayer film 36 is formed with a source contact 46 for making contact from the source metal 43 with respect to ^{the n +} type source region 30 and the p ^{+ type body contact region 31.} The source contact 46 is made of a metal via integrally formed with the source metal 43.

A gate metal 44, a gate finger 5, and a source metal 43 are formed on the interlayer film 36 at intervals from each other.
A passivation film 40 is formed on the interlayer film 36 so as to cover the gate metal 44, the gate finger 5, and the source metal 43. The passivation film 40 is formed with openings 41 and 42 that expose a part of the gate metal 44 and the source metal 43.

As described above, according to the semiconductor device 1, as shown in FIGS. 3 and 4, a polysilicon resistor (built-in resistor 21) is interposed between the gate metal 44 and the gate finger 5 (pad peripheral portion 12). ing. That is, the built-in resistance 21 is interposed in the middle of the current path from the outside to the plurality of transistor cells 18.
By adjusting the resistance value of the built-in resistance 21, the resistance value of the built-in resistance 21 can be dominated by the total resistance value (gate resistance) of the resistance value of the gate electrode 19 and the resistance value of the built-in resistance 21. can. Therefore, even when a plurality of semiconductor devices 1 having variations in the resistance values of the gate electrodes 19 are connected and used in parallel, the resistance values of the built-in resistors 21 are set to be larger than the variations so that the gates are relatively gated. It is possible to limit the inflow of current to the semiconductor device 1 having a low resistance value of the electrode 19. As a result, it is possible to reduce the generation of noise during the use.

Moreover, the polysilicon that constitutes the built-in resistance 21 is a material whose resistance value can be easily controlled by injecting impurities or the like, and its processing has also been established by conventional semiconductor manufacturing technology. Therefore, when the built-in resistance 21 is introduced, it is possible to avoid the structure of the semiconductor device 1 itself and the module including the semiconductor device 1 from becoming complicated.
As with the gate electrode 19, the built-in resistor 21 may have variations in size and thickness due to variations in processing accuracy (etching dimensions, etc.) when manufacturing the semiconductor device 1. The processing size is smaller than that of. Therefore, the variation in the built-in resistance 21 rarely triggers the generation of noise.

Further, since the built-in resistance 21 is connected to the gate metal 44 below the gate metal 44, the inflow of the gate current can be restricted at the inlet of the current path leading from the outside to the plurality of transistor cells 18. As a result, it is possible to prevent the inrush current from flowing only in the specific transistor cell 18.
For example, in FIG. 2, consider a case where the built-in resistance 21 is formed in the middle of the first finger 13 and the second finger 14 of the gate finger 5 as a detour for these fingers 13 and 14. In this case, on the side closer to the gate metal 44 than the built-in resistance 21, an inrush current may flow from the fingers 13 and 14 to the gate electrode 19 via the gate contact 20 before reaching the built-in resistance 21. On the other hand, if the gate current can be limited at the inlet of the current path as in this embodiment, the variation in switching speed among the plurality of transistor cells 18 can be reduced.

Further, as shown in FIG. 2, the built-in resistance 21 is arranged symmetrically. This feature also makes it possible to reduce variations in switching speed among the plurality of transistor cells 18.
Further, as shown in FIGS. 3 and 4, in the SiC epitaxial layer 28, the region facing the built-in resistance 21 ^{is a p-} type region 34 having an impurity concentration of ^{1 × 10 19} cm ^{-3 or less.} Therefore, the dielectric breakdown of the gate insulating film 35 can be satisfactorily suppressed. Further, since the p ^- type region is less likely to accumulate carriers than the n-type region, it is possible to reduce the capacitance between the ^{built-in resistance 21 and the p-} type region 34 facing each other with the gate insulating film 35 in between. can.

Further, as shown in FIGS. 3 and 4, the gate metal 44 and the built-in resistance 21 are connected by a pad-side contact 22 made of a metal via. Therefore, the built-in resistance 21 contributes to the current path leading from the outside to the plurality of transistor cells 18 by processing such as changing the position of the pad-side contact 22 along the surface of the SiC epitaxial layer 28 or changing the diameter of the via. The resistance value can be easily adjusted.

For example, as shown by the pad-side contact 37 shown by the broken line in FIG. 4, the distance from the contact position with respect to the built-in resistance 21 to the pad peripheral portion 12 can be changed from D _{1 to D simply by bringing the pad-side contact 22 closer to the pad peripheral portion 12.} It can be easily shortened to _2. As a result, the resistance value of the built-in resistor 21 can be reduced. On the contrary, the resistance value of the built-in resistance 21 can be increased by moving away from the pad peripheral portion 12. Further, as shown by the pad-side contact 38 shown by the broken line in FIG. 3, the resistance value of the current path toward the built-in resistance 21 can be increased only by making the via diameter smaller than that of the pad-side contact 22. On the contrary, if the via diameter is increased, the resistance value of the path can be reduced.

Moreover, in these processes, when forming the pad-side contact 22 (via), it is only necessary to use a mask that matches the distance design and the via diameter design, so that it is possible to prevent the manufacturing process from becoming complicated. ..
FIG. 5 is an enlarged view of the region surrounded by the alternate long and short dash line V in FIG. FIG. 6 is a cross-sectional view when the semiconductor device is cut along the cutting line VI-VI of FIG. In addition, in FIGS. 5 and 6, the scale of each component may be different from that of FIGS. 1 to 4 for clarification, and the scale of each component may be different between FIGS. 5 and 6. be. Further, in FIGS. 5 and 6, for clarity, a part of the elements not exposed on the outermost surface of the semiconductor device 1 in an actual plan view is shown by a solid line.

Next, a more detailed configuration of the peripheral edge portion and the outer peripheral region 3 of the active region 2 of the semiconductor device 1 will be described together with the cross-sectional structure of the semiconductor device 1.
As described above, in the outer cell region 45 formed on the peripheral edge of the active region 2, a plurality of transistor cells 18 are arranged in a matrix in a plan view. The configuration of each transistor cell 18 is the same as the configuration described with reference to FIGS. 3 and 4.

On the outside of the outer cell region 45, a p ^- type region 51 is formed on the surface portion of the SiC epitaxial layer 28. A p ⁺ type region 52 is formed on the surface of the ^{p − type region 51.} The p ^- type region 51 is formed linearly along the peripheral edge of the active region 2 ^{and is integrated with the p-} type body region 29 of the plurality of (outermost) transistor cells 18. Although only the portion of the p ^- type region 51 adjacent to the outer cell region 45 is shown in FIG. 5, in reality, the cell region (inner cell region 7 and the inner cell region 7 and the inner cell region 7) is shown along the entire circumference of the active region 2. The outer cell area 45) may be surrounded. p ⁺ -type region 52, p ^- inner region of the mold region 51 ^- in (p peripheral region spaced from the mold region 51) is formed in a linear shape extending in the longitudinal direction. The p ^- type region 51 and the p ⁺ type region 52 are ^{formed in the same process as the p-} type body region 29 and the p ⁺ type body contact region 31, respectively, and their impurity concentrations and depths are also the same.

A plurality of guard rings 53 as an example of the terminal structure of the present invention are further formed on the peripheral edge of the active region 2 so as to surround the cell region (inner cell region 7 and outer cell region 45). The plurality of guard rings 53 are guard ring regions having a predetermined width (G) from ^{the outermost region (p-} type region 51 in this embodiment) of the regions equipotential with the source metal 43 in the SiC epitaxial layer 28. Is located in. The predetermined width (G) is 5 μm to 100 μm (for example, 28 μm) in this embodiment. When the guard ring 53 is ^{formed in the same process as the p-} type body region 29, the impurity concentration and depth thereof are also the same. When formed in another step, the impurity concentration is, for example, 1 × 10 ¹⁴ cm ^-3 to 1 × 10 ¹⁹ cm ^-3 and the depth is 0.1 μm to 2 μm.

On the other hand, in the outer peripheral region 3, p in the surface portion of the SiC epitaxial layer 28 ^- -type region 55 is formed, p ^{- p +} -type region 56 in the surface of the mold region 55 is formed. p ^- type region 55 and ^{p +} -type region 56, p ^- like the type region 51 and ^{p +} -type region 52, p ^- is formed by type body region 29 and ^{p +} -type body contact region 31 and the same process Region (same impurity concentration and depth). However, the p ⁻ type region 55 and the p ⁺ type region 56 ^{form a laminated structure because the p +} type region 56 is formed over the entire surface portion of the ^{p − type region 55.}

^{The p-} type region 55 and the p ⁺ -type region 56 are formed in the outer peripheral region 3 at the dicing region 54 set at the end of the SiC epitaxial layer 28. As shown in FIGS. 7A and 7B, the dicing region 54 is a region having a predetermined width including a dicing line 58 set at the boundary between adjacent semiconductor devices 1 on the wafer 57. Each semiconductor device 1 is fragmented by cutting the wafer 57 along the dicing line 58. At this time, it is necessary to provide a margin having a predetermined width in consideration of the misalignment of the dicing saw, and this margin portion remains as the dicing region 54 after individualization.

The p ^- type region 55 and the p ⁺ type region 56 (p-type region) are arranged so as to be exposed to the end face 59 of the SiC epitaxial layer 28 in the dicing region 54. ^{The width (F) of the p-} type region 55 and the p ⁺ -type region 56 with respect to the exposed surface (end surface 59) is 5 μm to 100 μm (for example, 20 μm) in this embodiment. This width (F) may be set in a range equal to or greater than the difference between the width (D) of the dicing region 54 and twice the width (E) of the depletion layer 60 extending from the guard ring 53, for example. In the design of the width (F), the width (D) of the dicing region 54 may be the distance (for example, 13 μm) from the end face 59 of the SiC epitaxial layer 28 to the edge of the passivation film 40 in this embodiment. can. On the other hand, as the width (E) of the depletion layer 60, the value calculated by the following formula (1) can be used.

（ただし、ε_s：ＳｉＣの誘電率、Ｖ_ｂｉ：ｐ型ガードリング５３とｎ型ＳｉＣエピタキシャル層２８とのｐｎ接合のビルトインポテンシャル、ｑ：電荷の絶対値、Ｎ_Ｂ：ｎ型ＳｉＣエピタキシャル層２８のドナー濃度である。）

(However, epsilon _s: a dielectric constant of _{SiC, V bi:} built-in potential of the pn junction between the p-type guard ring 53 and the n-type SiC epitaxial layer 28, q: absolute value of the _{charge, N} B: n-type SiC epitaxial layer 28 Donor concentration.)

In addition to the interlayer film 36, the insulating film 47 further includes an under-metal insulating film 61 and an end insulating film 62 as examples of the sub-electrode insulating film of the present invention. ^{A contact hole 63 that exposes the p +} type region 52 is formed in the insulating film 47, and the inner portion of the contact hole 63 as a boundary is an interlayer film 36, which is formed on the gate insulating film 35. .. On the other hand, the outer portion adjacent to the interlayer film 36 with the contact hole 63 interposed therebetween is the metal undermetal insulating film 61.

The source metal 43 is connected to the ^{p + type region 52 via the contact hole 63.} Further, the source metal 43 has an overlapping portion 64 that is pulled out laterally so as to overlap the insulating film 61 under the metal. The overlapping portion 64 faces the guard ring 53 with the lower metal insulating film 61 interposed therebetween. In this embodiment, the overlap portion 64 is provided so as to partially cover the region (guard ring region having a width (G)) in which the guard ring 53 is formed, and the end portion thereof is the guard ring region. It is located inside the outer edge. The overlap portion 64 may cover the entire guard ring region, but the position of the end portion thereof is determined so that the distance (B) in FIG. 6 is 40 μm or more (for example, 45 μm to 180 μm). .. The distance (B) is the lateral length of the source metal 43 on the under-metal insulating film 61 and the SiC epitaxial layer 28. In this embodiment, the distance (B) is the length from the edge of the overlapping portion 64 to the edge of the metal lower insulating film 61. Further, the distance (B) may be twice or more the width (E) of the depletion layer 60.

Further, as described above, the source metal 43 preferably has a laminated structure represented by Ti / TiN / Al—Cu. For example, in this embodiment, the source metal 43 includes a Ti / TiN film 65 (barrier membrane) laminated in order from the SiC epitaxial layer 28 side, and an Al—Cu film 66. In FIG. 4, the Ti / TiN film 65 and the Al—Cu film 66 are not shown.

An n-type region 67 (first conductive type region) in which the SiC surface of the SiC epitaxial layer 28 is exposed is formed on the outside of the metal under-metal insulating film 61 over a distance (A). The n-type region 67 is a part of the SiC epitaxial layer 28 exposed from the opening 68 formed on the outside of the under-metal insulating film 61 (in this embodiment, between the under-metal insulating film 61 and the end insulating film 62). Is. As shown in FIG. 5, the opening 68 is formed linearly along the boundary between the active region 2 and the outer peripheral region 3, for example. The distance (A) of the n-type region 67 is 40 μm or more (for example, 45 μm to 180 μm), but it is preferably 180 μm or less in total with the distance (B). By setting the total of the distance (A) and the distance (B) to 180 μm or less, the chip size of the semiconductor device 1 can be kept at an appropriate size.

The end insulating film 62 is formed so as to cover the dicing region 54 of the SiC epitaxial layer 28. Specifically, the end insulating film 62 extends laterally from the end face 59 of the SiC epitaxial layer 28 beyond the dicing region 54 to an inward region. The width (H) of the end insulating film 62 with respect to the end face 59 is 10 μm to 105 μm (for example, 22 μm) in this embodiment. As a result, the p ^- type region 55 and the p ⁺ -type region 56 (p-type region) are covered with the end insulating film 62.

The passivation film 40 is an example of the insulating material of the present invention together with the insulating film 47, and is made of an organic insulating material. The organic insulating material that can be used is, for example, a polyimide-based material, a polybenzoxazole-based material, an acrylic-based material, or the like. That is, in this embodiment, the passivation film 40 is configured as an organic passivation film. The thickness of the passivation film 40 is, for example, 0.2 μm to 20 μm.

The passivation film 40 is formed so as to cover the insulating film 47. In this embodiment, the passivation film 40 covers almost the entire area of the SiC epitaxial layer 28, except that it does not cover the end of the SiC epitaxial layer 28 (in other words, the passivation film 40 partitions the dicing region 54). It is formed over. Therefore, the passivation film 40 is in contact with the n-type region 67 of the SiC epitaxial layer 28 at the opening 68 of the insulating film 47 over a distance (A) of 40 μm or more.

The passivation film 40 does not cover the end portion of the SiC epitaxial layer 28, but has an overlapping portion 69 that overlaps a part of the end insulating film 62. The overlap portion 69 prevents the SiC surface of the SiC epitaxial layer 28 from being exposed to the outside. The overlapping width (C) between the overlapping portion 69 and the end insulating film 62 is 5 μm or more (for example, 9 μm) in this embodiment. Further, in this embodiment, the overlap portion 69 is formed inwardly separated from the ^{p-type region (p-} type region 55 and p ^{+ type region 56) in a plan view.} As a result, the overlap portion 69 faces the n-type portion of the SiC epitaxial layer 28 with the end insulating film 62 interposed therebetween, and does not face the p-type region.

As described above, according to the semiconductor device 1, as shown in FIGS. 5 and 6, since the distance (A) is 40 μm or more, the organic passivation film 40 and the SiC epitaxial layer 28 (n-type region 67) are connected to each other. A sufficient contact area can be secured. Thereby, the adhesion of the organic passivation film 40 to the SiC epitaxial layer 28 can be improved. In addition, since the distance (B) is 40 μm or more, or more than twice the width (E) of the depletion layer 60, a high temperature, high humidity, high voltage test (for example, 85 ° C., 85% RH, 960 V). It can withstand application conditions for 1000 hours continuously). Making the distance (A) and the distance (B) within the above ranges is a completely new finding in SiC semiconductor devices. In SiC, since the lateral spread of the depletion layer 60 is smaller than that in Si, it has not been necessary to increase the distance (A) and the distance (B) to increase the chip size in the past. This is because the depletion layer 60 is unlikely to reach the chip end face 59 without increasing the chip size, and the increase in the chip size may cause an increase in the on-resistance in units of the chip area. Against this background, the inventors of the present application have found that the resistance to a high temperature, high humidity, and high voltage test can be improved by intentionally setting the distance (A) and the distance (B) to 40 μm or more.

Further, in this embodiment, a p-type region (p ^- type region 55 and p ⁺ type region 56) is formed on the SiC epitaxial layer 28, and the p-type region is further covered with an end insulating film 62. Therefore, when testing the electrical characteristics of the semiconductor device 1 in the state of the wafer 57 before dicing shown in FIG. 7A, the voltage Va applied to the atmosphere between the dicing region 54 and the source metal 43 (the portion exposed from the opening 42) The burden can be lightened.

In the test, for example, the source metal 43 of one semiconductor device 1 is set to 0 V, and the back surface of the wafer 57 is set to 1000 V or more (for example, 1700 V). As a result, the maximum applied voltage (BV) that generates a potential difference of 1000 V or more is applied between the source metal 43 and the wafer 57, and the withstand voltage of each MOSFET is measured. At this time, a part of the dicing regions 54 ^- including the (p type region 55 and ^{p +} -type region 56 other than the portion of) the n-type portion of the wafer 57 is fixed to a potential higher than 1000V, dicing area 54 and the source A potential difference of 1000 V or more is generated between the metal 43 and the metal 43. Even in such a case, according to this embodiment, a p-type region (p ⁻ type region 55 and p ⁺ type region 56) is formed along the dicing region 54, and the dicing region 54 is further formed by the end insulating film 62. It is covered. Therefore, the maximum applied voltage (BV) of 1000 V or more applied between the dicing region 54 and the source metal 43 is relaxed in two steps of ^{the end insulating film 62 and the p-type region (p-} type region 55 and p ^{+ type region 56).} can do. Thereby, the load of the voltage Va applied to the atmosphere between the dicing region 54 and the source metal 43 can be reduced. As a result, the semiconductor device 1 having a yield voltage value (BV) of 1000 V or more can be realized.

Further, by setting the thickness of the under-metal insulating film 61 to 1 μm or more, dielectric breakdown can be prevented even if a voltage of 1000 V or more is applied to the under-metal insulating film 61. If the insulating film 47 is a BPSG, the under-metal insulating film 61 and the end insulating film 62 can be easily flattened by reflow, and the corners of the insulating films 61 and 62 can be rounded (smoothly). can. As a result, the adhesion of the passivation film 40 to the insulating films 61 and 62 can be improved.

Further, since the dicing region 54 is not covered with the passivation film 40, the semiconductor device 1 in the state of the wafer 57b can be easily divided (diced).
8 to 14 are schematic cross-sectional views of the semiconductor device according to the second to eighth embodiments of the present invention, respectively. In FIGS. 8 to 14, the elements corresponding to those in FIG. 6 described above are designated by the same reference numerals.

Next, the other embodiments of the present invention will be mainly described as being different from the semiconductor device 1 of the first embodiment.
In the semiconductor device 72 of FIG. 8, the overlap portion 69 of the passivation film 40 is formed so as to selectively cover ^{the p-type region (p-} type region 55 and p ^{+ type region 56) via the end insulating film 62.} Has been done. As a result, the overlap portion 69 has an overlapping portion with respect to the p-type region.

In the semiconductor device 73 of FIG. 9, the end insulating film 62 is not formed, and instead, the passivation film 40 covers the SiC epitaxial layer 28 up to the end face 59. In this case, the dicing region 54 may be set with an appropriate width (D) from the end face 59. Further, the distance (A) may be defined by the length from the edge of the metal lower insulating film 61 to the end face 59 of the SiC epitaxial layer 28.

The semiconductor device 74 of FIG. 10 has the same configuration as the semiconductor device 73 of FIG. 9 except that the ^p- type region 55 and the p ^{+ type region 56 (p-type region) are formed in the dicing region 54.} ing. In this case, the distance (A) may be defined by the length from the edge of the metal lower insulating film 61 to the p-type region. That is, the distance (A) may be 40 μm or more with respect to the section where the passivation film 40 is in contact with the n-type portion of the SiC epitaxial layer 28.

In the semiconductor device 75 of FIG. 11, at least two openings 68 are formed on the outside of the under-metal insulating film 61 of the insulating film 47. In this embodiment, openings 68 are formed between the lower metal insulating film 61 and the outer insulating film 79, and between the outer insulating film 79 and the end face 59 of the SiC epitaxial layer 28, respectively. The passivation film 40 is in contact with the n-type region 67 of the SiC epitaxial layer 28 over a _{distance (A 1} ) and a distance (A _{2) at each opening 68.} In this case, if the distance of the section in which the passivation film 40 is in contact with the n-type region 67 is 40 μm or more in total of _{the distance (A 1} ) and the distance (A _{2) of the contact section in each of the plurality of n-type regions 67.} good.

The semiconductor device 76 of FIG. 12 has the same configuration as the semiconductor device 73 of FIG. 9 except that the recess 80 is selectively formed in the n-type region 67. In the recess 80, the passivation film 40 is in contact with the n-shaped region 67 on the inner surface (bottom surface and both side surfaces) of the recess 80. In this case, the distance of the section passivation film 40 is in contact with the n-type region 67, the contact distance in the region other than the recess 80 (A _5), the distance of the contact zone in each of the bottom surface and both side surfaces of the recess 80 ( The _{total length including A 3} ) and distance (A ₄ ) may be 40 μm or more.

In the semiconductor device 77 of FIG. 13, the transistor cell 18 is composed of a MOSFET cell having a trench gate structure. In this case, the gate electrode 19 is embedded in the gate trench 39 formed between each of the plurality of transistor cells 18 via the gate insulating film 35.
In the semiconductor device 78 of FIG. 14, a Schottky barrier diode 81 is formed in the active region 2. That is, instead of the source metal 43, a Schottky metal 82 that forms a Schottky junction with the SiC epitaxial layer 28 is provided.

As described above, in each of the semiconductor devices 72 to 78 of the second to eighth embodiments, (1) the distance (A) is 40 μm or more, (2) the distance (B) is 40 μm or more, or It has three characteristics: it is more than twice the width (E) of the depletion layer 60, and (3) the end of the SiC epitaxial layer 28 is covered with an insulator (end insulating film 62 or passivation film 40). Have. Therefore, also in the second to eighth embodiments, as in the first embodiment, it is possible to prevent discharge during the electrical property test carried out in the wafer state, and the SiC semiconductor can withstand the high temperature, high humidity and high voltage test. Equipment can be provided.

Although the embodiments of the present invention have been described above, the present invention can also be implemented in other embodiments.
For example, the transistor cell 18 may be an IGBT cell having a planar gate structure or a trench gate structure. In this case, in FIGS. 4 and 13, ^{the p +} type SiC substrate 27 may be used ^{instead of the n +} type SiC substrate 27. In addition, various semiconductor element structures may be formed in the active region 2.

Further, the surface electrodes such as the source metal 43 and the Schottky metal 82 do not have to be made of metal, and may be semiconductor electrodes such as polysilicon.
Further, the built-in resistance 21 does not need to be embedded in the interlayer film 36 below the gate metal 44. For example, a polysilicon wiring for connecting the gate metal 44 and the gate finger 5 is built-in resistance on the surface of the interlayer film 36. May be formed as.

Further, as the material of the built-in resistance 21, instead of polysilicon, a material having a resistance value equal to or larger than that of the gate metal 44 and the gate finger 5 (for example, Al (aluminum), AlCu (aluminum-copper alloy), etc. Metal wiring such as Cu (copper)) may be used. Even if the built-in resistance 21 is made of metal, the distance between the gate metal 44 and the gate finger 5 can be increased, so that the total resistance value of the gate electrode 19 and the built-in resistance 21 can be increased. can.

Further, the built-in resistance 21 does not have to be formed below the gate metal 44, and may be formed below the gate finger 5, for example.
Further, the built-in resistance 21 may be a linear shape along a part of the peripheral edge portion 24 of the gate metal 44, or may be an annular shape along the entire circumference of the peripheral edge portion 24 of the gate metal 44.
Further, a configuration in which the conductive type of each semiconductor portion of the above-mentioned semiconductor device 1 is inverted may be adopted. For example, in the semiconductor device 1, the p-type portion may be n-type and the n-type portion may be p-type.

In addition, various design changes can be made within the scope of the matters described in the claims.
In addition, the following features can be extracted from the above-described embodiment.
A first conductive type SiC layer, an electrode selectively formed on the SiC layer, and an insulator formed on the SiC layer and reaching a dicing region set at an end portion of the SiC layer. The insulating material includes a sub-electrode insulating film arranged so as to extend from below the electrode toward the dicing region and an organic insulating layer arranged so as to cover the sub-electrode insulating film. The distance (A) of the section where the organic insulating layer is in contact with the SiC layer is 40 μm or more, and is lateral to the end of the electrode on the insulating film under the electrode and the portion where the organic insulating layer is in contact with the SiC layer. A semiconductor device (item 1) in which the distance (B) in the direction is 40 μm or more.

According to this configuration, since the dicing region is covered with an insulating material, it is possible to reduce the load of the voltage applied to the atmosphere between the dicing region and the electrodes when testing the electrical characteristics of the semiconductor device in the wafer state. .. In other words, the voltage applied between the dicing region and the electrodes can be shared between the atmosphere and the insulator, so that discharge in the atmosphere can be prevented.

Further, since the distance (A) is 40 μm or more, a sufficient contact area between the organic insulating layer and the SiC layer can be sufficiently secured, so that the adhesion of the organic insulating layer to the SiC layer can be improved. In addition, since the distance (B) is 40 μm or more, it can withstand a high temperature, high humidity, and high voltage test. Making the distance (A) and the distance (B) within the above ranges is a completely new finding in SiC semiconductor devices. In SiC, since the lateral spread of the depletion layer is smaller than that in Si, it has not been necessary to increase the distance (A) and the distance (B) to increase the chip size in the past. This is because it is unlikely that the depletion layer will reach the end face of the chip without increasing the chip size, and the increase in the chip size may cause an increase in the on-resistance in units of the chip area. Against this background, the inventors of the present application have found that the resistance to a high temperature, high humidity, and high voltage test can be improved by intentionally setting the distance (A) and the distance (B) to 40 μm or more.

When the semiconductor device further includes a second conductive type region formed in the dicing region, the distance (A) is 40 μm with respect to a section in which the organic insulating layer is in contact with the first conductive type region of the SiC layer. It may be the above (item 2).
According to this configuration, the voltage applied between the dicing region and the electrode can be distributed to the second conductive type region as well. Therefore, it is possible to more effectively prevent the discharge in the atmosphere.

The organic insulating layer may be formed so as to cover the dicing region and may be in contact with the second conductive type region in the dicing region (Item 3).
An end portion in which the organic insulating layer does not cover the dicing region, and the insulating material is formed of the same layer as the subelectrode insulating film, covers the dicing region, and partially overlaps the organic insulating layer. When the insulating film is further included, the overlapping width (C) between the organic insulating layer and the end insulating film may be 5 μm or more (Item 4).

According to this configuration, since the dicing region is not covered with the organic insulating layer, the semiconductor device in the wafer state can be easily divided (diced). Even in this case, since the dicing region is covered with the end insulating film constituting the insulating material, the above-mentioned discharge prevention effect can be sufficiently realized.
When the insulating material is made of the same layer as the sub-electrode insulating film and further includes an end insulating film covering the dicing region, the organic insulating layer is the second conductive film via the end insulating film. The end insulating film is overlapped so as to selectively cover the mold region, and the overlapping width (C) between the organic insulating layer and the end insulating film may be 5 μm or more (Item 5).

The end insulating film may have the same thickness as the subelectrode insulating film (Item 6).
According to this configuration, the end insulating film can be manufactured in the same process as the subelectrode insulating film, so that the manufacturing process can be simplified.
The distance (A) may be 45 μm to 180 μm (Item 7), and the distance (B) may be 45 μm to 180 μm (Item 8). Further, the total of the distance (A) and the distance (B) may be 180 μm or less (Item 9).

By setting the distance (A) and the distance (B) in the above ranges, the chip size of the semiconductor device can be kept at an appropriate size. Further, when the distance (A) and the distance (B) are in the above ranges, an atmospheric discharge is likely to occur, so it is useful to cover the dicing region with an insulator.
The yield voltage value (BV) of the semiconductor device may be 1000 V or more (Item 10).

Since atmospheric discharge is likely to occur when the yield voltage value (BV) is 1000 V or higher, it is useful to cover the dicing region with an insulator.
The impurity concentration of the first conductive type of the SiC layer may be 1 × 10 ¹⁶ cm ^-3 or less, and the thickness of the SiC layer may be 5 μm or more (Item 11).
When the semiconductor device further includes a second conductive type terminal structure composed of an impurity region formed outside the electrode in the SiC layer, the width (F) of the second conductive type region is the dicing. It may be greater than or equal to the difference between the width (D) of the region and twice the width (E) of the depletion layer extending from the terminal structure (Item 12).

The electrode may have a laminated structure represented by Ti / TiN / Al—Cu (Item 13).
By using Al-Cu, the resistance to humidity can be further improved.
The sub-electrode insulating film may be made of a SiO ₂ film having a thickness of 1 μm or more (Item 14). In this case, the SiO ₂ film may contain phosphorus (P) and boron (B) (items 15 and 16).

_{If a SiO 2} film having a thickness of 1 μm or more is used, dielectric breakdown can be prevented even if a voltage of 1000 V or more is applied to the subelectrode insulating film. Further, if phosphorus (P) and boron (B) are contained, the sub-electrode insulating film can be easily flattened by reflow. In addition, the corners of the insulating film under the electrode can be rounded.
The sub-electrode insulating film may be made of a SiN film having a thickness of 1 μm or more (Item 17).

If a SiN film having a thickness of 1 μm or more is used, dielectric breakdown can be prevented even if a voltage of 1000 V or more is applied to the subelectrode insulating film.
The organic insulating layer may be made of a polyimide-based material, a polybenzoxazole-based material, an acrylic-based material, or the like (Items 18, 19, 20).
A MOSFET is formed in the SiC layer as a semiconductor element structure, and the electrode may include a source electrode electrically connected to the source of the MOSFET (Item 21). In this case, the MOSFET may have a planar gate structure (Item 22) or a trench gate structure (Item 23).

Further, a Schottky barrier diode is formed in the SiC layer as a semiconductor element structure, and the electrode may include a Schottky electrode forming a part of the Schottky barrier diode (Item 24).
Further, an IGBT is formed in the SiC layer as a semiconductor element structure, and the electrode may include a source electrode electrically connected to the source of the IGBT (Item 25).

When the organic insulating layer is in contact with the SiC layer in a plurality of regions, the distance (A) may be 40 μm or more in total of the distances of the contact sections in each of the plurality of regions (Item 26). ..
When the semiconductor device is selectively formed in the SiC layer and further includes a recess filled with the organic insulating layer, the distance (A) includes a contact section of the organic insulating layer on the inner surface of the recess. The total length may be 40 μm or more (Item 27).

Further, the semiconductor device extracted from the above-described embodiment includes a first conductive type SiC layer, an electrode selectively formed on the SiC layer, and an end of the SiC layer formed on the SiC layer. The insulator includes an insulator that reaches the dicing region set in the portion and a second conductive type terminal structure composed of an impurity region formed outside the electrode in the SiC layer, and the insulator is said to be said. The sub-electrode insulating film arranged so as to extend from below the electrode toward the dicing region and the organic insulating layer arranged so as to cover the sub-electrode insulating film are included, and the organic insulating layer is in contact with the SiC layer. The distance (A) of the section is 40 μm or more, and the lateral distance (B) between the end of the electrode on the subelectrode insulating film and the portion where the organic insulating layer is in contact with the SiC layer is the above. It may be at least twice the width (E) of the depleted layer extending from the terminal structure (Item 28).

According to this configuration, since the dicing region is covered with an insulating material, the applied voltage can be relaxed by the insulating material when testing the electrical characteristics of the semiconductor device in the wafer state. This makes it possible to reduce the load of the voltage applied to the atmosphere between the dicing region and the electrodes. In other words, the voltage applied between the dicing region and the electrodes can be shared between the atmosphere and the insulator, so that discharge in the atmosphere can be prevented.

Further, since the distance (A) is 40 μm or more and the distance (B) is more than twice the width (E) of the depletion layer extending from the terminal structure, it can withstand a high temperature, high humidity and high voltage test.

1 Semiconductor device 2 Active region 18 Transistor cell 19 Gate electrode 27 SiC substrate 28 SiC epitaxial layer 29 p ^- type body region 30 n ⁺ type source region 31 p ⁺ type body contact region 32 channel region 35 gate insulating film 36 interlayer film 39 gate Trench 40 Passion film 43 Source metal 44 Gate metal 47 Insulation film 51 p ^- type area 52 p ⁺ type area 53 Guard ring 54 Dying area 55 p ^- type area 56 p ⁺ type area 57 Wafer 58 Dying line 59 End face 60 Depleted layer 61 Insulation film under metal 62 End insulation film 63 Contact hole 64 Overlap part 65 Ti / TiN film 66 Al-Cu film 67 n-type region 68 Opening 69 Overlap part 72 Semiconductor device 73 Semiconductor device 74 Semiconductor device 75 Semiconductor device 76 Semiconductor Equipment 77 Semiconductor equipment 78 Semiconductor equipment 79 Semiconductor equipment 80 Recess 81 Shotkey barrier diode 82 Shotkey metal

Claims (21)

A first conductive type SiC layer having an active region in which a plurality of transistor elements are formed on the surface and an outer peripheral region which is a peripheral portion thereof.
An electrode selectively formed on the SiC layer and electrically connected to the transistor element,
It is provided with an insulator formed on the SiC layer so as to extend toward the dicing region at the end of the SiC layer.
The insulator includes an insulating film formed below the electrode at a distance from the end face of the SiC layer toward the electrode side, and a surface insulating film covering the insulating film and a part of the electrode.
The surface insulating film is formed so as to cover the SiC layer from the end portion of the insulating film on the dicing region side to the end surface of the SiC layer.
The surface insulating film has a first region formed so as to overlap the insulating film, and the surface insulating film comes into contact with the SiC layer outside the first region, and the SiC is formed from an end portion of the first region. A semiconductor device having a second region formed so as to extend toward the end face of the layer. The semiconductor device according to claim 1, further comprising a second insulator formed on the SiC layer from the insulator to the end face side of the SiC layer and not reaching the end face of the SiC layer. The semiconductor device according to claim 1 or 2, wherein the length (A) of the portion of the outer peripheral region where the surface insulating film is in contact with the SiC layer is 40 μm or more. The semiconductor device according to any one of claims 1 to 3, wherein the SiC layer includes a second conductive type region formed in the first conductive type region of the dicing region. Further comprising a terminal structure having a second conductive type impurity region formed on the outside of the electrode of the SiC layer.
The fourth aspect of the present invention, wherein the width (F) of the second conductive type region is equal to or more than a difference between the width (D) of the dicing region and twice the width (E) of the depletion layer extending from the terminal structure. Semiconductor device. The distance (A) from the end on the dicing region side to the insulating film is 40 μm or more.
The lateral distance (B) between the end of the electrode and the portion where the surface insulating film comes into contact with the SiC layer is 40 μm or more.
The semiconductor device according to claim 1, wherein the total of the distance (A) and the distance (B) is 180 μm or less. The semiconductor device according to any one of claims 1 to 6, wherein the yield voltage value is 1000 V or more. The impurity concentration of the first conductive type of the SiC layer is 1 × 10 ¹⁶ cm ^-3 or less.
The semiconductor device according to any one of claims 1 to 7, wherein the thickness of the SiC layer is 5 μm or more. The semiconductor device according to any one of claims 1 to 8, wherein the electrode has a laminated structure represented by Ti / TiN / Al—Cu. The semiconductor device according to any one of claims 1 to 9, _{wherein the insulating film is composed of a SiO 2} film having a thickness of 1 μm or more. The semiconductor device according to any one of claims 1 to 9, wherein the insulating film is made of a SiN film having a thickness of 1 μm or more. The semiconductor device according to any one of claims 1 to 11, wherein the surface insulating film is made of a polyimide-based material. A MOSFET is formed as the transistor element, and
The semiconductor device according to any one of claims 1 to 12, wherein the electrode includes a source electrode electrically connected to the source of the MOSFET. The semiconductor device according to claim 13, wherein the MOSFET has a planar gate structure. An IGBT is formed as the transistor element.
The semiconductor device according to any one of claims 1 to 12, wherein the electrode includes an emitter electrode electrically connected to the emitter of the IGBT. The semiconductor device according to any one of claims 1 to 15, wherein the surface insulating film includes an organic insulating film. The transistor element includes a switching element having a gate electrode.
The semiconductor device according to any one of claims 1 to 16, wherein a resistance element electrically connected to the gate electrode is formed between the insulating film and the surface insulating film. The transistor element is formed on the first portion of the second conductive type formed on the surface portion of the SiC layer and the second conductive portion formed on the surface portion of the first portion and having a higher impurity concentration than the first portion. Has a second part of the mold and
A contact hole for exposing the second portion of the transistor element is formed in the insulating film.
The semiconductor device according to any one of claims 1 to 17, wherein the electrode and the second portion of the transistor element are electrically connected via the contact hole. The semiconductor device according to claims 1 to 18, wherein the surface insulating film has an end face flush with the end face of the SiC layer. The semiconductor device according to any one of claims 1 to 19, wherein the surface portion of the SiC layer in contact with the second region of the surface insulating film includes a first conductive type region. The insulating film has an exposed portion exposed from the electrode on the end face side of the SiC layer with respect to the end portion of the electrode.
The surface insulating film has a portion in contact with the exposed portion of the insulating film between an end portion of the electrode and a portion in which the surface insulating film is in contact with the SiC layer. Item 2. The semiconductor device according to any one of Items 1 to 20.

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