JP7472356B2 - Semiconductor Device - Google Patents

Description

The present invention relates to a SiC semiconductor device.

Various proposals have been made in the past to prevent problems from occurring when testing the characteristics of semiconductor devices. For example, Patent Document 1 proposes a measure to prevent discharge from occurring in the atmosphere during electrical characteristic testing. Specifically, Patent Document 1 discloses a method for manufacturing a semiconductor device, including the steps of forming a base region and an emitter region in a semiconductor wafer, patterning the base electrode and the emitter electrode, and then depositing and patterning a polyimide film on the surface to cover the dicing region and other regions excluding the electrode bonding portion.

Japanese Patent Application Laid-Open No. 60-50937 Japanese Patent Application Laid-Open No. 54-45570 JP 2011-243837 A JP 2001-176876 A Republished Patent Publication No. WO2009/101668

Now, high temperature, high humidity, high voltage testing is beginning to be adopted as a method of testing semiconductor devices. In this test, the semiconductor device is exposed to conditions of, for example, 85°C, 85% RH, and 960 V applied for 1000 consecutive hours (about 40 days). Conventionally, measures have been taken to withstand the above temperature, humidity, and voltage conditions individually, but no measures have yet been proposed that can meet all three of these conditions.

The object of the present invention is to provide a SiC semiconductor device that can prevent discharge during electrical characteristic testing performed in the wafer state and can withstand high temperature, high humidity, and high voltage testing.

A semiconductor device according to one aspect of the present invention includes a first conductive type SiC layer having an active region on the surface of which a plurality of transistor elements are formed, and an outer peripheral region which is the periphery of the active region; an electrode selectively formed on the SiC layer and electrically connected to the transistor element; and an insulator formed on the SiC layer so as to extend toward a dicing region at an end of the SiC layer, the insulator including an insulating film formed below the electrode and a surface insulating film covering the insulating film and a part of the electrode, the surface insulating film being formed so as to reach the dicing region, the surface insulating film having a first region formed so as to overlap the insulating film, and a second region formed so that the surface insulating film contacts the SiC layer outside the first region and extends toward the end of the SiC layer.

FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is an enlarged view of the area surrounded by the dashed line II in FIG. FIG. 3 is an enlarged view of the area surrounded by the two-dot chain line III in FIG. FIG. 4 is a cross-sectional view of the semiconductor device taken along line IV-IV in FIG. FIG. 5 is an enlarged view of the area surrounded by the two-dot chain line V in FIG. FIG. 6 is a cross-sectional view of the semiconductor device taken along line VI-VI in FIG. FIG. 7A is a cross-sectional view for explaining a process related to cutting the wafer. FIG. 7B is a cross-sectional view showing the state of the wafer after cutting. FIG. 8 is a schematic cross-sectional view of a semiconductor device according to a second embodiment of the present invention. FIG. 9 is a schematic cross-sectional view of a semiconductor device according to a third embodiment of the present invention. FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention. FIG. 11 is a schematic cross-sectional view of a semiconductor device according to a fifth embodiment of the present invention. FIG. 12 is a schematic cross-sectional view of a semiconductor device according to a sixth embodiment of the present invention. FIG. 13 is a schematic cross-sectional view of a semiconductor device according to the seventh embodiment of the present invention. FIG. 14 is a schematic cross-sectional view of a semiconductor device according to an eighth embodiment of the present invention.

The following describes in detail an embodiment of the present invention with reference to the attached drawings.

Figure 1 is a schematic plan view of a semiconductor device 1 according to a first embodiment of the present invention. Note that in Figure 1, for clarity, some elements that are not exposed on the top surface of the semiconductor device 1 in an actual plan view are shown by solid lines.

The semiconductor device 1 is a semiconductor device that uses SiC, and is formed, for example, in the shape of a rectangular chip when viewed from the normal direction of its outermost surface (hereinafter simply referred to as "planar view").

The semiconductor device 1 has an active region 2 and a peripheral region 3 surrounding the active region 2. In this embodiment, the active region 2 is formed in an inner region of the semiconductor device 1 in a generally rectangular shape in plan view, but the shape is not particularly limited.

In the active region 2, a gate metal 44, a source metal 43 as an example of an electrode of the present invention, and a gate finger 5 are formed. A passivation film 40 is formed on the top surface of the semiconductor device 1 so as to cover these. In the passivation film 40, openings 41 and 42 are formed to expose a part of the gate metal 44 and a part of the source metal 43 as the gate pad 4 and the source pad 6, respectively. Meanwhile, the gate finger 5 is entirely covered by the passivation film 40. Note that in FIG. 1, the gate finger 5 is shown by a solid line and hatched for clarity.

The gate metal 44, gate finger 5, and source metal 43 are made of metal wiring such as Al (aluminum), AlCu (aluminum-copper alloy), Cu (copper), etc. As described in the explanation of FIG. 6, they preferably have a layered structure represented by Ti/TiN/Al-Cu.

By forming the gate finger 5 with metal wiring with lower resistance than polysilicon, it is possible to supply gate current in a short time even to the transistor cell 18 (see FIG. 2) located at a relatively long distance from the gate metal 44. In addition, since Al has good workability (easy to process), the process of forming these wirings can be simplified. On the other hand, AlCu can improve the power cycle resistance and humidity resistance of the semiconductor device 1 compared to when Al is used, and can also improve the bonding strength of the bonding wire with respect to the gate pad 4. When Cu is used, there is an advantage that the resistivity can be reduced more than in the cases of Al and AlCu.

The gate metal 44 is selectively formed in a portion of the periphery of the active region 2 (near the boundary with the outer peripheral region 3). The gate fingers 5 extend from the position where the gate pad 4 is formed, in a direction along the periphery of the active region 2 and in a direction toward the inside of the active region 2. As a result, cell regions 7 and 45 are formed in the active region 2 in a portion partitioned by multiple gate fingers 5 extending in different directions with the gate metal 44 in between, and in the outer region of the gate fingers 5.

More specifically, in this embodiment, the gate metal 44 is formed in a rectangular shape in a plan view, and is selectively disposed in the center of one side 8 of the active region 2. Note that the sides other than the side 8 of the active region 2 (the side on which the gate metal 44 is disposed) are the side 9 opposite the side 8, and sides 10 and 11 continuing to both ends of these sides 8 and 9, respectively.

The gate finger 5 includes a pad periphery 12 that surrounds the gate metal 44 with a gap therebetween, and a first finger 13 and a second finger 14 that extend from the pad periphery 12 in a direction along the side 8 of the active region 2 and in a direction perpendicular to the side 8, respectively.

The pad peripheral portion 12 is formed in a rectangular ring shape in a plan view along the periphery of the gate metal 44.

The first finger 13 is formed as a pair along side 8 in the direction toward side 10 and the opposite side 11 relative to the pad peripheral portion 12.

The second finger 14 includes a linear main portion 15 that crosses the active area 2 up to the side 9 in a direction perpendicular to the first finger 13, and a number of branch portions 16 that are integrally connected to the main portion 15 and extend from the connection point along the first finger 13. In this embodiment, the branch portions 16 are connected to two points, the tip portion of the main portion 15 and the middle portion of the main portion 15, to form a total of two pairs, but this number is not particularly limited.

Thus, in the active region 2, cell regions 7, 45 are defined by the first finger 13 and the second finger 14 (main portion 15 and branch portion 16). In this embodiment, a total of four inner cell regions 7 are formed, one at each corner of the intersection formed by the main portion 15 of the second finger 14 and the central branch portion 16. In addition, an annular outer cell region 45 is formed along the periphery of the active region 2 between the periphery of the active region 2 and the gate finger 5.

The source metal 43 is formed to cover almost the entire inner cell region 7 and the outer cell region 45. A total of four openings 42 are formed in the passivation film 40 so that one source pad 6 is placed in each inner cell region 7.

In addition, a recess 17 corresponding to the shape of the gate metal 44 is formed in the source metal 43. The recess 17 is a depression formed to avoid the gate metal 44, which is set back toward the inside of the active region 2 relative to the first finger 14.

Figure 2 is an enlarged view of the area surrounded by dashed line II in Figure 1. In other words, it is an enlarged view of the gate pad 4 of the semiconductor device 1 and the area nearby. Note that in Figure 2, for clarity, some of the elements that are not exposed on the top surface of the semiconductor device 1 in an actual plan view are shown by solid lines.

As shown in FIG. 2, a plurality of transistor cells 18 are arranged in the inner cell region 7 and the outer cell region 45 defined by the gate fingers 5 (pad peripheral portion 12, first finger 13, and second finger 14).

In this embodiment, the multiple transistor cells 18 are arranged in a matrix in plan view in each of the inner cell region 7 and the outer cell region 45. In the vicinity of the gate finger 5, the multiple transistor cells 18 are aligned to match the shape of the gate finger 5. For example, the multiple transistor cells 18 are aligned in a curved manner to match the shape of the corners of the pad peripheral portion 12, and are aligned in a straight line to match the shape of the main portion 15 of the linear second finger 14. The source metal 43 is formed to cover the multiple transistor cells 18.

2, for clarity, only a portion of the multiple transistor cells 18 covered with the source metal 43 is shown. The arrangement of the multiple transistor cells 18 is not limited to a matrix, and may be, for example, a stripe or staggered pattern. The planar shape of each transistor cell 18 is not limited to a square, and may be, for example, a circle, a triangle, a hexagon, etc.

A gate electrode 19 is formed between adjacent transistor cells 18. In the inner cell region 7 and the outer cell region 45, the gate electrode 19 is disposed between each of the matrix-shaped transistor cells 18, and is formed in a lattice shape in plan view as a whole. Meanwhile, the gate electrode 19 is formed not only in the inner cell region 7 and the outer cell region 45, but also in the region where the gate finger 5 is disposed, and the lower portion of the gate finger 5 is in contact with the gate finger 5.

In this embodiment, a part of the gate electrode 19 is formed in the region below the first finger 13 and the second finger 14, and faces the first finger 13 and the second finger 14 as a contact part. In FIG. 2, for clarity, the part of the gate electrode 19 formed in the region below is represented by a hatched region. As a result, the gate electrodes 19 of the adjacent inner cell regions 7 are continuous through the gate electrode 19 crossing the second finger 14 below. The continuous form of the gate electrode 19 is also the same between the inner cell region 7 and the outer cell region 45 adjacent to the gate metal 44. In other words, the gate electrodes 19 in these regions are continuous through the gate electrode 19 crossing the first finger 13 below.

The first finger 13 and the second finger 14 are each connected to a gate electrode 19 disposed in the region below them by a gate contact 20. The gate contact 20 is formed linearly along the longitudinal direction of each of the first finger 13 and the second finger 14 at the center of the finger spaced apart from each side edge.

In addition, in this embodiment, multiple built-in resistors 21 are arranged below the gate metal 44. It is preferable to provide symmetry in the arrangement of the multiple built-in resistors 21 by arranging the multiple built-in resistors 21 at positions that are approximately equidistant from each other from the center of gravity of the planar shape of the gate metal 44. In this embodiment, the multiple built-in resistors 21 are arranged one at each corner of the gate metal 44 that is equidistant from the center of gravity G of the gate metal 44 that is rectangular in plan view. This provides symmetry to the four built-in resistors 21.

Various such symmetrical patterns are possible. For example, two built-in resistors 21 may be arranged at each of two diagonally opposite corners of the gate metal 44, or may be arranged facing each other on each of two opposite sides of the gate metal 44. For example, when the gate metal 44 is circular in plan view, two built-in resistors 21 may be arranged at each of both ends of the diameter of the gate metal 44, and when the gate metal 44 is triangular in plan view, three built-in resistors 21 may be arranged at each of the three corners of the gate metal 44.

Each built-in resistor 21 is formed across the annular gap region 26 between the gate metal 44 and the gate finger 5 (pad peripheral portion 12), straddling them. This means that the built-in resistor 21 faces each of the gate metal 44 and the gate finger 5. The gate metal 44 and the gate finger 5 (pad peripheral portion 12) are each connected to the built-in resistor 21 located in the region below them by a pad-side contact 22 and a cell-side contact 23.

In this embodiment, the four built-in resistors 21 extend from below the peripheral portions 24 of the two opposing sides of the gate metal 44 in an outward direction perpendicular to the sides to below the pad peripheral portion 12. Each built-in resistor 21 is formed in a rectangular shape in a plan view, and has a size of, for example, 200 μm square or less (200 μm × 200 μm or less). In practice, if the size of each built-in resistor 21 is 200 μm square or less, the area of the region on the SiC epitaxial layer 28 (see FIG. 4) that is sacrificed for the built-in resistors 21 can be reduced, thereby saving space.

The pad side contact 22 and the cell side contact 23 are formed in parallel straight lines along the edges of the gate metal 44 and the pad peripheral portion 12, respectively.

The built-in resistor 21 is placed below the peripheral portion 24 avoiding the center of the gate metal 44, and the area above the area where the built-in resistor 21 is placed is covered with a passivation film 40, thereby providing a gate pad 4 as a wire area surrounded by the built-in resistor 21 in the center of the gate metal 44. The gate pad 4 is the area to which the bonding wire is connected.

That is, in this embodiment, each corner of the gate metal 44 where the built-in resistor 21 is arranged is selectively covered with the passivation film 40, and the other parts of the gate metal 44 are exposed from the openings 41. As a result, a gate pad 4 having a rectangular shape in plan view with each corner recessed inward is exposed on the top surface of the semiconductor device 1. In this way, by covering the area above the area where the built-in resistor 21 is arranged with the passivation film 40, it is possible to prevent the bonding wire from being erroneously joined to the part of the gate metal 44 that overlaps with the built-in resistor 21 when the bonding wire is joined. As a result, it is possible to prevent the built-in resistor 21 from being damaged or destroyed by impact such as ultrasonic waves when the bonding wire is joined.

Figure 3 is an enlarged view of the area surrounded by the two-dot chain line III in Figure 2. Figure 4 is a cross-sectional view of the semiconductor device 1 cut along the cutting line IV-IV in Figure 3. Note that in Figures 3 and 4, for clarity, the scale of each component may differ from that in Figures 1 and 2, and the scale of each component may also differ between Figures 3 and 4. Also, in Figures 3 and 4, for clarity, some of the elements that are not exposed on the top surface of the semiconductor device 1 in an actual plan view are shown by solid lines.

Next, a more detailed configuration of the built-in resistor 21 and its surrounding area will be described along with the cross-sectional structure of the semiconductor device 1.

The semiconductor device 1 includes a SiC substrate 27 and a SiC epitaxial layer 28. The SiC epitaxial layer 28 is laminated on the SiC substrate 27, and this laminated structure is shown as an example of a SiC layer of the present invention.

The SiC substrate 27 and the SiC epitaxial layer 28 are n ⁺ type and n ^- type SiC, respectively. The impurity concentration of the ^{n +} type SiC substrate 27 is, for example, 1×10 ¹⁷ cm ^-3 to 1×10 ²¹ cm ^-3 . On the other hand, the impurity concentration of the n ^- type SiC epitaxial layer 28 is, for example, 1×10 ¹⁴ cm ^-3 to 1×10 ¹⁶ cm ^-3 . In addition, examples of n type impurities that can be used include N (nitrogen), P (phosphorus), As (arsenic), etc. (the same applies below).

The thickness of the SiC substrate 27 is, for example, 50 μm to 1000 μm, and the thickness of the SiC epitaxial layer 28 is, for example, 5 μm or more (specifically, 5 μm to 100 μm).

In the inner cell region 7, a plurality of transistor cells 18 are formed on a surface portion of the SiC epitaxial layer 28. The plurality of transistor cells 18 include a p ^- type body region 29, an n ⁺ type source region 30 selectively formed in an inner region spaced apart from the periphery of the p ^- type body region 29, and a p ⁺ type body contact region 31 selectively formed in an inner region spaced apart from the periphery of the n ⁺ type source region 30. The n ^- type portion of the SiC epitaxial layer 28 serves as a common drain region for the plurality of transistor cells 18.

3, in a plan view, except for the transistor cells 18 along the pad peripheral portion 12 (gate fingers 5), an n ⁺ type source region 30 is formed so as to surround a p ⁺ type body contact region 31, and further, a ^p- type body region 29 is formed so as to surround the n ⁺ type source region 30. In the ^p- type body region 29, the annular region surrounding the n ⁺ type source region 30 is a channel region 32 in which a channel is formed when the semiconductor device 1 is turned on.

On the other hand, in the transistor cells 18 along the pad periphery 12 (gate fingers 5), ap ⁻ type body region 29 and p ⁺ type body contact region 31 are electrically connected to ap ⁻ type region 34 and p ⁺ type region 33, respectively, which will be described later.

The impurity concentration of the p ^- type body region 29 is, for example, 1× ¹⁰¹⁴ cm ^-3 to 1× ¹⁰¹⁹ cm ^-3 , the impurity concentration of the n ⁺ type source region 30 is, for example, 1× ¹⁰¹⁷ cm ^-3 to 1× ¹⁰²¹ cm ^-3 , and the impurity concentration of the p ⁺ type body contact region 31 is, for example, 1× ¹⁰¹⁹ cm ^-3 to 1× ¹⁰²¹ cm ^-3 .

To form these regions 29-31, for example, p ^{-type body region 29 is formed by ion implantation into the surface portion of SiC epitaxial layer 28. Then, n-type impurities and p-type impurities are ion-implanted in sequence into the surface portion of p- type} body region 29 to form n ⁺ type source region 30 and p ⁺ type body contact region 31. This forms transistor cell 18 made up of regions 29-31. For example, B (boron), Al (aluminum), etc. can be used as the p-type impurity (hereinafter the same).

In the active region 2, in a region other than the inner cell region 7 and the outer cell region 45, specifically, in the region below the gate metal 44, the gate finger 5 and the gap region 26, a p ^- type region 34 is formed in the surface portion of the SiC epitaxial layer 28. A p ⁺ type region 33 is formed in the surface portion of the p ^- type region 34.

The p ⁺ type region 33 is formed over almost the entire region below the gate metal 44, etc., so that the p ^- type portion of the p ^- type region 34 is selectively exposed to the SiC surface in the region facing the built-in resistor 21 of the SiC epitaxial layer 28, and the p ⁺ type portion of the p + type region 33 is selectively exposed to the SiC surface in the other region. That is, the gate metal 44 and the gate finger 5 face the p ^- type portion in the region where the built-in resistor 21 is arranged, but face the p ⁺ type portion in most other regions. The p ⁺ type region 33 and the p ^- type region 34 are formed to extend below the source metal 43, and are integrally connected to the p ⁺ type body contact region 31 and the p ^- type body region 29 below the source metal 43 (in this embodiment, the portion outside the source pad 6). 3, the p ⁺ type body contact region 31 and the p ⁺ type region 33 of the transistor cell 18 along the pad peripheral portion 12 (gate finger 5) are shown by hatched regions. In practice, the p ⁺ type body contact region 31 is fixed to the ground potential together with the source metal 43, and this stabilizes the p ⁺ type region 33 at 0 V. For this reason, it is preferable to have most of the gate metal 44 and the gate finger 5 facing the p ⁺ type region 33, as in this embodiment.

P ⁺ type region 33 and p ⁻ type region 34 are formed in the same process as p ⁺ type body contact region 31 and p ⁻ type body region 29, respectively, and also have the same impurity concentration and depth.

A gate insulating film 35 is formed on the surface of the SiC epitaxial layer 28. The gate insulating film 35 is made of an insulating material such as silicon oxide and has a thickness of, for example, 0.001 μm to 1 μm. The gate insulating film 35 is a common insulating film for insulating the gate electrode 19 and the built-in resistor 21 from the SiC epitaxial layer 28.

A gate electrode 19 and an internal resistor 21 are formed on the gate insulating film 35. The gate electrode 19 is formed to face the channel region 32 of each transistor cell 18 with the gate insulating film 35 in between. On the other hand, the internal resistor 21 is formed to face the exposed p ⁻ -type portion of the p ⁻ -type region 34 with the gate insulating film 35 in between.

The gate electrode 19 and the built-in resistor 21 may both be made of p-type polysilicon and formed in the same process. In this embodiment, the gate electrode 19 and the built-in resistor 21 contain B (boron) as a p-type impurity. B (boron)-containing polysilicon has a higher specific resistance than phosphorus (P)-containing polysilicon that is commonly used in Si semiconductor devices. Therefore, the boron-containing polysilicon (built-in resistor 21) requires a smaller area than the phosphorus-containing polysilicon even when achieving the same resistance value. Therefore, the area occupied by the built-in resistor 21 on the SiC epitaxial layer 28 can be reduced, allowing for more efficient use of space.

The concentration of the p-type impurity contained in the polysilicon can be appropriately changed according to the design resistance value of each of the gate electrode 19 and the built-in resistor 21. In this embodiment, the concentration is set so that the sheet resistance of the built-in resistor 21 is 10 Ω/□ or more. In practice, if the sheet resistance of the built-in resistor 21 is 10 Ω/□ or more, the resistance value of the entire built-in resistor 21 can be easily made larger than the variation in the resistance value between multiple semiconductor devices 1 without increasing the area of the built-in resistor 21. For example, when the variation in the resistance value is 0.1 Ω to 20 Ω, the resistance value of the built-in resistor 21 can be set to 2 Ω to 40 Ω with a small area. As a result, the area of the region on the SiC epitaxial layer 28 that is sacrificed for the built-in resistor 21 can be reduced, so that the impact on the layout of other elements is reduced. In addition, in this case, the resistance value obtained by summing the resistance value of the gate electrode 19 and the resistance value of the built-in resistor 21 is preferably 4 Ω to 50 Ω.

The thickness of the gate electrode 19 and the built-in resistor 21 is preferably 2 μm or less. By making the thickness of the built-in resistor 21 2 μm or less, the resistance value of the entire built-in resistor 21 can be easily made larger than the variation in resistance value between multiple semiconductor devices 1. Conversely, if the built-in resistor 21 is too thick, its resistance value becomes too low, which is not preferable.

An insulating film 47 is further formed on the SiC epitaxial layer 28. The insulating film 47 is made of an insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiN) and has a thickness of, for example, 1 μm to 5 μm. In particular, it is preferable to use a boron phosphorus silicon glass (BPSG) film having a thickness of 1 μm or more.

The insulating film 47 includes an interlayer film 36 formed to cover the gate electrode 19 and the built-in resistor 21. The interlayer film 36 is formed to penetrate into a region (first region) on the gate insulating film 35 where the gate electrode 19 and the built-in resistor 21 are not arranged. This makes it possible to increase the distance (insulating film thickness T) between the SiC epitaxial layer 28 and the gate metal 44 in the region where the built-in resistor 21 is not arranged, thereby reducing the capacitance between them.

The pad side contact 22 and the cell side contact 23 are formed to penetrate this interlayer film 36. The pad side contact 22 and the cell side contact 23 are each made of a metal via formed integrally with the gate metal 44 and the gate finger 5 (pad peripheral portion 12), respectively.

Further, a source contact 46 for making contact from a source metal 43 to the n ⁺ type source region 30 and the p ⁺ type body contact region 31 is formed penetrating the interlayer film 36. The source contact 46 is made of a metal via formed integrally with the source metal 43.

On the interlayer film 36, a gate metal 44, a gate finger 5, and a source metal 43 are formed at intervals from each other.

Then, a passivation film 40 is formed on the interlayer film 36 so as to cover the gate metal 44, the gate finger 5, and the source metal 43. The passivation film 40 has openings 41 and 42 that expose parts of the gate metal 44 and the source metal 43.

As described above, according to the semiconductor device 1, as shown in FIG. 3 and FIG. 4, a polysilicon resistor (built-in resistor 21) is interposed between the gate metal 44 and the gate finger 5 (pad peripheral portion 12). In other words, the built-in resistor 21 is interposed in the middle of the current path leading from the outside to the multiple transistor cells 18.

By adjusting the resistance value of the built-in resistor 21, the resistance value of the built-in resistor 21 can be made dominant in the resistance value (gate resistance) which is the sum of the resistance value of the gate electrode 19 and the resistance value of the built-in resistor 21. Therefore, even when multiple semiconductor devices 1 having gate electrode 19 resistance values varying are connected in parallel for use, the resistance value of the built-in resistor 21 can be made larger than the variation to limit the flow of current into the semiconductor device 1 having a relatively low resistance value of the gate electrode 19. As a result, the generation of noise during use can be reduced.

Moreover, the polysilicon that constitutes the built-in resistor 21 is a material whose resistance value can be easily controlled by, for example, doping impurities, and its processing has also been established using conventional semiconductor manufacturing technology. Therefore, when introducing the built-in resistor 21, it is possible to avoid complicating the structure of the semiconductor device 1 itself and the module that includes it.

As with the gate electrode 19, the size and thickness of the built-in resistor 21 may vary due to variations in processing accuracy (etching dimensions, etc.) when manufacturing the semiconductor device 1, but the processing dimensions are smaller than those of the gate electrode 19. Therefore, variations in the built-in resistor 21 rarely lead to noise generation.

In addition, since the built-in resistor 21 is connected to the gate metal 44 below the gate metal 44, the inflow of the gate current can be restricted at the entrance of the current path leading from the outside to the multiple transistor cells 18. This makes it possible to prevent an inrush current from flowing only to a specific transistor cell 18.

2, for example, consider a case where the built-in resistor 21 is formed in the middle of the first finger 13 or the second finger 14 of the gate finger 5 as a detour for these fingers 13, 14. In this case, on the side closer to the gate metal 44 than the built-in resistor 21, an inrush current may flow from the fingers 13, 14 to the gate electrode 19 via the gate contact 20 before reaching the built-in resistor 21. In contrast, if the gate current can be limited at the entrance of the current path as in this embodiment, the variation in switching speed between multiple transistor cells 18 can be reduced.

Furthermore, as shown in FIG. 2, the built-in resistors 21 are arranged symmetrically. This feature also reduces the variation in switching speed between multiple transistor cells 18.

3 and 4, in SiC epitaxial layer 28, the region facing built-in resistor 21 is p ^- type region 34 having an impurity concentration of 1×10 ¹⁹ cm ^-3 or less. This makes it possible to effectively suppress dielectric breakdown of gate insulating film 35. Furthermore, since p ^- type regions are less likely to accumulate carriers than n-type regions, it is also possible to reduce the capacitance between built-in resistor 21 and p ^- type region 34, which face each other with gate insulating film 35 interposed therebetween.

As shown in Figures 3 and 4, the gate metal 44 and the built-in resistor 21 are connected by a pad-side contact 22 made of a metal via. Therefore, the resistance value contributed by the built-in resistor 21 in the current path leading from the outside to the multiple transistor cells 18 can be easily adjusted by processing to change the position of the pad-side contact 22 along the surface of the SiC epitaxial layer 28 or by processing to change the diameter of the via.

For example, as in the case of pad-side contact 37 shown by the dashed line in FIG. 4, by simply moving the contact position for built-in resistor 21 closer to pad peripheral portion 12 than pad-side contact 22, the distance from the contact position for built-in resistor 21 to pad peripheral portion 12 can be easily shortened from _D1 to _D2 . This allows the resistance value of built-in resistor 21 to be reduced. Conversely, by moving the contact away from pad peripheral portion 12, the resistance value of built-in resistor 21 can be increased. Also, as in the case of pad-side contact 38 shown by the dashed line in FIG. 3, by simply making the via diameter smaller than that of pad-side contact 22, the resistance value of the current path toward built-in resistor 21 can be increased. Conversely, by making the via diameter larger, the resistance value of the path can be reduced.

Moreover, when forming the pad side contacts 22 (vias), these processes only require the use of a mask that matches the distance design and via diameter design, which prevents the manufacturing process from becoming complicated.

Figure 5 is an enlarged view of the area surrounded by the two-dot chain line V in Figure 2. Figure 6 is a cross-sectional view of the semiconductor device when cut along the cutting line VI-VI in Figure 5. Note that in Figures 5 and 6, for clarity, the scale of each component may differ from that in Figures 1 to 4, and the scale of each component may also differ between Figures 5 and 6. Also, in Figures 5 and 6, for clarity, some of the elements that are not exposed at the top surface of the semiconductor device 1 in an actual plan view are shown by solid lines.

Next, a more detailed configuration of the peripheral portion of the active region 2 and the outer peripheral region 3 of the semiconductor device 1 will be described together with the cross-sectional structure of the semiconductor device 1.

As described above, in the outer cell region 45 formed on the periphery of the active region 2, a plurality of transistor cells 18 are arranged in a matrix in a plan view. The configuration of each transistor cell 18 is similar to that described in Figures 3 and 4.

Outside the outer cell region 45, a p ^- type region 51 is formed in the surface portion of the SiC epitaxial layer 28. A p ⁺ type region 52 is formed in the surface portion of the p ^- type region 51. The p ^- type region 51 is formed in a straight line along the periphery of the active region 2, and is integrated with the p ^- type body regions 29 of the (outermost) transistor cells 18. Note that, although only the portion of the p ^{-type region 51 adjacent to the outer cell region 45 is shown in FIG. 5, the p-} type region 51 may actually surround the cell regions (the inner cell region 7 and the outer cell region 45) along the entire periphery of the active region 2. The p ⁺ type region 52 is formed in a straight line extending in the longitudinal direction in the inner region of the p ^- type region 51 (a region spaced from the periphery of the p ^- type region 51). It is to be noted that p ⁻ type region 51 and p ⁺ type region 52 are formed in the same process as p ⁻ type body region 29 and p ⁺ type body contact region 31, respectively, and also have the same impurity concentration and depth.

A plurality of guard rings 53 as an example of the termination structure of the present invention are further formed on the periphery of the active region 2 so as to surround the cell region (the inner cell region 7 and the outer cell region 45). The plurality of guard rings 53 are arranged in a guard ring region of a predetermined width (G) from the outermost region (in this embodiment, the p ^- type region 51) of the regions in the SiC epitaxial layer 28 that are set to the same potential as the source metal 43. In this embodiment, the predetermined width (G) is 5 μm to 100 μm (for example, 28 μm). When the guard ring 53 is formed in the same process as the p ^- type body region 29, the impurity concentration and depth are also the same. When formed in a different process, the impurity concentration is, for example, 1×10 ¹⁴ cm ⁻³ to 1×10 ¹⁹ cm ⁻³ , and the depth is 0.1 μm to 2 μm.

On the other hand, in the outer peripheral region 3, p ^-type region 55 is formed in the surface portion of SiC epitaxial layer 28, and p ⁺ type region 56 is formed in the surface portion of p ^-type region 55. Like p ^-type region 51 and p ⁺ type region 52, p ^-type region 55 and p ⁺ type region 56 are regions formed in the same process as p ^-type body region 29 and p ⁺ type body contact region 31 (they have the same impurity concentration and depth). However, p ^-type region 55 and p ⁺ type region 56 form a stacked structure because p ⁺ type region 56 is formed over the entire surface portion of p ^-type region 55.

The p ⁻ -type region 55 and p ⁺ -type region 56 in the outer peripheral region 3 are formed in a dicing region 54 set at an end of the SiC epitaxial layer 28. As shown in FIGS. 7A and 7B , the dicing region 54 is a region of a predetermined width including a dicing line 58 set at the boundary between adjacent semiconductor devices 1 in the wafer 57. Each semiconductor device 1 is separated into individual pieces by cutting the wafer 57 along the dicing line 58. At this time, it is necessary to provide a margin of a predetermined width in consideration of misalignment of the dicing saw, and this margin portion remains as the dicing region 54 after separation.

The p ⁻ type region 55 and the p ⁺ type region 56 (p type region) are arranged in the dicing region 54 so as to be exposed to an end face 59 of the SiC epitaxial layer 28. In this embodiment, the width (F) of the p ⁻ type region 55 and the p ⁺ type region 56 based on the exposed face (end face 59) is 5 μm to 100 μm (for example, 20 μm). For example, the width (F) may be set in a range of at least the difference between the width (D) of the dicing region 54 and twice the width (E) of the depletion layer 60 extending from the guard ring 53. In designing the width (F), the width (D) of the dicing region 54 can be the distance from the end face 59 of the SiC epitaxial layer 28 to the edge of the passivation film 40 (for example, 13 μm). On the other hand, the width (E) of the depletion layer 60 can be a value calculated by the following formula (1).

(where ε _s is the dielectric constant of SiC, V _bi is the built-in potential of the pn junction between the p-type guard ring 53 and the n-type SiC epitaxial layer 28, q is the absolute value of the charge, and N _B is the donor concentration of the n-type SiC epitaxial layer 28.)
In addition to the interlayer film 36, the insulating film 47 further includes an under-metal insulating film 61 and an end insulating film 62, which are examples of the under-electrode insulating film of the present invention. A contact hole 63 exposing the p ⁺ type region 52 is formed in the insulating film 47, and the inner portion of the contact hole 63 is the interlayer film 36, which is formed on the gate insulating film 35. On the other hand, the outer portion adjacent to the interlayer film 36 with the contact hole 63 in between is the under-metal insulating film 61.

The source metal 43 is connected to the p ⁺ -type region 52 via a contact hole 63. The source metal 43 has an overlapping portion 64 drawn outward in the lateral direction so as to overlap the under-metal insulating film 61. The overlapping portion 64 faces the guard ring 53 across the under-metal insulating film 61. In this embodiment, the overlapping portion 64 is provided so as to partially cover the region in which the guard ring 53 is formed (guard ring region of width (G)), and its end is disposed inside the outer end of the guard ring region. The overlapping portion 64 may cover the entire guard ring region, but the position of the end is determined so that the distance (B) in FIG. 6 is 40 μm or more (for example, 45 μm to 180 μm). The distance (B) is the lateral length between the source metal 43 and the SiC epitaxial layer 28 on the under-metal insulating film 61. In this embodiment, the distance (B) is the length from the edge of the overlapping portion 64 to the edge of the under-metal insulating film 61. Moreover, the distance (B) may be two or more times the width (E) of the depletion layer 60 .

As described above, the source metal 43 preferably has a layered structure represented by Ti/TiN/Al-Cu. For example, in this embodiment, the source metal 43 includes a Ti/TiN film 65 (barrier film) and an Al-Cu film 66, which are layered in this order from the SiC epitaxial layer 28 side. Note that the Ti/TiN film 65 and the Al-Cu film 66 are not shown in FIG. 4.

Outside the under-metal insulating film 61, an n-type region 67 (first conductive type region) is formed in which the SiC surface of the SiC epitaxial layer 28 is exposed over a distance (A). The n-type region 67 is a part of the SiC epitaxial layer 28 exposed from an opening 68 formed outside the under-metal insulating film 61 (between the under-metal insulating film 61 and the end insulating film 62 in this embodiment). As shown in FIG. 5, the opening 68 is formed in a straight line along the boundary between the active region 2 and the peripheral region 3, for example. The distance (A) of the n-type region 67 is 40 μm or more (for example, 45 μm to 180 μm), but the total distance (A) and the distance (B) are preferably 180 μm or less. By making the total of the distances (A) and (B) 180 μm or less, the chip size of the semiconductor device 1 can be kept at a reasonable size.

The end insulating film 62 is formed so as to cover the dicing region 54 of the SiC epitaxial layer 28. Specifically, the end insulating film 62 extends laterally from the end face 59 of the SiC epitaxial layer 28 beyond the dicing region 54 to a region further inward. In this embodiment, the width (H) of the end insulating film 62 based on the end face 59 is 10 μm to 105 μm (for example, 22 μm). As a result, the p ⁻ type region 55 and the p ⁺ type region 56 (p type region) are covered with the end insulating film 62.

The passivation film 40, together with the insulating film 47, is an example of an insulator of the present invention, and is made of an organic insulator. Examples of organic insulators that can be used include polyimide-based materials, polybenzoxazole-based materials, and acrylic-based materials. That is, in this embodiment, the passivation film 40 is configured as an organic passivation film. The thickness of the passivation film 40 is, for example, 0.2 μm to 20 μm.

The passivation film 40 is formed to cover the insulating film 47. In this embodiment, the passivation film 40 is formed over almost the entire area of the SiC epitaxial layer 28, except that it does not cover the end of the SiC epitaxial layer 28 (in other words, the passivation film 40 defines the dicing region 54). Therefore, the passivation film 40 contacts the n-type region 67 of the SiC epitaxial layer 28 over a distance (A) of 40 μm or more in the opening 68 of the insulating film 47.

The passivation film 40 does not cover the end of the SiC epitaxial layer 28, but has an overlapping portion 69 that overlaps a part of the end insulating film 62. This overlapping portion 69 prevents the SiC surface of the SiC epitaxial layer 28 from being exposed to the outside. In this embodiment, the overlapping width (C) between the overlapping portion 69 and the end insulating film 62 is 5 μm or more (for example, 9 μm). In this embodiment, the overlapping portion 69 is formed inwardly and apart from the p-type region (p ⁻ type region 55 and p ⁺ type region 56) in a plan view. As a result, the overlapping portion 69 faces the n-type portion of the SiC epitaxial layer 28 across the end insulating film 62, and does not face the p-type region.

As described above, according to the semiconductor device 1, as shown in FIG. 5 and FIG. 6, since the distance (A) is 40 μm or more, the contact area between the organic passivation film 40 and the SiC epitaxial layer 28 (n-type region 67) can be sufficiently secured. This improves the adhesion of the organic passivation film 40 to the SiC epitaxial layer 28. In addition, since the distance (B) is 40 μm or more or is twice the width (E) of the depletion layer 60 or more, it can also withstand a high temperature, high humidity, high voltage test (for example, 1000 hours continuously under conditions of 85° C., 85% RH, and 960 V application). Setting the distance (A) and the distance (B) to the above range is a completely new finding for SiC semiconductor devices. In SiC, the lateral spread of the depletion layer 60 is smaller than that of Si, so in the past, it was not necessary to increase the distance (A) and the distance (B) to increase the chip size. This is because the depletion layer 60 is unlikely to reach the chip end surface 59 even without increasing the chip size, and increasing the chip size could lead to an increase in the on-resistance per chip area. With this in mind, the inventors of the present application have discovered that by deliberately setting the distance (A) and the distance (B) to 40 μm or more, it is possible to improve resistance to high-temperature, high-humidity, high-voltage tests.

Furthermore, in this embodiment, p-type regions (p ⁻ -type region 55 and p ⁺ -type region 56) are formed in SiC epitaxial layer 28, and the p-type regions are covered with end insulating film 62. Therefore, when testing the electrical characteristics of semiconductor device 1 in the state of wafer 57 before dicing as shown in FIG. 7A, it is possible to reduce the burden of voltage Va applied to the atmosphere between dicing region 54 and source metal 43 (portion exposed from opening 42).

In the test, for example, the source metal 43 of one semiconductor device 1 is set to 0V, and the back surface of the wafer 57 is set to 1000V or more (for example, 1700V). As a result, a maximum applied voltage (BV) that generates a potential difference of 1000V or more between the source metal 43 and the wafer 57 is applied, and the breakdown voltage of each MOSFET is measured. At this time, the n-type portion of the wafer 57, including a part of the dicing region 54 (a portion other than the p ^- type region 55 and the p ⁺ type region 56), is fixed to a potential of 1000V or more, so that a potential difference of 1000V or more occurs between the dicing region 54 and the source metal 43. Even in such a case, according to this embodiment, a p-type region (p ^- type region 55 and p ⁺ type region 56) is formed along the dicing region 54, and the dicing region 54 is further covered with an end insulating film 62. Therefore, the maximum applied voltage (BV) of 1000V or more applied between dicing region 54 and source metal 43 can be mitigated in two stages, that is, end insulating film 62 and the p-type region (p- ^type region 55 and p ⁺ type region 56). This reduces the burden of voltage Va applied to the atmosphere between dicing region 54 and source metal 43. As a result, a semiconductor device 1 having a breakdown voltage value (BV) of 1000V or more can be realized.

In addition, by making the thickness of the under-metal insulating film 61 1 μm or more, it is possible to prevent dielectric breakdown even when a voltage of 1000 V or more is applied to the under-metal insulating film 61. In addition, if the insulating film 47 is BPSG, the under-metal insulating film 61 and the end insulating film 62 can be easily flattened by reflow, and the corners of the insulating films 61 and 62 can be rounded (smoothed). As a result, the adhesion of the passivation film 40 to the insulating films 61 and 62 can be improved.

In addition, since the dicing region 54 is not covered with the passivation film 40, the semiconductor device 1 in the form of wafer 57b can be easily divided (diced).

Figures 8 to 14 are schematic cross-sectional views of semiconductor devices according to the second to eighth embodiments of the present invention, respectively. In Figures 8 to 14, elements corresponding to those in Figure 6 described above are denoted by the same reference numerals.

Next, we will explain another embodiment of the present invention, focusing on the differences from the semiconductor device 1 of the first embodiment.

8, the overlap portion 69 of the passivation film 40 is formed so as to selectively cover the p-type region (p ⁻ -type region 55 and p ⁺ -type region 56) via the end insulating film 62. As a result, the overlap portion 69 has an overlapping portion with the p-type region.

In the semiconductor device 73 of FIG. 9, the end insulating film 62 is not formed, and instead, the passivation film 40 covers the SiC epitaxial layer 28 up to the end face 59. In this case, the dicing region 54 may be set to an appropriate width (D) from the end face 59. The distance (A) may be defined as the length from the edge of the under-metal insulating film 61 to the end face 59 of the SiC epitaxial layer 28.

10 has the same configuration as semiconductor device 73 of FIG 9, except that p ^- type region 55 and p ⁺ type region 56 (p-type region) are formed in dicing region 54. In this case, distance (A) may be defined as the length from the edge of under-metal insulating film 61 to the p-type region. In other words, distance (A) may be 40 μm or more with respect to the section where passivation film 40 contacts the n-type portion of SiC epitaxial layer 28.

In the semiconductor device 75 of Fig. 11, at least two openings 68 are formed outside the under-metal insulating film 61 of the insulating film 47. In this embodiment, the openings 68 are formed between the under-metal insulating film 61 and the outer insulating film 79, and between the outer insulating film 79 and the end face 59 of the SiC epitaxial layer 28. In each opening 68, the passivation film 40 contacts the n-type region 67 of the SiC epitaxial layer 28 over a distance (A ₁ ) and a distance (A ₂ ). In this case, the distance of the section where the passivation film 40 contacts the n-type region 67 may be 40 µm or more in total of the distances (A ₁ ) and distances (A ₂ ) of the contact sections in each of the multiple n-type regions 67.

12 has the same configuration as the semiconductor device 73 of FIG 9, except that a recess 80 is selectively formed in the n-type region 67. In the recess 80, the passivation film 40 contacts the n-type region 67 at the inner surface (bottom surface and both side surfaces) of the recess 80. In this case, the distance of the section where the passivation film 40 contacts the n-type region 67 may be 40 μm or more in total, including the contact distance (A ₅ ) in the region other than the recess 80 and the distances (A ₃ ) and (A ₄ ) of the contact sections at the bottom surface and both side surfaces of the recess 80, respectively.

In the semiconductor device 77 of FIG. 13, the transistor cells 18 are configured as MOSFET cells with a trench gate structure. In this case, the gate electrodes 19 are embedded in gate trenches 39 formed between the multiple transistor cells 18 via the gate insulating film 35.

In the semiconductor device 78 of FIG. 14, a Schottky barrier diode 81 is formed in the active region 2. In other words, instead of the source metal 43, a Schottky metal 82 is provided that forms a Schottky junction with the SiC epitaxial layer 28.

As described above, the semiconductor devices 72 to 78 of the second to eighth embodiments all have three features: (1) the distance (A) is 40 μm or more, (2) the distance (B) is 40 μm or more or is at least twice the width (E) of the depletion layer 60, and (3) the end of the SiC epitaxial layer 28 is covered with an insulator (end insulating film 62 or passivation film 40). Therefore, like the first embodiment, the second to eighth embodiments can provide a SiC semiconductor device that can prevent discharge during an electrical characteristic test performed in the wafer state and can withstand a high-temperature, high-humidity, high-voltage test.

The above describes an embodiment of the present invention, but the present invention can also be implemented in other forms.

For example, the transistor cell 18 may be an IGBT cell having a planar gate structure or a trench gate structure. In this case, a p ⁺ type SiC substrate 27 may be used instead of the n ⁺ type SiC substrate 27 in Fig. 4 and Fig. 13. In addition, various semiconductor element structures may be formed in the active region 2.

In addition, the surface electrodes such as the source metal 43 and Schottky metal 82 do not need to be made of metal and may be semiconductor electrodes such as polysilicon.

Furthermore, the built-in resistor 21 does not need to be embedded in the interlayer film 36 below the gate metal 44. For example, a polysilicon wiring that connects the gate metal 44 and the gate finger 5 may be formed as a built-in resistor on the surface of the interlayer film 36.

In addition, instead of polysilicon, the material for the built-in resistor 21 may be a material having a resistance value equal to or greater than that of the gate metal 44 and the gate finger 5 (for example, metal wiring such as Al (aluminum), AlCu (aluminum-copper alloy), Cu (copper) or the like). Even if the built-in resistor 21 is metal, the distance between the gate metal 44 and the gate finger 5 can be increased, so that the total resistance value of the gate electrode 19 and the built-in resistor 21 can be increased.

Furthermore, the built-in resistor 21 does not need to be formed below the gate metal 44, but may be formed, for example, below the gate finger 5.

The built-in resistor 21 may be linear and extend along a portion of the peripheral portion 24 of the gate metal 44, or may be annular and extend along the entire circumference of the peripheral portion 24 of the gate metal 44.

In addition, a configuration in which the conductivity type of each semiconductor portion of the semiconductor device 1 described above is inverted may be adopted. For example, in the semiconductor device 1, the p-type portion may be n-type, and the n-type portion may be p-type.

In addition, various design changes may be made within the scope of the claims.

In addition, the following features can be extracted from the above-mentioned embodiment:

A semiconductor device (item 1) including a first conductive type SiC layer, an electrode selectively formed on the SiC layer, and an insulator formed on the SiC layer and reaching a dicing area set at an end of the SiC layer, the insulator including an under-electrode insulating film arranged to extend from below the electrode toward the dicing area and an organic insulating layer arranged to cover the under-electrode insulating film, the distance (A) of the section where the organic insulating layer contacts the SiC layer is 40 μm or more, and the lateral distance (B) from the end of the electrode on the under-electrode insulating film to the portion where the organic insulating layer contacts the SiC layer is 40 μm or more.

With this configuration, the dicing area is covered with an insulator, so when testing the electrical characteristics of a semiconductor device in wafer form, the burden of the voltage applied in the atmosphere between the dicing area and the electrodes can be reduced. In other words, the voltage applied between the dicing area and the electrodes can be shared between the atmosphere and the insulator, preventing discharge in the atmosphere.

Furthermore, since the distance (A) is 40 μm or more, the contact area between the organic insulating layer and the SiC layer can be sufficiently secured, so that the adhesion of the organic insulating layer to the SiC layer can be improved. In addition, since the distance (B) is 40 μm or more, it can withstand a high-temperature, high-humidity, high-voltage test. Setting the distance (A) and the distance (B) to the above range is a completely new finding for SiC semiconductor devices. In SiC, the lateral spread of the depletion layer is smaller than that of Si, so in the past, it was not necessary to increase the distance (A) and the distance (B) to increase the chip size. This is because the depletion layer is unlikely to reach the chip end face even without increasing the chip size, and the increase in chip size could be a factor in increasing the on-resistance per chip area. Against this background, the inventors of the present application have found that by deliberately setting the distance (A) and the distance (B) to 40 μm or more, the resistance to the high-temperature, high-humidity, high-voltage test can be improved.

When the semiconductor device further includes a second conductivity type region formed in the dicing region, the distance (A) may be 40 μm or more in the section where the organic insulating layer contacts the first conductivity type region of the SiC layer (item 2).

With this configuration, the voltage applied between the dicing region and the electrode can be distributed to the second conductivity type region as well. This makes it possible to more effectively prevent discharge in the atmosphere.

The organic insulating layer may be formed to cover the dicing region and may be in contact with the second conductivity type region in the dicing region (item 3).

When the organic insulating layer does not cover the dicing region and the insulator is made of the same film layer as the under-electrode insulating film, and further includes an edge insulating film that covers the dicing region and partially overlaps the organic insulating layer, the overlap width (C) between the organic insulating layer and the edge insulating film may be 5 μm or more (item 4).

With this configuration, the dicing area is not covered with an organic insulating layer, so the semiconductor device in wafer form can be easily divided (diced). Even in this case, the dicing area is covered with an end insulating film that constitutes an insulator, so the above-mentioned discharge prevention effect can be fully achieved.

When the insulator is made of the same layer as the electrode insulating film and further includes an edge insulating film covering the dicing region, the organic insulating layer overlaps the edge insulating film so as to selectively cover the second conductivity type region via the edge insulating film, and the overlap width (C) between the organic insulating layer and the edge insulating film may be 5 μm or more (item 5).

The end insulating film may have the same thickness as the under-electrode insulating film (item 6).

With this configuration, the end insulating film can be fabricated in the same process as the under-electrode insulating film, simplifying the manufacturing process.

The distance (A) may be 45 μm to 180 μm (item 7), and the distance (B) may be 45 μm to 180 μm (item 8). The sum of the distance (A) and the distance (B) may be 180 μm or less (item 9).

By setting distance (A) and distance (B) within the above ranges, the chip size of the semiconductor device can be kept at a reasonable size. Also, since atmospheric discharge is likely to occur when distance (A) and distance (B) are within the above ranges, it is useful to cover the dicing area with an insulator.

The breakdown voltage value (BV) of the semiconductor device may be 1000V or more (item 10).

When the breakdown voltage (BV) is 1000V or higher, atmospheric discharge is likely to occur, so it is useful to cover the dicing area with an insulator.

The SiC layer may have a first conductivity type impurity concentration of 1×10 ¹⁶ cm ⁻³ or less, and a thickness of the SiC layer may be 5 μm or more (Item 11).

When the semiconductor device further includes a second conductivity type termination structure consisting of an impurity region formed in the SiC layer outward from the electrode, the width (F) of the second conductivity type region may be equal to or greater than the difference between the width (D) of the dicing region and twice the width (E) of the depletion layer extending from the termination structure (Item 12).

The electrode may have a laminated structure represented by Ti/TiN/Al-Cu (item 13).

By using Al-Cu, resistance to humidity can be further improved.

The insulating film under the electrode may be made of a SiO ₂ film having a thickness of 1 μm or more (item 14). In this case, the SiO ₂ film may contain phosphorus (P) or boron (B) (items 15 and 16).

If a _SiO2 film having a thickness of 1 μm or more is used, it is possible to prevent dielectric breakdown even if a voltage of 1000 V or more is applied to the insulating film under the electrode. In addition, if phosphorus (P) or boron (B) is contained, the insulating film under the electrode can be easily flattened by reflow. In addition, the corners of the insulating film under the electrode can be rounded.

The insulating film under the electrode may be made of a SiN film having a thickness of 1 μm or more (item 17).

If a SiN film with a thickness of 1 μm or more is used, dielectric breakdown can be prevented even if a voltage of 1000 V or more is applied to the insulating film under the electrode.

The organic insulating layer may be made of a polyimide-based material, a polybenzoxazole-based material, an acrylic-based material, or the like (items 18, 19, and 20).

A MOSFET is formed in the SiC layer as a semiconductor element structure, and the electrode may include a source electrode electrically connected to the source of the MOSFET (item 21). In this case, the MOSFET may have a planar gate structure (item 22) or a trench gate structure (item 23).

In addition, a Schottky barrier diode is formed in the SiC layer as a semiconductor element structure, and the electrode may include a Schottky electrode that constitutes part of the Schottky barrier diode (item 24).

Furthermore, an IGBT is formed as a semiconductor element structure in the SiC layer, and the electrode may include a source electrode electrically connected to the source of the IGBT (item 25).

When the organic insulating layer is in contact with the SiC layer in multiple regions, the distance (A) may be 40 μm or more in total for the distance of the contact section in each of the multiple regions (item 26).

When the semiconductor device further includes a recess selectively formed in the SiC layer and filled with the organic insulating layer, the distance (A) may be 40 μm or more in total, including the contact area of the organic insulating layer on the inner surface of the recess (item 27).

Also, the semiconductor device extracted from the above-mentioned embodiment includes a first conductive type SiC layer, an electrode selectively formed on the SiC layer, an insulator formed on the SiC layer and reaching a dicing region set at an end of the SiC layer, and a second conductive type termination structure consisting of an impurity region formed outside the electrode in the SiC layer, the insulator includes an under-electrode insulating film arranged to extend from below the electrode toward the dicing region and an organic insulating layer arranged to cover the under-electrode insulating film, the distance (A) of the section where the organic insulating layer contacts the SiC layer is 40 μm or more, and the lateral distance (B) from the end of the electrode on the under-electrode insulating film to the part where the organic insulating layer contacts the SiC layer may be twice or more the width (E) of the depletion layer extending from the termination structure (item 28).

With this configuration, the dicing area is covered with an insulator, so when testing the electrical characteristics of the semiconductor device in wafer form, the applied voltage can be mitigated by the insulator. This reduces the burden of the voltage applied in the atmosphere between the dicing area and the electrode. In other words, the voltage applied between the dicing area and the electrode can be shared between the atmosphere and the insulator, preventing discharge in the atmosphere.

Furthermore, since the distance (A) is 40 μm or more and the distance (B) is at least twice the width (E) of the depletion layer extending from the termination structure, it can also withstand high temperature, high humidity, and high voltage testing.

LIST OF SYMBOLS 1 semiconductor device 2 active region 18 transistor cell 19 gate electrode 27 SiC substrate 28 SiC epitaxial layer 29 p ^- type body region 30 n ⁺ type source region 31 p ⁺ type body contact region 32 channel region 35 gate insulating film 36 interlayer film 39 gate trench 40 passivation film 43 source metal 44 gate metal 47 insulating film 51 p ^- type region 52 p ⁺ type region 53 guard ring 54 dicing region 55 p ^- type region 56 p ⁺ type region 57 wafer 58 dicing line 59 end surface 60 depletion layer 61 under-metal insulating film 62 end insulating film 63 contact hole 64 overlapping portion 65 Ti/TiN film 66 Al-Cu film 67 n-type region 68 Opening 69 Overlap portion 72 Semiconductor device 73 Semiconductor device 74 Semiconductor device 75 Semiconductor device 76 Semiconductor device 77 Semiconductor device 78 Semiconductor device 79 Semiconductor device 80 Recess 81 Schottky barrier diode 82 Schottky metal

Claims (19)

an active area having a plurality of transistor elements formed on a surface thereof;
an outer peripheral region that is a periphery of the active region ;
a first conductivity type SiC layer having an end surface outside the outer circumferential region ;
an electrode selectively formed on the SiC layer and electrically connected to the plurality of transistor elements ;
an under-electrode insulating film below the electrode, at least partially overlapping the electrode, and extending toward the end surface of the SiC layer;
an interlayer film below the electrode and at least partially overlapping the electrode;
a surface insulating film covering at least a part of the electrode, the under-electrode insulating film, and the interlayer film;
the surface insulating film is formed to be in contact with the SiC layer in the outer circumferential region and to reach the end face of the SiC layer;
the surface insulating film has a step portion in contact with an end portion of the under-electrode insulating film and the SiC layer in the outer circumferential region,
a bottom surface portion of the surface insulating film including a first contact portion that is in contact with the SiC layer below a bottom surface of the electrode-underlying insulating film in a thickness direction of the SiC layer . 2 . The semiconductor device according to claim 1 , wherein, in a cross-sectional view, a contact width of the step portion with the SiC layer in a direction toward the end face of the SiC layer is narrower than a width of the first contact portion in the same direction. a recess is selectively formed in a surface portion of the SiC layer closer to the end face of the SiC layer than the step portion,
The semiconductor device according to claim 1 , wherein the first contact portion is embedded in the recess and is in contact with the SiC layer on an inner surface of the recess. The semiconductor device according to claim 3 , wherein a thickness of said surface insulating film in a region directly above said recess in a thickness direction of said SiC layer is greater than a thickness of said first contact portion. A dicing region is formed at an end of the SiC layer,
5. The semiconductor device according to claim 1 , wherein the SiC layer includes a second conductivity type region formed in the first conductivity type region of the dicing region. a termination structure having an impurity region of a second conductivity type formed on the SiC layer outside the electrode;
6. The semiconductor device according to claim 5 , wherein a width (F) of said second conductivity type region is equal to or greater than a difference between a width (D) of said dicing region and twice a width (E) of a depletion layer extending from said termination structure. 7. The semiconductor device according to claim 1 , wherein a breakdown voltage value is 1000 V or more. The SiC layer has a first conductivity type impurity concentration of 1×10 ¹⁶ cm ⁻³ or less,
The semiconductor device according to claim 1 , wherein the SiC layer has a thickness of 5 μm or more. 9. The semiconductor device according to claim 1 , wherein the electrode has a layered structure represented by Ti/TiN/Al--Cu. 10. The semiconductor device according to claim 1, wherein the insulating film under the electrode is made of a SiO ₂ film having a thickness of 1 μm or more. 10. The semiconductor device according to claim 1, wherein the insulating film under the electrode is made of a SiN film having a thickness of 1 μm or more. 12. The semiconductor device according to claim 1 , wherein the surface insulating film includes an organic insulating layer made of a polyimide-based material. A MOSFET is formed as the transistor element,
13. The semiconductor device according to claim 1, wherein the electrodes include a source electrode electrically connected to a source through which an on-current of the MOSFET flows. The semiconductor device according to claim 13 , wherein the MOSFET has a planar gate structure. An IGBT is formed as the transistor element,
13. The semiconductor device according to claim 1, wherein the electrodes include an emitter electrode electrically connected to an emitter through which an on-current of the IGBT flows. the transistor element includes a switching element controlled by a gate electrode;
The semiconductor device according to claim 1 , further comprising a resistive element electrically connected to the gate electrode. the transistor element has a first region of a second conductivity type formed in a surface portion of the SiC layer, and a second region of the second conductivity type formed in a surface portion of the first region and having a higher impurity concentration than the first region;
a contact hole exposing the second region of the transistor element is formed between the electrode under- insulation film and the interlayer film ;
17. The semiconductor device according to claim 1, wherein the electrode and the second region of the transistor element are electrically connected via the contact hole. The semiconductor device according to claim 1 , wherein the surface insulating film has an end face that is flush with the end face of the SiC layer. The semiconductor device according to claim 18 , wherein the surface insulating film has a flat upper surface in the vicinity of the end face of the SiC layer.

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