JP2023085505A5 - - Google Patents

Claims (19)

an active region having a plurality of transistor elements formed on its surface;
an outer peripheral region that is a peripheral edge of the active region ;
a first conductivity type SiC layer having an end face outside the outer peripheral region ;
an electrode selectively formed on the SiC layer and electrically connected to the plurality of transistor elements ;
an under-electrode insulating film at least partially overlapping with the electrode under the electrode and extending toward the end surface of the SiC layer;
an interlayer film that at least partially overlaps with the electrode below the electrode;
a surface insulating film covering at least part of the electrode, the insulating film under the electrode, and the interlayer film;
the surface insulating film is formed in contact with the SiC layer in the outer peripheral region and reaches the end face of the SiC layer;
the surface insulating film has a stepped portion in contact with the SiC layer and an end portion of the under-electrode insulating film in the outer peripheral region;
The semiconductor device, wherein the bottom surface portion of the surface insulating film includes a first contact portion that contacts the SiC layer below the bottom surface of the under-electrode insulating film in the thickness direction of the SiC layer. 2 . The semiconductor device according to claim 1 , wherein a contact width of said step portion with said SiC layer in a direction toward said end surface of said SiC layer is narrower than a width of said first contact portion in the same direction in a cross-sectional view. a recess is selectively formed on the surface portion of the SiC layer closer to the end surface of the SiC layer than the stepped portion;
3. The semiconductor device according to claim 1, wherein said first contact portion is embedded in said recess and is in contact with said SiC layer on an inner surface of said recess. 4. The semiconductor device according to claim 3, wherein the thickness of said surface insulating film in a region immediately above said recess is greater than the thickness of said first contact portion in the thickness direction of said SiC layer. A dicing region is formed at an end of the SiC layer,
5. The semiconductor device according to claim 1, wherein said SiC layer includes a second conductivity type region formed in said first conductivity type region of said dicing region. further comprising a termination structure having a second conductivity type impurity region formed outside the electrode of the SiC layer;
6. The method according to claim 5 , wherein the width (F) of said second conductivity type region is at least twice the difference between the width (D) of said dicing region and the width (E) of a depletion layer extending from said termination structure. semiconductor device. 7. The semiconductor device according to claim 1, wherein the breakdown voltage value is 1000V or higher. The SiC layer has a first conductivity type impurity concentration of 1×10 ¹⁶ cm ⁻³ or less,
8. The semiconductor device according to claim 1, wherein said SiC layer has a thickness of 5 μm or more. 9. The semiconductor device according to claim 1 , wherein said electrode has a laminated structure represented by Ti/TiN/Al--Cu. 10. The semiconductor device according to claim 1, wherein said under-electrode insulating film is made of a SiO ₂ film having a thickness of 1 μm or more. 10. The semiconductor device according to claim 1, wherein said under-electrode insulating film is made of a SiN film having a thickness of 1 μm or more. 12. The semiconductor device according to claim 1, wherein said surface insulating film includes an organic insulating layer made of a polyimide-based material. A MOSFET is formed as the transistor element,
13. The semiconductor device according to claim 1, wherein said electrode includes a source electrode electrically connected to a source through which on-current of said MOSFET flows. 14. The semiconductor device according to claim 13 , wherein said MOSFET has a planar gate structure. an IGBT is formed as the transistor element,
13. The semiconductor device according to claim 1, wherein said electrode includes an emitter electrode electrically connected to an emitter through which on-current of said IGBT flows. the transistor element includes a switching element controlled by a gate electrode;
16. The semiconductor device according to claim 1, further comprising a resistive element electrically connected to said gate electrode. The transistor element includes a first region of a second conductivity type formed in the surface portion of the SiC layer and a second conductivity type region formed in the surface portion of the first region and having an impurity concentration higher than that of the first region. a second region of the mold;
a contact hole exposing the second region of the transistor element is formed between the insulating film under the electrode and the interlayer film ;
17. The semiconductor device according to claim 1, wherein said electrode and said second region of said transistor element are electrically connected through said contact hole. 18. The semiconductor device according to claim 1, wherein said surface insulating film has an end face flush with said end face of said SiC layer. 19. The semiconductor device according to claim 18 , wherein said surface insulating film has a flat upper surface near said end surface of said SiC layer.