JP7001785B2 - Semiconductor devices and semiconductor modules - Google Patents

Description

The present invention relates to a semiconductor device and a semiconductor module including the semiconductor device.

In switching devices, for example, if an overcurrent continues to flow during a short circuit, thermal destruction may occur. In order to prevent this defect, for example, Patent Document 1 includes a semiconductor switching element, a semiconductor drive circuit, a sense element formed in the semiconductor switching element, and an overcurrent detection unit formed in the semiconductor drive circuit. , Discloses semiconductor devices. The sense element is composed of a sense terminal through which a current proportional to the main current of the semiconductor switching element flows, and a sense resistor connected between the main terminal and the sense terminal of the semiconductor switching element to convert the sense current into a voltage. Further, the overcurrent detection unit detects the sense current flowing through the above-mentioned sense element, and when the sense current exceeds a predetermined value, turns off the semiconductor switching element to protect the semiconductor switching element from the overcurrent.

Japanese Unexamined Patent Publication No. 2013-247804

Since the overcurrent protection method of Patent Document 1 is a method of turning off the semiconductor switching element based on the sense current, it is easily affected by noise, and sometimes the sense current containing noise is erroneously detected as an overcurrent. There is. In order to prevent malfunction due to such noise, there is a method in which the semiconductor switching element is not turned off immediately even if the sense current exceeds a predetermined threshold value, but is turned off after a certain waiting time (mask time) has elapsed. ..

However, there remains a problem in the method of providing this waiting time. A certain waiting time is required to consider the influence of noise (for example, about 500 nsec), but while the on-resistance of the device is being lowered, the time required for the device to be destroyed due to overcurrent is longer than the waiting time. In some cases, the overcurrent protection system itself is not established.
Therefore, one embodiment of the present invention provides a semiconductor device capable of reducing malfunction due to current noise and satisfactorily protecting a switching element from overcurrent, and a semiconductor module including the same.

In one embodiment of the present invention, a semiconductor substrate, a switching element formed on the semiconductor substrate, and a temperature sense element provided on the surface side of the semiconductor substrate independently of the switching element and having characteristics depending on the temperature. Provided are semiconductor devices including and.
Further, in one embodiment of the present invention, a semiconductor substrate, a switching element formed on the semiconductor substrate, and a temperature provided on the surface side of the semiconductor substrate independently of the switching element and having characteristics depending on the temperature. Provided is a single-function semiconductor device including a sense element and the switching element.

According to the above configuration, if a temperature change occurs on the surface side of the semiconductor substrate, the characteristics (voltage value, resistance value, etc.) of the temperature sense element change accordingly. Therefore, by monitoring the change in the characteristics of the temperature sense element, it is possible to detect the temperature change in the semiconductor substrate. Utilizing this relationship, when an overcurrent flows in the switching element due to, for example, a short circuit, the temperature rise of the semiconductor substrate due to the overcurrent is detected, and based on the detection result, is the overcurrent flowing in the switching element? It can be determined whether or not. Moreover, since the monitoring target is not the sense current flowing through the switching element, even if noise is included in the sense current and superimposed, it is not erroneously detected as an overcurrent due to the superimposed current. Therefore, it is possible to reduce malfunction due to current noise.

One embodiment of the present invention includes a first electrode and a second electrode paired with each other on the semiconductor substrate, and the electric circuit between the first electrode and the second electrode has the temperature as a circuit element. Only the sense element is provided.
In one embodiment of the invention, the temperature sense device includes a pn diode made of a polysilicon layer formed on the semiconductor substrate.

Polysilicon can be easily formed into a desired shape and position by the already established semiconductor manufacturing technology. Therefore, by forming the polysilicon layer (pn diode) in the vicinity of the surface which is the heat generating portion of the semiconductor substrate, the temperature change of the semiconductor substrate can be detected with high accuracy. For example, by constantly applying a constant current to the pn diode and monitoring the forward voltage _VF of the pn diode, the temperature change of the semiconductor substrate can be detected.

In one embodiment of the invention, the switching element comprises a planar gate type MISFET having a gate electrode formed along the surface of the semiconductor substrate, and the polysilicon layer is formed in the same layer as the gate electrode. ing.
According to this configuration, since the polysilicon layer (pn diode) can be formed in the same process as the gate electrode, it is possible to suppress an increase in the number of steps due to the formation of the pn diode. Further, since the pn diode can be arranged on the semiconductor substrate via the gate insulating film which is thinner than the relatively thick film such as the interlayer insulating film, the position of the pn diode can be brought closer to the current path on the surface side of the semiconductor substrate. be able to. This makes it possible to improve the accuracy of detecting the temperature change of the semiconductor substrate.

In one embodiment of the invention, the pn diode includes a p-type region and an n-type region surrounding the p-type region in plan view.
According to this configuration, since the p-type region and the n-type region do not overlap in a plan view, no separate wiring or the like is required, and both the p-type region and the n-type region can be easily contacted. be able to.

In one embodiment of the invention, the switching element comprises a trench gate type MISFET having a gate trench formed in the semiconductor substrate and a gate electrode embedded in the gate trench, and the polysilicon layer is the semiconductor substrate. Is embedded in a second trench formed independently of the gate trench.
According to this configuration, the second trench can be formed in the same process as the gate trench, and the polysilicon layer (pn diode) can be formed in the same process as the gate electrode, so that the increase in the number of steps due to the formation of the pn diode can be suppressed. be able to. Further, since the pn diode is embedded in the surface portion of the semiconductor substrate, the position of the pn diode can be brought close to the current path on the surface side of the semiconductor substrate. This makes it possible to improve the accuracy of detecting the temperature change of the semiconductor substrate.

In one embodiment of the present invention, the gate trench and the second trench are formed to have the same width as each other.
According to this configuration, the etching rates when forming the gate trench and the second trench can be made substantially the same, so that the gate trench and the second trench having substantially the same depth can be finally formed. can. By making the depth of the second trench substantially the same as the gate trench in which the channel of the MISFET is formed, it is possible to quickly detect the temperature rise of the semiconductor substrate due to the overcurrent.

In one embodiment of the present invention, the temperature sense element includes a pn diode composed of an impurity region formed on the surface portion of the semiconductor substrate.
The impurity region can be easily formed at a desired position by the already established semiconductor manufacturing technology. Therefore, by forming an impurity region (pn diode) in the vicinity of the current path on the surface side, which is the heat generating portion of the semiconductor substrate, the temperature change of the semiconductor substrate can be detected with high accuracy. For example, by constantly applying a constant current to the pn diode and monitoring the forward voltage _VF of the pn diode, the temperature change of the semiconductor substrate can be detected. Further, a pn diode composed of an impurity region operates well even in a high temperature region (for example, 200 ° C. or higher), and is particularly effective for power devices such as SiC and GaN.

In one embodiment of the invention, the pn diode includes a p-type region and an n-type region surrounding the p-type region in plan view.
According to this configuration, since the p-type region and the n-type region do not overlap in a plan view, no separate wiring or the like is required, and both the p-type region and the n-type region can be easily contacted. be able to.

In one embodiment of the invention, the temperature sense element includes a series connection unit in which a plurality of the pn diodes are connected in series.
According to this configuration, the amount of temperature change of the forward voltage _VF increases in proportion to the number of connections of the pn diode, so that the temperature change detection sensitivity can be improved. For example, when the fluctuation width of the forward voltage VF per pn diode is _XmV / ° C., if five pn diodes are connected in series to form a series connection unit, the total series connection unit is The runout width can be set to 5 XmV / ° C.

In one embodiment of the present invention, the temperature sense element includes a configuration in which at least a pair of the series connection units are connected in parallel in opposite directions to each other.
According to this configuration, since there is no distinction between the polarities of the anode side and the cathode side at the terminals of the aggregate of pn diodes, it is possible to improve the degree of freedom in wiring the bonding wire or the like when assembling the module or the like.

In one embodiment of the invention, the temperature sense element comprises a reverse series connection unit in which at least a pair of the pn diodes are connected in series in opposite directions to each other.
According to this configuration, a reverse bias is applied to at least one of the pair of pn diodes, so that the total resistance of the reverse series connection unit becomes high. Therefore, the current required for monitoring the temperature change can be kept small, and power saving can be achieved.

In one embodiment of the present invention, the temperature sense element includes a configuration in which a plurality of the reverse series connection units are connected in series.
According to this configuration, further power saving can be achieved.
In one embodiment of the present invention, the temperature sense element includes a configuration in which at least a pair of the pn diodes are connected in parallel in opposite directions to each other.

According to this configuration, since the polarities of the anode side and the cathode side are not distinguished between the terminals of the pair of pn diodes, it is possible to improve the degree of freedom in wiring the bonding wire or the like when assembling the module or the like.
In one embodiment of the present invention, the temperature sense element is arranged on the peripheral edge of the semiconductor substrate.

According to this configuration, a relatively wide area can be secured in a portion other than the installation area of the temperature sense element, so that the area of the terminal for the switching element can be widened. Therefore, even if the chip size is reduced, a wiring member such as a bonding plate or a relatively thick bonding wire can be connected to the terminal.
In one embodiment of the invention, the semiconductor substrate comprises a SiC semiconductor substrate.

According to this configuration, the low on-resistance SiC switching element can be well protected from overcurrent.
One embodiment of the present invention is a circuit electrically connected to the semiconductor device, the switching element, and the temperature sense element, and an overcurrent is applied to the switching element based on a change in the characteristics of the temperature sense element. Provided is a semiconductor module including a second semiconductor device having a circuit that cuts off the current path of the switching element when it is determined that the current is flowing.

According to this configuration, since the above-mentioned semiconductor device is provided, it is possible to realize a semiconductor module capable of reducing malfunction due to current noise and satisfactorily protecting the switching element from overcurrent.

FIG. 1 is a schematic external view of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a circuit diagram of a semiconductor module including the semiconductor device of FIG. FIG. 3 is a diagram showing the planar structure of the semiconductor device of FIG. 1 more specifically. FIG. 4A is a schematic plan view showing the structure of the cell region of the semiconductor device of FIG. FIG. 4B is a cross-sectional view of FIG. 4A (cross-sectional view taken along the line BB). FIG. 5A is a schematic plan view showing the structure of the temperature sense region of the semiconductor device of FIG. FIG. 5B is a cross-sectional view of FIG. 5A (cross-sectional view taken along the line BB). FIG. 5C is a diagram showing a modified example of the structure of FIG. 5B. FIG. 6 is a flow chart of the manufacturing process of the semiconductor device. FIG. 7A is a diagram showing a part of the manufacturing process of the semiconductor device. FIG. 7B is a diagram showing the next step of FIG. 7A. FIG. 7C is a diagram showing the next step of FIG. 7B. FIG. 7D is a diagram showing the next step of FIG. 7C. FIG. 7E is a diagram showing the next step of FIG. 7D. FIG. 7F is a diagram showing the next step of FIG. 7E. FIG. 7G is a diagram showing the next step of FIG. 7F. FIG. 7H is a diagram showing the next step of FIG. 7G. FIG. 7I is a diagram showing the next step of FIG. 7H. FIG. 7J is a diagram showing the next step of FIG. 7I. FIG. 7K is a diagram showing the next step of FIG. 7J. FIG. 7L is a diagram showing the next step of FIG. 7K. FIG. 8 is a graph for explaining how the forward voltage of the temperature sense diode changes due to a temperature change. 9A is a schematic plan view showing the structure of the temperature sense region of the semiconductor device of FIG. 9B is a cross-sectional view of FIG. 9A (cross-sectional view taken along the line BB). FIG. 10 is a diagram showing an example of the connection form of the temperature sense diode. FIG. 11 is a diagram showing an example of the connection form of the temperature sense diode. FIG. 12 is a diagram showing an example of the connection form of the temperature sense diode. FIG. 13 is a diagram showing an example of the connection form of the temperature sense diode. FIG. 14 is a diagram showing an example of the connection form of the temperature sense diode. It is a schematic plan view which shows the structure of the cell region of the semiconductor device of FIG. FIG. 15B is a cross-sectional view of FIG. 15A (cross-sectional view taken along the line BB). FIG. 16A is a schematic plan view showing the structure of the temperature sense region of the semiconductor device of FIG. 16B is a cross-sectional view of FIG. 16A (cross-sectional view taken along the line BB). 16C is a cross-sectional view of FIG. 16A (cross-sectional view taken along the line CC).

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic external view of a semiconductor device 1 according to an embodiment of the present invention.
The semiconductor device 1 is a discrete semiconductor device and has a single function by a switching element SW. The switching element SW may be, for example, a MISFET (Metal Insulator Semiconductor Field Effect Transistor), or may be an IGBT (Insulated Gate Bipolar Transistor), a JFET (Junction Field Effect Transistor), a bipolar transistor, a thyristor, or the like. .. In this embodiment, the case where the switching element SW is a MISFET is shown. A source pad 2 and a gate pad 3 are formed on the surface of the semiconductor device 1 formed as a chip having a rectangular shape in a plan view. The source pad 2 covers almost the entire surface of the surface, and the gate pad 3 is arranged in the inner region of the source pad 2. Although not shown, a drain electrode is formed on the back surface of the semiconductor device 1.

In addition to the switching element SW described above, the semiconductor device 1 is provided with a temperature sense element TS. The temperature sense element TS is arranged on the surface side of the semiconductor device 1. The temperature sense element TS is independent of the switching element SW and does not directly contribute to the switching operation by the switching element SW.
Next, an outline of the overcurrent protection method in the semiconductor module 4 provided with the semiconductor device 1 will be described. FIG. 2 is a circuit diagram of a semiconductor module 4 including the semiconductor device 1 of FIG.

The semiconductor module 4 includes a semiconductor device 1 and a gate driver G / D as an example of the second semiconductor device of the present invention having the short circuit protection circuit 5. The semiconductor module 4 may include a semiconductor chip (IC, discrete, etc.) other than those shown in FIG.
The short-circuit protection circuit 5 is independently and electrically connected to the gate G of the switching element SW and the temperature sense element TS, respectively. The short-circuit protection circuit 5 constantly monitors the characteristics of the temperature sense element TS. For example, when a short circuit occurs in the switching element SW and an overcurrent flows, the characteristics of the temperature sense element TS change due to the heat generated by the short circuit. The short-circuit protection circuit 5 senses the change in the characteristics as the occurrence of a short circuit in the switching element SW, and turns off the gate G of the switching element SW. As a result, the drain current Id flowing between the source and drain (SD) of the switching element SW is cut off, and the switching element SW is protected.

FIG. 3 is a diagram showing the planar structure of the semiconductor device 1 of FIG. 1 more specifically.
The semiconductor device 1 includes a semiconductor substrate 6 that defines its outer shape, and has a structure in which a switching element SW and a temperature sense element TS are formed on the semiconductor substrate 6.
The semiconductor substrate 6 has a quadrangular shape in a plan view, and almost the entire surface thereof is covered with a source pad 2 having a substantially quadrangular view in a plan view. A cell region 7 constituting the switching element SW is formed in most of the lower part of the source pad 2. The gate pad 3 is arranged on at least one side of the outer periphery of the semiconductor substrate 6. A gate finger 8 is connected to the gate pad 3. The gate finger 8 extends to the central portion of the semiconductor substrate 6 to distribute the cell region 7 to one side and the other side, and extends to the peripheral edge portion of the semiconductor substrate 6 to surround the cell region 7.

A temperature sense region 9 constituting the temperature sense element TS is formed in the inner region of the cell region 7. The temperature sense region 9 is surrounded by the cell region 7. The position of the temperature sense region 9 may be, for example, the peripheral portion of the semiconductor substrate 6. If the temperature sense region 9 is arranged on the peripheral edge of the semiconductor substrate 6, a relatively wide region can be secured on the semiconductor substrate 6 in a portion other than the temperature sense region 9, so that the area of the source pad 2 should be wide. Can be done. Therefore, even if the chip size is reduced, a wiring member such as a bonding plate or a relatively thick bonding wire can be connected to the source pad 2.

In a plan view, the first electrode 10 and the second electrode 11 are provided so as to sandwich the temperature sense region 9. That is, the paired first electrode 10 and the second electrode 11 are arranged on the semiconductor substrate 6 at intervals from each other, and the temperature sense region 9 is located in the region between the first electrode 10 and the second electrode 11. Is formed. The first electrode 10 and the second electrode 11 are arranged side by side along one side of the semiconductor substrate 6 in which the gate pad 3 is arranged, for example. As a result, wiring members such as bonding wires can be easily pulled out from each of the gate pad 3, the first electrode 10, and the second electrode 11 in the same direction (to the left of the paper in FIG. 3). Further, the first electrode 10 and the second electrode 11, and the source pad 2, the gate pad 3, and the gate finger 8 are made of an electrode film made of the same material. For example, after forming the electrode film on the semiconductor substrate 6, the electrode film is formed. It can be formed at the same time by patterning the electrode film.
<Cell structure>
FIG. 4A is a schematic plan view showing the structure (planar gate structure) of the cell region 7 of the semiconductor device 1 of FIG. FIG. 4B is a cross-sectional view of FIG. 4A (cross-sectional view taken along the line BB).

The semiconductor substrate 6 may be, for example, a SiC substrate, or may be a GaN substrate, a Si substrate, or the like. Further, the semiconductor substrate 6 may be an epitaxial substrate including a base substrate and an epitaxial layer in which crystals are grown. In this embodiment, the case where the semiconductor substrate 6 is an n-type SiC epitaxial substrate is shown. The n-type SiC epitaxial substrate may include an n ⁺ type base substrate and an n ⁻ type epitaxial layer on the n ⁺ type substrate. The impurity concentration of the n ⁺ type base substrate is, for example, 1.0 × 10 ¹⁸ cm ^-3 to 1.0 × 10 ²⁰ cm ^-3 , and the impurity concentration of the n ⁻ type epitaxial layer is, for example, 5.0 ×. It may be 10 ¹⁴ cm ^-3 to 5.0 × 10 ¹⁶ cm ^-3 . Examples of the n-type impurity include N (nitrogen), As (arsenic), P (phosphorus) and the like.

As shown in FIGS. 4A and 4B, a plurality of p-type body regions 12 are formed on the surface portion of the semiconductor substrate 6 in the cell region 7. The plurality of p-shaped body regions 12 may be formed in a planar matrix shape (matrix shape) as shown in FIG. 4A, or may be formed in a striped shape or a honeycomb shape. A line for partitioning each unit cell 13 of the switching element SW is set between adjacent p-type body regions 12. The p-type impurity concentration in the p-type body region 12 may be, for example, 1 × 10 ¹⁵ cm ^-3 to 1 × 10 ²⁰ cm ^-3 . Examples of the p-type impurity include B (boron) and Al (aluminum).

An n ⁺ -type source region 14 is formed on the surface of the inner region of the p-type body region 12 at a distance from the peripheral edge of the p-type body region 12. The concentration of n-type impurities in the n ^- type source region 14 is higher than the concentration of impurities in the n-type semiconductor substrate 6, and may be, for example, 1 × 10 ¹⁸ cm ^-3 to 5 × 10 ²¹ cm ^-3 .
A p ⁺ type body contact region 15 is formed in the inner region of the n ⁺ type source region 14. The p ⁺ type body contact region 15 is formed so as to penetrate the n ⁺ type source region 14 in the depth direction. The p-type impurity concentration in the p ^- type body contact region 15 is higher than that in the p-type body region 12, and may be, for example, 1 × 10 ¹⁸ cm ^-3 to 5 × 10 ²¹ cm ^-3 .

A gate insulating film 16 is formed on the surface of the semiconductor substrate 6. The gate insulating film 16 may be made of, for example, silicon oxide (SiO ₂ ). The thickness of the gate insulating film 16 may be, for example, 300 Å to 600 Å.
A gate electrode 17 is formed on the gate insulating film 16. The gate electrode 17 faces the peripheral portion of the p-type body region 12 (the portion surrounding the n ⁺ -type source region 14 in a plan view) with the gate insulating film 16 interposed therebetween. The gate electrode 17 is made of, for example, n-type polysilicon (n-type doped polysilicon), but may be made of p-type polysilicon. The thickness of the gate electrode 17 may be, for example, 6000 Å to 12000 Å.

An interlayer insulating film 18 covering the gate electrode 17 is formed on the entire surface of the semiconductor substrate 6. The interlayer insulating film 18 may be made of, for example, silicon oxide (SiO ₂ ), or may have a structure in which a plurality of films made of silicon oxide are laminated (FIGS. 7I to 7I). (See FIG. 7L). The thickness of the interlayer insulating film 18 (total thickness in the case of a plurality of films) may be, for example, 1000 Å to 2000 Å. Although not shown, the interlayer insulating film 18 includes wiring for electrically connecting the source pad 2 and the n ⁺ type source region 14 and the p ⁺ type body contact region 15, and a gate pad 3 and a gate electrode 17. Wiring that electrically connects the two is formed through each of them.
<Temperature sense element structure>
FIG. 5A is a schematic plan view showing the structure of the temperature sense region 9 of the semiconductor device 1 of FIG. FIG. 5B is a cross-sectional view of FIG. 5A (cross-sectional view taken along the line BB). FIG. 5C is a diagram showing a modified example of the structure of FIG. 5B.

As shown in FIGS. 5A and 5B, a p-type region 19 is formed on the surface portion of the semiconductor substrate 6 in the temperature sense region 9. The p-type region 19 may be the same conductive type impurity region as the p-type body region 12, and the p-type impurity concentration and depth thereof may be the same as the p-type body region 12.
On the surface of the semiconductor substrate 6, the gate insulating film 16 of the cell region 7 extends to the temperature sense region 9 and is formed. In the temperature sense region 9, a temperature sense diode 20 (pn diode) as an example of the temperature sense element TS is formed on the gate insulating film 16. The temperature sense diode 20 faces the semiconductor substrate 6 with the gate insulating film 16 interposed therebetween. For example, as shown in FIG. 5B, the entire temperature sense diode 20 may face a single impurity region (p-type region 19 in this embodiment) of the semiconductor substrate 6.

The temperature sense diode 20 is composed of, for example, a monolayer polysilicon layer 21. The temperature sense diode 20 made of the polysilicon layer 21 may be formed in the same layer as the gate electrode 17 by being formed in the same process as the gate electrode 17. That is, the polysilicon layer 21 may be formed to have a thickness of 6000 Å to 12000 Å, similarly to the gate electrode 17. Of course, the polysilicon layer 21 may be formed in a separate process from the gate electrode 17, or may have a thickness different from that of the gate electrode 17.

The temperature sense diode 20 includes a p-type region 22 and an n ⁺ -type region 23 surrounding the p-type region 22. If the p-type region 22 is surrounded by the n ⁺ type region 23, the p-type region 22 and the n ⁺ type region 23 do not overlap in a plan view, so that no separate wiring or the like is required, and the p-type region 22 and the p-type region 22 and Contact can be easily made to either of the n ⁺ type regions 23.

The p-type region 22 and the n ⁺ -type region 23 may be formed so as to reach from the front surface to the back surface of the polysilicon layer 21, respectively, as shown in FIG. 5B, and although not shown, the photoresist layer 21 may be formed. It may be selectively formed on the surface portion. The p-type region 22 does not have to be surrounded by the n ⁺ type region 23. For example, the p-type region 22 and the n ⁺ type region 23 are formed adjacent to each other so as to have one unshared peripheral edge. You may have it in the part. The concentration of p-type impurities in the p-type region 22 may be, for example, 1 × 10 ¹⁵ cm ^-3 to 1 × 10 ²⁰ cm ^-3 (same as the p-type body region 12). The n-type impurity concentration in the n ⁺ type region 23 may be, for example, 1 × 10 ¹⁸ cm ^-3 to 5 × 10 ²¹ cm ^-3 (same as the n ⁺ type source region 14).

The temperature sense diode 20 may further include a p ⁺ type contact region 24 and a p-type outer peripheral region 25. The p ⁺ type contact region 24 is formed in the inner region of the p-type region 22 at a distance from the peripheral edge of the p-type region 22, and the p-type outer peripheral region 25 is formed so as to surround the n ⁺ type region 23. May be. The p ⁺ type contact region 24 and the p-type outer peripheral region 25 may be formed so as to reach the back surface from the front surface of the polysilicon layer 21 as shown in FIG. 5B, respectively, and although not shown, the polysilicon layer may be formed. It may be selectively formed on the surface portion of 21. The p-type impurity concentration in the p ⁺ type contact region 24 may be, for example, 1 × 10 ¹⁸ cm ^-3 to 5 × 10 ²¹ cm ^-3 (same as the p ⁺ type body contact region 15). The p-type impurity concentration in the p-type outer peripheral region 25 may be, for example, 1 × 10 ¹⁵ cm ^-3 to 1 × 10 ²⁰ cm ^-3 (same as the p-type body region 12).

As shown in FIG. 5C, the temperature sense diode 20 includes a p-type base layer 26 made of a gate electrode 17 and an opposite conductive p-type polysilicon (p-type doped polysilicon), and the p-type base layer. It may have a configuration including an n ⁺ type region 23 and a p ⁺ type contact region 24 selectively formed on the surface portion of 26.
The temperature sense diode 20 is covered with an interlayer insulating film 18 on the semiconductor substrate 6. The first electrode 10 is connected to the p ⁺ type contact region 24 as an anode electrode via the contact hole 27 of the interlayer insulating film 18. The second electrode 11 is connected to the n ⁺ type region 23 as a cathode electrode via the contact hole 28 of the interlayer insulating film 18. As described above, the first electrode 10 and the second electrode 11 connected to both ends of the temperature sense diode 20 are formed separately from the source pad 2 and the gate pad 3 for the switching element SW. Therefore, the temperature sense diode 20 is electrically independent of the switching element SW.

Polysilicon can be easily formed into a desired shape and position by the already established semiconductor manufacturing technology. Therefore, the temperature sense diode 20 can be formed in the vicinity of the switching element SW and in the vicinity of the surface which is the heat generating portion of the semiconductor substrate 6, and the temperature change of the semiconductor substrate 6 can be detected with high accuracy. For example, by applying a constant current to the temperature sense diode 20 and monitoring the forward voltage _VF of the temperature sense diode 20, the temperature change of the semiconductor substrate 6 can be detected. For example, 1 μA may be applied as a constant current and the forward voltage _VF may be monitored. The current may be a constant current in the range of 1 μA to 100 μA.

The second electrode 11 integrally includes an annular contact portion 30 having an open portion 29 partially and a line-shaped lead-out portion 31 extending from the contact portion 30 on the interlayer insulating film 18. The contact portion 30 surrounds the p-shaped region 22 in a plan view. Further, the contact hole 28 is formed in an annular shape with a part open along the contact portion 30.
The first electrode 10 has a contact portion 32 surrounded by a contact portion 30 of the second electrode 11 on the interlayer insulating film 18, and a line-shaped drawing portion 33 extending from the contact portion 32 through the opening portion 29. Is included integrally. The contact portion 32 is arranged on the p ⁺ type contact region 24. Further, the contact hole 27 is formed so as to overlap below the contact portion 32.

Next, a method of manufacturing the semiconductor device 1 will be described. FIG. 6 is a flow chart of the manufacturing process of the semiconductor device 1. 7A to 7L are diagrams showing a part of the manufacturing process of the semiconductor device 1 in the order of processes. Note that FIGS. 7A to 7L do not correspond to each step in FIG. 6, respectively. Hereinafter, the manufacturing process of the semiconductor device 1 will be described according to the flow of FIG. 6, and FIGS. 7A to 7L will be referred to as necessary.

In order to manufacture the semiconductor device 1, for example, an n ^- type epitaxial layer is formed on an n ⁺ type base substrate by epitaxial growth (step S1). As a result, the semiconductor substrate 6 is formed.
Next, the p-type body region 12 and the p-type region 19 are formed by selectively injecting p-type impurities into the semiconductor substrate 6 (step S2). Similarly, by selectively injecting n-type impurities and p-type impurities into the semiconductor substrate 6, an n ⁺ type source region 14 and a p ⁺ type body contact region 15 are formed (steps S3 and S4).

Next, as shown in FIG. 7A, the gate insulating film 16 is formed on the surface of the semiconductor substrate 6 by thermally oxidizing the semiconductor substrate 6 (step S5). Next, for example, by the CVD method, the polysilicon layer 21 that is the base of the gate electrode 17 and the temperature sense diode 20 is formed (step S6). Next, for example, a hard mask 34 (for example, a thickness of about 9000 Å) made of silicon oxide (SiO ₂ ) is formed by a CVD method (step S7).

Next, as shown in FIG. 7B, a resist film 35 for lithography of the hard mask 34 is formed (step S8). The resist film 35 is formed so as to cover the hard mask 34 on the region 36 on which the p-type region 22 and the n ⁺ type region 23 should be formed.
Next, as shown in FIG. 7C, the hard mask 34 is selectively etched via the resist film 35 (step S9). Etching may be performed, for example, by wet etching with hydrofluoric acid. After etching, the resist film 35 is removed.

Next, as shown in FIG. 7D, n-type impurities (for example, phosphorus) are deposited in the region 37 exposed from the hard mask 34 of the polysilicon layer 21 (the region other than the region 36 of the polysilicon layer 21). For example, by diffusing at about 1000 ° C., n-type impurities are introduced into the region 37 (step S10). As a result, the region 37 including the gate electrode 17 portion of the polysilicon layer 21 becomes n-type polysilicon, while the region 36 is maintained in a non-doped state.

Next, as shown in FIG. 7E, the hard mask 34 remaining on the polysilicon layer 21 is removed by etching (step S11). Etching may be performed, for example, by wet etching with hydrofluoric acid.
Next, as shown in FIG. 7F, boron, which is a p-type impurity, is injected onto the entire surface of the polysilicon layer 21 in a state where the gate electrode 17 portion of the polysilicon layer 21 is selectively covered with a mask (not shown). (Step S12). As a result, the region from the surface of the polysilicon layer 21 to the middle in the thickness direction becomes the p-type region 38.

Next, as shown in FIG. 7G, a mask (not shown) that selectively exposes the region to form the n ⁺ type region 23 of the polysilicon layer 21 is formed by lithography, and then through the mask. , N-type impurities are injected into the region 36 (step S13). As a result, the n ⁺ type region 23 is formed. At this time, as shown in FIG. 7G, the n ⁺ type region 23 may be formed only halfway from the surface of the polysilicon layer 21 in the thickness direction.

Next, as shown in FIG. 7H, a mask (not shown) that selectively exposes the region to form the p ⁺ type contact region 24 of the polysilicon layer 21 is formed by lithography, and then through the mask. Then, the p-type impurity is injected into the region 36 (step S14). As a result, the p ⁺ type contact region 24 is formed. At this time, as shown in FIG. 7H, the p ⁺ type contact region 24 may be formed only halfway from the surface of the polysilicon layer 21 in the thickness direction.

Next, as shown in FIG. 7I, a hard mask 39 that selectively covers the region where the temperature sense diode 20 and the gate electrode 17 of the polysilicon layer 21 are to be formed is formed, and then the poly is formed through the hard mask 39. The silicon layer 21 is selectively etched. As a result, the temperature sense diode 20 and the gate electrode 17 (not shown in FIG. 7I) are formed.
Next, as shown in FIG. 7J, a plurality of insulating films are formed with the hard mask 39 left, for example, by a CVD method. As shown in FIG. 7J, the plurality of insulating films include a lower silicon oxide film 40 (for example, NSG (Non-doped Silicate Glass) film) and an upper silicon oxide film 41 (for example, PSG (Phosphorus Silicate)). Glass) film, BPSG (Boron Phosphorus Silicate Glass) film, etc.) may be included. As a result, the interlayer insulating film 18 composed of the hard mask 39, the silicon oxide film 40, and the silicon oxide film 41 is formed (step S15).

Next, as shown in FIG. 7K, the contact holes 27 and 28 are formed by selectively etching the interlayer insulating film 18 (step S16).
Next, as shown in FIG. 7L, the semiconductor substrate 6 is heat-treated (reflowed) (step S17). The heat treatment is performed, for example, in a nitrogen (N ₂ ) atmosphere at 900 ° C to 1200 ° C for 5 to 15 minutes. As a result, the p-type region 38, the n ⁺ type region 23, and the p ⁺ type contact region 24 remaining on the surface portion of the polysilicon layer 21 are diffused until they reach the back surface of the polysilicon layer 21.

After that, the semiconductor device 1 is obtained by forming various wirings, a source pad 2, a gate pad 3, a first electrode 10, a second electrode 11, a passivation film, and the like.
Next, the operation of the semiconductor device 1 in the semiconductor module 4 and the overcurrent protection method will be described more specifically.
The electrical circuit configuration of the semiconductor module 4 is as shown in FIG. A voltage is applied to the semiconductor device 1 so connected by the gate driver G / D. Specifically, with reference mainly to FIGS. 3 and 4B, a bias voltage is applied between the source pad 2 and the drain electrode (not shown) so that the drain electrode side becomes positive. As a result, a reverse voltage is applied to the pn junction at the interface between the n-type semiconductor substrate 6 and the p-type body region 12, and as a result, between the n ⁺ -type source region 14 and the semiconductor substrate 6, that is, the source-. The drains are cut off. In this state, when a predetermined voltage is applied between the source pad 2 and the gate pad 3 so that the gate pad 3 side becomes positive, a bias with respect to the p-type body region 12 is applied to the gate electrode 17. As a result, electrons are induced in the peripheral portion of the p-type body region 12 to form an inversion channel. The n ⁺ type source region 14 and the semiconductor substrate 6 conduct with each other via this inverting channel. In this way, the source and the drain become conductive and the drain current Id flows.

On the other hand, referring to FIGS. 5A and 5B, a constant current is applied to the temperature sense diode 20 by the gate driver G / D. Further, the short-circuit protection circuit 5 of the gate driver G / _D constantly monitors the forward voltage VF of the temperature sense diode 20. Normally, the IV characteristic of the temperature sense diode 20 draws a curve shown by a solid line in FIG. 8, for example.
When a short circuit occurs in the switching element SW (MISFET) of FIGS. 4A and 4B and an overcurrent flows, a temperature rise occurs on the surface side of the semiconductor substrate 6. Since this temperature rise is also transmitted to the temperature sense region 9 (see FIG. 5B) formed on the semiconductor substrate 6 common to the cell region 7, in the temperature sense region 9, the temperature sense diode 20 is accompanied by the temperature rise. The forward voltage _VF drops. For example, as shown by the curve shown by the broken line in FIG. 8, the rising voltage of the temperature sense diode 20 shifts to the low voltage side. The short-circuit protection circuit 5 senses this decrease in the forward voltage _VF as the occurrence of a short circuit in the switching element SW, and turns off the voltage applied to the gate pad 3. As a result, the drain current Id flowing between the source and drain (SD) of the switching element SW is cut off, and the switching element SW is protected.

In this way, when an overcurrent flows through the switching element SW due to, for example, a short circuit, the temperature rise of the semiconductor substrate 6 due to the overcurrent is detected based on the decrease in the forward voltage _VF of the temperature sense diode 20, and the detection is performed. According to the result, it can be determined whether or not an overcurrent is flowing in the switching element SW. Moreover, since the monitoring target is not the sense current flowing through the switching element SW, even if noise is included in the sense current and superimposed, it is not erroneously detected as an overcurrent due to the superimposed current. Therefore, it is possible to reduce malfunction due to current noise. Also, unlike the conventional overcurrent protection method, a fixed waiting time (mask time) is not provided, or even if it is provided, it can be done in a short time, so the time required for the device to be destroyed by overcurrent is relatively short. Very effective for devices (SiC, GaN, etc.).

Further, in this embodiment, as shown in FIG. 5B, since the temperature sense diode 20 is made of the polysilicon layer 21 which is the same layer as the gate electrode 17, the increase in the number of steps accompanying the formation of the temperature sense diode 20 is suppressed. be able to. Further, the temperature sense diode 20 can be arranged on the semiconductor substrate 6 via the gate insulating film 16 which is thinner than the relatively thick film such as the interlayer insulating film 18. Therefore, the position of the temperature sense diode 20 can be brought close to the current path on the surface side of the semiconductor substrate 6. This makes it possible to improve the accuracy of detecting the temperature change of the semiconductor substrate 6.

9A is a schematic plan view showing the structure of the temperature sense region 9 of the semiconductor device 1 of FIG. 9B is a cross-sectional view of FIG. 9A (cross-sectional view taken along the line BB). 9A and 9B show another example of the structure of the temperature sense region 9. In FIGS. 9A and 9B, the same components as those shown in FIGS. 5A and 5B described above are designated by the same reference numerals, and the description thereof will be omitted.
In FIGS. 5A and 5B, the temperature sense diode 20 is composed of the polysilicon layer 21 on the semiconductor substrate 6, whereas the temperature sense diode 42 (pn diode) in FIGS. 9A and 9B is the surface portion of the semiconductor substrate 6. It consists of an impurity region selectively formed in the diode. Specifically, the temperature sense diode 42 includes a p-type region 43 and an n ⁺ -type region 44 that surrounds the p-type region 43 in a plan view. If the p-type region 43 is surrounded by the n ⁺ type region 44, the p-type region 43 and the n ⁺ type region 44 do not overlap in a plan view, so that no separate wiring or the like is required, and the p-type region 43 and the p-type region 43 and Contact can be easily made to either of the n ⁺ type regions 44.

The p-type region 43 is composed of a part of the p-type region 19. On the other hand, the n ⁺ type region 44 is formed in a floating state on the surface portion of the p-type region 19. The n ⁺ type region 44 may be formed in the same process as the n ⁺ type source region 14 (see FIG. 4B). That is, the n ⁺ type region 44 may have an n-type impurity concentration of 1 × 10 ¹⁸ cm ^-3 to 5 × 10 ²¹ cm ^-3 like the n ⁺ type source region 14, and may have the same depth. It may be formed by a saucer.

The temperature sense diode 42 may further include a p ⁺ type contact region 45 and a p-type outer peripheral region 46. The p ⁺ type contact region 45 is formed in the inner region of the p-type region 43 at a distance from the peripheral edge of the p-type region 43, and the p-type outer peripheral region 46 is formed so as to surround the n ⁺ type region 44. May be. The p-type outer peripheral region 46 is composed of a part of the p-type region 19, and is electrically connected to the p-type region 43 via the p-type region 19 below the n ⁺ type region 44. On the other hand, the p ⁺ type contact region 45 is formed in a floating state on the surface portion of the p-type region 19. The p ⁺ type contact region 45 may be formed in the same process as the p ⁺ type body contact region 15 (see FIG. 4B). That is, the p ⁺ type contact region 45 may have a p-type impurity concentration of 1 × 10 ¹⁸ cm ^-3 to 5 × 10 ²¹ cm ^-3 , similarly to the p ⁺ type body contact region 15. It may be formed at the same depth.

The first electrode 10 is connected to the p ⁺ type contact region 45 as an anode electrode via the contact hole 27 of the interlayer insulating film 18. The second electrode 11 is connected to the n ⁺ type region 44 as a cathode electrode via the contact hole 28 of the interlayer insulating film 18.
As described above, the temperature sense diode 42 can also perform the same function as the temperature sense diode 20 described above. Further, since the temperature sense diode 42 is formed on the semiconductor substrate 6 itself, the pn junction can be brought closer to the current path on the surface side, which is the heat generating portion of the semiconductor substrate 6, than in the case of the temperature sense diode 20. As a result, the temperature change of the semiconductor substrate 6 can be detected with high accuracy. Further, a pn diode composed of an impurity region operates well even in a high temperature region (for example, 200 ° C. or higher), and is particularly effective for power devices such as SiC and GaN.

Next, variations in the connection form when a plurality of temperature sense diodes 20 and 42 are provided will be described. 10 to 14 are diagrams showing an example of the connection form of the temperature sense diodes 20 and 42, respectively. In addition, in FIGS. 10 to 14, among the constituent elements shown in FIGS. 5A and 9A described above, only the elements necessary for explanation are designated by reference numerals.
First, as shown in FIG. 10, the plurality of temperature sense diodes 20 and 42 are configured by connecting one first electrode 10 (anode) and the other second electrode 11 (cathode) in series. The series connection unit 47 may be included. As shown in FIG. 10, the series connection unit 47 may be composed of two temperature sense diodes 20 and 42, or may be composed of three or more temperature sense diodes 20 and 42 (not shown). good.

According to the configuration of FIG. 10, the temperature change amount (shift amount) of the forward voltage _VF shown in FIG. 8 increases in proportion to the number of connections of the temperature sense diodes 20 and 42, so that the temperature change detection sensitivity can be determined. Can be improved. For example, when the fluctuation width of the forward voltage VF per one of the temperature sense diodes 20 and 42 is _XmV / ° C., five temperature sense diodes 20 and 42 are connected in series to form a series connection unit 47. For example, the total swing width of the series connection unit 47 can be set to 5 XmV / ° C.

Next, as shown in FIG. 11, at least a pair of series connection units 47 may be connected in parallel in opposite directions to each other. That is, the terminal first electrode 10 of one series connection unit 47 is connected to the terminal second electrode 11 of the other series connection unit 47 to form a terminal 48, and the terminal second electrode 11 of one series connection unit 47 is the other. It may be connected to the terminal first electrode 10 of the series connection unit 47 and used as the terminal 49.

According to the configuration of FIG. 11, since the terminals 48 and 49 of the aggregate of the temperature sense diodes 20 and 42 in which the plurality of series connection units 47 are combined have no distinction between the anode side and the cathode side polarities, the semiconductor module 4 (FIG. 11). 2) When assembling etc., the degree of freedom of wiring such as bonding wire can be improved. That is, even if a reverse bias is applied to one series connection unit 47, a forward bias is applied to the other series connection unit 47 at that time, so that at least one can function as a temperature sense diode. ..

Next, as shown in FIG. 12, in the plurality of temperature sense diodes 20 and 42, one and the other first electrodes 10 (anodes) or one and the other second electrodes 11 (cathodes) are in series. It may include a reverse series connection unit 50 configured by being connected. The reverse series connection unit 50 may be composed of two temperature sense diodes 20 and 42 as shown in FIG. 12, or may be composed of three or more temperature sense diodes 20 and 42 (not shown). It is also good. Further, as shown in FIG. 13, a plurality of the reverse series connection units 50 may be connected in reverse series.

According to the configurations of FIGS. 12 and 13, a reverse bias is applied to at least one of the temperature sense diodes 20 and 42 constituting the reverse series connection unit 50, so that the reverse series connection unit 50 total The resistance in is high. Therefore, the current required for monitoring the temperature change of the temperature sense diodes 20 and 42 can be suppressed to a small value, and power saving can be achieved.

Next, as shown in FIG. 14, the temperature sense diodes 20 and 42 may include a configuration in which at least a pair of the temperature sense diodes 20 and 42 are connected in parallel in opposite directions to each other. That is, the first electrode 10 of one of the temperature sense diodes 20 and 42 is connected to the second electrode 11 of the other temperature sense diodes 20 and 42 to form a terminal 51, and the second electrode of one of the temperature sense diodes 20 and 42. 11 may be connected to the first electrode 10 of the other temperature sense diodes 20 and 42 to form a terminal 52.

According to the configuration of FIG. 14, as in the configuration of FIG. 11, since the terminals 51 and 52 of the aggregate of the temperature sense diodes 20 and 42 have no distinction between the anode side and the cathode side polarities, the semiconductor module 4 (FIG. 2). (See), etc. can be improved in the degree of freedom of wiring such as bonding wires when assembling. That is, even if a reverse bias is applied to one of the temperature sense diodes 20 and 42, a forward bias is applied to the other temperature sense diodes 20 and 42 at that time, so that at least one of them functions as a temperature sense diode. Can be made to.

As described above, the connection form of the plurality of temperature sense diodes 20 and 42 is not limited to the configurations shown in FIGS. 10 to 14, and any appropriate form can be adopted. Further, the concept of the connection form shown above (series, series + anti-parallel, anti-series, plurality of anti-series, anti-parallel, etc.) can be applied to the temperature sense diodes 66 of FIGS. 16A to 16C described later. can.
FIG. 15A is a schematic plan view showing the structure (trench gate structure) of the cell region 7 of the semiconductor device 1 of FIG. FIG. 15B is a cross-sectional view of FIG. 15A (cross-sectional view taken along the line BB). 15A and 15B show another example of the structure of the cell region 7. In FIGS. 15A and 15B, the same components as those shown in FIGS. 4A and 4B described above are designated by the same reference numerals, and the description thereof will be omitted.

As shown in FIGS. 15A and 15B, a gate trench 53 is formed in the semiconductor substrate 6 in the cell region 7. The gate trench 53 partitions each unit cell 54 of the switching element SW. The gate trench 53 may be formed in a planar grid shape as shown in FIG. 15A, or may be formed in a striped shape or a honeycomb shape, for example.

A p-type body region 55 is formed on the surface portion of each unit cell 54, and an n ⁺ -type source region 56 is formed on the surface portion of the p-type body region 55. The p-type impurity concentration in the p-type body region 55 may be, for example, 1 × 10 ¹⁵ cm ^-3 to 1 × 10 ²⁰ cm ^-3 . Further, the n-type impurity concentration in the n ⁺ -type source region 56 is higher than the impurity concentration in the n-type semiconductor substrate 6, and may be, for example, 1 × 10 ¹⁸ cm ^-3 to 5 × 10 ²¹ cm ^-3 .

A p ⁺ type body contact region 57 is formed in the inner region of the n ⁺ type source region 56. The p ⁺ type body contact region 57 is formed so as to penetrate the n ⁺ type source region 56 in the depth direction. The p-type impurity concentration in the p ^- type body contact region 57 is higher than that in the p-type body region 55, and may be, for example, 1 × 10 ¹⁸ cm ^-3 to 5 × 10 ²¹ cm ^-3 .

A gate insulating film 58 is formed on the inner surface of the gate trench 53 and the surface of the semiconductor substrate 6. The gate insulating film 58 may be made of, for example, silicon oxide (SiO ₂ ). The thickness of the gate insulating film 58 may be, for example, 300 Å to 600 Å.
A gate electrode 59 is embedded in the gate trench 53. The gate electrode 59 faces the p-shaped body region 55 on the side surface of the gate trench 53 with the gate insulating film 58 interposed therebetween. The gate electrode 59 is made of, for example, n-type polysilicon (n-type doped polysilicon), but may be made of p-type polysilicon.

Next, the structure of the temperature sense region 9 when the cell region 7 is FIG. 15A and FIG. 15B will be described. FIG. 16A is a schematic plan view showing the structure of the temperature sense region 9 of the semiconductor device 1 of FIG. 16B is a cross-sectional view of FIG. 16A (cross-sectional view taken along the line BB). 16C is a cross-sectional view of FIG. 16A (cross-sectional view taken along the line CC). In FIGS. 16A to 16C, the same components as those shown in FIGS. 5A and 5B described above are designated by the same reference numerals, and the description thereof will be omitted.

As shown in FIGS. 16A to 16C, the temperature sense region 9 is partitioned by the gate trench 53, and the periphery thereof is surrounded by the gate trench 53. As shown in FIG. 16A, the temperature sense region 9 may have, for example, a rectangular shape in a plan view surrounded by a gate trench 53 on all sides.
In the temperature sense region 9, an n ⁺ type region 60 is formed on the surface portion of the semiconductor substrate 6, and a p-type region 61 is formed below the n ⁺ type region 60. The p-type region 61 is in contact with the n ⁺ type region 60. The n ⁺ type region 60 may have the same n + type impurity concentration and depth as the n ⁺ type source region 56. Further, the p-type region 61 may have the same p-type impurity concentration and depth as the p-type body region 55, but the depth of the p-type region 61 may be the same as that of the p-type body region 55, as shown in FIGS. 16B and 16C. It may have a protrusion 62 that is deeper and selectively projects downward.

A temperature sense trench 63 as an example of the second trench of the present invention is formed in the inner region of the temperature sense region 9. That is, the temperature sense trench 63 is independent of the gate trench 53 that surrounds the temperature sense region 9. The temperature sense trench 63 may be formed, for example, with the same width as the gate trench 53.
The temperature sense trench 63 may be formed through the p-type region 61, but as shown in FIGS. 16B and 16C, the temperature sense trench 63 is formed on the protrusion 62 so as not to penetrate the p-type region 61. , The bottom thereof may be arranged inside the p-shaped region 61 (protruding portion 62).

Further, the temperature sense trench 63 is formed in an annular shape in a plan view, and a closed region 64 is partitioned inward thereof. A p ⁺ type contact region 65 is formed in the closed region 64. The p ⁺ type contact region 65 may be formed on the entire surface of the closed region 64 as shown in FIG. 16A, or may be selectively formed only on a part of the closed region 64 (not shown). .. The p ⁺ type contact region 65 may have the same p-type impurity concentration and depth as the p ⁺ type body contact region 57.

On the inner surface of the temperature sense trench 63, the gate insulating film 58 of the cell region 7 is formed so as to extend to the temperature sense region 9. A temperature sense diode 66 (pn diode) as an example of the temperature sense element TS is formed inside the gate insulating film 58.
The temperature sense diode 66 is composed of an embedded polysilicon layer 67 embedded in the temperature sense trench 63. The temperature sense diode 66 made of the embedded polysilicon layer 67 may be formed in the same process as the gate electrode 59, or may be formed in a separate process from the gate electrode 59.

The temperature sense diode 66 includes a p-type region 68 and an n ⁺ -type region 69 laterally adjacent to the p-type region 68. That is, the p-type region 68 is embedded to the bottom in a certain region of the annular temperature sense trench 63, and the n ⁺ type region 69 extends to the bottom in another region of the temperature sense trench 63 so as to be adjacent to the p-type region 68. It may be embedded. If the p-type region 68 and the n ⁺ type region 69 are adjacent to each other in the horizontal direction, the p-type region 68 and the n ⁺ type region 69 do not overlap in a plan view, so that no separate wiring or the like is required. Contact can be easily made to both the p-type region 68 and the n ⁺ type region 69.

The p-type impurity concentration in the p-type region 68 may be, for example, 1 × 10 ¹⁵ cm ^-3 to 1 × 10 ²⁰ cm ^-3 (same as the p-type body region 55). The n-type impurity concentration in the n ⁺ -type region 69 may be, for example, 1 × 10 ¹⁸ cm ^-3 to 5 × 10 ²¹ cm ^-3 (same as the n ⁺ -type source region 56).
The temperature sense diode 66 may further include a p ⁺ type contact region 70. The p ⁺ type contact region 70 is formed so as to be in contact with the p-type region 68, but is separated from the n ⁺ type region 69 by a p-type region 68. As shown in FIG. 16C, the p ⁺ type contact region 70 may be embedded up to the bottom of the temperature sense trench 63 and be laterally adjacent to the p-type region 68, or may be adjacent to the p-type region 68 in the lateral direction, although not shown, the p-type region 68 and the p-type region 68. It may be selectively formed on the surface portion of the p-type region 68 at a position away from the boundary with the n ⁺ type region 69. The p-type impurity concentration in the p ⁺ type contact region 70 may be, for example, 1 × 10 ¹⁸ cm ^-3 to 5 × 10 ²¹ cm ^-3 (same as the p ⁺ type body contact region 57).

The first electrode 10 in FIG. 3 is connected to the p ⁺ type contact region 70 as an anode electrode, and the second electrode 11 in FIG. 3 is connected to the n ⁺ type region 69 as a cathode electrode.
As described above, the temperature sense diode 66 can also perform the same function as the temperature sense diode 20 described above. Further, since the temperature sense diode 66 (pn diode) is embedded in the surface portion of the semiconductor substrate 6, the pn junction portion is connected to the current path on the surface side, which is the heat generating portion of the semiconductor substrate 6, as compared with the case of the temperature sense diode 20. Can be brought closer. As a result, the temperature change of the semiconductor substrate 6 can be detected with high accuracy.

Although one embodiment of the present invention has been described above, the present invention can also be implemented in other embodiments.
For example, a configuration in which the conductive type of each semiconductor portion of the semiconductor device 1 is inverted may be adopted. That is, in the semiconductor device 1, the p-type portion may be n-type and the n-type portion may be p-type.

Further, as the temperature sense element TS, in addition to the temperature sense diodes 20 and 42 (pn diode) described above, a Schottky barrier diode or the like can also be adopted.
In addition, various design changes can be made within the scope of the matters described in the claims.

1 Semiconductor device 2 Source pad 3 Gate pad 4 Semiconductor module 5 Short circuit protection circuit 6 Semiconductor substrate 7 Cell area 9 Temperature sense area 10 1st electrode 11 2nd electrode 12 p-type body area 13 Unit cell 14 n ⁺ type source area 16 Gate Insulating film 17 Gate electrode 20 Temperature sense diode 21 Polysilicon layer 22 p-type region 23 n ⁺ type region 24 p ⁺ type contact region 25 p-type outer peripheral region 26 p-type base layer 42 Temperature sense diode 43 p-type region 44 n ⁺ type Area 45 p ⁺ type contact area 46 p type outer peripheral area 47 series connection unit 48 terminal 49 terminal 50 reverse series connection unit 51 terminal 52 terminal 53 gate trench 54 unit cell 55 p type body area 56 n ⁺ type source area 58 gate insulating film 59 Gate electrode 63 Temperature sense trench 66 Temperature sense diode 67 Embedded polysilicon layer 68 p-type area 69 n ⁺ type area 70 p ⁺ type contact area SW switching element TS Temperature sense element G / D Gate driver

Claims (11)

A semiconductor chip with a substantially quadrangular plan view made of a semiconductor substrate,
A switching element that performs a switching operation between the first output electrode and the second output electrode according to a signal input to the control electrode formed on the semiconductor substrate.
A temperature having a first electrode provided on the surface side of the semiconductor substrate independently of the switching element and capable of outputting a temperature-dependent signal, and a second electrode arranged at a distance from the first electrode. Including sense element
The temperature sense element is a pn diode formed by introducing impurities into a polysilicon layer formed on the semiconductor substrate, and is formed in a temperature sense region between the first electrode and the second electrode. Includes pn diode
The first electrode and the second electrode are connected to terminals that are electrically independent from the terminals to which the first output electrode and the second output electrode of the switching element are connected .
The control electrode, the first electrode, and the second electrode have substantially the same size and shape as each other.
The control electrode, the first electrode, and the second electrode are semiconductors arranged independently of each other along the one side in order from the control electrode arranged at the center of one side of the semiconductor chip. Device. It has a gate finger that extends from the control electrode along the outer circumference of the semiconductor chip.
The semiconductor device according to claim 1, wherein the anode and cathode of the pn diode are connected to the first electrode and the second electrode, respectively. The semiconductor device according to claim 2, wherein the gate finger extends so as to cross the central portion of the semiconductor chip. The switching element according to any one of claims 1 to 3 , wherein the first output electrode is a source electrode, the second output electrode is a drain electrode, and the control electrode is a MISFET which is a gate electrode. The semiconductor device described. The switching element has a trench gate structure having a trench formed from the surface of the semiconductor substrate and a gate electrode embedded in the trench and electrically connected to the control electrode. The semiconductor device according to any one of claims 1 to 4 , which is a type MISFET. Between the temperature sense element and the switching element, a trench having the same structure as the control electrode forms a second conductive region formed on the surface of the semiconductor substrate on which the temperature sense element is formed in a plan view. The semiconductor device according to claim 5 , which is arranged so as to surround the semiconductor device. The semiconductor device according to any one of claims 1 to 6 , wherein the temperature sense element includes a series connection unit in which at least a pair of the pn diodes are connected in series. The semiconductor device according to any one of claims 1 to 7 , wherein the polysilicon layer forming the temperature sense element has the same thickness as the control electrode. Any of claims 1 to 8 , wherein the polysilicon layer forming the temperature sense element includes a second conductive type base layer and a first conductive type impurity region selectively introduced on the surface of the base layer. The semiconductor device according to one item. The switching element is formed on a second conductive type first semiconductor layer formed on the surface of the semiconductor substrate, a first conductive type second semiconductor layer formed on the surface thereof, and a back surface side of the semiconductor substrate. It also has a second conductive type third semiconductor layer.
The second semiconductor layer is connected to the first output electrode to be an emitter electrode, the third semiconductor layer is connected to the second output electrode to be a collector electrode, and the control electrode is an IGBT that serves as a gate electrode. The semiconductor device according to any one of claims 1 to 3 . The semiconductor device according to any one of claims 1 to 10 , wherein the semiconductor substrate includes a SiC semiconductor layer.

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