JP6718140B2 - Semiconductor device - Google Patents

Description

The technique disclosed by the present invention relates to a semiconductor device.

Patent Document 1 discloses a semiconductor device including a semiconductor substrate divided into a main element region and a sense element region. The main switching element is formed on the semiconductor substrate in the range corresponding to the main element region, and the sense switching element is formed on the semiconductor substrate in the range corresponding to the sense element region. The area of the main element region is larger than the area of the sense element region. The ratio of the current flowing through the main switching element and the current flowing through the sense switching element is substantially equal to the ratio of the total channel lengths formed in the main element region and the sense element region. Therefore, the current flowing through the main switching element can be known by detecting the current flowing through the sense switching element.

JP, 2006-93459, A

A surge may be applied to such a semiconductor device due to a load short circuit or the like.
Conventionally, in a semiconductor device including a sense element, the unit cell structure is often unified in the main element region and the sense element region.
Here, if the sense element is turned on before the main element due to manufacturing variations or the like, the load current concentrates on the sense element having a small area, and element breakdown due to the large current may occur in the sense element region. On the other hand, if a defect layer or the like is provided to limit the amount of current per unit area flowing in the sense element, it is necessary to increase the area of the sense element region in order to secure the amount of current used for current detection. Leads to larger semiconductor devices.

This specification describes a semiconductor device in which a main element region and a sense element region are formed on the same semiconductor substrate, and suppresses concentration of load current in the sense element region without increasing the size of the semiconductor device. The present invention provides a semiconductor device that does.

The present specification provides a semiconductor device in which a main element region and a sense element region having an area smaller than that of the main element region are formed on the same semiconductor substrate. The main element region is a second conductivity type first main semiconductor region formed on the front surface side of the semiconductor substrate, and a first conductivity type second main semiconductor layer formed on the back surface side of the first main semiconductor region. A third main semiconductor layer of the second conductivity type formed on the back surface side of the second main semiconductor layer, and a first main semiconductor region formed on the front surface of the semiconductor substrate along the first direction. A plurality of main trenches that penetrate the second main semiconductor layer and reach the third main semiconductor layer, a main gate insulating film that covers the inner surface of the main trench, and a main gate insulating film that is arranged inside the main trench. A main gate electrode insulated from the semiconductor substrate by. The sense element region is a second conductivity type first sense semiconductor region formed on the front surface side of the semiconductor substrate, and a first conductivity type second sense semiconductor layer formed on the back surface side of the first sense semiconductor region. A third sense semiconductor layer of the second conductivity type formed on the back surface side of the second sense semiconductor layer, and a first sense semiconductor region formed on the front surface of the semiconductor substrate along the first direction. A plurality of first sense trenches that penetrate the second sense semiconductor layer and reach the third sense semiconductor layer, and are formed on the surface of the semiconductor substrate at intervals in the first direction. And the second sense trench, which penetrates the second sense semiconductor layer to reach the third sense semiconductor layer and is connected to the first sense trench, and integrally covers the inner faces of the first sense trench and the second sense trench. A sense gate insulating film and a sense gate electrode disposed inside the first sense trench and the second sense trench and insulated from the semiconductor substrate by the sense gate insulating film. An area of the sense gate insulating film in contact with the second sense semiconductor layer per unit area of the sense element region is larger than an area of the main gate insulating film in contact with the second main semiconductor layer per unit area of the main element region.

According to the above configuration, by making the trench formed in the sense element region into a substantially lattice shape, the area where the gate insulating film is in contact with the body layer is defined as the unit area of the main element region per unit area of the sense element region. In this regard, the gate capacitance of the sense element region is made larger than that of the main element region by making the area of the gate insulating film in contact with the body layer larger. This delays the turn-on of the sense element later than the turn-on of the main element, and suppresses the load current from concentrating in the sense element region having a small area.
Further, by forming the trench gate formed in the sense element region in a substantially lattice shape, the channel area is increased and the area of the sense element region is reduced.

1 is a schematic circuit diagram of a semiconductor device. The top view of a semiconductor device is shown typically. FIG. 3 schematically shows a cross-sectional view of a main part of the semiconductor device, and is a cross-sectional view corresponding to line I-I of FIG. FIG. 3 schematically shows an enlarged view of a plan view of the semiconductor device, and is a plan view corresponding to a region II in FIG. 2 and a cross-sectional view corresponding to a line III-III in FIG. 3.

FIG. 1 is a schematic circuit diagram of a semiconductor device 1 according to an embodiment. The semiconductor device 1 includes an IGBT that constitutes the main switching element SW1 and the sense switching element SW2, a main emitter electrode 22, a sense emitter electrode 24, a collector electrode 28, and a gate pad 26. The main emitter electrode 22 is connected to the external electrode 44. The sense emitter electrode 24 is connected to the external electrode 44 via the sense resistor R1.

As shown in FIG. 2, the semiconductor device 1 has a semiconductor substrate 10 made of silicon. A plurality of main emitter electrodes 22, sense emitter electrodes 24, and gate pads 26 are formed on the surface of the semiconductor substrate 10. A gate wiring (not shown) electrically connected to the gate pad 26 is provided around the main emitter electrode 22 and between the adjacent main emitter electrodes 22. A collector electrode 28 is formed on the back surface of the semiconductor substrate 10. The range in which the main emitter electrode 22 is formed corresponds to the main element region 10A, and the range in which the sense emitter electrode 24 is formed corresponds to the sense element region 10B. Thus, the semiconductor substrate 10 is divided into the main element region 10A and the sense element region 10B, and the area of the main element region 10A is larger than the area of the sense element region 10B.

FIG. 3 is a cross-sectional view corresponding to the line I-I in FIG. As shown in FIG. 3, the main switching element SW1 is formed on the semiconductor substrate 10 in a range corresponding to the main element region 10A in which the main emitter electrode 22 is formed, and the sense emitter electrode 24 is formed in the sense. The sense switching element SW2 is formed on the semiconductor substrate 10 in the range corresponding to the element region 10B. An isolation range 10C in which no switching element is formed exists between the main element region 10A and the sense element region 10B.

The semiconductor substrate 10 has a collector region 11, a buffer region 12, a drift region 13, body regions 14A and 14B, body contact regions 15A and 15B, and emitter regions 16A and 16B. The collector region 11 is formed on the back surface side of the semiconductor substrate 10 and is a p-type region having a high p-type impurity concentration. Each of the collector regions 11 of the main switching element SW1 and the sense switching element SW2 is commonly connected to the collector electrode 28 and is in ohmic contact with the collector electrode 28. The buffer region 12 is arranged between the collector region 11 and the drift region 13, and is an n-type region. The drift region 13 is arranged between the buffer region 12 and the body region 14 and is an n-type region having a low n-type impurity concentration. Body regions 14A and 14B are arranged between drift region 13 and emitter regions 16A and 16B, and are p-type regions. The body region 14 is separated by the drift region 13 between the main element region 10A and the sense element region 10B. The body contact regions 15A and 15B are formed on the front surface side of the semiconductor substrate 10 and are connected to the body regions 14A and 14B, and are p-type regions having a high p-type impurity concentration. The body contact region 15A of the main switching element SW1 makes ohmic contact with the main emitter electrode 22. The body contact region 15B of the sense switching element SW2 makes ohmic contact with the sense emitter electrode 24. The emitter regions 16A and 16B are n-type regions that are formed on the front surface side of the semiconductor substrate 10 and are in contact with the body region 14 and have a high n-type impurity concentration. The emitter region 16A of the main switching element SW1 makes ohmic contact with the main emitter electrode 22. The emitter region 16B of the sense switching element SW2 is in ohmic contact with the sense emitter electrode 24.

FIG. 4 is an enlarged plan view corresponding to the area II in FIG. 2, and is a cross-sectional view corresponding to the line III-III in FIG. A plurality of trenches are formed on the front surface side of the semiconductor substrate 10. Here, as shown in FIG. 4, trenches are formed in a stripe pattern in the main element region 10A, and trenches are formed in a grid pattern in the sense element region 10B. Each trench penetrates the emitter regions 16A and 16B and the body regions 14A and 14B and reaches the drift region 13. Insulated trench gates 30A and 30B having gate insulating films 32A and 32B and gate electrodes 34A and 34B are formed in the respective trenches. The gate insulating films 32A and 32B are formed so as to cover the inner surface of the trench. The gate electrodes 34A and 34B are insulated from the semiconductor substrate 10 by the gate insulating films 32A and 32B. The gate electrodes 34A and 34B face the emitter regions 16A and 16B, the body regions 14A and 14B, and the drift region 13 via the gate insulating films 32A and 32B. An interlayer insulating film is formed on the gate electrodes 34A and 34B, the gate electrode 34A and the main emitter electrode 22 are insulated by the interlayer insulating film, and the gate electrode 34B and the sense emitter electrode 24 are also insulated by the interlayer insulating film. There is. The gate electrodes 34A and 34B are electrically connected to the gate pad 26 (see FIG. 2) by a gate wiring (not shown).

As described above, the main switching element SW1 includes the collector electrode 28, the collector region 11, the buffer region 12, the drift region 13, the body region 14A, the body contact region 15A, the emitter region 16A, the main emitter electrode 22, and the insulating trench gate 30A. It is configured. The sense switching element SW2 is composed of a collector electrode 28, a collector region 11, a buffer region 12, a drift region 13, a body region 14B, a body contact region 15B, an emitter region 16B, a sense emitter electrode 24 and an insulating trench gate 30B. There is. The main switching element SW1 switches the current flowing between the collector electrode 28 and the main emitter electrode 22 based on the gate voltage applied to the gate electrode 34. The sense switching element SW2 switches the current flowing between the collector electrode 28 and the sense emitter electrode 24 based on the gate voltage applied to the gate electrode 34.

According to the above configuration, by forming the trench 30B formed in the sense element region 10B into a substantially lattice shape, the area where the gate insulating film 32B is in contact with the body layer 14B per unit area of the sense element region 10B is The area per unit area of the element region 10A is larger than the area where the gate insulating film 32A is in contact with the body layer 14A. As a result, the gate capacitance of the sense element region 10B is made larger than that of the main element region 10A.

Next, the operation of the semiconductor device 1 will be described. When the main switching element SW1 and the sense switching element SW2 are turned on at the same time, a current flows from the collector electrode 28 toward the external electrode 44 (see FIG. 1). Most of the current flows via the main switching element SW1 (that is, the main emitter electrode 22). Part of the current flows through the sense switching element SW2 (that is, the sense emitter electrode 24). The current flowing through the sense switching element SW2 can be measured by the potential difference across the sense resistor R1. Further, the ratio of the current flowing through the main switching element SW1 and the current flowing through the sense switching element SW2 is substantially equal to the ratio of the total channel lengths formed in the main element region 10A and the sense element region 10B. Therefore, the current of the main switching element SW1 can be detected by detecting the current of the sense switching element SW2.

A surge may be applied to the semiconductor device 1 due to a load short circuit or the like. In the semiconductor device 1, the gate capacitance of the sense element region 10A is larger than the gate capacitance of the main element region 10B. Therefore, the turn-on of the sense switching element SW2 is delayed compared to the turn-on of the main switching element SW1, and the load current is concentrated in the small-sized sense element region 10B, which suppresses the element breakdown due to the large current in the sense element region 10B. To do. Further, by forming the trench gate formed in the sense element region in a substantially lattice shape, the channel area is increased and the area of the sense element region is decreased.

In the above, the example in which the trenches are formed in a stripe shape in the main element region 10A has been described. Instead of this example, also in the main element region 10A, trenches are partially formed in a grid pattern, and in the sense element region 10B, the area where the gate insulating film 32B is in contact with the body layer 14B is The structure may be such that the gate insulating film 32A is larger than the area in contact with the body layer 14A. In this case, on-resistance can be reduced in the main element region 10A.

1: semiconductor device 10: semiconductor substrate 10A: main element region 10B: sense element region 10C: isolation range 11: collector region 12: buffer region 13: drift region (third main region, third sense region)
14A, 14B: body region (second main region, second sense region)
15A, 15B: Body contact regions 16A, 16B: Emitter region (first main region, first sense region)
22: main emitter electrode 24: sense emitter electrode 26: gate pad 28: collector electrodes 30A, 30B: insulating trench gates 32A, 32B: gate insulating film (main gate insulating film, sense gate insulating film)
34A, 34B: Gate electrodes (main gate electrode, sense gate electrode)
SW1: Main switching element SW2: Sense switching element External resistance: R1

Claims (1)

A main device region, it said and a small sensing element region area than the main device region is a semiconductor device which is formed on the same semiconductor substrate,
The main element region is
A first main semiconductor region of a second conductivity type formed on the front surface side of the semiconductor substrate;
A second main semiconductor layer of a first conductivity type formed on the back surface side of the first main semiconductor region;
A third main semiconductor layer of a second conductivity type formed on the back surface side of the second main semiconductor layer;
A plurality of main trenches formed along the first direction on the surface of the semiconductor substrate, penetrating the first main semiconductor region and the second main semiconductor layer to reach the third main semiconductor layer; ,
A main gate insulating film covering the inner surface of the main trench;
A main gate electrode disposed inside the main trench and insulated from the semiconductor substrate by the main gate insulating film;
Equipped with
The sense element region is
A second sense type first sense semiconductor region formed on the front surface side of the semiconductor substrate;
A second sense semiconductor layer of a first conductivity type formed on the back surface side of the first sense semiconductor region;
A second sense type third sense semiconductor layer formed on the back surface side of the second sense semiconductor layer;
A plurality of first semiconductor layers are formed on the surface of the semiconductor substrate along the first direction and penetrate the first sense semiconductor region and the second sense semiconductor layer to reach the third sense semiconductor layer. With sense trench,
The semiconductor substrate is formed on the surface of the semiconductor substrate with a space in the first direction, penetrates the first sense semiconductor region and the second sense semiconductor layer, reaches the third sense semiconductor layer, and A second sense trench connected to the first sense trench;
A sense gate insulating film integrally covering inner surfaces of the first sense trench and the second sense trench;
A sense gate electrode disposed inside the first sense trench and the second sense trench and insulated from the semiconductor substrate by the sense gate insulating film;
Equipped with
The area of the sense gate insulating film contacting the second sense semiconductor layer per unit area of the sense element region contacts the second main semiconductor layer of the main gate insulating film per unit area of the main element region. A semiconductor device that is larger than the area.

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