JP2013105932A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which is capable of suitably performing protection by overcurrent detection and protection by temperature detection.SOLUTION: The semiconductor device comprises a semiconductor substrate. The semiconductor substrate comprises a main element region and a sub element region through which a current smaller than that flowing through the main element region flows. The sub element region is formed at a position overlapping the center of the semiconductor substrate in a plan view of the semiconductor substrate. A temperature detection element is formed at a position on the semiconductor substrate, which overlaps the sub element region in the plan view of the semiconductor substrate.

Description

  The present invention relates to a semiconductor device having a main element region and a sub-element region in which a smaller current flows than the main element region.

  Patent Document 1 discloses a semiconductor device having a main element region (main emitter) and a sub-element region (attached emitter). A smaller current flows in the sub element region than in the main element region. In this semiconductor device, energization of the entire semiconductor device is stopped when the current flowing through the sub-element region exceeds a predetermined value. This suppresses overcurrent from flowing through the main element region.

JP-A-8-204180

  When a current is passed through the semiconductor device, the semiconductor substrate generates heat. Since heat does not easily escape from the central portion of the semiconductor substrate, the central portion of the semiconductor substrate becomes the hottest when energized. For this reason, electrical resistance is higher in the central portion of the semiconductor substrate than in the outer peripheral portion of the semiconductor substrate. In the technique of Patent Document 1, the sub element region is formed on the outer peripheral portion of the semiconductor substrate. Since the outer peripheral portion of the semiconductor substrate has a lower temperature than the central portion, the electrical resistance is lowered. For this reason, current flows more easily in the sub element region than in the main element region. Therefore, it is difficult to predict the current at the time of overcurrent in the main element region, and it is difficult to appropriately protect the semiconductor device against overcurrent.

  In addition, although not as large as the above-described overcurrent, when a relatively large current flows through the semiconductor device continuously, the temperature of the semiconductor substrate excessively increases. In order to prevent such overheating of the semiconductor substrate, there is a semiconductor device having a temperature detection element.

  The present specification provides a semiconductor device capable of suitably performing protection by overcurrent detection and protection by temperature detection.

  A semiconductor device disclosed in this specification includes a semiconductor substrate. In this semiconductor device, a semiconductor substrate has a main element region and a sub-element region in which a smaller current flows than the main element region. The sub element region is formed at a position overlapping the center of the semiconductor substrate when the semiconductor substrate is viewed in plan. A temperature detection element is formed on the semiconductor substrate at a position overlapping the sub-element region when the semiconductor substrate is viewed in plan.

  In this semiconductor device, the sub-element region is formed at a position overlapping the center of the semiconductor substrate when the semiconductor substrate is viewed in plan. For this reason, it is possible to accurately detect the current in the central portion of the semiconductor substrate by detecting the current flowing through the sub-element region. Thereby, the semiconductor device can be suitably protected against overcurrent. In this semiconductor device, the temperature detection element is formed at a position overlapping the sub element region. For this reason, the temperature of the central part of the semiconductor substrate can be accurately detected by the temperature detection element. Thus, the semiconductor device can be suitably protected from overheating by detecting the temperature of the central portion of the semiconductor substrate where the temperature rises most easily.

  In the semiconductor device described above, the first upper electrode is formed on the semiconductor substrate in the main element region, the first conductivity type is in the main element region, and the first upper electrode is electrically connected to the first upper electrode. A region, a second conductivity type, a second region in contact with the first region, and a first conductivity type, in contact with the second region, separated from the first region by the second region. It is preferable that a first gate electrode is formed so as to face the third region and the second region in a range separating the first region and the third region via an insulating film. A second upper electrode separated from the first upper electrode is formed on the semiconductor substrate in the sub-element region, and is of the first conductivity type in the sub-element region and is electrically connected to the second upper electrode. The fourth region, the second conductivity type, the fifth region in contact with the fourth region, and the first conductivity type, in contact with the fifth region, and from the fourth region by the fifth region. It is preferable that a second gate electrode is formed opposite to the separated sixth region and the fifth region in a range separating the fourth region and the sixth region through an insulating film. .

  Note that one of the first conductivity type and the second conductivity type means n-type, and the other means p-type. In this configuration, an insulated gate type transistor is formed in the main element region, and an insulated gate type transistor is formed in the sub element region. Note that the insulated gate transistor may be an FET or an IGBT.

  In the semiconductor device described above, it is preferable that the temperature detection element is formed at a position overlapping the fourth region when the semiconductor substrate is viewed in plan.

  In the above-described semiconductor device, a contact connecting the fourth region to the second upper electrode is formed in a part of a range where the fourth region is exposed on the upper surface of the semiconductor substrate. It is preferable that an interlayer insulating film is formed in a portion other than the contact in the range exposed on the upper surface of the semiconductor substrate, and the temperature detecting element is formed on the interlayer insulating film.

3 is a top view of the semiconductor device 10 in which illustration of electrodes and insulating films on the semiconductor substrate 12 is omitted. FIG. FIG. 3 is a top view of the semiconductor device 10 showing the arrangement of the emitter electrode 40 and the temperature detection element 80 on the semiconductor substrate 12. The longitudinal cross-sectional view of the semiconductor device 10 in the III-III line | wire of FIG. FIG. 4 is a longitudinal sectional view of the semiconductor device 10 taken along line IV-IV in FIGS. The top view corresponding to FIG. 1 of the semiconductor device of a modification.

  A semiconductor device 10 shown in FIGS. 1 to 4 includes a semiconductor substrate 12 and electrodes, wirings, insulating films and the like formed on the surface of the semiconductor substrate 12. FIG. 1 shows the upper surface of the semiconductor substrate 12. As shown in FIG. 1, two annular p-type regions 70 and 72 are formed on the upper surface of the semiconductor substrate 12. As shown in FIG. 3, the p-type regions 70 and 72 extend from the upper surface of the semiconductor substrate 12 to a relatively deep position. A region inside the p-type region 70 is a sub-element region 20 in which a current detection element is formed. A region outside the p-type region 72 is a main element region 60 in which an element for supplying a main current is formed. The main element region 60 and the sub element region 20 are divided by p-type regions 70 and 72 and an n-type region 74 existing therebetween.

  A point 14 in FIG. 1 indicates the center of the semiconductor substrate 12 when the semiconductor substrate 12 is viewed in plan view from the upper surface side. As shown in FIG. 1, the sub element region 20 is formed so as to overlap the center 14 of the semiconductor substrate 12. That is, the center 14 is included in the sub-element region 20.

  As shown in FIG. 3, a trench is formed on the upper surface of the semiconductor substrate 12 in the sub-element region 20. The inner surface of the trench is covered with the gate insulating film 50. A gate electrode 52 is formed in the trench. Hereinafter, the gate insulating film 50 and the gate electrode 52 in the trench are collectively referred to as a trench gate electrode 54. As shown in FIG. 1, the trench gate electrode 54 extends along the X direction.

  As shown in FIG. 3, an n-type emitter region 22, a p-type body region 24, an n-type drift region 26, and a p-type collector region 28 are formed on the semiconductor substrate 12 in the sub-element region 20. Has been. The emitter region 22 is exposed in the upper surface of the semiconductor substrate 12 and is formed in a range in contact with the gate insulating film 50. As shown in FIG. 1, the emitter region 22 extends along the trench gate electrode 54 (that is, along the X direction). As shown in FIG. 3, the body region 24 is formed on the side and the lower side of the emitter region 22. The body region 24 is exposed on the upper surface of the semiconductor substrate 12 in a range where the emitter region 22 is not formed. The drift region 26 is formed below the body region 24. The drift region 26 is separated from the emitter region 22 by the body region 24. The drift region 26 is connected to the n-type region 74 between the p-type regions 70 and 72. The collector region 28 is formed below the drift region 26 and is exposed on the lower surface of the semiconductor substrate 12. An IGBT is formed in the sub-element region 20 by the emitter region 22, the body region 24, the drift region 26, the collector region 28, and the trench gate electrode 54.

  An emitter region 62, a body region 64, a drift region, a collector region, and a trench gate electrode 68 are also formed on the semiconductor substrate 12 in the main element region 60. As a result, an IGBT is formed in the main element region 60. As shown in FIG. 1, the trench gate electrodes 68 in the main element region 60 extend along the X direction and are formed at substantially the same interval as the trench gate electrodes 54 in the sub element region 20. As a result, the same collector-emitter breakdown voltage can be obtained in the sub-element region 20 and the main element region 60. Further, as shown in FIG. 1, the emitter region 62 in the main element region 60 extends along the Y direction (direction orthogonal to the X direction) (however, in other embodiments, the main element region 60). The inner emitter region 62 may extend along the trench gate electrode 68 in the same manner as the emitter region 22 of the sub-element region 20. The drift region in the main element region 60 is connected to the drift region 26 in the sub element region 20. The collector region in the main element region 60 is connected to the collector region 28 in the sub element region 20. When the semiconductor substrate 12 is viewed in plan view from the upper surface side, the area of the main element region 60 is larger than the area of the sub element region 20. For this reason, when the IGBT formed on the semiconductor substrate 12 is turned on, a larger current flows in the main element region 60 than in the sub element region 20.

  As shown in FIG. 3, a collector electrode 90 is formed on the lower surface of the semiconductor substrate 12. The collector electrode 90 is electrically connected to the collector region 28 in the sub element region 20 and the collector region in the main element region 60.

  Although not shown, an emitter electrode is formed on the semiconductor substrate 12 in the main element region 60. The emitter electrode in the main element region 60 is electrically connected to the emitter region 62 and the body region 64 in the main element region 60. The emitter electrode is insulated from the gate electrode in the main element region 60 by an interlayer insulating film.

  On the semiconductor substrate 12 in the sub-element region 20, a sub-element emitter electrode 92 and a temperature detection element 80 are formed. FIG. 2 shows the arrangement of the emitter electrode 92 and the temperature detection element 80. In consideration of the visibility of the figure, the emitter electrode 92 is indicated by a broken line in FIG.

  As shown in FIG. 2, the temperature detection element 80 includes a p-type polysilicon layer 82 and an n-type polysilicon layer 84. The p-type polysilicon layer 82 includes two portions 82a and 82b extending in the Y direction and a portion 82c that connects these portions 82a and 82b. The p-type polysilicon layer 82 is connected to an electrode pad (not shown) by a wiring 82d. The n-type polysilicon layer 84 includes two portions 84a and 84b extending in the Y direction and a portion 84c that connects these portions 84a and 84b. The tip of the portion 82a is in contact with the tip of the portion 84a, and the tip of the portion 82b is in contact with the tip of the portion 84b. The n-type polysilicon layer 84 is connected to an electrode pad (not shown) by a wiring 84d. The forward voltage at the pn junction between the p-type polysilicon layer 82 and the n-type polysilicon layer 84 changes according to the temperature. Therefore, the temperature of the semiconductor substrate 12 can be detected using the temperature detection element 80. As shown in FIG. 3, an interlayer insulating film 86 a is formed between the temperature detection element 80 (that is, the p-type polysilicon layer 82 and the n-type polysilicon layer 84) and the semiconductor substrate 12. The temperature detecting element 80 is insulated from the semiconductor substrate 12 by the interlayer insulating film 86a.

  As shown in FIG. 2, the emitter electrode 92 is formed on the semiconductor substrate 12 so as to cover the temperature detection element 80. The emitter electrode 92 is connected to an electrode pad (not shown) by a wiring 92a. As shown in FIG. 3, in the region where the temperature detecting element 80 exists, an interlayer insulating film 86b is formed on the temperature detecting element 80, and an emitter electrode 92 is formed on the interlayer insulating film 86b. The emitter electrode 92 is insulated from the temperature detecting element 80 by the interlayer insulating film 86b. In a region where the temperature detecting element 80 does not exist, a thick interlayer insulating film 86 is formed on the semiconductor substrate 12 as shown in FIG. A contact hole 94 that penetrates the interlayer insulating film 86 is formed in a region where the temperature detecting element 80 does not exist. The emitter region 22 and the body region 24 are connected to the emitter electrode 92 by the contact hole 94. An interlayer insulating film 86 exists on the trench gate electrode 54, and the gate electrode 52 is insulated from the emitter electrode 92 by the interlayer insulating film 86.

  The gate electrode 52 in the sub-element region 20 and the gate electrode in the main element region 60 are connected to a common electrode pad by wiring not shown. For this reason, the gate voltage of the IGBT in the sub element region 20 and the gate voltage of the IGBT in the main element region 60 are similarly controlled.

  Next, the operation of the semiconductor device 10 will be described. When the semiconductor device 10 is operated, the gate pad of the semiconductor device 10 is connected to an external gate drive circuit. When the emitter electrode 92 in the sub-element region 20 and the emitter electrode in the main element region 60 are connected to substantially the same low potential, the collector electrode 90 is connected to a high potential, and the gate drive circuit applies a gate voltage higher than the threshold value. The IGBTs in the sub-element region 20 and the main element region 60 are turned on. The gate drive circuit detects the current flowing through the sub-element region 20, and when the detected current exceeds a predetermined value, the gate drive circuit reduces the gate voltage below the threshold value. Thereby, the current of the IGBT is cut off and the IGBT is protected from overcurrent. Further, when a current is passed through the semiconductor device 10, the temperature of the semiconductor substrate 12 increases. The gate drive circuit reads the detected temperature of the temperature detecting element 80, and when the detected temperature exceeds a predetermined value, the gate drive circuit lowers the gate voltage below the threshold value. This interrupts the current of the IGBT and protects the IGBT from overheating.

  During energization, the region near the center 14 of the semiconductor substrate 12 is the highest temperature in the semiconductor substrate 12. In the semiconductor device 10, the sub element region 20 is formed at a position overlapping the center 14 of the semiconductor substrate 12. For this reason, the current in the sub-element region 20 accurately correlates with the current density at the center 14 of the semiconductor substrate 12. That is, the sub-element region 20 can accurately identify the current density at the center 14 of the semiconductor substrate 12 that operates under the most thermally disadvantageous condition. Therefore, the semiconductor device 10 can perform a more preferable overcurrent protection operation. That is, when the sub element region is formed near the outer periphery of the semiconductor substrate, the current density at the center of the semiconductor substrate cannot be accurately specified. This is because the electrical resistance is distributed in the semiconductor substrate due to the temperature distribution in the semiconductor substrate, and the correlation coefficient between the current flowing through the sub-element region and the current density at the center of the semiconductor substrate changes. Since the current density at the center of the semiconductor substrate cannot be accurately specified, the semiconductor device must be controlled with a certain margin with respect to the current value. For this reason, even when the current density at the center of the semiconductor substrate is not so high, the IGBT may be cut off. On the other hand, in the semiconductor device 10 of the present embodiment, the current density at the center 14 of the semiconductor substrate 12 and the current flowing through the sub-element region 20 are accurately correlated, so that the current density at the center 14 of the semiconductor substrate 12 is high. Only the IGBT can be cut off. Since the above margin can be reduced, the current that can be passed through the IGBT increases (or the element size can be reduced as compared with a conventional semiconductor device having the same current that can be passed through).

  In the semiconductor device 10, the temperature detection element 80 is formed at a position overlapping the sub element region 20. For this reason, the temperature detection element 80 can accurately detect the temperature of the region near the center 14 of the semiconductor substrate 12 that is at the highest temperature. Therefore, the semiconductor device 10 can perform a more preferable overheat protection operation. That is, when the temperature detection element is formed in the vicinity of the outer periphery of the semiconductor substrate, the temperature at the center of the semiconductor substrate cannot be accurately specified. This is because temperature distribution occurs in the semiconductor substrate. Since the temperature at the center of the semiconductor substrate cannot be specified accurately, the semiconductor device must be controlled with a certain margin with respect to the temperature. For this reason, even when the temperature at the center of the semiconductor substrate is not so high, the IGBT may be cut off. On the other hand, in the semiconductor device 10 of the present embodiment, the temperature near the center 14 of the semiconductor substrate 12 can be accurately specified by the temperature detection element 80, so that the temperature of the center 14 of the semiconductor substrate 12 is high. Only the IGBT can be blocked. Since the above margin can be reduced, the current that can be passed through the IGBT increases (or the element size can be reduced as compared with a conventional semiconductor device having the same current that can be passed through).

  As described above, the semiconductor device 10 can suitably execute both the overcurrent protection operation and the overheat protection operation. In the semiconductor device 10, since the sub-element region 20 and the temperature detection element 80 are formed so as to overlap each other, the element size can be reduced as compared with the semiconductor device in which these are formed at different positions.

  In the above-described embodiment, the temperature detecting element 80 is disposed so as to cross each trench gate electrode 54. However, as shown in FIG. 5, the temperature detection element 80 may be disposed on one trench gate electrode 54 along the trench gate electrode 54. In such a configuration, since a contact hole cannot be provided in the semiconductor region in the vicinity of the trench gate electrode 54 immediately below the temperature detection element 80, the contact hole is adjacent to the trench gate electrode 54 immediately below the temperature detection element 80. The emitter region may not be provided in the portion. That is, the trench gate electrode 54 immediately below the temperature detection element 80 can be a dummy. Thus, by providing the dummy trench gate electrode 54 immediately below the temperature detection element 80, the distance between the trench gate electrodes 54 can be made uniform between the sub element region 20 and the main element region 60. As a result, the collector-emitter breakdown voltage of the sub-element region 20 can be made comparable to that of the main element region 60. Such a configuration is preferable in a semiconductor device having a relatively low current density (for example, a semiconductor device having an interval between trench gate electrodes of 4 μm or more). In a semiconductor device in which the distance between the trench gates is narrower, it is difficult to form the temperature detecting element 80 as shown in FIG. 5, and therefore it is more preferable to form the temperature detecting element 80 as in the above-described embodiment. .

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

10: Semiconductor device 12: Semiconductor substrate 14: Center 20: Sub element region 22: Emitter region 24: Body region 26: Drift region 28: Collector region 50: Gate insulating film 52: Gate electrode 54: Trench gate electrode 60: Main element Region 80: Temperature detecting element 82: p-type polysilicon layer 84: n-type polysilicon layer 86: interlayer insulating film 86a: interlayer insulating film 86b: interlayer insulating film 90: collector electrode 92: emitter electrode 94: contact hole

Claims (4)

A semiconductor device having a semiconductor substrate,
The semiconductor substrate has a main element region and a sub element region through which a smaller current flows than the main element region,
The sub-element region is formed at a position overlapping the center of the semiconductor substrate when the semiconductor substrate is viewed in plan view,
A temperature detection element is formed on the semiconductor substrate at a position overlapping the sub-element region when the semiconductor substrate is viewed in plan view.
Semiconductor device. A first upper electrode is formed on the semiconductor substrate in the main element region,
In the main element area,
A first region of the first conductivity type and in conduction with the first upper electrode;
A second region of the second conductivity type and in contact with the first region;
A third region of the first conductivity type, in contact with the second region, and separated from the first region by the second region;
A first gate electrode opposed to a second region in a range separating the first region and the third region through an insulating film;
Is formed,
A second upper electrode separated from the first upper electrode is formed on the semiconductor substrate in the sub-element region;
In the sub-element region,
A fourth region of the first conductivity type and in conduction with the second upper electrode;
A fifth region of second conductivity type and in contact with the fourth region;
A sixth region of the first conductivity type, in contact with the fifth region and separated from the fourth region by the fifth region;
A second gate electrode facing the fifth region in a range separating the fourth region and the sixth region through an insulating film;
Is formed,
The semiconductor device according to claim 1.   The semiconductor device according to claim 2, wherein a temperature detection element is formed at a position overlapping the fourth region when the semiconductor substrate is viewed in plan. A contact connecting the fourth region to the second upper electrode is formed in a part of a range where the fourth region is exposed on the upper surface of the semiconductor substrate,
An interlayer insulating film is formed in a portion other than the contact in the range where the fourth region is exposed on the upper surface of the semiconductor substrate,
The semiconductor device according to claim 3, wherein the temperature detection element is formed on an interlayer insulating film.

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