JP6638662B2 - Semiconductor device - Google Patents

Description

  The technology disclosed in this specification relates to a semiconductor device.

  Patent Document 1 discloses a semiconductor device in which a temperature detecting diode is provided at the center of an element region of a semiconductor substrate. With the temperature detecting diode, the temperature of the semiconductor substrate can be measured during operation of the semiconductor device.

JP 2014-232803 A

  During operation of a semiconductor device, the temperature around an element region of a semiconductor substrate (hereinafter, referred to as a peripheral region) may become high. For example, the heat generation spot may change due to the distortion of the semiconductor substrate or the like, and the peripheral region may become hot. Further, depending on the usage environment of the semiconductor substrate, the peripheral region may be heated to a high temperature. Therefore, there is a need to measure the temperature in the peripheral region. This specification provides a technique capable of suitably detecting the temperature of a peripheral region of a semiconductor substrate.

  A semiconductor device disclosed in this specification includes a semiconductor substrate, an upper main electrode provided on an upper surface of the semiconductor substrate, a lower main electrode provided on a lower surface of the semiconductor substrate, and a gate electrode. The semiconductor substrate has an element region and a peripheral region arranged around the element region. The element region includes a switching element that turns on and off a current path between the upper main electrode and the lower main electrode according to a potential of the gate electrode. The semiconductor device includes a first wiring disposed on the upper surface of the semiconductor substrate in the peripheral region and connected to the gate electrode; a first wiring connected to the upper main electrode and the first wiring; A first semi-insulating film having a resistance changed by the first region, a second wiring disposed on the upper surface of the semiconductor substrate in the peripheral region, and disposed on the outer peripheral side of the semiconductor substrate with respect to the first wiring; A third wiring disposed on the upper surface of the semiconductor substrate and on the outer peripheral side of the semiconductor substrate with respect to the second wiring; a third wiring connected to the second wiring and the third wiring; And a second semi-insulating film that changes.

  In this semiconductor device, the resistance of the first semi-insulating film can be measured by flowing a current between the upper main electrode and the first wiring via the first semi-insulating film. The temperature of the semiconductor substrate at the position of the first semi-insulating film can be measured from the resistance of the first semi-insulating film. Further, by flowing a current between the second wiring and the third wiring via the second semi-insulating film, the resistance of the second semi-insulating film can be measured. The temperature of the semiconductor substrate at the position of the second semi-insulating film can be measured from the resistance of the second semi-insulating film. That is, according to this semiconductor device, the temperature of the peripheral region can be measured. Further, the temperature distribution in the peripheral region can be measured from the temperature of the first semi-insulating film and the temperature of the second semi-insulating film.

FIG. 2 is a cross-sectional view of the semiconductor device 10. FIG. 4 is a top view of a semiconductor substrate (a diagram showing a positional relationship between an upper main electrode 50 and a first wiring 71). FIG. 4 is a top view of a semiconductor substrate (a diagram showing a positional relationship between an upper main electrode 50 and a first wiring 71). FIG. 4 is a cross-sectional view of a semiconductor device.

  The semiconductor device 10 of the embodiment shown in FIG. The semiconductor substrate 18 has an element region 11 in which a switching element (in this embodiment, an IGBT (insulated gate bipolar transistor)) is provided, and a peripheral region 15 arranged around the element region 11. The element region 11 is provided in a range including the center of the semiconductor substrate 18. The peripheral region 15 is provided between the element region 11 and the outer peripheral end surface of the semiconductor substrate 18.

  A plurality of trenches 40 are provided on the upper surface 18a of the semiconductor substrate 18 in the element region 11. Each trench 40 extends in parallel on the upper surface 18a.

  The inner surface of each trench 40 is covered with a gate insulating film 32. In each trench 40, a gate electrode 30 is arranged. Each gate electrode 30 is insulated from the semiconductor substrate 18 by a gate insulating film 32. The upper surface of each gate electrode 30 is covered with an interlayer insulating film 66.

  An upper main electrode 50 is provided on the upper surface 18a of the semiconductor substrate 18 in the element region 11. The upper main electrode 50 has an AlSi layer 51 made of AlSi (an alloy of aluminum and silicon) and a Ni layer 52 made of nickel. The AlSi layer 51 covers the interlayer insulating film 66 and the upper surface 18a of the semiconductor substrate 18 in the element region 11. The Ni layer 52 covers the surface of the AlSi layer 51. Each gate electrode 30 is insulated from the upper main electrode 50 by an interlayer insulating film 66. The upper main electrode 50 is connected to a metal block 57 by a solder layer 58.

  The lower main electrode 56 is provided on the lower surface 18 b of the semiconductor substrate 18. The lower main electrode 56 covers substantially the entire area of the lower surface 18b of the semiconductor substrate 18.

  In the element region 11, an emitter region 22, a body region 24, a drift region 26, a buffer region 27, and a collector region 28 are arranged.

  Emitter region 22 is an n-type region. Two emitter regions 22 are provided in each semiconductor region between the trenches 40. The emitter region 22 is arranged in a range exposed on the upper surface 18a of the semiconductor substrate 18. Emitter region 22 is in contact with upper main electrode 50. Emitter region 22 is in contact with gate insulating film 32 at the top of trench 40.

  Body region 24 is a p-type region. The body region 24 is exposed on the upper surface 18a of the semiconductor substrate 18 between the two emitter regions 22. The body region 24 extends from a position exposed on the upper surface 18a to a position below the emitter region 22. The body region 24 has a high concentration region 24a and a low concentration region 24b having a lower p-type impurity concentration than the high concentration region 24a. The high-concentration region 24a is arranged in a range exposed on the upper surface 18a. The high concentration region 24a is in contact with the upper main electrode 50. The low-concentration region 24b is arranged below the emitter region 22. The low concentration region 24b is in contact with the gate insulating film 32 below the emitter region 22.

  Drift region 26 is an n-type region having a low n-type impurity concentration. The drift region 26 is arranged below the body region 24 in the element region 11. Drift region 26 is in contact with gate insulating film 32 below body region 24. Drift region 26 is separated from emitter region 22 by body region 24. Drift region 26 is distributed from element region 11 to peripheral region 15.

  Buffer region 27 is an n-type region having a higher n-type impurity concentration than drift region 26. The buffer region 27 is distributed over the element region 11 and the peripheral region 15. Buffer region 27 is arranged below drift region 26.

  Collector region 28 is a p-type region. Collector region 28 is distributed over element region 11 and peripheral region 15. Collector region 28 is arranged below buffer region 27. Collector region 28 is in contact with lower main electrode 56.

  In the peripheral region 15, a deep region 41, a resurf layer 42, and a termination region 44 are arranged.

  The deep region 41 is a p-type region and is provided in a range exposed on the upper surface 18a of the semiconductor substrate 18. The deep region 41 extends from the upper surface 18 a of the semiconductor substrate 18 to a depth substantially equal to each trench 40.

  The RESURF layer 42 is a p-type region. The resurf layer 42 is arranged on the outer peripheral side of the deep region 41. The resurf layer 42 is in contact with the deep region 41. The RESURF layer 42 is provided in a range exposed on the upper surface 18 a of the semiconductor substrate 18. The resurf layer 42 is distributed in a range shallower than the deep region 41.

  The termination region 44 is an n-type region having an n-type impurity concentration higher than that of the drift region 26. The termination region 44 is provided in a range exposed at the outermost peripheral portion of the upper surface 18a of the semiconductor substrate 18.

  The drift region 26 is distributed below the deep region 41, the resurf layer 42, and the termination region 44. Further, the drift region 26 is distributed between the termination region 44 and the RESURF layer 42.

  A first wiring 61, a second wiring 62, a third wiring 63, a first semi-insulating film 71, a second semi-insulating film 72, and an insulating protection layer 60 are provided on the upper surface 18a of the semiconductor substrate 18 in the peripheral region 15. Have been.

  The first wiring 61 is arranged near the upper main electrode 50. The first wiring 61 is connected to each gate electrode 30 at a position (not shown). That is, the first wiring 61 is a gate wiring. The first wiring 61 and the semiconductor substrate 18 are insulated by the insulating film 64. The first wiring 61 is made of AlSi.

  The first semi-insulating film 71 is composed of a SInSiN (semi-insulated silicon nitride) film. The first semi-insulating film 71 covers part of the surface of the upper main electrode 50, part of the surface of the first wiring 61, and the surface of the interlayer insulating film 66 between the upper main electrode 50 and the first wiring 61. ing. The upper main electrode 50 and the first wiring 61 are connected by the first semi-insulating film 71. The first semi-insulating film 71 allows a current to flow, but has a high resistance. Therefore, a potential difference can be generated between the upper main electrode 50 and the first wiring 61. The resistance of the first semi-insulating film 71 has a temperature characteristic. As the temperature increases, the resistance of the first semi-insulating film 71 decreases.

  Although not shown, a resistance measurement circuit for measuring the resistance of the first semi-insulating film 71 is provided outside the semiconductor device 10. This resistance measuring circuit measures the resistance of the first semi-insulating film 71 by passing a current between the upper main electrode 50 and the first wiring 61 via the first semi-insulating film 71. The temperature of the first semi-insulating film 71 can be measured from the resistance of the first semi-insulating film 71 measured by the resistance measuring circuit. The resistance measuring circuit may be a circuit that measures a current by applying a constant voltage, a circuit that measures a voltage by flowing a constant current, or another circuit. .

  The second wiring 62 is arranged on the outer peripheral side of the first wiring 61. The second wiring 62 is arranged above the deep region 41. A contact hole is provided in the interlayer insulating film 66 below the second wiring 62. The second wiring 62 is connected to the deep region 41 via this contact hole. The second wiring 62 is made of AlSi.

  The third wiring 63 is arranged on the outer peripheral side of the second wiring 62. The third wiring 63 is arranged above the termination region 44. A contact hole is provided in the interlayer insulating film 66 below the third wiring 63. The third wiring 63 is connected to the termination region 44 via this contact hole. The third wiring 63 is made of AlSi.

  The second semi-insulating film 72 is made of a SInSiN film. The second semi-insulating film 72 covers part of the surface of the second wiring 62, part of the surface of the third wiring 63, and the surface of the interlayer insulating film 66 between the second wiring 62 and the third wiring 63. ing. The second wiring 62 and the third wiring 63 are connected by the second semi-insulating film 72. The second semi-insulating film 72 allows current to flow, but has a high resistance. For this reason, a potential difference can be generated between the second wiring 62 and the third wiring 63. The resistance of the second semi-insulating film 72 has a temperature characteristic. As the temperature increases, the resistance of the second semi-insulating film 72 decreases.

  Although not shown, a resistance measuring circuit for measuring the resistance of the second semi-insulating film 72 is provided outside the semiconductor device 10. This resistance measurement circuit measures the resistance of the second semi-insulating film 72 by passing a current between the second wiring 62 and the third wiring 63 via the second semi-insulating film 72. The temperature of the second semi-insulating film 72 can be measured from the resistance of the second semi-insulating film 72 measured by the resistance measurement circuit.

  The insulating protection layer 60 is made of polyimide. The insulating protective layer 60 covers substantially the entire surface of the peripheral region 15.

  An IGBT is formed in the element region 11 by the emitter region 22, the body region 24, the drift region 26, the buffer region 27, the collector region 28, the gate electrode 30, and the like. The IGBT switches according to the potential of the gate electrode 30. When the IGBT is turned on, a current flows from the lower main electrode 56 to the upper main electrode 50. When the IGBT turns off, the current stops. When a current flows through the IGBT, the element region 11 generates heat. Normally, during the operation of the IGBT, the temperature of the center of the semiconductor substrate 18 becomes high, and the temperature becomes lower toward the outer periphery of the semiconductor substrate 18. That is, the temperature of the element region 11 becomes higher than that of the peripheral region 15. However, when a high current flows through the IGBT or the like, the metal block 57 and the solder layer 58 cannot sufficiently radiate heat, and the semiconductor substrate 18 may become hot near the outer peripheral end of the solder layer 58. . In this case, the temperature of the first semi-insulating film 71 located near the outer peripheral end of the solder layer 58 becomes high. Further, the temperature of the semiconductor substrate 18 may be high near the first semi-insulating film 71 depending on the distortion of the semiconductor substrate 18 or the operating environment of the IGBT. On the other hand, the temperature of the second semi-insulating film 72 located near the outermost peripheral portion of the semiconductor substrate 18 is lower than that of the first semi-insulating film 71. The temperature of the second semi-insulating film 72 is stable. As described above, these temperatures can be detected from the resistance of the first semi-insulating film 71 and the second semi-insulating film 72. That is, in the semiconductor device 10, the temperature of the peripheral region 15 can be detected. Further, the temperature distribution can be specified from the temperature difference between the first semi-insulating film 71 and the second semi-insulating film 72. When the temperature difference between the first semi-insulating film 71 and the second semi-insulating film 72 is large, it is understood that the temperature near the first semi-insulating film 71 is locally high. If the IGBT is feedback-controlled using the detected temperature, the temperature of the semiconductor substrate 18 can be more appropriately controlled.

  Further, in this semiconductor device 10, a temperature sensor can be constructed by the first semi-insulating film 71 between the upper main electrode 50 and the first wiring 61. The upper main electrode 50 is a main electrode of the IGBT, and the first wiring 61 is a gate wiring. According to this configuration, it is possible to provide a temperature sensor using the first semi-insulating film 71 without providing a dedicated wiring for temperature measurement.

  Further, in this semiconductor device 10, a temperature sensor can be constructed by the second semi-insulating film 72 between the second wiring 62 and the third wiring 63. The second wiring 62 and the third wiring 63 are wirings for suppressing the disturbance of the electric field distribution in the peripheral region 15 due to foreign ions (ions flying from the outside). According to this configuration, it is possible to provide a temperature sensor using the second semi-insulating film 72 without providing a dedicated wiring for temperature measurement.

  Further, in a temperature sensor using a semi-insulating film, variation in characteristics can be suppressed as compared with a temperature sensor using a diode. Therefore, the temperature can be accurately detected.

  The first semi-insulating film 71 and the second semi-insulating film 72 described above may be provided in an annular shape so as to surround the element region 11 or may be provided only in necessary places. For example, as shown in FIG. 2, an annular first semi-insulating film 71 may be provided so as to surround the upper main electrode 50, or as shown in FIG. A semi-insulating film 71 may be provided.

  In the above-described embodiment, the first semi-insulating film 71 and the second semi-insulating film 72 are composed of AlSi (ie, the AlSi layer 51, the first wiring 61, the second wiring 62, and the third wiring 63). ) Was partially covered. However, as shown in FIG. 4, the first semi-insulating film 71 and the second semi-insulating film 72 may be partially covered with a layer made of AlSi. That is, the first semi-insulating film 71 may be arranged in any manner as long as the upper main electrode 50 and the first wiring 61 are connected, and the second semi-insulating film 72 is formed of the second wiring 62 and the third wiring 63. May be arranged in any way as long as they are connected.

  The embodiments have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and alterations of the specific examples illustrated above. The technical elements described in the present specification or the drawings exhibit technical usefulness singly or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Further, the technology exemplified in the present specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

10: semiconductor device 11: element region 15: peripheral region 18: semiconductor substrate 22: emitter region 24: body region 26: drift region 27: buffer region 28: collector region 30: gate electrode 32: gate insulating film 40: trench 41: Deep area 42: RESURF layer 44: Terminating area 50: Upper main electrode 56: Lower main electrode 57: Metal block 58: Solder layer 60: Insulating protective layer 61: First wiring 62: Second wiring 63: Third wiring 71: First semi-insulating film 72: second semi-insulating film

Claims (1)

A semiconductor substrate;
An upper main electrode provided on the upper surface of the semiconductor substrate,
A lower main electrode provided on the lower surface of the semiconductor substrate,
Gate electrode,
Has,
The semiconductor substrate has an element region and a peripheral region arranged around the element region,
The element region has a switching element that turns on and off a current path between the upper main electrode and the lower main electrode according to a potential of the gate electrode,
A first wiring disposed on the upper surface of the semiconductor substrate in the peripheral region and connected to the gate electrode;
A first semi-insulating film connected to the upper main electrode and the first wiring, the resistance of which changes with temperature;
A second wiring disposed on the upper surface of the semiconductor substrate in the peripheral region and closer to the outer periphery of the semiconductor substrate than the first wiring;
A third wiring disposed on the upper surface of the semiconductor substrate in the peripheral region and closer to the outer periphery of the semiconductor substrate than the second wiring;
A second semi-insulating film connected to the second wiring and the third wiring, the resistance of which changes with temperature;
A semiconductor device further comprising:

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