JP2020065084A - Method of manufacturing semiconductor device - Google Patents

Abstract

To provide a method for manufacturing a trench gate type semiconductor device having a dummy trench MOS cell and having a low market failure rate.SOLUTION: First, on a front surface of an ntype semiconductor substrate 1 are formed a trench MOS cell having a gate electrode 8 extending in a depth direction of a device and a dummy trench MOS cell having a dummy gate electrode 18 extending in the depth direction of the device. Next, an emitter electrode 9 and a screening pad DG are formed on the front surface of the ntype semiconductor substrate 1. The dummy gate electrode 18 is connected to the screening pad DG. Next, a predetermined voltage is applied between the emitter electrode 9 and the screening pad DG to perform screening on a dummy gate insulating film 17. Next, a product is completed by short-circuiting the emitter electrode 9 and the screening pad DG with a plating film 13 that covers the emitter electrode 9 and the screening pad DG.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a method of manufacturing a semiconductor device.

  Conventionally, as a semiconductor device such as an IGBT (Insulated Gate Bipolar Transistor: Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a MOS gate (metal-oxide film) is formed in a trench. A trench gate type having an insulated gate structure made of a semiconductor is known. In the trench gate type semiconductor device, a large number of trench MOS cells having trench side walls as channel regions (inversion layers) are provided at predetermined intervals on a semiconductor substrate by a MOS gate structure formed in the trench.

  All trench MOS cells provided on the semiconductor substrate are normally at the gate potential. However, when all the trench MOS cells are operated at the same time, there is a problem that a parasitic thyristor is latched up due to excessive saturation current and the effective parasitic capacitance Qg is increased to increase switching loss. Therefore, there is proposed a device in which the number of trench MOS cells is reduced (thinned out) to increase the distance between adjacent trench MOS cells so that the trench MOS cells are not provided at high density. However, when the trench MOS cells are thinned out, there are problems that the electric field concentration at the bottom of the trench becomes large and the breakdown voltage of the device is lowered.

  As a device for solving this problem, in addition to the trench MOS cell having the gate potential, a trench MOS cell (hereinafter referred to as a dummy trench MOS cell) in which a channel region is not formed is provided on the side wall of the trench to form the dummy trench MOS cell. There has been proposed a device in which the dummy gate electrode for short-circuiting is shorted to the emitter electrode. By providing the dummy trench MOS cells having the emitter potential, the number of trench MOS cells having the gate potential can be reduced without thinning the trench MOS cells. Therefore, the effective parasitic capacitance Qg can be prevented from increasing and the electric field concentration at the bottom of the trench can be relaxed.

  In the manufacturing process of a trench gate type semiconductor device, normally, at the time of wafer inspection after the wafer process, by applying a voltage between the gate electrode in the trench and the semiconductor portion sandwiched between the trenches, the gate on the trench sidewall is gated. A predetermined voltage is applied to the insulating film, and screening is performed to evaluate the reliability of the gate insulating film. However, since the dummy gate electrode forming the dummy trench MOS cell has a potential (eg, emitter potential) other than the gate potential, no potential difference is generated between the dummy gate electrode and the semiconductor portion sandwiched between the trenches. Therefore, in the conventional screening, a voltage cannot be applied to the dummy gate insulating film forming the dummy trench MOS cell, and the reliability of the dummy gate insulating film cannot be measured.

  As a screening method for evaluating the reliability of the dummy gate insulating film forming the dummy trench MOS cell, the dummy gate electrode forming the dummy trench MOS cell is connected to the dummy gate pad, and the dummy pad electrode is connected to the emitter pad during the wafer inspection after the wafer process. A method of applying a voltage to the dummy gate insulating film by connecting a DC power supply between the dummy gate pad and the dummy gate pad has been proposed (for example, refer to Patent Document 1 below).

  Further, the following method has been proposed as another screening method. The outer peripheral region provided around the cell region is used as a region for routing the wiring of the IGBT element and the diode element. In this outer peripheral region, active regions between the trenches are connected, and a plurality of pads for electrically connecting the gate electrode or the trench electrode to the outside are provided. The gate electrode and the trench electrode are electrically connected to each pad (for example, refer to Patent Document 2 (paragraphs 0034 to 0036) below).

  Further, the following method has been proposed as another screening method. The first float wiring has a two-layer structure, and in the lower layer portion, a portion electrically connected to the doped Poly-Si connected to the dummy gate electrode and a portion electrically connected to the first float layer are separated by a predetermined distance. Make it a structure. Then, prior to the formation of the upper layer portion, a screening inspection step is performed (for example, refer to Patent Document 3 below).

  In the above-mentioned Patent Documents 1 and 2, the dummy gate electrode is electrically connected to the outside, and an external component such as a driver circuit for controlling the potential of the dummy gate electrode is required.

  Further, as a method of connecting the predetermined electrodes to each other, one of the plurality of conductive patterns, and a plurality of the other conductive pattern arranged so as to be separated from the one conductive pattern and sandwich the one conductive pattern. And a step of covering at least one conductive pattern of a portion sandwiched by the other conductive pattern with an insulating material, and a step between the plurality of other conductive patterns above the portion covered with the insulating material. A method including a step of electrically connecting by electrolytic plating has been proposed (for example, see Patent Document 4 below).

  As another method of connecting predetermined electrodes to each other, each of the plurality of devices is provided in association with each of the plurality of devices, and the plurality of devices are close to each other so as to be electrically isolated. Forming defective bridges and passing devices by individually testing multiple devices and measuring each device's functionality for given operating parameters. And a step of covering the bridging points of the defective device with a coating fluid to prevent solder leakage, and applying solder over the entire plurality of devices to separate them in close proximity. A step of electrically interconnecting the bridging points of the pass device by bridging the pads with a solder to electrically isolate the defective device into an electrically isolated state; Methods including has been proposed (e.g., Patent Document 5 reference.).

JP, 2013-251466, A JP, 2011-243695, A JP, 2010-050211, A JP 2006-186154 A JP-A-2-010855

  However, in the above Patent Document 3, in the active region and the runner wiring portion, a portion of the lower layer portion of the float wiring (metal wiring) electrically connected to the doped Poly-Si connected to the dummy gate electrode, and the first float layer. In order to form a structure in which a portion electrically connected to the substrate is separated at a predetermined interval, fine processing of metal wiring is required. For this reason, the process variations are likely to be adversely affected, and there is a risk that metal wirings formed at a predetermined interval may be short-circuited. Therefore, there is a problem that the reliability of the dummy gate insulating film cannot be evaluated by the screening, and the failure rate of the product after it is put on the market (hereinafter referred to as the market failure rate) becomes high.

  In order to solve the above-mentioned problems of the prior art, the present invention provides a trench gate type semiconductor device provided with a dummy trench MOS cell in which a channel region is not formed on a trench side wall, and a semiconductor device capable of reducing a market failure rate. It is intended to provide a manufacturing method.

  In order to solve the above-mentioned problems and achieve the object of the present invention, a method for manufacturing a semiconductor device according to the present invention includes a plurality of trench gate structures each including a gate electrode extending in the depth direction of an element, and the plurality of trenches. A method of manufacturing a semiconductor device, the gate structure of which includes a first trench gate structure that contributes to control of an element and a second trench gate structure that does not contribute to control of an element, and has the following features. First, a first step of forming the plurality of trench gate structures on the front surface side of the semiconductor substrate is performed. Next, a second step is performed on the front surface of the semiconductor substrate to form an electrode pad to which the gate electrodes of one or more of the trench gate structures among the plurality of trench gate structures are connected. Next, screening is performed by applying a predetermined voltage between an electrode portion having a potential other than the gate potential and the electrode pad, and applying the predetermined voltage to a gate insulating film in contact with the gate electrode connected to the electrode pad. The third step is performed. Next, a fourth step including a dicing step of singulating the semiconductor substrate and a back surface soldering step of soldering the back surface of the singulated semiconductor substrate is performed. After the fourth step, a fifth step of forming the second trench gate structure including the gate electrode connected to the electrode pad by short-circuiting the electrode part and the electrode pad is performed. The electrode portion is an emitter electrode electrically connected to a portion of the semiconductor substrate along the trench of the trench gate structure. The emitter electrode has an emitter electrode pad having the same potential as the emitter electrode. In the fifth step, a first wire bonding step of connecting between the emitter electrode pad and the screening electrode pad, and a second wire bonding step of connecting between a wiring layer of an insulating substrate and the gate electrode pad. ,including. The method further includes a plating step of forming a plating film on the front surface of the semiconductor substrate between the second step and the third step.

  Further, the manufacturing method of the semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the second predetermined voltage is the same voltage as the first predetermined voltage.

  In order to solve the above problems and achieve the object of the present invention, a method for manufacturing a semiconductor device according to the present invention includes a plurality of trench gate structures each including a gate electrode extending in the depth direction of an element, and a plurality of trench gate structures. A method of manufacturing a semiconductor device, wherein the trench gate structure includes a first trench gate structure that contributes to device control and a second trench gate structure that does not contribute to device control, and has the following characteristics. First, a first step of forming the plurality of trench gate structures on the front surface side of the semiconductor substrate is performed. Next, on the front surface of the semiconductor substrate, a gate electrode pad to which one or more of the plurality of trench gate structures constituting the first trench gate structure are connected, and a plurality of gate electrode pads are connected. A second step of forming a screening electrode pad to which the gate electrode forming one or more second trench gate structures of the trench gate structure is connected is performed. Next, a third step of forming a plating film on the front surface of the semiconductor substrate is performed. Next, a predetermined voltage is applied between the electrode portion having a potential other than the gate potential and the screening electrode pad, and the predetermined voltage is applied to the gate insulating film in contact with the gate electrode connected to the screening electrode pad. The fourth step of performing the screening is performed. Next, a fifth step including a dicing step of singulating the semiconductor substrate and a back surface soldering step of soldering the back surface of the singulated semiconductor substrate is performed. Next, a sixth step of electrically connecting the electrode portion and the screening electrode pad to form the second trench gate structure including the gate electrode connected to the screening electrode pad is performed. In the sixth step, the emitter electrode pad having the same potential as the electrode portion and the screening electrode pad are connected by wire bonding.

  Further, in the method of manufacturing a semiconductor device according to the present invention, in the above-mentioned invention, the sixth step includes a wire bonding step of connecting a wiring layer of an insulating substrate and the gate electrode pad. .

  Also, in the method for manufacturing a semiconductor device according to the present invention, in the above-mentioned invention, an electrode terminal is provided on the electrode portion on the front surface of the semiconductor substrate separated into individual pieces between the fifth step and the sixth step. It is characterized in that a front surface soldering step of soldering is performed.

  According to the above-described invention, in the MOS semiconductor device having the second trench gate structure having a potential other than the gate potential (for example, the emitter potential), the gate insulating film having the second trench gate structure and the electrode portion are provided until screening is performed. By electrically disconnecting the gate electrode of the second trench gate structure, a predetermined voltage is applied between the electrode portion and the gate electrode of the second trench gate structure during the manufacturing process, It is possible to screen a gate insulating film having a trench gate structure. Thus, after dicing the semiconductor wafer, it is possible to remove the semiconductor chip in which the gate insulating film of the second trench gate structure is defective. Further, according to the above-described invention, after screening the gate insulating film of the second trench gate structure, the electrode portion and the second trench are formed in various steps (eg, plating step and assembly step) for manufacturing (manufacturing) a semiconductor device. Even if the gate insulating film of the second trench gate structure is screened during the manufacturing process in order to short-circuit the gate electrode of the gate structure, the electrode portion and the gate electrode of the second trench gate structure are separated at the end of the product process. The product can be completed in a short-circuited state.

  The method for manufacturing a semiconductor device according to the present invention has an effect of reducing the market failure rate in a trench gate type semiconductor device including a dummy trench MOS cell in which a channel region is not formed on the side wall of a trench.

FIG. 3 is a cross-sectional view showing an example of a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first exemplary embodiment. FIG. 3 is a plan view showing a planar layout of each electrode pad of the semiconductor device according to the first exemplary embodiment. It is a top view which expands and shows the screening pad vicinity of FIG. FIG. 3 is a cross-sectional view showing a cross-sectional structure taken along the section line A-A ′ in FIG. 2. 3 is a flowchart showing an outline of a method for manufacturing a semiconductor device according to the first embodiment. FIG. 6 is a plan view showing a planar layout of each electrode pad of the semiconductor device according to the second exemplary embodiment. FIG. 9 is a plan view showing another example of a planar layout of each electrode pad of the semiconductor device according to the second exemplary embodiment. It is a top view which expands and shows the screening pad vicinity of FIG. 9 is a flowchart showing an outline of a method of manufacturing a semiconductor device according to a third embodiment. FIG. 11 is a plan view showing a planar layout of each electrode pad of the semiconductor device according to the third exemplary embodiment. 9 is a flowchart showing an outline of a method of manufacturing a semiconductor device according to a fourth embodiment. FIG. 11 is a plan view showing a planar layout of each electrode pad of the semiconductor device according to the fourth exemplary embodiment. FIG. 13 is a cross-sectional view showing a cross-sectional structure taken along the section line B-B ′ of FIG. 12. FIG. 11 is a plan view showing another example of a planar layout of each electrode pad of the semiconductor device according to the third exemplary embodiment. FIG. 11 is a plan view showing another example of a planar layout of each electrode pad of the semiconductor device according to the third exemplary embodiment. FIG. 11 is a plan view showing another example of a planar layout of each electrode pad of the semiconductor device according to the third exemplary embodiment.

  Preferred embodiments of a method for manufacturing a semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In the present specification and the accompanying drawings, it is meant that electrons or holes are majority carriers in the layers or regions prefixed with n or p. In addition, + and − attached to n and p mean that the impurity concentration is higher and the impurity concentration is lower than that of the layer or region not attached thereto, respectively. In the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same configurations, and duplicate description will be omitted.

(Embodiment 1)
First, a structure of a trench gate type IGBT will be described as an example of a semiconductor device manufactured (manufactured) by the method for manufacturing a semiconductor device according to the first embodiment. FIG. 1 is a sectional view showing an example of a semiconductor device manufactured by the method for manufacturing a semiconductor device according to the first embodiment. FIG. 1A schematically shows a state at the time of screening during manufacturing. FIG. 1B schematically shows a state after assembly. As shown in FIG. 1, in the semiconductor device according to the first embodiment, a trench having sidewalls of a trench 6 as a channel region (inversion layer) is formed on an n ⁻ type semiconductor substrate (semiconductor chip) 1 serving as an n ⁻ type drift layer. A MOS cell (first trench gate structure), a trench MOS cell (hereinafter referred to as dummy trench MOS cell (second trench gate structure)) in which a channel region is not formed on the side wall of a trench (hereinafter referred to as dummy trench) 16; Equipped with.

Specifically, the p-type base layer 2 is provided on the surface layer of the front surface of the n ⁻ type semiconductor substrate 1 in the active region in which a current flows in the ON state. The p-type base layer 2 is divided into a plurality of regions (hereinafter, referred to as first and second base regions) by a plurality of trenches that penetrate the p-type base layer 2 in the depth direction from the front surface of the substrate and reach the n ⁻ -type drift layer. It is divided into 3 and 4. The plurality of trenches are arranged, for example, in a striped plane pattern extending in a direction parallel to the front surface of the substrate. The plurality of trenches includes one or more trenches 6 in which trench MOS cells are formed and the remaining dummy trenches 16 in which dummy trench MOS cells are formed.

The trench MOS cell has a trench gate type MOS gate structure including a gate electrode 8 extending in the depth direction of the device. Specifically, the trench MOS cell includes the first base region 3, the n ⁺ type emitter region 5, the trench 6, the gate insulating film 7 and the gate electrode 8. The first base region 3 is a portion of the p-type base layer 2 sandwiched between the adjacent trenches 6 and the dummy trenches 16 and between the adjacent trenches 6. The n ⁺ type emitter region 5 is selectively provided inside the first base region 3 so as to be exposed at the sidewall of the trench 6. Inside the trench 6, a gate insulating film 7 is provided along the sidewall of the trench 6, and a gate electrode 8 is provided inside the gate insulating film 7. All the gate electrodes 8 are electrically connected to the gate pad G via a general gate runner (not shown) provided on the front surface of the substrate so as to surround the active region, for example. The gate electrode 8 and a dummy gate runner described later are electrically insulated by, for example, an interlayer insulating film 10 covering the gate electrode 8.

On the other hand, the dummy trench MOS cell has a trench gate type MOS gate structure provided with a dummy gate electrode 18 extending in the depth direction of the element and not contributing to control of the element. Specifically, the dummy trench MOS cell includes the second base region 4, the dummy trench 16, the dummy gate insulating film 17, and the dummy gate electrode 18. The second base region 4 is a portion of the p-type base layer 2 sandwiched between the adjacent dummy trenches 16. The n ⁺ type emitter region 5 is not provided inside the second base region 4. A dummy gate insulating film 17 is provided inside the dummy trench 16 along the sidewall of the dummy trench 16, and a dummy gate electrode 18 is provided inside the dummy gate insulating film 17.

  The dummy gate electrode 18 is electrically insulated from the gate electrode 8 by the dummy gate insulating film 17 and the interlayer insulating film 10. In addition, all the dummy gate electrodes 18 are electrode pads (hereinafter referred to as screening) provided for screening through, for example, dummy gate runners (not shown) arranged in the inside or outside of the gate runner in the same configuration as the gate runner. Electrically connected to DG (referred to as a pad). The dummy gate electrode 18 and the gate runner are electrically insulated by, for example, the interlayer insulating film 10 covering the dummy gate electrode 18. Further, when the product is completed, the dummy gate electrode 18 is short-circuited to an electrode portion (for example, an external circuit (not shown) or an emitter electrode 9 described later) having a potential other than the gate potential via the screening pad DG. Here, a case where the emitter electrode 9 and the dummy gate electrode 18 are short-circuited will be described as an example. The size of the screening pad DG can be variously changed, but by making the size as small as possible, it is possible to reduce the ineffective region that is not involved in the device operation.

The emitter electrode 9 is in contact with the first and second base regions 3 and 4 and the n ⁺ -type emitter region 5 through a contact hole penetrating the interlayer insulating film 10 in the depth direction, and is also connected to the gate electrode 8 by the interlayer insulating film 10. It is electrically isolated. Further, during screening for measuring the breakdown voltage of the gate insulating film 7 and the dummy gate insulating film 17, the emitter electrode 9 is electrically insulated from the dummy gate electrode 18 (FIG. 1A). On the other hand, the emitter electrode 9 is short-circuited to the screening pad DG by the metal member (plating film 13 described later) after the screening and before the completion of the assembled product, so that the dummy gate electrode 18 is short-circuited as described above. (Fig. 1 (b)). The thickness of the emitter electrode 9 may be, for example, 0.5 μm or more and 10 μm or less.

The plating film 13 is formed so as to cover the emitter electrode 9 and the screening pad DG, and short-circuits the emitter electrode 9 and the screening pad DG. The thickness of the plating film 13 may be, for example, 0.5 μm or more and 10 μm or less. The plating film 13 has a function of enhancing adhesion to a solder layer (not shown) when soldering a copper (Cu) block (not shown) to be an electrode terminal to the emitter electrode 9 and the screening pad DG, for example. On the front surface of the n ⁻ type semiconductor substrate 1, a polyimide extending from the edge termination structure portion surrounding the active region to the active region side and covering the edge termination structure portion and the portion of the active region on the edge termination structure portion side. The film is provided as a front surface protection film (not shown). The edge termination structure portion is a region that relaxes the electric field on the front surface side of the substrate of the n ⁻ type drift layer and maintains the breakdown voltage.

A p ⁺ -type collector layer 11 is provided on the front surface layer of the n ⁻ -type semiconductor substrate 1. An n-type field stop layer (not shown) may be provided at a position deeper than the p ⁺ -type collector layer 11 in the surface layer on the back surface of the n ⁻ -type semiconductor substrate 1. In the n-type field stop layer, a depletion layer extending from the pn junction on the front surface side of the substrate (the pn junction between the first base region 3 and the n ⁻ type drift layer) reaches the p ⁺ type collector layer 11 when turned off. It has a function to prevent it. The collector electrode 12 is in contact with the p ⁺ type collector layer 11.

  During the screening for measuring the breakdown voltage of the gate insulating film 7 and the dummy gate insulating film 17 during the manufacturing of the semiconductor device according to the first embodiment described above, the dummy gate electrode 18 and the emitter electrode 9 are electrically connected to each other as described above. It is in a state of being electrically insulated (FIG. 1A). That is, the dummy gate electrode 18 is in a state of being electrically insulated (separated) from the first and second base regions 3 and 4. Therefore, for example, the second base region 4 that opposes the dummy gate electrode 18 via the dummy gate insulating film 17 on the sidewall of the dummy trench 16 (the dummy gate electrode 18 is arranged at a position adjacent to the gate electrode 8). In this case, a predetermined voltage is applied between the first base region 3) and the withstand voltage of the dummy gate insulating film 17 is measured to perform screening for evaluating the reliability of the dummy gate insulating film 17. be able to.

  Specifically, the screening for evaluating the reliability of the dummy gate insulating film 17 is performed by a screening pad DG to which all dummy gate electrodes 18 are connected and an emitter connected to the first, second base regions 3 and 4. A predetermined voltage is applied between the electrodes 9. The predetermined voltage applied between the dummy gate electrode 18 and the emitter electrode 9 during screening is equal to or higher than the voltage applied to the dummy gate electrode 18 when the product is used and less than the dielectric breakdown voltage of the dummy gate insulating film 17. Good. Although not particularly limited, for example, when the thickness of the dummy gate insulating film 17 is about 1000Å, the dielectric breakdown voltage is about 80V. In addition, a voltage of about 15 V is usually applied to the dummy gate insulating film 17 when the product is used. Therefore, the predetermined voltage applied between the dummy gate electrode 18 and the emitter electrode 9 during the screening may be, for example, 15 V or more and less than 80 V.

  In this screening, it is only necessary to remove the semiconductor chip which may be destroyed due to deterioration over time due to factors such as the thickness of the dummy gate insulating film 17 being partially thinned. . That is, it suffices if a semiconductor chip capable of withstanding aging deterioration and less likely to fail can be identified by screening. For example, when the dummy gate insulating film 17 is defective, the defective semiconductor chip cannot be detected by a general wafer inspection, and the dummy gate insulating film 17 has a voltage lower than a predetermined dielectric breakdown voltage due to deterioration over time. May be destroyed. In addition, usually, the dielectric breakdown voltage of the dummy gate insulating film 17 is set sufficiently larger than the voltage that may be actually applied to the dummy gate insulating film 17 when the product is used, in consideration of a safety margin against deterioration over time. To be done. Therefore, the predetermined voltage applied between the dummy gate electrode 18 and the emitter electrode 9 at the time of screening may be a voltage value larger than the rated voltage (upper limit value set in product specifications). The value may be lower than the dielectric breakdown voltage of 17. Specifically, the predetermined voltage applied between the dummy gate electrode 18 and the emitter electrode 9 at the time of screening may be about 20V or 30V when the rated voltage is, for example, 15V. The breakdown voltage may be about 80% (≈65 V) or less.

  When the semiconductor device according to the first embodiment described above is completed, the emitter electrode 9 and the screening pad DG are short-circuited by the plating film 13 as described above. Next, the arrangement of the screening pad DG when the plating film 13 is used as a metal member for short-circuiting the emitter electrode 9 and the screening pad DG will be described. FIG. 2 is a plan view showing a planar layout of each electrode pad of the semiconductor device according to the first exemplary embodiment. FIG. 3 is an enlarged plan view showing the vicinity of the screening pad of FIG. FIG. 4 is a cross-sectional view showing the cross-sectional structure taken along the section line A-A ′ in FIG. 2. The plating film 13 is omitted in FIG. 2 (the same applies to FIGS. 6 and 7).

  As shown in FIGS. 2 to 4, the emitter electrode 9 is arranged, for example, near the center of the active region 1a. The emitter pad E is an auxiliary pad that has the same potential as the emitter electrode 9 that passes the main current. General electrode pads such as the emitter pad E and the gate pad G are arranged outside the inner end 14a of the front surface protection film 14 (for example, near the boundary between the active region 1a and the edge end region 1b). It The gate pad G, the emitter pad E, and the like have openings (not shown) in the front surface protection film 14 at locations where wires and the like are to be bonded. The screening pad DG is arranged, for example, in the vicinity of the outer periphery of the emitter electrode 9 at a predetermined distance w from the emitter electrode 9. That is, one side of the substantially rectangular screening pad DG faces the emitter electrode 9.

  The screening pad DG has only to be arranged at a position where it can be short-circuited with the emitter electrode 9, and may be arranged in the active region or the edge termination region. Further, it is preferable that the screening pad DG is disposed inside (on the side of the center of the chip) the inner end (inner end) 14a of the front surface protection film 14. The reason why it is preferable to dispose the screening pad DG inside the inner end 14a of the front surface protection film 14 is as follows. A plating film 13 is formed on the emitter electrode 9 and the screening pad DG. The plating film 13 spreads on the basis of its wettability, and spreads over the entire surface of the substrate from the central portion of the substrate to the inner end 14a of the front surface protection film 14 (hereinafter referred to as wet spread). . Therefore, by disposing the screening pad DG inside the inner terminal 14a of the front surface protection film 14, it is possible to reliably fill the gap between the emitter electrode 9 and the screening pad DG with the plating film 13. is there.

  That is, the distance w between the emitter electrode 9 and the screening pad DG is set to a size such that the emitter electrode 9 and the screening pad DG are short-circuited via the plating film 13 that spreads wet from the emitter electrode 9 and the screening pad DG. Has become. Specifically, the plating film 13 has a width similar to its own thickness (thickness of the portion on the emitter electrode 9 and the screening pad DG) t, and from the side of the emitter electrode 9 to the side of the screening pad DG and the screening. It spreads from the pad DG side to the emitter electrode 9 side. Therefore, the distance w between the emitter electrode 9 and the screening pad DG may be twice or less the thickness t of the plating film 13 (w ≦ 2t). More specifically, for example, the thickness t of the plating film 13 may be about 5 μm, and the distance w between the emitter electrode 9 and the screening pad DG may be about 10 μm or less.

Next, a method of manufacturing the semiconductor device according to the first embodiment will be described in detail. FIG. 5 is a flowchart showing an outline of the method of manufacturing the semiconductor device according to the first embodiment. First, according to a general method, a trench MOS cell having a trench sidewall as a channel region and a dummy trench not having a channel region formed on the trench sidewall are formed on the front surface side of an n ⁻ type semiconductor wafer to be an n ⁻ type drift layer. And a MOS cell. Specifically, in the active region 1a, a semiconductor portion (p-type base layer 2 and n ⁺ -type emitter region 5) forming a MOS gate structure is formed on the surface layer of the front surface of the n ⁻ -type semiconductor wafer ( Step S1).

Next, a trench 6 penetrating the p-type base layer 2 and the n ⁺ -type emitter region 5 to reach the n ⁻ -type drift layer is formed in the depth direction from the front surface of the wafer, and the trench 6 is deeply formed from the front surface of the wafer. A dummy trench 16 penetrating the p-type base layer 2 in the depth direction and reaching the n ⁻ -type drift layer is formed (step S2). In step S2, the trench 6 and the dummy trench 16 divide the p-type base layer 2 into a plurality of regions (first, second base regions 3, 4). Next, the gate insulating film 7 is formed inside the trench 6 along the inner wall of the trench 6, and the dummy gate insulating film 17 is formed inside the dummy trench 16 along the inner wall of the dummy trench 16 (step. S3).

Next, a polysilicon (poly-Si) layer is formed on the front surface of the n ⁻ type semiconductor wafer so as to be embedded in the trench 6 and the dummy trench 16. Then, the polysilicon layer is etched back, and the polysilicon layers to be the gate electrode 8 and the dummy gate electrode 18 are left inside the trench 6 and the dummy trench 16 (step S4). Next, the interlayer insulating film 10 is formed so as to cover the front surface of the wafer (step S5). Next, the interlayer insulating film 10 is selectively removed to form a contact hole, and the first and second base regions 3, 4 and the n ⁺ -type emitter region 5 are exposed inside the contact hole.

  Next, for example, an aluminum (Al) electrode (front surface electrode) formed on the entire front surface of the wafer so as to be embedded in the contact hole is patterned to form the emitter electrode 9, the screening pad DG and each electrode pad ( Step S6). Next, after the front surface of the wafer is covered with the front surface protection film 14 (step S7), the front surface protection film 14 is patterned to expose the emitter electrode 9, the screening pad DG and each electrode pad. . At this time, the emitter electrode 9 and the screening pad DG are exposed to the inside of the inner end 14a of the front surface protection film 14. Also, at any timing up to the step S7, each gate electrode 8 and gate pad G are connected via a gate runner, and each dummy gate electrode 18 and screening pad DG are connected via a dummy gate runner. To do.

  Next, screening is performed to evaluate the reliability of the gate insulating film 7 and the dummy gate insulating film 17 (step S8). Specifically, in the screening for evaluating the reliability of the dummy gate insulating film 17, the dummy gate insulating film 17 is applied by applying a predetermined voltage between the emitter electrode 9 and the dummy gate electrode 18 as described above. The withstand voltage of can be measured. That is, a predetermined voltage is applied between the emitter electrode 9 and the screening pad DG. The screening for evaluating the reliability of the gate insulating film 7 may be performed by applying a predetermined voltage between the emitter electrode 9 and the gate electrode 8 and measuring the breakdown voltage of the gate insulating film 7. That is, for example, the same voltage as the screening for the dummy gate insulating film 17 is applied between the emitter electrode 9 and the gate pad G. The screening result of each semiconductor chip is stored in the evaluation device for screening as electronic information based on, for example, a unique identification number of the semiconductor wafer and site information in which the position of each chip of each semiconductor wafer is addressed. Section or an external storage section.

Next, after forming a semiconductor portion (p ⁺ type collector layer 11 or n type field stop layer) on the back surface side of the n ⁻ type semiconductor wafer, a collector electrode 12 in contact with the p ⁺ type collector layer 11 is formed as a back surface electrode. (Step S9). Next, the plating film 13 is formed on the emitter electrode 9 and the screening pad DG. At this time, the emitter electrode 9 and the screening pad DG are short-circuited (short-circuited) by utilizing the wet spread of the plating film 13. That is, the emitter electrode 9 and the dummy gate electrode 18 are short-circuited (step S10).

  Next, general wafer inspection except screening is performed (step S11). In step S11, as a wafer inspection, for example, a WAT (Wafer Acceptance Test) for evaluating whether or not the device normally operates by applying electricity is performed. Specifically, in the wafer inspection, the threshold voltage, the presence / absence of leakage current, the ON voltage, etc. are evaluated. Further, in step S11, after the wafer inspection, based on the electronic information stored in the storage section in the screening of step S8 and the wafer inspection result, the semiconductor chip determined to be a non-defective product and the semiconductor chip determined to be defective. Mark so that can be identified. Specifically, for example, a predetermined mark such as a pattern, a character, or a bar code is marked (added) on all the semiconductor chips determined to be defective.

  In this way, the marking on the semiconductor chip is performed after the plating film 13 is formed. Thereby, it is possible to prevent the plating solution used for forming the plating film 13 from being adversely affected by the marking on the semiconductor chip. In addition, after the screening, the plating result for forming the plating film 13 can be reliably maintained until dicing into individual chips, so that the semiconductor film can be reliably maintained even after the plating film 13 is formed. It is possible to accurately recognize the predetermined mark added to the chip. Here, the case where the screening result of step S8 is stored as electronic information is described as an example, but it is sufficient that marking on the semiconductor chip can be performed after the plating film 13 is formed, and another method is used. Good.

  Next, the semiconductor wafer is diced (cut) into individual chips (step S12). At this time, the semiconductor chips determined to be defective in the screening in step S8 and the wafer inspection in step S11 are removed. Specifically, for example, after dicing a semiconductor wafer, a semiconductor chip that is determined to be defective and to which a predetermined mark is added is left as it is on a stage (stage on which the semiconductor wafer is placed during dicing), and a semiconductor chip that is determined to be a good product. Only (that is, the semiconductor chip to which the predetermined mark is not added) is picked up (taken out) and conveyed to the next assembly process.

  Next, a general assembly process for mounting the semiconductor chip on the package is performed. Specifically, the back surface of the semiconductor chip is soldered (mounted) to an insulating substrate (not shown) such as a DCB (Direct Copper Bonding) substrate (step S13). As described above, since only the semiconductor chips that are determined to be non-defective are picked up, the semiconductor chips that are determined to be defective are not mounted on the DCB substrate. Therefore, in the wiring process described later, it is not necessary to perform the wiring process except for the semiconductor chip which is determined to be defective, and the process can be simplified. After that, the emitter electrode 9 and the emitter pad E are connected to each other and the emitter pad E and the gate are connected by wire bonding or soldering (wireless bonding) of the front surface of the chip to a copper block (not shown) to be an electrode terminal. By performing a wiring process for connecting the pads G to predetermined electrode leads (not shown) (step S14), the trench gate type IGBT shown in FIG. 1B is completed.

  As described above, according to the first embodiment, in the MOS semiconductor device including the dummy trench MOS cell having a potential (eg, emitter potential) other than the gate potential, screening of the gate insulating film having the second trench gate structure is performed. By performing a state where the emitter electrode and the dummy gate electrode are electrically separated until performing, a predetermined voltage is applied between the emitter electrode and the dummy gate electrode during the manufacturing process, and the dummy gate insulating film is applied to the dummy gate insulating film. Screening can be done. As a result, after dicing the semiconductor wafer, it is possible to remove the defective semiconductor chip due to the dummy gate insulating film being partially thin. Further, according to the embodiment, after screening the dummy gate insulating film, the emitter electrode and the dummy gate electrode are formed in various steps for manufacturing the IGBT (specifically, a plating step performed on the front surface electrode). Because of the short circuit, even if the dummy gate insulating film is screened during the manufacturing process, the product can be completed with the emitter electrode and the dummy gate electrode having the trench gate structure short-circuited at the end of the product process. Therefore, it is possible to provide a trench gate type semiconductor device having a dummy trench MOS cell in which a channel region is not formed on the trench side wall and having a low market failure rate.

(Embodiment 2)
Next, the structure of the semiconductor device manufactured by the method for manufacturing a semiconductor device according to the second embodiment will be described. FIG. 6 is a plan view showing a planar layout of each electrode pad of the semiconductor device according to the second exemplary embodiment. The sectional structure taken along the section line AA ′ of FIG. 6 is similar to that of the first embodiment (FIG. 4). FIG. 7 is a plan view showing a planar layout of another example of each electrode pad of the semiconductor device according to the second exemplary embodiment. FIG. 8 is an enlarged plan view showing the vicinity of the screening pad of FIG. The semiconductor device manufactured by the method of manufacturing a semiconductor device according to the second embodiment is different from the semiconductor device manufactured by the method of manufacturing a semiconductor device according to the first embodiment in that two or more sides around the screening pad DG are emitters. It is a point facing the electrode 9.

  Specifically, as shown in FIG. 6, the screening pad DG is arranged, for example, on the outer peripheral portion of the emitter electrode 9 such that the three sides thereof are opposed to the emitter electrode 9. Further, as shown in another example of FIG. 7, the screening pad DG may be arranged at the center of the emitter electrode 9 and four sides thereof may face the emitter electrode 9. As shown in FIG. 8, the distance w between the screening pad DG and the emitter electrode 9 is, for example, all three sides of the screening pad DG facing the emitter electrode 9 (in the case of another example of FIG. 7, although not shown). May have the same size on all four sides facing the emitter electrode 9.

  As described above, according to the second embodiment, the same effect as that of the first embodiment can be obtained.

(Embodiment 3)
Next, a method of manufacturing the semiconductor device according to the third embodiment will be described. FIG. 9 is a flowchart showing the outline of the method of manufacturing the semiconductor device according to the third embodiment. FIG. 10 is a plan view showing a planar layout of each electrode pad of the semiconductor device according to the third exemplary embodiment. The semiconductor device manufacturing method according to the third embodiment differs from the semiconductor device manufacturing method according to the first embodiment in the following two points. The first difference is that the gate insulating film 7 and the dummy gate insulating film 17 are screened at the time of wafer inspection. The second difference is that the emitter electrode 9 and the screening pad DG are short-circuited by wire bonding in the assembly process.

Specifically, first, after sequentially performing from the step of forming the semiconductor portion forming the MOS gate structure to the step of forming the front surface protective film 14 (steps S21 to S27), the n ⁻ type semiconductor wafer is formed. The step of forming the semiconductor portion on the back surface side, the step of forming the back surface electrode (step S28) and the plating step (step S29) are sequentially performed. In the third embodiment, for example, the gap w between the emitter electrode 9 and the screening pad DG is wider than the width of the wet spread of the plating film, so that the emitter electrode 9 and the screening pad DG are short-circuited in the plating process of step S29. Not done. The method of forming the constituent portion in each of these steps is the same as that in the first embodiment.

Next, a wafer inspection is performed (step S30). During the wafer inspection, the gate insulating film 7 and the dummy gate insulating film 17 are screened. Then, based on the wafer inspection result (including the screening result), as in the first embodiment, marking is performed so that the semiconductor chip determined to be a good product and the semiconductor chip determined to be defective can be distinguished. The screening method, other wafer inspection methods, the semiconductor chip marking method for determining a non-defective product / defective product, and the semiconductor chip marking timing are the same as those in the first embodiment. Next, similarly to the first embodiment, the dicing process for the n ⁻ type semiconductor wafer and the soldering process for the back surface of the chip are sequentially performed (steps S31 and S32). In the step of soldering the back surface of the chip in step S32, only the semiconductor chip determined to be a good product is picked up and the back surface of the semiconductor chip is soldered to an insulating substrate such as a DCB substrate. That is, the semiconductor chips (semiconductor chips with a predetermined mark) determined to be defective in the wafer inspection (including screening) in step S30 are removed. Next, the emitter electrode 9 and the emitter pad E are connected by wire bonding, and the emitter pad E and the gate pad G are connected to predetermined electrode leads (not shown). Further, by connecting the emitter electrode 9 and the screening pad DG by wire bonding (step S33), the trench gate type IGBT shown in FIG. 1B is completed.

  That is, in the third embodiment, a bonding wire (not shown) is used as a metal member that short-circuits the emitter electrode 9 and the screening pad DG. The screening pad DG may be arranged outside the inner terminal 14a of the front surface protection film 14 as in the case of other electrode pads (FIG. 10). When the screening pad DG is arranged inside the inner end 14a of the front surface protection film 14 as in the first embodiment (FIG. 2), the screening pad DG and the emitter pad E are short-circuited by wire bonding. You may let me. The size (surface area) of the screening pad DG is preferably, for example, a substantially rectangular aspect ratio in which the length of one side is equal to or larger than the wire diameter (eg, about 30 μm to 400 μm).

  Further, the screening pad DG and the emitter pad E may be short-circuited by connecting the emitter pad E or the screening pad DG or both of them to a wiring layer on an insulating substrate such as a DCB substrate by wire bonding. Specifically, a semiconductor chip including a diode (temperature sense diode) used for measuring the temperature of the semiconductor chip will be described as an example. 14 to 16 are plan views each showing a planar layout of another example of each electrode pad of the semiconductor device according to the third exemplary embodiment. The configuration of the semiconductor chip shown in FIGS. 14 to 16 is different from that shown in FIG. 10 except that a temperature sense diode (not shown) is provided and the screening pad DG and the emitter pad E are connected to a wiring layer on an insulating substrate. Similar to a chip.

  As shown in FIG. 14, a screening pad DG and an emitter pad (pad having the same potential as the emitter electrode 9) E are arranged adjacent to each other, and the screening pad DG and the emitter pad E are insulated by different bonding wires 22 and 23, respectively. It may be connected to, for example, a metal terminal (hereinafter, simply referred to as a wiring layer) 21 formed of an upper wiring layer (metal foil) (not shown). The metal terminal 21 has a floating potential, for example.

  Further, as shown in FIG. 15, the screening pad DG and the emitter pad E are arranged adjacent to each other, and the screening pad DG, the emitter pad E and the wiring layer 21 are connected (stitched) by one bonding wire 24. May be. In this case, for example, after bonding (ultrasonic bonding) the first location (screening pad DG or wiring layer 21) and, for example, the emitter pad E arranged in the middle with the bonding wire 24, the bonding wire 24 is not cut. Then, the remaining third portion may be further bonded by a bonding wire. In this case, the number of bonding wires forming the module can be reduced.

  Further, as shown in FIG. 16, when the current value of the emitter electrode 9 is a relatively small current value of about several A, the screening pad DG and the emitter pad E are arranged adjacent to each other, and the emitter pad E and the wiring layer are arranged. 21 may be connected by a bonding wire 25, and the emitter electrode 9 and the screening pad DG may be connected by a lead frame 26. A lead frame for connecting the emitter electrode 9 and the emitter pad E is omitted in the drawing.

  The screening pad DG and the emitter pad E are, for example, arranged outside the inner end 14a of the front surface protection film 14, like other electrode pads. 14 to 16, the other electrode pads are the temperature sense cathode pad K, the temperature sense anode pad A, the gate pad G and the current sense pad S. The temperature sensing cathode pad K is connected to the cathode of the temperature sensing diode. The temperature sense anode pad A is connected to the anode of the temperature sense diode. The current sense pad S is connected to a current sense element arranged between the power supply and the load or the ground and the load.

  In the method for manufacturing a semiconductor device according to the third embodiment described above, the gate insulating film 7 and the dummy gate insulating film 17 may be screened after the wire bonding in step S33 instead of the wafer inspection in step S30. Good. In this case, the screening pad DG may be short-circuited to an external circuit (not shown) after the screening.

  As described above, according to the third embodiment, the dummy gate insulating film is screened before the assembly process, and the emitter electrode and the dummy gate electrode having the second trench gate structure are short-circuited in the assembly process. Then, the same effects as those of the first and second embodiments can be obtained.

(Embodiment 4)
Next, a method of manufacturing the semiconductor device according to the fourth embodiment will be described. FIG. 11 is a flowchart showing the outline of the method of manufacturing the semiconductor device according to the fourth embodiment. FIG. 12 is a plan view showing a planar layout of each electrode pad of the semiconductor device according to the fourth embodiment. FIG. 13 is a sectional view showing a sectional structure taken along the section line BB ′ in FIG. The manufacturing method of the semiconductor device according to the fourth embodiment differs from the manufacturing method of the semiconductor device according to the third embodiment in that the emitter electrode 9 and the emitter electrode 9 are formed by soldering the front surface of the chip to the copper block 19 in the assembly process. The point is to short-circuit the screening pad DG.

  Specifically, first, similarly to the third embodiment, the steps from the step of forming the semiconductor portion forming the MOS gate structure to the step of soldering the back surface of the chip are sequentially performed (steps S41 to S52). That is, also in the fourth embodiment, as in the third embodiment, in the wafer inspection (including screening) in step S50, the marking on the semiconductor chip is performed to determine the non-defective product / defective product. Then, in the step of soldering the back surface of the chip in step S52, only the semiconductor chip determined to be a good product is picked up and the back surface of the semiconductor chip is soldered to an insulating substrate such as a DCB substrate. Next, as shown in FIG. 13, by soldering the front surface of the chip to the copper block 19, the emitter electrode 9 and the emitter pad E are connected via the solder layer 15, and the emitter pad E and the gate pad are connected. Each G is connected to a predetermined electrode lead (not shown). At this time, the emitter electrode 9 and the screening pad DG are further short-circuited via the solder layer 15 (step S53). As a result, the trench gate type IGBT shown in FIG. 1B is completed.

  In the fourth embodiment, the solder layer 15 is used as a metal member that short-circuits the emitter electrode 9 and the screening pad DG. A copper block 19 is bonded to the front surface of the chip by the solder layer 15. It suffices that the screening pad DG be arranged inside the inner terminal 14 a of the front surface protection film 14. The reason is the same as in the case where the plating film 13 is used as the metal member in the first embodiment. That is, since the solder layer 15 spreads over the entire inner side of the inner end 14a of the front surface protective film 14, the space between the emitter electrode 9 and the screening pad DG can be surely filled with the solder layer 15 (FIG. 13). . Therefore, it is particularly useful when the gap between the emitter electrode 9 and the screening pad DG is wide enough that the emitter electrode 9 and the screening pad DG are not short-circuited by the wet spread of the plating film 13 formed on the emitter electrode 9 and the screening pad DG. Is. The thickness of the solder layer 15 may be, for example, 50 μm or more and 200 μm or less. The thickness of the front surface protection film 14 may be, for example, 3 μm or more and 15 μm or less, and is preferably 7 μm, which is thicker than the total thickness of the emitter electrode 9 and the plating film 13.

  Specifically, for example, the screening pad DG may be arranged in the vicinity of the outer periphery of the emitter electrode 9 so that one side around the screening pad DG faces the emitter electrode 9 as in the first embodiment ( (Fig. 2). Further, the screening pad DG is similar to the second embodiment, so that two or more sides around the screening pad DG face the emitter electrode 9 and the outer peripheral portion of the emitter electrode 9 on the side of each electrode pad or the emitter electrode 9. It may be arranged in the central part (FIGS. 6 and 7). Further, the screening pad DG may be arranged on the opposite side of each electrode pad with the emitter electrode 9 interposed therebetween (FIG. 12).

  As described above, according to the fourth embodiment, the dummy gate insulating film is screened before the assembly process, and the emitter electrode and the dummy gate electrode having the second trench gate structure are short-circuited in the assembly process. Then, the same effects as those of the first to third embodiments can be obtained.

(Embodiment 5)
Next, a method of manufacturing the semiconductor device according to the fifth embodiment will be described with reference to FIG. The semiconductor device manufacturing method according to the fifth embodiment is different from the semiconductor device manufacturing method according to the first embodiment in that all trench gate structures are once formed as trench MOS cells (that is, n ⁻ type semiconductor substrate). All the trench gate structures formed in the above are connected to the gate runners as the gate electrodes 8), and after all the gate insulating films 7 are collectively screened, some of the gate electrodes 8 connected to the gate runners are electrically connected. This is a point where the dummy gate electrode 18 is separated from the above.

  Specifically, first, similarly to the first embodiment, a step of forming a semiconductor portion forming a MOS gate structure and a step of forming a trench are sequentially performed (steps S1 and S2). Then, in steps S3 and S4, the gate electrode to be the dummy gate electrode 18 in the step described later is also connected to the gate pad G via the gate runner at any timing until the step of step S7 described later, and the gate potential G To do. That is, in steps S3 and S4, the trench gate structure (gate insulating film 7 and gate electrode 8) having the gate potential is once formed in all the trenches.

  Next, similarly to the first embodiment, the steps from the step of forming the interlayer insulating film 10 to the step of forming the front surface protective film 14 are sequentially performed (steps S5 to S7). Next, in step S8, a predetermined voltage is applied between the emitter electrode 9 and the gate pad G to screen all the gate insulating films 7 of the trench gate structure. That is, the gate insulating film that will become the gate insulating film 17 in the process described below is screened as the gate insulating film 7. Next, as in the first embodiment, the step of forming the back electrode is performed (step S9).

  After the screening in step S8 and before the plating process in step S10, which will be described later, the gate runner is partially removed by, for example, etching to remove a part of the trench gate structure (gate insulating film 7 and gate electrode 8). It is electrically separated from the gate pad G. Then, the gate electrode 8 separated from the gate pad G is connected to the screening pad DG via, for example, a dummy gate runner in the same manner as in the first embodiment to form the dummy gate electrode 18. Thereafter, similar to the first embodiment, the steps after the plating step are sequentially performed (steps S10 to S14), and the trench gate type IGBT of FIG. 1B is completed.

  The semiconductor device manufacturing method according to the fifth embodiment described above may be applied to the second embodiment. That is, it is sufficient that one or more sides around the screening pad DG face the emitter electrode 9 at a predetermined interval w, and the arrangement of the screening pad DG can be variously changed. Further, the method of manufacturing the semiconductor device according to the fifth embodiment described above may be applied to the third and fourth embodiments. That is, after screening the gate insulating film 7 in the wafer inspection and before the bonding step, a part of the gate electrode 8 is electrically separated from the gate runner to form the dummy gate electrode 18. The layout of the screening pad DG can be variously changed depending on the type of metal member used for short-circuiting the emitter electrode 9 and the screening pad DG.

  As described above, according to the fifth embodiment, the same effects as those of the first to fourth embodiments can be obtained.

In the above, the present invention is not limited to the above-described embodiments, but can be variously modified without departing from the spirit of the present invention. For example, in each of the above-described embodiments, the case where the portion of the p-type base region sandwiched between the dummy trench MOS cells is the emitter potential has been described as an example. It can be applied to a MOS type semiconductor device in which a portion sandwiched between dummy trench MOS cells has a floating potential (floating potential). Further, in each of the above-described embodiments, the case where the screening for the gate insulating film is performed together with the screening for the dummy gate insulating film is described as an example, but the gate electrode forming the trench MOS cell is not short-circuited to the emitter electrode. Therefore, a predetermined voltage can be applied to the gate insulating film at any timing. Further, when the emitter electrode and the screening pad are electrically insulated from each other during screening, all trench gate structures formed on the n ⁻ type semiconductor substrate are connected to the dummy gate runner as dummy gate electrodes, After the dummy gate insulating film is collectively screened, a part of the gate electrode connected to the dummy gate runner may be electrically separated to form the gate electrode 8. Therefore, the timing of screening the gate insulating film can be variously changed. Further, the present invention is similarly applicable even when the conductivity type is reversed.

  As described above, the method for manufacturing a semiconductor device according to the present invention is useful for a MOS semiconductor device including a dummy trench MOS cell short-circuited to an emitter electrode.

1 n ⁻ type semiconductor substrate (n ⁻ type drift layer)
1a active region 1b edge termination region 2 p-type base layer 3 first base region 4 second base region 5 n ⁺ type emitter region 6 trench 7 gate insulating film 8 gate electrode 9 emitter electrode 10 interlayer insulating film 11 p ⁺ type collector layer 12 collector electrode 13 plating film 14 front surface protective film 14a inner end of front surface protective film 15 solder layer 16 dummy trench 17 dummy gate insulating film 18 dummy gate electrode 19 copper block DG screening pad E emitter pad G gate pad w Distance between emitter electrode and screening pad

Claims (5)

A plurality of trench gate structures having a gate electrode extending in the depth direction of the device, wherein the plurality of trench gate structures contribute to the control of the device, and a second trench gate structure that does not contribute to the control of the device. A method of manufacturing a semiconductor device comprising a structure,
A first step of forming a plurality of trench gate structures on the front surface side of the semiconductor substrate;
A plurality of trench gate structures on the front surface of the semiconductor substrate, a gate electrode pad to which the gate electrodes forming one or more of the first trench gate structures are connected, and a plurality of the trench gates; A second step of forming one or more of the structures, a screening electrode pad to which the gate electrode forming the second trench gate structure is connected,
A first predetermined voltage is applied between an electrode portion having a potential other than the gate potential and the screening electrode pad, and the first predetermined voltage is applied to the gate insulating film in contact with the gate electrode connected to the screening electrode pad. Screening is performed, a second predetermined voltage is applied between the electrode portion and the gate electrode pad, and the second predetermined voltage is applied to the gate insulating film in contact with the gate electrode connected to the gate electrode pad. A third step of applying screening,
A fourth step including a dicing step of separating the semiconductor substrate into pieces after the third step, and a back surface soldering step of soldering the back surface of the separated semiconductor substrate;
After the fourth step, a fifth step of electrically connecting the electrode portion and the screening electrode pad to form the second trench gate structure including the gate electrode connected to the screening electrode pad. When,
Including,
The electrode portion is an emitter electrode electrically connected to a portion of the semiconductor substrate along the trench of the trench gate structure,
The emitter electrode has an emitter electrode pad having the same potential as the emitter electrode,
The fifth step includes a first wire bonding step of connecting between the emitter electrode pad and the screening electrode pad, and a second wire bonding step of connecting between a wiring layer of an insulating substrate and the gate electrode pad. Including,
A method of manufacturing a semiconductor device, further comprising a plating step of forming a plating film on a front surface of the semiconductor substrate between the second step and the third step.   The method of manufacturing a semiconductor device according to claim 1, wherein the second predetermined voltage is the same voltage as the first predetermined voltage. A plurality of trench gate structures having a gate electrode extending in the depth direction of the device, wherein the plurality of trench gate structures contribute to the control of the device, and a second trench gate structure that does not contribute to the control of the device. A method of manufacturing a semiconductor device comprising a structure,
A first step of forming a plurality of trench gate structures on the front surface side of the semiconductor substrate;
A plurality of trench gate structures on the front surface of the semiconductor substrate, a gate electrode pad to which the gate electrodes forming one or more of the first trench gate structures are connected, and a plurality of the trench gates; A second step of forming one or more of the structures, a screening electrode pad to which the gate electrode forming the second trench gate structure is connected,
A third step of forming a plating film on the front surface of the semiconductor substrate after the second step,
After the third step, a predetermined voltage is applied between the electrode portion having a potential other than the gate potential and the screening electrode pad, and the gate insulating film in contact with the gate electrode connected to the screening electrode pad is subjected to the above-mentioned process. A fourth step of performing a screening in which a predetermined voltage is applied,
After the fourth step, a fifth step including a dicing step of dividing the semiconductor substrate into pieces, and a back surface soldering step of soldering the back surface of the separated semiconductor substrate,
After the fifth step, a sixth step of electrically connecting the electrode portion and the screening electrode pad to form the second trench gate structure including the gate electrode connected to the screening electrode pad. When,
Including,
In the sixth step, the method of manufacturing a semiconductor device, wherein the emitter electrode pad having the same potential as the electrode portion and the screening electrode pad are connected by wire bonding.   The method for manufacturing a semiconductor device according to claim 3, wherein the sixth step includes a wire bonding step for connecting a wiring layer of an insulating substrate and the gate electrode pad.   Between the fifth step and the sixth step, a front surface soldering step of soldering an electrode terminal to the electrode portion on the front surface of the individualized semiconductor substrate is performed. The method for manufacturing a semiconductor device according to claim 3.

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