JP5359182B2 - Semiconductor device - Google Patents

Abstract

The invention discloses a semiconductor device with an insulated gate semiconductor component and an insulated gate bipolar transistor. A semiconductor device having an IGBT includes: a substrate; a drift layer and a base layer on the substrate; trenches penetrating the base layer to divide the base layer into base parts; an emitter region in one base part; a gate element in the trenches; an emitter electrode; and a collector electrode. The one base part provides a channel layer, and another base part provides a float layer having no emitter region. The gate element includes a gate electrode next to the channel layer and a dummy gate electrode next to the float layer. The float layer includes a first float layer adjacent to the channel layer and a second float layer apart from the channel layer. The dummy gate electrode and the first float layer are coupled with a first float wiring on the base layer. The dummy gate electrode is isolated from the second float layer.

Description

  The present invention relates to an insulated gate semiconductor device such as an insulated gate transistor (hereinafter referred to as IGBT) having a trench gate structure.

2. Description of the Related Art Conventionally, a semiconductor device having an IGBT having a structure shown in FIGS. 17 and 18 is generally known as a high breakdown voltage insulated gate semiconductor element such as an IGBT having a trench gate structure (see, for example, Patent Document 1). In these IGBTs, an n ⁺ -type emitter region 101 to be contacted with the emitter electrode is selectively formed in the p-type base region 102 and a dummy trench 103 is formed in a portion where the n ⁺ -type emitter region 101 is not present. As a result, a trench gate structure having a uniform distribution is provided. That is, in the trench 105 in which the gate electrode 104 for applying the gate voltage is formed in the thinned region while the n ⁺ type emitter region 101 is thinned instead of being formed in the entire p type base region 102. A dummy trench 103 provided with a dummy gate electrode 106 for no dummy is arranged.

As described above, by selectively forming the n ⁺ -type emitter region 101, conductivity modulation of the high-resistance p-type base region 102 can be promoted to further reduce the conduction loss, and by forming the dummy trench 103. The breakdown voltage can be improved. For this reason, it is possible to improve the trade-off between current loss and breakdown voltage. In the IGBT having such a structure, in order to stabilize the potential of the dummy gate electrode 106, it is connected to the emitter electrode as shown in FIG. 17 or to the gate electrode 104 as shown in FIG. Yes.
JP 2006-49455 A

  However, when the dummy gate electrode 106 in the dummy trench 103 is connected to the emitter electrode or the gate electrode 104, although the potential can be stabilized, there are the following problems.

  That is, when the dummy gate electrode 106 is connected to the gate electrode 104, there is a problem that the capacitance between G and C (capacitance between the gate and the collector) increases and the switching loss becomes too large. Further, when the dummy gate electrode 106 is connected to the emitter electrode, there is a problem that the capacitance between GE (gate-emitter capacitance) increases and the switching surge becomes too large.

  Further, depending on the application, an intermediate part thereof, that is, a balanced switching surge and switching loss may be desired. To realize this, a dummy gate in the dummy trench 103 as shown in FIG. 19 is used. A structure in which the electrode 106 is connected to the float layer 107 is also conceivable.

However, in the structure in which the dummy gate electrode 106 is connected to the float layer 107 in this way, the potential of the float layer 107 is unbalanced at the connected portion and at a location away from the connected portion, causing a reduction in breakdown resistance due to current concentration. There is a problem. For example, when a plurality of dummy trenches 103 are arranged in a stripe shape, the float layer 107 is arranged between each of the plurality of dummy trenches 103 and is formed on the dummy trench 103 and the float layer 107. The dummy gate electrode 106 and the float layer 107 are electrically connected by a single wiring. At this time, since the emitter electrode connected to the n ⁺ -type emitter region 101 must have a large area, one wiring used for electrical connection between the dummy gate electrode 106 and the float layer 107 is thin. Therefore, a portion of each float layer 107 that is electrically connected to the wiring has the same potential, and a potential difference is generated as the distance from that portion increases. For example, the depth direction of FIG. The potential difference between the float layers 107 increases as the distance in the (installation direction) increases. As described above, the difference in the potential difference between the float layers in the longitudinal direction causes a non-uniform operation (unbalance) at the time of switching, and causes a reduction in breakdown resistance due to current concentration.

  In view of the above points, an object of the present invention is to suppress an increase in potential difference between float layers in the extending direction of the float layer, and to prevent a reduction in breakdown resistance due to current concentration.

  In order to achieve the above object, according to the first aspect of the present invention, the base region (3) is divided into a plurality of regions by the trench (4), and each of the plurality of separated base regions (3) extends in the same direction. Thus, a structure having portions arranged in parallel is formed, and among the plurality of base regions (3), the one in which the emitter region (5) is formed functions as the channel layer (3a), and the emitter region Those in which (5) is not formed function as the float layers (3b to 3d), and the channel layer (3a) and the float layers (3b to 3d) are repeatedly arranged in a certain ratio and in a certain arrangement order. The electrodes (7a to 7c) include a gate voltage application gate electrode (7a) embedded in the trench (4) in contact with the emitter region (5), and the emitter region (5) in the trench (4). And dummy gate electrodes (7b, 7c) embedded in non-contacting layers, and the dummy gate electrodes (7b, 7c) are adjacent to the channel layer (3a) in the float layers (3b-3d). Are electrically connected to the first float wiring (12) extending in the direction perpendicular to the longitudinal direction of the trench (4) together with the first float layer (3b) located at the position of the float layer (3b-3d) Of these, the first float layer (3b) is separated from the second float layer (3c) arranged farther from the channel layer (3a) than the first float layer (3b).

  Thus, by electrically connecting the dummy gate electrodes (7b, 7c) to the first float layer (3b), it is possible to obtain a structure in which switching surge and switching loss are balanced.

  Further, the float layers (3b to 3d) are not connected to the same wiring, but are connected to different wirings. For this reason, at the time of turn-off, the potentials at the places where the float layers (3b to 3d) are in contact with the wirings have different potentials. The potential difference of each of the float layers (3b to 3d) in the longitudinal direction and the vertical direction of the trench (4) does not vary greatly even if the potential difference is away from the contact point with the wiring. That is, almost the same potential difference is maintained. For this reason, it is possible to prevent a difference in potential between the float layers (3b to 3d) in the longitudinal direction. As a result, the uniformity of operation during switching can be maintained, and it is possible to prevent the breakdown tolerance from being reduced due to current concentration.

Specifically, in the first aspect of the present invention, the second float wiring (2) extending in a direction perpendicular to the longitudinal direction of the trench (4) to which the second float layer (3c) is electrically connected. 13) or al dummy gate electrode (7b, 7c) are electrically discrete configure.

In the invention according to claim 2 , the base region (3) is separated into a plurality of regions by the trench (4), and the plurality of separated base regions (3) are arranged in parallel by extending in the same direction. Among the plurality of base regions (3), the one in which the emitter region (5) is formed functions as the channel layer (3a), and the emitter region (5) is formed. Those that do not function as the float layers (3b to 3d), the channel layers (3a) and the float layers (3b to 3d) are repeatedly arranged in a certain ratio and in a certain arrangement order, and the gate electrodes (7a to 7c) The gate electrode (7a) for applying a gate voltage embedded in the trench (4) that is in contact with the emitter region (5) and the trench (4) that is not in contact with the emitter region (5) Among the dummy gate electrodes (7b, 7c), the one closest to the channel layer (3a) (7b) is the float layer (3b-3d). Of these, the first float layer (3b) closest to the channel layer (3a) and the first float wiring (12) extending in the direction perpendicular to the longitudinal direction of the trench (4) are electrically connected. It is characterized by.

  Even in such a structure, the relationship between the potential differences of the respective float layers (3b to 3d) is maintained at any place in the longitudinal direction of the trench (4). Uniformity is maintained, and it is possible to prevent a reduction in breakdown resistance due to current concentration.

In this case, as described in claim 2 , among the dummy gate electrodes (7b, 7c), the first float layer (7c) farther from the channel layer (3a) than the first float layer (3b) Electrically connected to the second float wiring (13) extending in the direction perpendicular to the longitudinal direction of the trench (4) together with the second float layer (3c) farther from the channel layer (3a) than (3b) It has to be.

For example, as described in claim 3 , the trench (4) can have an annular structure, and a plurality of trenches (4) can form a set to form a multiple ring structure.

Further, as described in claim 4 , the gate wiring (11), the first float wiring (12), and the second float wiring (13) to which the gate electrode (7a) for applying the gate voltage is electrically connected are provided. The gate voltage application gate electrode (7a) and the dummy gate electrodes (7b, 7c) can be arranged in parallel to the longitudinal tip position.

Furthermore, as described in claim 5 , the emitter electrode (15) is divided into two at the center position in the longitudinal direction of the gate voltage application gate electrode (7a) and the dummy gate electrodes (7b, 7c), A gate line (11), a first float line (12), and a second float line (to which a gate voltage application gate electrode (7a) is electrically connected between the divided emitter electrodes (15), 13) can also be arranged side by side in parallel.

  With such a structure, even if the chip size is increased, it is possible to suppress an imbalance due to a delay in potential transmission inside the dummy gate electrodes (7b, 7c), and further obtain the effect described in claim 1. It becomes possible.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
A first embodiment of the present invention will be described. FIG. 1 is a schematic cross-sectional view showing a cross-sectional structure and a wiring structure of a semiconductor device having an IGBT according to the present embodiment. FIG. 2 is a cross-sectional view of the semiconductor device shown in FIG. 3 is a top layout view of the semiconductor device having the IGBT shown in FIGS. 1 and 2, and FIG. 4 is a partial cross-sectional perspective view of the semiconductor device having the IGBT shown in FIGS. 1 and 2. 1 and FIG. 2 correspond to the AA cross section and the BB cross section of FIG. 3, respectively. Although FIG. 3 is not a cross-sectional view, hatching is partially shown to facilitate understanding of the drawing. Hereinafter, the semiconductor device having the IGBT according to the present embodiment will be described with reference to these drawings.

As shown in FIG. 1, an IGBT is formed on a p ⁺ -type substrate 1 having a main surface on one side. The p ⁺ type substrate 1 has a high impurity concentration. P ⁺ -type n also formed such that the lower impurity concentration than the substrate 1 by epitaxial growth or the like on the main surface of the p ⁺ -type substrate 1 ^- -type drift layer 2 is provided.

A p-type base region 3 having a predetermined thickness is formed in the surface layer portion of the n ⁻ -type drift layer 2. Further, a plurality of trenches 4 are formed so as to penetrate the p-type base region 3 and reach the n ⁻ -type drift layer 2, and the p-type base region 3 is separated into a plurality of trenches 4. Specifically, in the cross section of FIGS. 1 and 2 (the AA cross section or the BB cross section of FIG. 3), a plurality of trenches 4 are formed at equal intervals, and the depth direction of FIGS. After each trench 4 is extended in parallel (in the direction perpendicular to the paper surface), as shown in FIG. 3 and FIG. Each of the trenches 4 constitutes a multiple ring structure with a plurality of annular structures (three in the case of this embodiment) as one set, and the longitudinal directions of adjacent multiple ring structures are parallel to each other. Is arranged. Hereinafter, among the plurality of trenches 4, the one arranged on the outermost periphery is the outermost periphery trench 4 a, the one on the inner side is the first inner periphery trench 4 b, and the one arranged on the inner side (the innermost periphery). This is referred to as a second inner peripheral trench 4c.

The p-type base region 3 disposed between the outermost peripheral trenches 4a of adjacent multiple ring structures is a channel p layer 3a constituting a channel region, and an n ⁺ type is formed on the surface layer portion of the channel p layer 3a. An emitter region 5 is formed.

The n ⁺ -type emitter region 5 has a higher impurity concentration than the n ⁻ -type drift layer 2, terminates in the p-type base region 3, and is disposed so as to be in contact with the side surface of the outermost peripheral trench 4 a. Yes. More specifically, a structure is provided that extends in a rod shape along the longitudinal direction of the outermost peripheral trench 4a and terminates inside the front end of the outermost peripheral trench 4a. For this reason, among the plurality of trenches 4, the outermost peripheral trenches 4 a disposed on both sides of the n ⁺ -type emitter region 5 are used for forming the gate electrode, and the other first and second inner peripheral trenches 4 b and 4 c are used. Is for a dummy trench.

Specifically, each trench 4 is constituted by a gate insulating film 6 formed so as to cover the inner wall surface of each trench 4 and doped Poly-Si formed on the surface of the gate insulating film 6. It is embedded with gate electrodes 7a-7c. As shown in FIGS. 1 and 3, among the gate electrodes 7a to 7c, a gate voltage is applied to the gate electrode 7a formed in the outermost peripheral trench 4a disposed on both sides of the n ⁺ -type emitter region 5. The dummy gate electrodes 7b and 7c formed in the first and second inner peripheral trenches 4b and 4c are electrically connected to the gate wiring 11 to be formed, and the dummy gate electrodes 7b and 7c are formed in the trenches 4 constituting the multiple ring structure. First float wiring 12 electrically connected to the first float layer 3b constituted by the p-type base region 3 sandwiched between the outermost peripheral trench 4a and the first inner peripheral trench 4b one inner side of the outermost trench 4a. It is connected to the. In addition, the second float layer 3c is formed by the p-type base region 3 sandwiched between the first inner peripheral trench 4b and the second inner peripheral trench 4c which is one further inside than the first inner peripheral trench 4b. Connected. Further, the third float layer 3d is configured by the p-type base region 3 disposed inside the second inner peripheral trench 4c, and is electrically connected to the third float wiring.

  The electrical connection between the first to third float wirings 12, 13, 14 and the dummy gate electrodes 7 b, 7 c and the float layers 3 b to 3 c is not limited as long as the wirings are not short-circuited. However, in this embodiment, for example, the electrical connection between the second float wiring 13 and each part is realized by the structure shown in FIG.

  That is, the surface of each of the float layers 3b to 3d is covered with the insulating film 8, and the doped Poly-Si 9 constituting the dummy gate electrodes 7b and 7c is extended over the second and third float layers 3c and 3d. Thus, the dummy gate electrodes 7b and 7c are electrically connected through the doped Poly-Si 9. Then, each part is insulated by the interlayer insulating film 10, and only a part of the doped Poly-Si 9 and a part of the first float layer 3 b are exposed through the contact holes 10 a and 10 b formed in the interlayer insulating film 10. By disposing the first float wiring 12, the dummy gate electrodes 7 b and 7 c are electrically connected to the first float layer 3 b and the first float wiring 12.

  In the present embodiment, in addition to the first float wiring 12 that electrically connects the dummy gate electrodes 7b and 7c and the first float layer 3b, the second float wiring that is electrically connected to the second float layer 3c. 13 and the third float wiring 14 electrically connected to the third float layer 3d have been described. However, the second float wiring 13 and the third float wiring 14 may not be provided. In that case, the second float layer 3c and the third float layer 3d are in a floating state.

Also, the emitter electrode 15 electrically connected to the first to third float wires 12, 13, 14 and the n ⁺ -type emitter region 5 and the gate wire 11 electrically connected to the gate electrode 7a are shown in FIG. As shown, the trenches 4 are arranged so as to be parallel to the longitudinal direction and the vertical direction. Specifically, the emitter electrode 15 is disposed so as to cover the cell interior with a large area, and the third float wiring 14, the second float wiring 13, the first float wiring 12 and the gate are arranged at the tip position of the trench 4. The wirings 11 are arranged in a straight line parallel to the order.

The first float wiring 12 is electrically connected to the doped Poly-Si 9 formed on the insulating film 8 through the contact hole 10b formed in the interlayer insulating film 10 as described above and through the contact hole 10a. Although it is electrically connected to the first float layer 3b, the same applies to other wirings. That is, the second float wiring 13 is electrically connected to the second float layer 3 c through a contact hole 10 c formed in the interlayer insulating film 10, and the third float wiring 14 is a contact hole formed in the interlayer insulating film 10. It is electrically connected to the third float layer 3d through 10d. The gate wiring 11 is electrically connected to doped Poly-Si 9 formed on the insulating film 8 through a contact hole 10 e formed in the interlayer insulating film 10. The emitter electrode 15 is electrically connected to the n ⁺ -type emitter region 5 and the channel p layer 3a through a contact hole 10f formed in the interlayer insulating film 10.

A collector electrode 16 is formed on the back side of the p ⁺ type substrate 1. In this manner, a semiconductor device including the IGBT according to the present embodiment is configured.

  In the semiconductor device according to the present embodiment described above, the gate electrode 7a is electrically connected to the gate wiring 11 to which the gate voltage is applied, and the dummy gate electrodes 7b and 7c are electrically connected to the first float layer 3b. And a structure in which the second float layer 3c is electrically connected to the second float wiring 13 and the third float layer 3d is electrically connected to the third float wiring 14. Has been.

  As described above, by electrically connecting the dummy gate electrodes 7b and 7c to the first float layer 3b, a structure in which switching surge and switching loss are balanced can be achieved.

  The first to third float layers 3b to 3d are not connected to the same wiring, but are connected to different wirings. For this reason, at the time of turn-off, the potentials of the first to third float layers 3b to 3d at the place of contact with the wiring are different from each other. The potential difference between the first to third float layers 3b to 3d in the longitudinal direction and the vertical direction of the trench 4 greatly fluctuates even if the potential difference between the first and third float layers 3b to 3d is away from the contact point with the wiring. do not do. That is, almost the same potential difference is maintained.

  For example, when the first to third float layers 3b to 3d are brought into contact with the same wiring, the potential P1 of the first float layer 3b = the potential P2 of the second float layer 3c = the potential P3 of the third float layer 3d at the contact location. It becomes. However, since the potential P1 of the first float layer 3b <the potential P2 of the second float layer 3c <the potential P3 of the third float layer 3d, the potential difference increases as the distance from the contact location increases. On the other hand, in the structure of this embodiment, the relationship of the potential P1 of the first float layer 3b <the potential P2 of the second float layer 3c <the potential P3 of the third float layer 3d is any place in the longitudinal direction of the trench 4. Kept.

  For this reason, it is possible to prevent a difference in potential between the first to third float layers 3b to 3d in the longitudinal direction. As a result, the uniformity of operation during switching can be maintained, and it is possible to prevent the breakdown tolerance from being reduced due to current concentration. Here, not only the dummy gate electrodes 7b and 7c disposed between the two adjacent channel p layers 3a through the first float wiring 12, but also the dummy gate electrodes 7b disposed further outside the dummy gate electrodes 7b and 7c. 7c are electrically connected, but only the dummy gate electrodes 7b and 7c arranged between two adjacent channel p layers 3a are connected to each other via doped Poly-Si 9 etc. Further, the structure may be such that it is electrically separated from the outer dummy gate electrodes 7b and 7c.

(Second Embodiment)
A second embodiment of the present invention will be described. In the present embodiment, the connection form between the gate electrode 7a and the dummy gate electrodes 7b and 7c and the first to third float layers 3b to 3d is changed with respect to the first embodiment. Since it is the same as that of 1st Embodiment, only a different part is demonstrated.

  FIG. 5 is a schematic cross-sectional view showing a cross-sectional structure and a wiring structure of the semiconductor device having the IGBT according to the present embodiment. 6 to 10 are cross-sectional views of the semiconductor device having the IGBT according to the present embodiment, and show cross-sectional views in different cross-sections, respectively. FIG. 11 is a top layout view of the semiconductor device having the IGBT shown in FIGS. 6 to 10 correspond to the CC section to the GG section in FIG. 11, respectively. Although FIG. 11 is not a cross-sectional view, hatching is partially shown to facilitate understanding of the drawing. Hereinafter, the semiconductor device having the IGBT according to the present embodiment will be described with reference to these drawings.

  As shown in FIG. 5, in this embodiment, the dummy gate electrode 7b formed in the first inner peripheral trench 4b is electrically connected to the first float wiring 12 together with the first float layer 3b, and the second inner The dummy gate electrode 7c formed in the peripheral trench 4c is electrically connected to the second float wiring 13 together with the second float layer 3c, and the third float layer 3d is electrically connected to the third float wiring 14. Yes. That is, of the dummy gate electrodes 7b and 7c, the dummy gate electrode 7b closest to the channel layer 3a is the first float wiring together with the first float layer 3b closest to the channel layer 3a among the first to third float layers 3b to 3d. 12, the dummy gate electrode 7 c of the dummy gate electrodes 7 b and 7 c that is further away from the channel layer 3 a than the first float layer 3 b is the second away from the channel layer 3 a than the first float layer 3 b. It is electrically connected to the second float wiring 13 together with the float layer 3c. As shown in FIG. 11, the arrangement of the gate wiring 11, the float wirings 12 to 14, and the emitter electrode 15 is the same as that of the first embodiment, but the contact hole position connected to each part and the doped Poly-Si 9 The electrical connection as described above is performed by changing the formation position with respect to the first embodiment.

  In the present embodiment, in addition to the first float wiring 12 that electrically connects the dummy gate electrodes 7b and 7c and the first float layer 3b, the second float wiring that is electrically connected to the second float layer 3c. 13 and the third float wiring 14 electrically connected to the third float layer 3d have been described. However, the second float wiring 13 and the third float wiring 14 may not be provided. In that case, the second float layer 3c and the third float layer 3d are in a floating state.

Specifically, as shown in FIG. 6, the gate wiring 11 is electrically connected to doped Poly-Si 9 formed on the insulating film 8 through a contact hole 10 e formed in the interlayer insulating film 10. Has been. Further, as shown in FIG. 7, the first float wiring 12 is electrically connected to the doped Poly-Si 9 formed on the insulating film 8 through the contact hole 10 b formed in the interlayer insulating film 10. And electrically connected to the first float layer 3b through the contact hole 10a. Further, as shown in FIG. 8, the second float wiring 13 is electrically connected to the second float layer 3 c through the contact hole 10 b formed in the interlayer insulating film 10 and is formed in the interlayer insulating film 10. The doped poly-Si 9 formed on the insulating film 8 is electrically connected through the contact hole 10g. As shown in FIG. 9, the third float wiring 14 is electrically connected to the third float layer 3 d through a contact hole 10 d formed in the interlayer insulating film 10. As shown in FIG. 10, the emitter electrode 15 is electrically connected to the n ⁺ -type emitter region 5 and the channel p layer 3 a through a contact hole 10 f formed in the interlayer insulating film 10.

  In such a structure, at the time of turn-off, the potential P1 of the first float layer 3b = the potential of the gate electrode 7a <the potential P2 of the second float layer 3c = the potential of the dummy gate electrode 7b <the potential P3 of the third float layer 3d = The potential relationship of the dummy gate electrode 7c is established. For this reason, the relationship between the potential differences of the first to third float layers 3b to 3d is maintained everywhere in the longitudinal direction of the trench 4, and the operation uniformity during switching is the same as in the first embodiment. Thus, it is possible to prevent the breakdown resistance from being reduced due to current concentration.

(Third embodiment)
A third embodiment of the present invention will be described. In the present embodiment, the arrangement of the gate wiring 11, the first to third float wirings 12 to 14, and the emitter electrode 15 is changed with respect to the first to third embodiments, and the other parts are the first. Since it is the same as that of 3rd Embodiment, only a different part is demonstrated.

  FIG. 12 is a top surface layout diagram of the semiconductor device having the IGBT according to the present embodiment. In addition, although this figure is not sectional drawing, in order to make an understanding of a figure easy, hatching is partially shown. As shown in this figure, the first to third float wirings 12 to 14 are separately routed on both sides of the emitter electrode 15, and further on both sides so as to sandwich the emitter electrode 15 and the first to third float wirings 12 to 14. The gate wiring 11 is routed around. Then, a gate pad 11a for connecting the gate wiring 11 and the outside, a first float pad 12a for connecting the first float wiring 12 and the outside, and a second for connecting the second float wiring 13 and the outside. The second float pad 13a and the third float pad 14a for connecting the third float wiring 14 and the outside are provided at a position away from the trench 4 (outside the cell).

  Even with such a structure, the same effects as those of the first and second embodiments can be obtained. It is also possible to perform a disconnection inspection through the pads 11a to 14a. For example, the presence or absence of separation between the first float wiring 12 and the emitter electrode 15 can be examined by applying a voltage to the gate pad 11a and the first float pad 12a and examining the presence or absence of leakage. Similarly, the presence or absence of separation between the first float wiring 12 and the first float wiring 13 can be examined by applying a voltage to the first float pad 12a and the second float pad 13a and examining the presence or absence of leakage. it can. Furthermore, the presence or absence of separation between the second float wiring 13 and the third float wiring 14 can be examined by applying a voltage to the second float pad 13a and the third float pad 14a and examining the presence or absence of leakage. . In this way, it is possible to inspect whether or not the potential imbalance of the first to second float layers 3b to 3d is caused by a defect in the trench gate structure.

(Fourth embodiment)
A fourth embodiment of the present invention will be described. In the present embodiment, the connection form between the gate electrode 7a and the dummy gate electrodes 7b and 7c and the first to third float layers 3b to 3d is changed with respect to the first to third embodiments. Since is the same as in the first to third embodiments, only different parts will be described.

  FIG. 13 is a top surface layout diagram of the semiconductor device having the IGBT according to the present embodiment. In addition, although this figure is not sectional drawing, in order to make an understanding of a figure easy, hatching is partially shown. As shown in this figure, the emitter electrode 15 is divided into two at the center position in the longitudinal direction of the trench 4, and the gate wiring 11 and the first to third float wirings 12 to 14 are provided between the two emitter electrodes 15. In addition to the arrangement, the gate wiring 11 is also routed to the front end position of the trench 4 in the longitudinal direction.

  Since the dummy gate electrodes 7b and 7c are made of doped poly-Si similarly to the gate electrode 7a, the dummy gate electrodes 7b and 7c basically have a low resistance, and when the chip size is small (for example, 5 mm □ or less), the trench 4 may be brought into contact with the first to third float wirings 12 to 14 at the front end position in the longitudinal direction. However, when the chip size increases, even if the resistance is low, an imbalance due to a delay in potential transmission may occur. For this reason, if it is set as the structure like this embodiment, the imbalance due to the delay in the transmission of the potential inside the dummy gate electrodes 7b and 7c can be suppressed, and the same effect as in the first to third embodiments can be obtained. Is possible.

(Other embodiments)
In the first to fourth embodiments, the channel p layer 3a and the float layers 3b to 3d have a constant ratio and are repeatedly arranged in a certain arrangement order, whereby a certain thinning rate ( (Float layer formation ratio with respect to channel P layer formation ratio). Specifically, the multiple ring structure is tripled and the first to third float layers 3b to 3d are formed in addition to the channel p layer 3a, so that the thinning-out ratio is 5: 1. However, this is merely an example, and other thinning rates may be used.

  14 and 15 are top surface layout diagrams of a semiconductor device having an IGBT when the thinning rate is changed with respect to the structure of the first embodiment, and FIG. 14 shows a case where the thinning rate is 3: 1. Indicates the case where the thinning rate is 4: 1. FIG. 16 is a cross-sectional view when the thinning rate is 3: 1 as shown in FIG.

  As shown in FIGS. 14 and 16, when the thinning ratio is 3: 1, the structure is provided with the first and second float wirings 12 and 13, and is formed in the first inner peripheral trench 4b. The dummy gate electrode 7b can be electrically connected to the first float wiring 12 together with the first float layer 3b, and the second float layer 3c can be electrically connected to the second float wiring 13.

  Further, as shown in FIG. 15, the first inner peripheral trench 4c has a structure in which the trench 4 is also formed in the center, so that the second float layer 3c is separated into two, and the first and second float wirings are separated. 12 and 13, the dummy gate electrode 7b formed in the first inner peripheral trench 4b is electrically connected to the first float wiring 12 together with the first float layer 3b, and the second float layer 3c is connected to the second float layer 3c. A structure in which the two float wirings 13 are electrically connected may be employed.

  As described above, even if the thinning rate is changed, the second float wiring 13 may not be provided. In that case, the second float layer 3c is in a floating state. Of course, when the thinning-out rate is 5: 1 or more, for example 7: 1, if at least the first float layer 3b is electrically connected to the dummy gate electrode 7b, the other float layers are brought into a floating state. It does not matter.

  In each of the embodiments described above, the trench 4 for insulating and separating the first to third float layers 3b to 3d is annular, but the layout of the trench 4 is arbitrary, and a plurality of float layers are provided via the trench 4. Any structure that is adjacently disposed may be used. For example, a structure in which a plurality of float layers are simply arranged in a stripe shape may be used.

It is the cross-sectional schematic diagram which showed the cross-section of the semiconductor device which has IGBT concerning 1st Embodiment of this invention, and wiring structure. It is sectional drawing in another cross section of the semiconductor device shown in FIG. FIG. 3 is a top layout view of the semiconductor device having the IGBT shown in FIGS. 1 and 2. FIG. 3 is a partial cross-sectional perspective view of a semiconductor device having the IGBT shown in FIGS. 1 and 2. It is the cross-sectional schematic diagram which showed the cross-section of the semiconductor device which has IGBT concerning 2nd Embodiment of this invention, and wiring structure. FIG. 6 is a cross-sectional view of the semiconductor device shown in FIG. 5. FIG. 6 is a cross-sectional view of another step of the semiconductor device shown in FIG. 5. FIG. 6 is a cross-sectional view of another step of the semiconductor device shown in FIG. 5. FIG. 6 is a cross-sectional view of another step of the semiconductor device shown in FIG. 5. FIG. 6 is a cross-sectional view of another step of the semiconductor device shown in FIG. 5. FIG. 6 is a top layout view of the semiconductor device shown in FIG. 5. It is a top surface layout figure of a semiconductor device which has IGBT concerning a 3rd embodiment of the present invention. It is a top surface layout figure of the semiconductor device which has IGBT concerning 4th Embodiment of this invention. It is an upper surface layout figure of the semiconductor device which has IGBT concerning other embodiments. It is an upper surface layout figure of the semiconductor device which has IGBT concerning other embodiments. FIG. 15 is a cross-sectional view when the thinning rate is 3: 1 as shown in FIG. 14. It is the cross-sectional schematic diagram which showed the cross-section of the semiconductor device which has IGBT at the time of connecting a dummy gate to a gate electrode, and wiring structure. It is the cross-sectional schematic diagram which showed the cross-section of the semiconductor device which has IGBT at the time of connecting a dummy gate to an emitter electrode, and wiring structure. It is the cross-sectional schematic diagram which showed the cross-section of the semiconductor device which has IGBT at the time of connecting a dummy gate to a float layer, and wiring structure.

Explanation of symbols

1 p ⁺ type substrate 2 n ⁻ type drift layer 3 p type base region 3a channel p layer 3b to 3d first to third float layers 4 trench 4a outermost peripheral trench 4b and 4c inner peripheral trench 5 n ⁺ type emitter region 6 gate Insulating film 7a Gate electrodes 7b, 7c Dummy gate electrode 8 Insulating film 10 Interlayer insulating film 11 Gate wiring 12-14 First to third float wirings 15 Emitter electrode 16 Collector electrode

Claims (5)

A first conductivity type semiconductor substrate (1);
A second conductivity type drift layer (2) formed on the semiconductor substrate (1);
A first conductivity type base region (3) formed on the drift layer (2);
A trench (4) is formed so as to penetrate the base region (3) and reach the drift region (2), thereby separating the base region (3) into a plurality of pieces and extending in one direction as a longitudinal direction. )When,
Said the plurality of separated is formed on a part of the base region (3), the base region (3) a second conductivity type formed in contact with the front SL side of the trench (4) in the emitter region (5 )When,
A gate insulating film (6) formed on the surface of the trench (4);
In the trench (4), gate electrodes (7a to 7c) formed on the gate insulating film (6);
An emitter electrode (15) electrically connected to the emitter region (5);
A semiconductor device having an insulated gate semiconductor element comprising a collector electrode (16) formed on the back side of the semiconductor substrate (1),
The base region (3) is separated into a plurality by the trench (4), and each of the separated base regions (3) has a portion disposed in parallel by extending in the same direction. Among the plurality of base regions (3), the one in which the emitter region (5) is formed functions as a channel layer (3a), and the one in which the emitter region (5) is not formed. It functions as a float layer (3b-3d), the channel layer (3a) and the float layer (3b-3d) are repeatedly arranged in a certain ratio and in a certain arrangement order,
The gate electrodes (7a to 7c) include a gate voltage application gate electrode (7a) embedded in the trench (4) in contact with the emitter region (5) and the trench (4). A dummy gate electrode (7b, 7c) embedded in one not in contact with the emitter region (5),
The dummy gate electrodes (7b, 7c) are connected to the longitudinal direction of the trench (4) together with the first float layer (3b) located next to the channel layer (3a) in the float layers (3b to 3d). Electrically connected to the first float wiring (12) extending in the vertical direction,
Of the float layers (3b to 3d), a second float layer (3c) arranged farther from the channel layer (3a) than the first float layer (3b) is in the longitudinal direction of the trench (4). And electrically connected to the second float wiring (13) extending vertically.
The dummy gate electrode, the first float layer (3b) and the first float wiring (12) are electrically separated from the second float layer (3c) and the second float wiring (13). A featured semiconductor device. A first conductivity type semiconductor substrate (1);
A second conductivity type drift layer (2) formed on the semiconductor substrate (1);
A first conductivity type base region (3) formed on the drift layer (2);
A trench (4) is formed so as to penetrate the base region (3) and reach the drift region (2), thereby separating the base region (3) into a plurality of pieces and extending in one direction as a longitudinal direction. )When,
Said the plurality of separated is formed on a part of the base region (3), the base region (3) a second conductivity type formed in contact with the front SL side of the trench (4) in the emitter region (5 )When,
A gate insulating film (6) formed on the surface of the trench (4);
In the trench (4), gate electrodes (7a to 7c) formed on the gate insulating film (6);
An emitter electrode (15) electrically connected to the emitter region (5);
A semiconductor device having an insulated gate semiconductor element comprising a collector electrode (16) formed on the back side of the semiconductor substrate (1),
The base region (3) is separated into a plurality by the trench (4), and each of the separated base regions (3) has a portion disposed in parallel by extending in the same direction. Among the plurality of base regions (3), the one in which the emitter region (5) is formed functions as a channel layer (3a), and the one in which the emitter region (5) is not formed. It functions as a float layer (3b-3d), the channel layer (3a) and the float layer (3b-3d) are repeatedly arranged in a certain ratio and in a certain arrangement order,
The gate electrodes (7a to 7c) include a gate voltage application gate electrode (7a) embedded in the trench (4) in contact with the emitter region (5) and the trench (4). A dummy gate electrode (7b, 7c) embedded in one not in contact with the emitter region (5),
Of the dummy gate electrodes (7b, 7c), the one closest to the channel layer (3a) (7b) is the first float layer (3b-3d) closest to the channel layer (3a). 3b) and electrically connected to a first float wiring (12) extending in a direction perpendicular to the longitudinal direction of the trench (4) ,
Of the dummy gate electrodes (7b, 7c), the one (7c) that is further away from the channel layer (3a) than the first float layer (3b) is more than the channel layer (3b) than the first float layer (3b). It is electrically connected to a second float wiring (13) extending in a direction perpendicular to the longitudinal direction of the trench (4) together with a second float layer (3c) separated from 3a). Semiconductor device. The semiconductor device according to claim 1 or 2 , wherein the trench (4) has an annular structure, and a plurality of the trenches (4) are combined to form a multiple ring structure. The gate wiring (11), the first float wiring (12) and the second float wiring (13) to which the gate electrode (7a) for applying the gate voltage is electrically connected are connected to the gate voltage applying gate electrode (7a). the gate electrode (7a) and the dummy gate electrode (7b, 7c) the semiconductor device according to any one of claims 1 to 3, characterized in that each arranged in parallel to the longitudinal front end position in the . The emitter electrode (15) is divided into two at the longitudinal center position of the gate voltage application gate electrode (7a) and the dummy gate electrodes (7b, 7c). Between the emitter electrode (15), the gate wiring (11a), the first float wiring (12), and the second float wiring (7) to which the gate voltage application gate electrode (7a) is electrically connected are electrically connected. 13) the semiconductor device according to any one of claims 1 to 4, characterized in that each arranged in parallel.

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