CN117352554B - Semiconductor power device with gate trench - Google Patents
Semiconductor power device with gate trench Download PDFInfo
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- CN117352554B CN117352554B CN202311644284.3A CN202311644284A CN117352554B CN 117352554 B CN117352554 B CN 117352554B CN 202311644284 A CN202311644284 A CN 202311644284A CN 117352554 B CN117352554 B CN 117352554B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 58
- 210000000746 body region Anatomy 0.000 claims abstract description 23
- 239000000463 material Substances 0.000 abstract description 7
- 230000003014 reinforcing effect Effects 0.000 abstract description 4
- 239000002019 doping agent Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention relates to the technical field of semiconductor power devices, in particular to a semiconductor power device with a grid groove, which comprises a drift region of a first conductivity type; a body region of a second conductivity type is arranged in the drift region; a source region of the first conductivity type embedded in the body region; a first conductivity type reinforcing region located directly under the body region; a gate trench comprising wide and narrow mesas of uniform length connected end to end surrounding the body region, source region and enhancement region, the gate trench being electrically isolated from the semiconductor by a dielectric layer and in contact with the gate of the device; a contact region formed only within the wide mesa of the gate trench structure, forming an electrical contact to the semiconductor material and to the emitter or source of the semiconductor device; a plurality of the structures described above are laid out with the narrow mesas and the wide mesas alternating in adjacent cells; the semiconductor power device with the grid groove provided by the invention enables the table top to be reduced to the minimum size.
Description
Technical Field
The present invention relates to the field of semiconductor power devices, and more particularly to a semiconductor power device with gate trenches, and the specification describes a novel layout for a high power density or improved process.
Background
The present invention relates to a semiconductor power device with a gate trench, comprising a trench MOSFET (metal oxide semiconductor field effect transistor) and a trench IGBT (insulated gate bipolar transistor), these devices having a gate contact, which is electrically isolated from the rest of the transistor structure by a suitable insulating material, such as silicon dioxide, for controlling and switching the device from a blocking state to a conducting state or vice versa. The gate may be a trench that forms a body of semiconductor material by etching or the like. The design as in US patent 8633510 includes an additional trench, i.e. a dummy trench, that is not connected to the gate potential in order to provide shielding for the gate bias trench, i.e. the source trench. The active trenches and dummy trenches may be alternately laid out (e.g., U.S. patent No. 8633510) or separated into different regions on the device (e.g., U.S. patent No. 20100276728), and the trenches may be arranged in a linear stripe pattern or a closed rectangular layout (e.g., U.S. patent No. 20100276728) to form a regular grid layout in the conductive regions of the semiconductor device.
As for the contact between the top metal material and the semiconductor material, the contact region can also be made by etching to the surface of the material, which must be electrically isolated from the gate to ensure the function of the device, but there is still a need to minimize the distance between the active trenches, commonly referred to as the mesa size, which is often considered a key indicator of device performance and process maturity; in many designs, however, the formation of contact regions limits the size of the mesa, as in U.S. patent No. 7846799 and U.S. patent No. 20190305083 attempt to overcome this limitation by forming x-directional trenches.
Accordingly, the present invention has been made in view of the above-mentioned problems, and it is highly desirable to provide a semiconductor power device having a gate trench.
Disclosure of Invention
The invention provides a semiconductor power device with a gate trench, which is characterized by comprising:
a drift region of the first conductivity type;
a body region of a second conductivity type is arranged in the drift region;
a source region of the first conductivity type embedded in the body region;
a first conductivity type reinforcing region located directly under the body region;
a gate trench comprising a wide mesa and a narrow mesa connected end to end and having a uniform length, surrounding the body region, the source region, and the enhancement region, the gate trench having a dielectric layer disposed therein, electrically isolated from the semiconductor by the dielectric layer, and in contact with the gate of the device;
a contact region formed only within the wide mesa of the gate trench, forming an electrical contact to the semiconductor material and to the emitter or source of the semiconductor device;
a plurality of the structures described above are laid out with the narrow mesas and the wide mesas alternating in adjacent cells.
Preferably, a highly doped floating region of the second conductivity type, i.e. a floating p-well, is formed between two adjacent gate trenches.
Preferably, the floating p-wells are laid out in a rectangular stripe pattern.
Preferably, the source region does not extend through the entire wide mesa region, but forms a rectangular stripe pattern of approximately the same width as the narrow mesa and surrounding the contact region.
Preferably, a floating p-well is formed under the gate trench.
Preferably, a floating p-well is formed under a selected region of the gate trench.
Preferably, some gate trenches do not enclose a source region, i.e., are dummy trenches, and the semiconductor power device including the dummy trenches is a dummy device.
Preferably, the dummy device has no contact region.
Preferably, the dummy device has a floating p-well.
Preferably, the dummy device is connected to an emitter or source potential.
Preferably, the dummy device is electrically floating.
Preferably, the enhancement region may not be provided.
Preferably, an additional layer of the second conductivity type, a p-ring, is provided below the contact region for improving the electrical contact.
Preferably, the connection between the wide mesa and the narrow mesa is spherical, elliptical or circular.
Preferably, the connection between the wide mesa and the narrow mesa is hypotenuse, or comprises a portion of a polygon having any number of edges.
Preferably, the lengths of the narrow mesa and the wide mesa are not equal in some semiconductor power devices having gate trenches.
Preferably, the floating p-well is formed only where two of said narrow mesas are adjacent to each other.
Preferably, the source regions are arranged with interruption between some of the contact regions in the longitudinal direction.
Preferably, the thickness of the gate trench varies in the longitudinal direction in order to form the contact region.
Drawings
Fig. 1a is a top view of a conventional semiconductor power device with gate trenches having a striped layout;
fig. 1b is a top view of a conventional semiconductor power device with gate trenches having a grid layout;
fig. 1c is a top view of one embodiment of a semiconductor power device structure with gate trenches in accordance with the present invention;
fig. 2a is a top view of an embodiment of a semiconductor power device with a gate trench comprising a floating p-well for providing gate trench protection, wherein the contact region is formed only within the wide mesa of the gate trench;
FIG. 2b is a cross-sectional view of the embodiment of FIG. 2a taken along line A;
FIG. 3a is a top view of an embodiment of a semiconductor power device with a gate trench including a floating p-well for providing gate trench protection, wherein the floating p-well is striped;
FIG. 3B is a cross-sectional view of the embodiment of FIG. 3a taken along line B;
fig. 4a is a top view of an embodiment of a semiconductor power device with gate trenches that does not contain a floating p-well, wherein the distance between the gate trenches can be reduced sufficiently for gate trench protection;
FIG. 4b is a cross-sectional view of the embodiment of FIG. 4a taken along line C;
figure 5a is a top view of one embodiment of a semiconductor power device with a gate trench that does not contain a floating p-well, wherein the source regions are disposed only in stripes that are approximately the same width as the active mesa;
FIG. 5b is a cross-sectional view of the embodiment of FIG. 5a taken along line D;
fig. 6a is a top view of one embodiment of a semiconductor power device with a gate trench in accordance with the present invention, wherein an additional layer of dopant of the second conductivity type is formed under the gate trench;
FIG. 6b is a cross-sectional view of the embodiment of FIG. 6a taken along line E;
fig. 7a is a top view of one embodiment of a semiconductor power device having a gate trench in accordance with the present invention, wherein an additional layer of dopant of the second conductivity type is formed beneath selected gate trenches and/or gate trench regions;
FIG. 7b is a cross-sectional view of the embodiment of FIG. 7a taken along line F;
FIG. 8a is a top view of one embodiment of a semiconductor power device with a gate trench containing a dummy cell with a floating p-well, the dummy cell having no source region, but may or may not have a floating p-well and contact region, the dummy trench may be connected to a gate, emitter, or electrically floating;
FIG. 8b is a cross-sectional view of the embodiment of FIG. 8a taken along line G;
fig. 9a is a top view of one embodiment of a semiconductor power device having a gate trench with a circular shape;
fig. 9b is a top view of one embodiment of a semiconductor power device having a gate trench with a polygonal shape;
figure 10a is a top view of one embodiment of a semiconductor power device with a gate trench having an interrupted source region;
figure 10b is a top view of one embodiment of a semiconductor power device with gate trenches having a narrow mesa and a wide mesa of unequal length;
figure 10c is a top view of one embodiment of a semiconductor power device with gate trenches having different lengths of narrow mesa and wide mesa regions with different floating p-well injection modes;
FIG. 11 is a top view of one embodiment of a semiconductor power device having a gate trench with a gate trench thickness that varies in a longitudinal direction;
figure 12 is a top view of one embodiment of a semiconductor power device with a gate trench where a floating p-well is formed only where two narrow mesas are adjacent to each other.
Reference numerals illustrate:
1. a body region; 2. a source region; 3. a contact region; 4. a reinforcing region; 5. floating the p-well; 6. a gate trench; 7. a p-ring; 8. and a dummy trench.
Detailed Description
The technical solutions of the present invention will be clearly and completely described in conjunction with the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As shown in fig. 1a, 1b and 1c, the present invention provides a semiconductor power device with a gate trench, comprising: a drift region of the first conductivity type; a body region 1 of a second conductivity type is arranged in the drift region; a source region 2 of the first conductivity type embedded in the body region 1; a first conductivity type reinforcing region 4 located directly below the body region; a gate trench 6 comprising a wide mesa and a narrow mesa connected end to end and of uniform length surrounding the body region 1, the source region 2 and the enhancement region 4, the gate trench 6 being provided with a dielectric layer therein, being electrically isolated from the semiconductor by the dielectric layer and being in contact with the gate of the device; a contact region 3 formed only within the wide mesa of the gate trench 6, forming an electrical contact to the semiconductor material and to the emitter or source of the semiconductor device; a plurality of the structures described above are laid out with the narrow mesas and the wide mesas alternating in adjacent cells.
An object of the present invention is to provide a semiconductor power device, such as a MOSFET, an IGBT or the like having a source region of a plurality of trench structures, comprising a semiconductor substrate of a first conductivity type, including a region of a second conductivity type, i.e. a body region 1, in which a highly doped region of the first conductivity type, i.e. a source region 2, is formed; in some embodiments, another layer of the first conductivity type may be included under the body region, i.e., enhancement region 4; gate trenches 6 are formed on either side of the body region 1 and are electrically isolated from the remainder of the semiconductor material by an insulating material, such as silicon dioxide, and then the gate trenches 6 are filled with a conductive material and connected to the gate. Within the body region 1, a contact region 3 may also be formed which is connected to the emitter or source of the device, the device being switched from a conducting state to a blocking state and vice versa by adjusting the voltage on the gate, the gate trenches 6 in the prior art forming a stripe or a net-like layout, one stripe or rectangle may be referred to as a cell.
In some cells, the source region 2 may be omitted, in which case the cell is in an inactive state, i.e. a dummy cell with a dummy trench 8, which technique is used to adjust the overall conductivity of the semiconductor device and to add additional protection to the active trench affected by the elevated electric field, the dummy cell may or may not contain an emitter contact, which affects the switching of the device. The dummy trench 8 may be in contact with the gate or emitter electrode, or left floating.
In some embodiments, the dummy cells without contact regions 3 may also include highly doped regions of the second conductivity type, which are not strongly connected to any potential in the device, referred to in some embodiments as floating p-wells 5, the floating p-wells 5 may serve as protection for high voltage electric fields in the device.
The invention is shown schematically, not to scale, in fig. 2a and 2b, the gate trenches 6 are not formed in a stripe or net pattern, but rather are shaped such that within a single cell there is a wider area for accommodating the contact regions 3 and a narrower area for shrinking the mesa between the active trenches. The high conductivity source region 2 is used to conduct current from the contact region 3 to the active mesa region where the current flows in the vertical region of the device. In this embodiment the area between the active cells is filled with a floating p-well 5.
In another embodiment as shown in fig. 3a and 3b, the floating p-wells 5 are arranged in stripes, which may be needed if the distance between the gate trenches 6, i.e. the non-active mesa, becomes small so that patterning becomes difficult.
As shown in fig. 4a and 4b, the present invention also provides an embodiment in which the floating p-well 5 may be omitted, wherein the active and passive mesas are minimized to provide shielding for the gate trench 6 everywhere in the device.
As shown in fig. 5a and 5b, the present invention provides a further variation of this embodiment, in which the source region 2 no longer fills the entire wide mesa with the contact region 3, but only forms stripes of approximately the same width as the active mesa, since the channel region is formed only at the location of the active mesa, the switching uniformity of the device is ensured. The gate trenches 6 in the wide mesas act as dummy trenches 8 in this embodiment and provide shielding for adjacent active trenches. Since the length of the widened and narrowed regions is equal in the present embodiment, the active region and the dummy region alternately provide dummy protection for each source region 2 on both sides.
As shown in fig. 6a and 6b, the present invention provides the same embodiment of the semiconductor device as in fig. 5a and 5b, but after the formation of the gate trench 6, a dopant of the second conductivity type is introduced into the region directly under the gate trench 6, sometimes referred to as the p-ring 7, which acts like a floating p-well 5, however, the p-ring 7 does not require an additional masking step, as the dopant can be introduced directly through the opening of the gate trench 6; furthermore, a p-ring 7 is located directly under the gate trench 6 to provide optimal protection.
As shown in fig. 7a and 7b, the present invention provides a similar embodiment in which part of the gate trench 6 is masked and no dopant is introduced to the region under this part of the gate trench 6, but only the p-ring 7 is included in the wide mesa, which protects the more fragile part of the cell, but does not introduce the p-ring 7 under part of the gate trench 6 to avoid causing bipolar effects.
As shown in fig. 8a and 8b, the present invention provides another embodiment in which the cells alternate between active cells and dummy cells, which enables the highest level of protection of the gate trench 6 with less conductivity. The dummy cells may be implemented with or without floating p-wells 5; the dummy cell may include contact region 3 when floating p-well 5 is not provided. The dummy trenches 8 may be gate or emitter biased or electrically floating, and any of the above types of active cells and dummy cells may be mixed in any order and combination.
As shown in fig. 9a and 9b, all of the above embodiments can also be implemented with a circle or a general polygon by widening and then narrowing back to the original size.
As shown in fig. 10a, the listed embodiments may also have interrupted source regions 2, so that the conductivity of the device is adjusted, and the connection regions and the interruption regions may be alternately present in any proportion.
As shown in fig. 10b or 10c, the wide mesa and the narrow mesa may also be of unequal length in any of the embodiments listed.
As shown in fig. 11, the thickness of the gate trench 6 is changed in the longitudinal direction so as to form the contact region 3.
As shown in fig. 12, the floating p-well 5 is formed only where two of the narrow mesas are adjacent to each other.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While still being apparent from variations or modifications that may be made by those skilled in the art are within the scope of the invention.
Claims (9)
1. A semiconductor power device having a gate trench, comprising:
a drift region of the first conductivity type;
a plurality of cells, each cell comprising a body region (1) of a second conductivity type opposite to the first conductivity type within the drift region;
a source region (2) of the first conductivity type embedded in the body region (1);
an enhancement region (4) of the first conductivity type located directly below and in contact with the body region;
the gate trenches (6) define a narrow mesa and a wide mesa between the gate trenches (6) in a top view, wherein the narrow mesa and the wide mesa are alternately arranged at intervals along the length direction of the gate trenches (6), and the main body region (1), the source region (2) and the enhancement region (4) are arranged in the narrow mesa and the wide mesa; a grid electrode is arranged in the grid electrode groove (6), and is electrically isolated from the drift region, the main body region (1), the source region (2) and the enhancement region (4) through a dielectric layer positioned in the grid electrode groove (6);
a contact region (3) formed only within the wide mesa of the gate trench (6), forming an electrical contact with the body region (1) and the source region (2);
wherein the width of the gate trench (6) in top view at the wide mesa is smaller than the width thereof at the narrow mesa;
forming a highly doped floating region of a second conductivity type, namely a floating p-well (5), below the gap between two adjacent gate trenches (6), and forming the floating p-well (5) only at the positions where two narrow mesas are adjacent;
the source region (2) does not extend through the entire wide mesa but forms a rectangular stripe pattern of approximately the same width as the narrow mesa and surrounding the contact region (3);
wherein adjacent ones of the cells are arranged with the narrow mesas alternating with the wide mesas.
2. The semiconductor power device with gate trench of claim 1, wherein: the floating p-wells (5) are arranged in a rectangular stripe pattern.
3. The semiconductor power device with gate trench of claim 2, wherein: some gate trenches (6) do not enclose a source region (2), namely a dummy trench (8), and a semiconductor power device including the dummy trench (8) is a dummy device.
4. The semiconductor power device with gate trench of claim 3, wherein: the dummy device has no contact region (3).
5. The semiconductor power device with gate trench as defined in claim 4, wherein: the dummy device has a floating p-well (5).
6. The semiconductor power device with gate trench of claim 5, wherein: the dummy device is connected to a source potential.
7. The semiconductor power device with gate trench of claim 6, wherein: the dummy device is electrically floating.
8. The semiconductor power device with gate trench of claim 7, wherein: an additional layer of a second conductivity type, a p-ring (7), is provided below the contact region (3) for improving the electrical contact.
9. The semiconductor power device with gate trench of claim 8, wherein: the source regions (2) are arranged with interruption between some of the contact regions (3) in the longitudinal direction.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311644284.3A CN117352554B (en) | 2023-12-04 | 2023-12-04 | Semiconductor power device with gate trench |
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| CN202311644284.3A CN117352554B (en) | 2023-12-04 | 2023-12-04 | Semiconductor power device with gate trench |
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| CN117352554B true CN117352554B (en) | 2024-02-27 |
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| CN101499473A (en) * | 2008-01-28 | 2009-08-05 | 株式会社电装 | Semiconductor device having insulated gate semiconductor element, and insulated gate bipolar transistor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3524850B2 (en) * | 2000-08-03 | 2004-05-10 | 三洋電機株式会社 | Insulated gate field effect semiconductor device |
| JP5634318B2 (en) * | 2011-04-19 | 2014-12-03 | 三菱電機株式会社 | Semiconductor device |
| US11004969B2 (en) * | 2019-10-07 | 2021-05-11 | Nami MOS CO., LTD. | Trench MOSFETs having dummy cells for avalanche capability improvement |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006093457A (en) * | 2004-09-24 | 2006-04-06 | Toyota Motor Corp | Insulated gate type semiconductor device |
| JP2008177297A (en) * | 2007-01-17 | 2008-07-31 | Toyota Central R&D Labs Inc | Semiconductor device |
| CN101499473A (en) * | 2008-01-28 | 2009-08-05 | 株式会社电装 | Semiconductor device having insulated gate semiconductor element, and insulated gate bipolar transistor |
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| CN117352554A (en) | 2024-01-05 |
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