JP2007116190A - Semiconductor element and its manufacturing method - Google Patents

Semiconductor element and its manufacturing method Download PDF

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JP2007116190A
JP2007116190A JP2006335068A JP2006335068A JP2007116190A JP 2007116190 A JP2007116190 A JP 2007116190A JP 2006335068 A JP2006335068 A JP 2006335068A JP 2006335068 A JP2006335068 A JP 2006335068A JP 2007116190 A JP2007116190 A JP 2007116190A
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semiconductor layer
conductivity type
layer
type semiconductor
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Shoichi Yamaguchi
口 正 一 山
Wataru Saito
藤 渉 齋
Ichiro Omura
村 一 郎 大
Masaru Izumisawa
沢 優 泉
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Toshiba Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor element having high withstand voltage characteristics and low on-resistance characteristics by easily realizing a high withstand voltage. <P>SOLUTION: This semiconductor element 1 includes an n-type drain layer 20, a drain electrode 40 formed so as to be brought into contact with the n-type drain layer 20, an n-type drift layer 26 formed so as to be brought into contact with the n-type drain layer 20, and to make drift currents flow in the on state, and to be depleted in the off state, a p-type drift layer 28 formed so as to be brought into contact with the n-type drain layer 20 and the n-type drift layer 26, and to be depleted in the off state, a p-type base layer 30 formed so as to be brought into contact with the n-type drift layer 26 and the p-type drift layer 28, an n+ source layer 32 formed at the surface part of the p-type base layer 30, an insulating gate electrode 36, and a source electrode 38. This semiconductor element 1 is provided with a cell area part where the drift currents are made to flow and a connection terminal area part formed so that the cell area part can be surrounded. In this case, a second n-type drift layer 26a and a second p-type drift layer 28a formed in at least one of two orthogonal directions are formed in the connection terminal area part. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、半導体素子およびその製造方法に関し、特に電力用スイッチング素子として好適なパワー半導体素子の接合終端領域部の構造を対象とする。   The present invention relates to a semiconductor element and a method for manufacturing the same, and particularly to a structure of a junction termination region portion of a power semiconductor element suitable as a power switching element.

近年のパワーエレクトロニクス分野における電源機器の小型化・高性能化への要求を受けて、パワー半導体素子では、高耐圧化・大電流化とともに、低損失化・高速化・高破壊耐量化に対する性能改善が注力されている。その中で、パワーＭＯＳＦＥＴ（Metal Oxide Semiconductor Field Effect Transistor）はその高速スイッチング性能のため、スイッチング電源分野などでキーデバイスとして定着している。   In response to the recent demand for miniaturization and high performance of power supply equipment in the field of power electronics, power semiconductor devices have improved performance for higher breakdown voltage, higher current, lower loss, higher speed, and higher breakdown capability. Has been focused. Among them, a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) has been established as a key device in the field of switching power supplies because of its high-speed switching performance.

ＭＯＳＦＥＴは多数キャリアデバイスであるため、少数キャリア蓄積時間がなくスイッチングが速いという利点を有する。しかし、この反面、伝導度変調がないために高耐圧素子ではＩＧＢＴ（Insulated Gate Bipolar Transistor）などのバイポーラ素子と比べるとオン抵抗の面で不利になる。これは、ＭＯＳＦＥＴにおいて高い耐圧を得るには、ｎ型ベース層を厚くし不純物濃度も低くする必要があるため、高耐圧の素子ほどＭＯＳＦＥＴのオン抵抗が増大することに起因する。   Since a MOSFET is a majority carrier device, it has the advantage of fast switching with no minority carrier accumulation time. However, on the other hand, since there is no conductivity modulation, a high breakdown voltage element is disadvantageous in terms of on-resistance compared to a bipolar element such as an IGBT (Insulated Gate Bipolar Transistor). This is because, in order to obtain a high breakdown voltage in the MOSFET, it is necessary to increase the thickness of the n-type base layer and reduce the impurity concentration, and therefore the higher the breakdown voltage, the higher the on-resistance of the MOSFET.

パワーＭＯＳＦＥＴのオン抵抗は、伝導層（ｎ型ドリフト層）部分の電気抵抗に大きく依存する。そして、このｎ型ドリフト層の電気抵抗を決定する不純物濃度は、ｐ型ベースとｎ型ドリフト層が形成するｐｎ接合の耐圧に応じて限界以上には上げられない。このため、素子耐圧とオン抵抗にはトレードオフの関係が存在する。このトレードオフを改善することが低消費電力素子には重要となる。このトレードオフには素子の材料により決定される限界があり、この限界を越えることが既存のパワー素子を超える低オン抵抗素子の実現への道である。   The on-resistance of the power MOSFET greatly depends on the electric resistance of the conductive layer (n-type drift layer) portion. The impurity concentration that determines the electric resistance of the n-type drift layer cannot be increased beyond the limit depending on the breakdown voltage of the pn junction formed by the p-type base and the n-type drift layer. For this reason, there is a trade-off relationship between element breakdown voltage and on-resistance. Improving this tradeoff is important for low power consumption devices. This trade-off has a limit determined by the material of the element, and exceeding this limit is the way to realizing a low on-resistance element exceeding the existing power element.

この問題を解決するＭＯＳＦＥＴの一例として、ｎ型ドリフト層にスーパージャンクション構造と呼ばれるリサーフ構造を埋め込んだ構造が知られている。従来の技術によるスーパージャンクション構造を有するパワーＭＯＳＦＥＴについて図３６を参照しながら説明する。なお、以下の各図において同一の部分には同一の参照番号を付してその詳細な説明を省略する。   As an example of a MOSFET that solves this problem, a structure in which a resurf structure called a super junction structure is embedded in an n-type drift layer is known. A power MOSFET having a super junction structure according to the prior art will be described with reference to FIG. In the following drawings, the same parts are denoted by the same reference numerals, and detailed description thereof is omitted.

図３６は、従来の技術によるパワーＭＯＳＦＥＴの一例の概略構成を模式的に示す断面図である。同図に示すＭＯＳＦＥＴは、ｎ−型ドリフト層１０２の一方の表面にｎ＋型ドレイン層１００が形成され、このｎ＋型ドレイン層１００上にはドレイン電極４０が形成されている。また、ｎ−型ドリフト層１０２の他方の表面部には複数のｐ型ベース層１０８が選択的に形成され、この各ｐ型ベース層１０８の表面にはｎ＋型ソース層１１０が選択的に形成されている。また、ｎ＋型ソース層１１０およびｐ型ベース層１０８の表面からｎ−型ドリフト層１０２の表面を通って隣り合うｐ型ベース層１０８およびｎ＋型ソース層１１０の表面に至る領域上には、ゲート絶縁膜１１２を介してゲート電極１１４が形成されている。また、ｐ型ベース層１０８の表面部に隣り合って形成されたｎ＋型ソース層１１０の表面とこれらに挟まれたｐ型ベース層１０８の表面の領域上には、各々ソース電極１１６が形成され、ゲート電極１１４を挟むように配置されている。さらに、ｐ型ベース層１０８とｎ＋型ドレイン層１００との間のｎ−型ドリフト層１０２中には、リサーフ層をなすように形成されてｐ型ベース層１０８に接続されたｐ型ドリフト層１０６が形成されている。このように、図３６に示すパワーＭＯＳＦＥＴは、ｐ型ドリフト層１０６と、ｎ−型ドリフト層１０２のうちこれらｐ型ドリフト層１０６に挟まれた部分とが交互に横方向に繰り返す縦型リサーフ構造となっている。 FIG. 36 is a cross-sectional view schematically showing a schematic configuration of an example of a power MOSFET according to a conventional technique. In the MOSFET shown in the figure, an n + -type drain layer 100 is formed on one surface of an n − -type drift layer 102, and a drain electrode 40 is formed on the n + -type drain layer 100. A plurality of p-type base layers 108 are selectively formed on the other surface portion of the n − -type drift layer 102, and an n + -type source layer 110 is selectively formed on the surface of each p-type base layer 108. Is formed. Further, on the region from the surface of the n + -type source layer 110 and the p-type base layer 108 to the surface of the adjacent p-type base layer 108 and the n + -type source layer 110 through the surface of the n − -type drift layer 102, A gate electrode 114 is formed through the gate insulating film 112. A source electrode 116 is formed on the surface of the n + -type source layer 110 formed adjacent to the surface portion of the p-type base layer 108 and the region of the surface of the p-type base layer 108 sandwiched therebetween. The gate electrode 114 is interposed therebetween. Further, in the n − type drift layer 102 between the p type base layer 108 and the n + type drain layer 100, a p type drift layer formed so as to form a RESURF layer and connected to the p type base layer 108. 106 is formed. As described above, the power MOSFET shown in FIG. 36 has a vertical RESURF structure in which the p-type drift layer 106 and the portion sandwiched between the p-type drift layers 106 in the n − -type drift layer 102 are alternately repeated in the horizontal direction. It has become.

オフ状態では、これらのｐ型ドリフト層１０６と、ｎ−型ドリフト層１０２との間の接合に空乏層が広がり、ｎ−型ドリフト層１０２の不純物濃度を高くしても、ブレークダウンする前にｎ−型ドリフト層１０２とｐ型ドリフト層１０６とが完全に空乏化する。これにより、従来のＭＯＳＦＥＴと同様の耐圧が得られる。 In the off state, a depletion layer spreads at the junction between the p-type drift layer 106 and the n − type drift layer 102, and even if the impurity concentration of the n − type drift layer 102 is increased, before the breakdown occurs. The n − type drift layer 102 and the p type drift layer 106 are completely depleted. Thereby, the breakdown voltage similar to that of the conventional MOSFET can be obtained.

ここで、ｎ−型ドリフト層１０２の不純物濃度は、素子の耐圧ではなく、ｐ型ドリフト層１０６の幅とこれらのｐ型ドリフト層１０６の間のｎ−型ドリフト層１０２自身の幅に依存する。ｎ−型ドリフト層１０２の幅とｐ型ドリフト層１０６の幅をさらに狭くすれば、ｎ−型ドリフト層１０２の不純物濃度をいっそう高くすることができ、オン抵抗の更なる低減化と更なる高耐圧化を達成することが可能である。 Here, the impurity concentration of the n − type drift layer 102 does not depend on the breakdown voltage of the element, but depends on the width of the p type drift layer 106 and the width of the n − type drift layer 102 itself between these p type drift layers 106. . If the width of the n − type drift layer 102 and the width of the p type drift layer 106 are further reduced, the impurity concentration of the n − type drift layer 102 can be further increased, and the on-resistance can be further reduced and further increased. It is possible to achieve a breakdown voltage.

このようなＭＯＳＦＥＴを設計する際には、ｎ−型ドリフト層１０２とｐ型ドリフト層１０６の不純物濃度が耐圧とオン抵抗を決める重要なポイントとなる。原理的にｎ−型ドリフト層１０２とｐ型リサーフ層１０６のそれぞれの不純物量を等しくすることにより等価的に不純物濃度がゼロとなって、高耐圧が得られる。 When designing such a MOSFET, the impurity concentration of the n − -type drift layer 102 and the p-type drift layer 106 is an important point that determines the breakdown voltage and the on-resistance. In principle, by making the respective impurity amounts of the n − type drift layer 102 and the p type RESURF layer 106 equal, the impurity concentration becomes equivalently zero, and a high breakdown voltage is obtained.

しかしながら、従来のスーパージャンクション構造の半導体素子については、素子活性領域部（以下、セル領域部という）を囲むように設けられた接合終端領域部において、阻止状態（オフ状態）やターンオフ時に高耐圧を得るための有効な構造が見出されていない。このため、セル領域部と接合終端領域部では、空乏層の広がり方が異なるため、最適の不純物濃度が異なる。従って、セル領域部と接合終端領域部とで同じ不純物量となるように製造すると、終端部で耐圧が低下し、この箇所に局所的に電界が集中する結果、素子が破壊されることがある。このように、従来の技術では素子全体としては充分な高耐圧が得られないという問題があった。   However, a conventional super junction structure semiconductor device has a high withstand voltage in a blocking state (off state) or turn-off in a junction termination region portion provided so as to surround an element active region portion (hereinafter referred to as a cell region portion). No effective structure has been found to obtain. For this reason, the cell region portion and the junction termination region portion have different ways of spreading the depletion layer, so that the optimum impurity concentration differs. Therefore, if the cell region portion and the junction termination region portion are manufactured so as to have the same impurity amount, the breakdown voltage is reduced at the termination portion, and as a result of local concentration of the electric field at this portion, the element may be destroyed. . As described above, the conventional technology has a problem that a sufficient high breakdown voltage cannot be obtained as the whole element.

また、実際に製造するときにはプロセス間でばらつきがあるため、ｎ−型ドリフト層１０２とｐ型ドリフト層１０６のそれぞれの不純物量を完全に等しくすることは困難であり、これによって耐圧が劣化する。従って、このようなプロセスマージンによる耐圧劣化を考慮して素子設計を行う必要がある。オン抵抗を下げるためには、ｎ−型ドリフト層１０２の不純物濃度を上げることが有効である。この一方、耐圧に対するプロセスマージンは、ｎ−型ドリフト層１０２とｐ型ドリフト層１０６との間の不純物量の差で決まる。このため、ｎ−型ドリフト層１０２の不純物濃度を上げた場合、プロセスマージンを決める不純物量の差自体が変わるわけではないので、許容される不純物量とｎ−型ドリフト層１０２の不純物量との比が小さくなる。つまり、プロセスマージンが小さくなってしまう。 Further, since there are variations between processes when actually manufacturing, it is difficult to make the respective impurity amounts of the n − -type drift layer 102 and the p-type drift layer 106 completely equal to each other, which deteriorates the breakdown voltage. Therefore, it is necessary to design an element in consideration of the breakdown voltage degradation due to such a process margin. In order to reduce the on-resistance, it is effective to increase the impurity concentration of the n − -type drift layer 102. On the other hand, the process margin for the breakdown voltage is determined by the difference in the amount of impurities between the n − -type drift layer 102 and the p-type drift layer 106. For this reason, when the impurity concentration of the n − type drift layer 102 is increased, the difference in impurity amount itself that determines the process margin does not change, so that the allowable impurity amount and the impurity amount of the n − type drift layer 102 are not changed. The ratio becomes smaller. That is, the process margin becomes small.

本発明は、上記事情に鑑みてなされたものであり、その目的は、従来よりも容易かつ良好に高耐圧化でき、高耐圧特性と低オン抵抗特性とを両立し得る半導体素子およびその製造方法を提供することにある。   The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device that can easily and satisfactorily have a higher breakdown voltage than conventional ones, and can achieve both a high breakdown voltage characteristic and a low on-resistance characteristic, and a method for manufacturing the same Is to provide.

本発明によれば、
セル領域部と、このセル領域部を囲むように設けられた接合終端領域部とを有し、前記接合終端領域部での不純物濃度が前記セル領域部での不純物濃度よりも低くなるように形成された第１の第１導電型半導体層と、
前記第１の第１導電型半導体層の一方の表面上に形成された第２の第１導電型半導体層と、
前記第２の第１導電型半導体層に電気的に接続された第１の主電極と、
前記第１の第１導電型半導体層の前記セル領域部内で前記第１の第１導電型半導体層の一方の表面にほぼ垂直な方向でそれぞれが形成され、前記一方の表面に平行な任意の方向である第１の方向に周期的に配置された第１の第２導電型半導体層と、
前記第１の第１導電型半導体層の他方の表面部において前記第１の第２導電型半導体層に接続するように選択的に形成された第２の第２導電型半導体層と、
前記第２の第２導電型半導体層の表面部に選択的に形成された第３の第１導電型半導体層と、
前記第２の第２導電型半導体層の表面と前記第３の第１導電型半導体層の表面とに接するように形成された第２の主電極と、
前記第１の第１導電型半導体層の他方の表面のうち隣り合う前記第２の第２導電型半導体層に挟まれた領域と、前記隣り合う第２の第２導電型半導体層の表面と前記第３の第１導電型半導体層の表面の上にゲート絶縁膜を介して形成された制御電極と、
前記接合終端領域部内で前記セル領域部との境界面近傍の表面部において前記セル領域部を取り囲むように形成され、前記第２の主電極に電気的に接続される第３の第２導電型半導体層と、
を備える半導体素子が提供される。 According to the present invention,
It has a cell region portion and a junction termination region portion provided so as to surround the cell region portion, and is formed so that the impurity concentration in the junction termination region portion is lower than the impurity concentration in the cell region portion. A first first conductivity type semiconductor layer formed;
A second first conductivity type semiconductor layer formed on one surface of the first first conductivity type semiconductor layer;
A first main electrode electrically connected to the second first conductivity type semiconductor layer;
Each of the first first conductivity type semiconductor layers is formed in a direction substantially perpendicular to one surface of the first first conductivity type semiconductor layer within the cell region portion of the first first conductivity type semiconductor layer, and is arbitrary in parallel to the one surface. A first second conductivity type semiconductor layer periodically disposed in a first direction which is a direction;
A second second conductivity type semiconductor layer selectively formed so as to be connected to the first second conductivity type semiconductor layer at the other surface portion of the first first conductivity type semiconductor layer;
A third first conductivity type semiconductor layer selectively formed on a surface portion of the second second conductivity type semiconductor layer;
A second main electrode formed so as to be in contact with the surface of the second second conductivity type semiconductor layer and the surface of the third first conductivity type semiconductor layer;
Of the other surface of the first first conductivity type semiconductor layer, a region sandwiched between the adjacent second second conductivity type semiconductor layers, and the surface of the adjacent second second conductivity type semiconductor layer, A control electrode formed on the surface of the third first conductivity type semiconductor layer via a gate insulating film;
A third second conductivity type formed so as to surround the cell region portion in a surface portion in the vicinity of the boundary surface with the cell region portion in the junction termination region portion and electrically connected to the second main electrode. A semiconductor layer;
A semiconductor device is provided.

また、本発明によれば、
アスペクト比Ｒのトレンチ溝が設けられた第１導電型半導体層と前記トレンチ溝内に埋め込まれた第２導電型半導体層とを有するスーパージャンクション構造の半導体素子の製造方法であって、
第１導電型半導体層内にＲ／Ｎ（Ｎは２以上の自然数）のアスペクト比を有するトレンチ溝を形成する第１の工程と、
前記トレンチ溝を埋め込むように第２導電型半導体層をエピタキシャル成長させる第２の工程と、
前記第１導電型半導体層の表面が露出するまで前記第２導電型半導体層を除去する第３の工程と、
前記第１導電型半導体層および前記第２導電型半導体層の上に、前記第１の工程により形成されたトレンチ溝の深さと実質的に同一の長さだけ層厚が増大するように前記第１導電型半導体層をエピタキシャル成長させる第４の工程と、
前記第１の工程により形成されたトレンチ溝に埋め込まれた前記第２導電型半導体層が露出するように前記第１導電型半導体層を選択的に除去する第５の工程と、
前記第２乃至第５の工程を（Ｎ−１）回だけ繰り返す工程と、
を備える半導体素子の製造方法が提供される。 Moreover, according to the present invention,
A method for manufacturing a semiconductor device having a super junction structure having a first conductivity type semiconductor layer provided with a trench groove having an aspect ratio R and a second conductivity type semiconductor layer embedded in the trench groove,
Forming a trench groove having an aspect ratio of R / N (N is a natural number of 2 or more) in the first conductivity type semiconductor layer;
A second step of epitaxially growing a second conductivity type semiconductor layer so as to fill the trench groove;
A third step of removing the second conductive semiconductor layer until a surface of the first conductive semiconductor layer is exposed;
The thickness of the first conductive semiconductor layer and the second conductive semiconductor layer is increased by a length substantially the same as the depth of the trench formed in the first step. A fourth step of epitaxially growing the one conductivity type semiconductor layer;
A fifth step of selectively removing the first conductive type semiconductor layer so that the second conductive type semiconductor layer embedded in the trench groove formed by the first step is exposed;
Repeating the second to fifth steps (N-1) times;
A method for manufacturing a semiconductor device is provided.

以上詳述したとおり、本発明は、以下の効果を奏する。
即ち、本発明によれば、低オン抵抗と高耐圧とを同時に実現する半導体素子が提供される。 As described above in detail, the present invention has the following effects.
That is, according to the present invention, there is provided a semiconductor element that can simultaneously realize a low on-resistance and a high breakdown voltage.

また、本発明によれば、スーパージャンクション構造を有する半導体素子を少ない工程数で形成することができる。   Further, according to the present invention, a semiconductor element having a super junction structure can be formed with a small number of steps.

本発明の実施の形態のいくつかについて図面を参照しながら説明する。以下では先ず本発明にかかる半導体素子の実施の形態について説明し、最後に本発明にかかる半導体素子の製造方法の実施の形態について説明する。   Several embodiments of the present invention will be described with reference to the drawings. Hereinafter, an embodiment of a semiconductor device according to the present invention will be described first, and finally, an embodiment of a method for manufacturing a semiconductor device according to the present invention will be described.

（Ａ）半導体素子の実施形態
以下では、スーパージャンクション構造を有するパワーＭＯＳＦＥＴを取り上げて説明する。しかしながら、本発明にかかる半導体素子は、これに限ることなく、スーパージャンクション構造を有するＳＢＤやＭＰＳダイオード、ＳＩＴ、ＪＦＥＴ、ＩＧＢＴ等のスイッチング素子、ダイオードとスイッチング素子の複合素子または集積素子に対しても適用可能である。 (A) Embodiment of Semiconductor Device Hereinafter, a power MOSFET having a super junction structure will be described. However, the semiconductor element according to the present invention is not limited to this, and is also applicable to a switching element such as SBD, MPS diode, SIT, JFET, IGBT, etc. having a super junction structure, a composite element or an integrated element of a diode and a switching element. Applicable.

（１）第１の実施形態
図１は、本発明にかかる半導体素子の第１の実施の形態の概略構造を示す平面図である。図２および図３は、それぞれ図１の切断線Ａ−Ａ、Ｂ−Ｂに沿った本実施形態の半導体素子の断面図である。図３６との対比において明らかなように、本実施形態の半導体素子１の特徴は、ｎ型ドリフト層２６とｐ型ドリフト層２８とがセル領域部のみならず、接合終端領域部の周縁近傍に至るまで形成されている点にある。以下、本実施形態の半導体素子１の構造をより詳細に説明する。 (1) 1st Embodiment FIG. 1: is a top view which shows schematic structure of 1st Embodiment of the semiconductor element concerning this invention. 2 and 3 are cross-sectional views of the semiconductor device of the present embodiment taken along section lines AA and BB in FIG. 1, respectively. As is clear from comparison with FIG. 36, the semiconductor element 1 of the present embodiment is characterized in that the n-type drift layer 26 and the p-type drift layer 28 are not only in the cell region portion but also in the vicinity of the periphery of the junction termination region portion. It is in the point formed until. Hereinafter, the structure of the semiconductor element 1 of the present embodiment will be described in more detail.

本実施形態の半導体素子１は、ｎ＋型ドレイン層２０と、ドレイン電極４０と、ｎ型ドリフト層２６と、ｐ型ドリフト層２８と、ｐ型ベース層３０と、ｎ＋型ソース層３２と、ソース電極３８と、絶縁ゲート電極３６と、フィールド電極４８とを備える。 The semiconductor element 1 of this embodiment includes an n + type drain layer 20, a drain electrode 40, an n type drift layer 26, a p type drift layer 28, a p type base layer 30, an n + type source layer 32, Source electrode 38, insulated gate electrode 36, and field electrode 48.

ドレイン電極４０は、ｎ＋型ドレイン層２０の一方の表面、図２および３においては下面に形成される。ｐ型ドリフト層２８は、ｎ＋型ドレイン層２０の他方の表面、図２および３においては上面に形成されたｎ型半導体層２６内でそれぞれｎ＋型ドレイン層２０との境界面からｎ型半導体層２６の表面部に至るまでストライプ形状をなすように形成され、各ストライプ状のｐ型ドリフト層２８は、ｎ＋型ドレイン層２０の表面に水平な所定方向においてセル領域部のみならず接合終端領域部にまで所定の間隔で配置される。ｎ型半導体層２６内でこれらのｐ型ドリフト層２８に挟まれた領域は、ｎ型ドリフト層２６を構成する。ｎ型ドリフト層２６とｐ型ドリフト層２８のいずれについても、その幅および不純物濃度は、例えば幅が５μｍの場合で不純物濃度が約４×１０１５ｃｍ−３であり、幅が１μｍであれば、その不純物濃度は約２×１０１６ｃｍ−３である。 The drain electrode 40 is formed on one surface of the n + -type drain layer 20, that is, the lower surface in FIGS. The p-type drift layer 28 is n-type from the interface with the n + -type drain layer 20 in the n-type semiconductor layer 26 formed on the other surface of the n + -type drain layer 20, or the upper surface in FIGS. The stripe-shaped p-type drift layer 28 is formed not only in the cell region portion but also in a predetermined direction on the surface of the n + -type drain layer 20 so as to form a stripe shape up to the surface portion of the semiconductor layer 26. They are arranged at predetermined intervals up to the termination region. A region sandwiched between these p-type drift layers 28 in the n-type semiconductor layer 26 constitutes the n-type drift layer 26. The width and impurity concentration of both the n-type drift layer 26 and the p-type drift layer 28 are, for example, when the width is 5 μm and the impurity concentration is about 4 × 10 15 cm −3 and the width is 1 μm. The impurity concentration is about 2 × 10 16 cm −3 .

ｐ型ベース層３０は、ｐ型ドリフト層２８に接続するようにｎ型半導体層内２６の表面部に選択的に形成される。ｎ＋型ソース層３２は、ｐ型ベース層３０の表面部に選択的に形成される。ソース電極３８は、ｐ型ベース層３０の表面において隣り合うｎ＋型ソース層３２とこれらに挟まれたｐ型ベース層３０に接続するように形成される。さらに、これらのソース電極３８に囲まれるように、絶縁ゲート電極３６は、ｎ型ドリフト層２６の表面、これに隣接するｐ型ベース層３０の表面およびこのｐ型ベース層３０に接するｎ＋型ソース層３２の表面上に絶縁膜３４を介して配設される。このような構造により、半導体素子１は、絶縁ゲート３６直下のｐ型ベース層３０の表面部をチャネル領域とする電子注入用ｎチャネルＭＯＳＦＥＴを構成する。本実施形態では、プレーナ型のゲート構造を有する場合について説明するが、トレンチ型のゲート構造を用いても良い。この点は、以下の各実施形態についても同様である。 The p-type base layer 30 is selectively formed on the surface portion of the n-type semiconductor layer 26 so as to be connected to the p-type drift layer 28. The n + type source layer 32 is selectively formed on the surface portion of the p type base layer 30. The source electrode 38 is formed so as to be connected to the n + -type source layer 32 adjacent on the surface of the p-type base layer 30 and the p-type base layer 30 sandwiched therebetween. Further, the insulated gate electrode 36 is surrounded by the source electrode 38, and the n + type is in contact with the surface of the n-type drift layer 26, the surface of the p-type base layer 30 adjacent thereto, and the p-type base layer 30. An insulating film 34 is disposed on the surface of the source layer 32. With such a structure, the semiconductor element 1 constitutes an n-channel MOSFET for electron injection in which the surface portion of the p-type base layer 30 immediately below the insulating gate 36 is a channel region. In this embodiment, the case of having a planar gate structure is described, but a trench gate structure may be used. This also applies to each of the following embodiments.

半導体素子１はまた、接合終端領域部のうちセル領域部との境界近傍の表面部でセル領域部を囲むように形成されたｐ型ベース層３０ａを備える。ｐ型ベース層３０ａは、接合終端領域部に設けられたｐ型ドリフト層２８ａのうちセル領域部に最も近いｐ型ドリフト層２８ａに離散的に接続される。接合終端領域部の表面には、ｐ型ベース層３０ａ上の一部の領域を除いて絶縁膜４６が形成され、この絶縁膜４６上にフィールド電極４８がセル領域を囲むように形成され、ｐ型ベース層３０ａの表面にコンタクトするとともに、ソース電極３８と電気的に接続される。接合終端領域の周縁には、ｎ型ドリフト層２６の表面部に高濃度のｎ＋型チャネルストッパ層４２が形成され、このｎ＋型チャネルストッパ層４２上に電極４４が設けられる。 The semiconductor element 1 also includes a p-type base layer 30a formed so as to surround the cell region portion at the surface portion near the boundary with the cell region portion in the junction termination region portion. The p-type base layer 30a is discretely connected to the p-type drift layer 28a closest to the cell region portion among the p-type drift layers 28a provided in the junction termination region portion. An insulating film 46 is formed on the surface of the junction termination region except for a part of the region on the p-type base layer 30a, and a field electrode 48 is formed on the insulating film 46 so as to surround the cell region. It contacts the surface of the mold base layer 30 a and is electrically connected to the source electrode 38. A high concentration n + type channel stopper layer 42 is formed on the surface of the n type drift layer 26 at the periphery of the junction termination region, and an electrode 44 is provided on the n + type channel stopper layer 42.

図２および図３内の破線は、等電位線を表わし、これは、ｎ型ドリフト層２６とｐ型ドリフト層２８の幅が８μｍ、不純物濃度が２×１０１５ｃｍ−３、厚さが５０μｍの条件を用いて計算したシミュレーション結果である。 2 and 3 represent equipotential lines. The width of the n-type drift layer 26 and the p-type drift layer 28 is 8 μm, the impurity concentration is 2 × 10 15 cm −3 , and the thickness is 50 μm. It is the simulation result calculated using the conditions.

本実施形態の半導体素子１は、ターンオフ時において、平面視におけるドリフト層２６（２６ａ），２８（２８ａ）のストライプ長手方向（図１のＢ−Ｂ方向、以下、水平方向という）に直交する方向（図１のＡ−Ａ方向、以下、垂直方向という）についてはｎ型ドリフト層２６ａとｐ型ドリフト層２８ａのセル領域部に近い側から素子周縁へ向けて空乏化が進み、水平方向では、ドリフト層２６ａ，２８ａの素子周縁部からセル領域部にかけて、その境界面で同時に空乏化が進む。このとき、電子はｎ型ドリフト層２６ａからｎ＋型ドレイン層２０を介してドレイン電極４０に排出され、この一方、正孔はｐ型ドリフト層２８ａからｐ型ベース層３０ａおよびフィールド電極４８を介してソース電極３８に排出される。ただし、垂直方向においては、正孔はｎ型ドリフト層２６ａとｐ型ドリフト層２８ａとの接合を横切るように排出される。さらに、阻止状態（オフ時）においては、図２および図３に示すように、フィールド電極４８により等電位線の間隔が均一化されるので、これにより電界が緩和される。この結果、半導体素子１について安定した高耐圧を得ることができる。 The semiconductor element 1 of the present embodiment is perpendicular to the stripe longitudinal direction of the drift layers 26 (26 a) and 28 (28 a) in plan view (BB direction in FIG. 1, hereinafter referred to as the horizontal direction) when turned off. For the A-A direction in FIG. 1 (hereinafter referred to as the vertical direction), depletion proceeds from the side close to the cell region portion of the n-type drift layer 26a and the p-type drift layer 28a toward the periphery of the element. Depletion proceeds simultaneously at the boundary surface from the peripheral edge of the drift layers 26a, 28a to the cell region. At this time, electrons are discharged from the n-type drift layer 26 a to the drain electrode 40 via the n + -type drain layer 20, while holes are transferred from the p-type drift layer 28 a to the p-type base layer 30 a and the field electrode 48. To the source electrode 38. However, in the vertical direction, holes are discharged so as to cross the junction between the n-type drift layer 26a and the p-type drift layer 28a. Further, in the blocking state (OFF state), as shown in FIGS. 2 and 3, the field electrode 48 makes the equipotential line intervals uniform, thereby relaxing the electric field. As a result, a stable high breakdown voltage can be obtained for the semiconductor element 1.

なお、ｎ型ドレイン層２０の構造は、図１〜図３に示す形態に限られることなく、例えばエピタキシャル・ウェーハの基板やこれを所定の深さだけ熱拡散した層、または不純物を熱拡散した拡散層などを適用することができる。また、本実施形態ではｎ型ドレイン層２０およびｎ型半導体層２６の２層構造としたが、これらの間に濃度が連続的に変化する中間層を介装しても良い。また、本実施形態では、図２および図３に示すように単一の厚さを有する絶縁膜４６上にフィールド電極４８を形成したが、これに限ることなく、例えば後述する第１１〜第１６の実施形態におけるように、絶縁膜４６の厚さを周縁部に近づくにつれて漸次増大するように設定しても良い。これらの点は、以下の第２〜第１０の実施形態についても同様である。   The structure of the n-type drain layer 20 is not limited to the form shown in FIGS. 1 to 3. For example, the substrate of an epitaxial wafer, a layer obtained by thermally diffusing the substrate by a predetermined depth, or impurities are thermally diffused. A diffusion layer or the like can be applied. In the present embodiment, the n-type drain layer 20 and the n-type semiconductor layer 26 have a two-layer structure. However, an intermediate layer having a continuously changing concentration may be interposed therebetween. In the present embodiment, the field electrode 48 is formed on the insulating film 46 having a single thickness as shown in FIGS. 2 and 3, but the present invention is not limited to this. As in the embodiment, the thickness of the insulating film 46 may be set so as to gradually increase as it approaches the peripheral edge. These points are the same in the following second to tenth embodiments.

（２）第２の実施形態
図４は、本発明にかかる半導体素子の第２の実施の形態の概略構造を示す平面図である。図５および図６は、それぞれ図４の切断線Ａ−Ａ、Ｂ−Ｂに沿った本実施形態の半導体素子の断面図である。 (2) Second Embodiment FIG. 4 is a plan view showing a schematic structure of a second embodiment of a semiconductor element according to the present invention. 5 and 6 are cross-sectional views of the semiconductor device of the present embodiment taken along section lines AA and BB in FIG. 4, respectively.

本実施形態の半導体素子２は、図１に示す半導体素子１が備えるフィールド電極４８に代えて、接合終端領域部内でセル領域を囲むように配置されたｐ型ベース層３０ａに接続してさらにこれを囲むように形成されたｐ−型リサーフ層５２を備える。半導体素子２のその他の構造は、図１に示す半導体素子１と実質的に同一である。 The semiconductor element 2 of this embodiment is connected to a p-type base layer 30a arranged so as to surround the cell region in the junction termination region instead of the field electrode 48 provided in the semiconductor element 1 shown in FIG. The p − type RESURF layer 52 is formed so as to surround the substrate. The other structure of the semiconductor element 2 is substantially the same as that of the semiconductor element 1 shown in FIG.

図２および図３の等電位線に示すように、このようなｐ−型リサーフ層５２を備えることによっても、オフ時に電界が緩和されので、安定した高耐圧を得ることができる。 As shown by the equipotential lines in FIG. 2 and FIG. 3, by providing such a p − type RESURF layer 52, the electric field is relaxed at the time of OFF, so that a stable high breakdown voltage can be obtained.

（３）第３の実施形態
図７は、本発明にかかる半導体素子の第３の実施の形態の概略構造を示す平面図である。なお、同図中の切断線Ａ−Ａに沿った断面図は、図２と実質的に同一である。 (3) Third Embodiment FIG. 7 is a plan view showing a schematic structure of a semiconductor device according to a third embodiment of the present invention. In addition, the cross-sectional view along the cutting line AA in the figure is substantially the same as FIG.

本実施形態の半導体素子３の特徴は、上述した実施形態と異なり、ｐ型ドリフト層５４，５４ａが円形の平面形状を有する点にある。このような形状でｐ型ドリフト層を構成することにより、素子の表面に水平な面内のどの方向にも同様に空乏層を伸ばすことができる。   The feature of the semiconductor element 3 of this embodiment is that the p-type drift layers 54 and 54a have a circular planar shape, unlike the above-described embodiment. By configuring the p-type drift layer in such a shape, the depletion layer can be similarly extended in any direction in a plane horizontal to the surface of the element.

なお、図７では円形パターンを有する場合について示したが、四角形や六角形等の多角形のパターンでも良い。また、ｎ型ドリフト層２６がパターンを有するように形成しても良い。また、上述した第２の実施形態と同様に、フィールド電極４８に代えてリサーフ層を適用することもできる。   Although FIG. 7 shows a case where a circular pattern is provided, a polygonal pattern such as a square or a hexagon may be used. Further, the n-type drift layer 26 may be formed to have a pattern. Further, similarly to the second embodiment described above, a RESURF layer can be applied instead of the field electrode 48.

（４）第４の実施形態
図８は、本発明にかかる半導体素子の第４の実施の形態の概略構造を示す平面図である。図９は、図８の切断線Ａ−Ａに沿った本実施形態の半導体素子の断面図である。 (4) Fourth Embodiment FIG. 8 is a plan view showing a schematic structure of a fourth embodiment of a semiconductor element according to the present invention. FIG. 9 is a cross-sectional view of the semiconductor device of the present embodiment taken along the cutting line AA of FIG.

本実施形態の半導体素子４は、上述した第１〜第３の実施形態とは異なり、接合終端領域部のｎ型ベース層としてセル領域部のｎ型ドリフト層２６よりも低濃度のｎ−型ベース層６８を備える。さらに、半導体素子４は、後述するｐ型ドリフト層２７を除き、接合終端領域部内にドリフト層を有しない。ｎ−型ベース層６８の表面部には、セル領域を囲むようにｐ型ベース層３０ａおよび複数のｐ型ガードリング層６２が選択的に形成される。ｐ型ベース層３０ａの下方にはその配置に対応してｐ型ドリフト層２７が形成され、これによりｐ型ベース層３０ａがドレイン層２０を介してドレイン電極４０に接続される。 Unlike the first to third embodiments described above, the semiconductor element 4 of the present embodiment is an n − type having a lower concentration than the n type drift layer 26 of the cell region as the n type base layer of the junction termination region. A base layer 68 is provided. Further, the semiconductor element 4 does not have a drift layer in the junction termination region except for a p-type drift layer 27 described later. A p-type base layer 30a and a plurality of p-type guard ring layers 62 are selectively formed on the surface portion of the n − -type base layer 68 so as to surround the cell region. A p-type drift layer 27 is formed below the p-type base layer 30a in accordance with the arrangement thereof, whereby the p-type base layer 30a is connected to the drain electrode 40 through the drain layer 20.

このように、本実施形態によれば、接合終端領域部内に複数のドリフト層を有しない場合であっても、セル領域部を取り囲む単一のスーパージャンクション構造と、その周辺の表面部で同様にセル領域を取り囲むように形成されたｐ型ガードリング層６２により、安定した高耐圧を得ることができる。   As described above, according to the present embodiment, even in the case where a plurality of drift layers are not provided in the junction termination region portion, the single super junction structure surrounding the cell region portion and the surface portion around it are similarly applied. A stable high breakdown voltage can be obtained by the p-type guard ring layer 62 formed so as to surround the cell region.

本実施形態の一変形例の断面図を図１０に示す。同図に示す半導体素子４’は、セル領域部のｎ型ドリフト層２６と同一濃度のｎ型ベース層２２を接合終端領域部に有し、接合終端領域部にもｐ型ドリフト層２９が設けられ、ｎ型ベース層２２の表面部に選択的に設けられたｐ型ガードリング層６２’に接続される。さらに、接合終端領域部の周縁部には、ｎ型ベース層２２の表面に露出するようにｐ型ドリフト層２９’が形成されている。これらの構成により、接合終端領域部に広がる等電位線がなだらかになるので、安定した高耐圧が得られる。この結果、接合終端領域部での耐圧低下が抑制される。   A cross-sectional view of a modification of this embodiment is shown in FIG. The semiconductor element 4 ′ shown in the figure has an n-type base layer 22 in the junction termination region having the same concentration as the n-type drift layer 26 in the cell region, and a p-type drift layer 29 is also provided in the junction termination region. And connected to a p-type guard ring layer 62 ′ selectively provided on the surface of the n-type base layer 22. Further, a p-type drift layer 29 ′ is formed on the periphery of the junction termination region so as to be exposed on the surface of the n-type base layer 22. With these configurations, the equipotential lines extending in the junction termination region portion become gentle, so that a stable high breakdown voltage can be obtained. As a result, a decrease in breakdown voltage at the junction termination region is suppressed.

（５）第５の実施形態
図１１は、本発明にかかる半導体素子の第５の実施の形態の概略構造を示す平面図である。図１２は、図１１の切断線Ａ−Ａに沿った本実施形態の半導体素子の断面図である。なお、図１１の切断線Ｂ−Ｂに沿った断面図は図３と同様である。 (5) Fifth Embodiment FIG. 11 is a plan view showing a schematic structure of a semiconductor device according to a fifth embodiment of the present invention. FIG. 12 is a cross-sectional view of the semiconductor device of the present embodiment taken along the cutting line AA of FIG. Note that the cross-sectional view along the cutting line BB in FIG. 11 is the same as FIG.

本実施形態は、セル領域部のｎ型ドリフト層２６内で水平方向に平行に形成された絶縁膜を有する半導体素子に好適な接合終端領域構造を提供するものである。   The present embodiment provides a junction termination region structure suitable for a semiconductor element having an insulating film formed in parallel in the horizontal direction within the n-type drift layer 26 in the cell region portion.

図１１および図１２に示すように、本実施形態の半導体素子５では、ｎ型ドリフト層２６（２６ａ）内で水平方向にトレンチ溝６４が形成され、その内部に絶縁膜６６が形成されている。このような絶縁膜は、例えば、低濃度のｎ−型ベース層６８により構成される基板にストライプ状のトレンチ溝６４をセル領域部から接合終端領域部に延在するように形成し、このトレンチ溝６４の側壁にイオン注入等の方法を用いてｎ型不純物とｐ型不純物を導入した後に熱拡散することにより製造することができる。これにより、絶縁膜６６を周回するようにｎ型ドリフト層２６（２６ａ）とｐ型ドリフト層２８（２８ａ）とが形成される。従って、接合終端領域部では、水平方向で絶縁膜６６と両ドリフト層２６ａ、２８ａが周縁部近傍まで延在するが、垂直方向には、絶縁膜６６とドリフト層は形成されない。 As shown in FIGS. 11 and 12, in the semiconductor element 5 of this embodiment, the trench groove 64 is formed in the horizontal direction in the n-type drift layer 26 (26a), and the insulating film 66 is formed therein. . Such an insulating film is formed by, for example, forming a striped trench groove 64 from a cell region portion to a junction termination region portion in a substrate constituted by a low concentration n − -type base layer 68, It can be manufactured by introducing an n-type impurity and a p-type impurity into the sidewall of the groove 64 using a method such as ion implantation and then thermally diffusing. Thereby, the n-type drift layer 26 (26a) and the p-type drift layer 28 (28a) are formed so as to go around the insulating film 66. Therefore, in the junction termination region, the insulating film 66 and both drift layers 26a and 28a extend to the vicinity of the peripheral edge in the horizontal direction, but the insulating film 66 and drift layer are not formed in the vertical direction.

この理由は、仮に垂直方向に絶縁膜６６とドリフト層２６ａ、２８ａを形成すると、絶縁膜６６が存在するためにターンオフ時にｐ型ドリフト層２８ａ内の正孔が排出されず、結果的に空乏層が伸びなくなって最外周のセルに電界が集中し素子を破壊するおそれがあるためである。   This is because if the insulating film 66 and the drift layers 26a and 28a are formed in the vertical direction, the holes in the p-type drift layer 28a are not discharged at the time of turn-off due to the presence of the insulating film 66, resulting in a depletion layer. This is because the electric field concentrates on the outermost peripheral cell and the element may be destroyed.

図１２に示すように、本実施形態の半導体素子５は、接合終端領域において低濃度のｎ−型ベース層６８上に絶縁膜４６を介してセル領域を囲むように設けられたフィールドプレート電極４８をさらに備えるので、空乏層が十分に広がり高耐圧を得ることができる。 As shown in FIG. 12, the semiconductor element 5 of this embodiment includes a field plate electrode 48 provided on a low-concentration n − type base layer 68 so as to surround a cell region via an insulating film 46 in a junction termination region. Further, the depletion layer is sufficiently spread and a high breakdown voltage can be obtained.

（６）第６の実施形態
図１３は、本発明にかかる半導体素子の第６の実施の形態の概略構造を示す平面図である。図１４および図１５は、それぞれ図１３の切断線Ａ−Ａ、Ｂ−Ｂに沿った本実施形態の半導体素子の断面図である。 (6) Sixth Embodiment FIG. 13 is a plan view showing a schematic structure of a semiconductor device according to a sixth embodiment of the present invention. 14 and 15 are cross-sectional views of the semiconductor device of the present embodiment taken along section lines AA and BB in FIG. 13, respectively.

本実施形態の半導体素子６では、前述した第５の実施形態と異なり、絶縁膜６６はセル領域部内でのみ形成され、接合終端領域部に延在しない。さらに、半導体素子６の接合終端領域部には、ｎ型ドリフト層もｐ型ドリフト層も形成されていない。本実施形態では、接合終端領域部にｎ型ドリフト層２６よりも低濃度のｎ−型ベース層６８が形成され、このｎ−型ベース層６８の表面部には、セル領域を囲むようにｐ型ベース層３０ａおよび複数のｐ型ガードリング層６２が選択的に形成される。ｐ型ベース層３０ａの表面にソース電極３８ａがコンタクトしている。また、ｐ型ベース層３０ａの下方にはその配置に対応してｐ型ベース層２７が形成され、これによりｐ型ベース層３０ａがドレイン層２０を介してドレイン電極４０に接続される。このような接合終端領域部の構造によっても、本実施形態の半導体素子６は、充分な高耐圧を得ることができる。 In the semiconductor element 6 of this embodiment, unlike the above-described fifth embodiment, the insulating film 66 is formed only in the cell region portion and does not extend to the junction termination region portion. Furthermore, neither an n-type drift layer nor a p-type drift layer is formed in the junction termination region of the semiconductor element 6. In the present embodiment, an n − -type base layer 68 having a lower concentration than the n-type drift layer 26 is formed in the junction termination region, and the surface of the n − -type base layer 68 has a p-type so as to surround the cell region. A mold base layer 30a and a plurality of p-type guard ring layers 62 are selectively formed. A source electrode 38a is in contact with the surface of the p-type base layer 30a. Further, a p-type base layer 27 is formed below the p-type base layer 30a corresponding to the arrangement thereof, whereby the p-type base layer 30a is connected to the drain electrode 40 through the drain layer 20. Even with such a structure of the junction termination region, the semiconductor element 6 of the present embodiment can obtain a sufficiently high breakdown voltage.

図１６は、本実施形態の一変形例を示す平面図である。本例の半導体素子６’では、絶縁膜７２がセル領域部内に限り垂直方向にも形成され、これにより、絶縁膜７２が網目の平面形状を有する。半導体素子６’のその他の構造は、図１３に示す半導体素子６と実質的に同一である。絶縁膜７２がセル領域部でこのような構造を有する場合であっても、絶縁膜７２が接合終端領域部に延在することなく、かつ、接合終端領域部でｐ型ガードリング層６２が形成されているので、半導体素子６’は充分な高耐圧を得ることができる。   FIG. 16 is a plan view showing a modification of the present embodiment. In the semiconductor element 6 ′ of this example, the insulating film 72 is also formed in the vertical direction only in the cell region portion, whereby the insulating film 72 has a mesh planar shape. The other structure of the semiconductor element 6 'is substantially the same as that of the semiconductor element 6 shown in FIG. Even when the insulating film 72 has such a structure in the cell region portion, the insulating film 72 does not extend to the junction termination region portion, and the p-type guard ring layer 62 is formed in the junction termination region portion. Therefore, the semiconductor element 6 ′ can obtain a sufficiently high breakdown voltage.

（７）第７の実施形態
図１７は、本発明にかかる半導体素子の第７の実施の形態の概略構造を示す平面図である。図１８は、図１７の切断線Ａ−Ａに沿った本実施形態の半導体素子の断面図である。なお、図１７の切断線Ｂ−Ｂに沿った断面図は図３と同様である。 (7) Seventh Embodiment FIG. 17 is a plan view showing a schematic structure of a seventh embodiment of a semiconductor element according to the present invention. 18 is a cross-sectional view of the semiconductor device of the present embodiment taken along the cutting line AA of FIG. Note that the cross-sectional view along the cutting line BB in FIG. 17 is the same as FIG.

本実施形態の半導体素子７は、上述した第５の実施形態における半導体素子５の構成に加え、接合終端領域部内で垂直方向に形成された絶縁膜７６と、接合終端領域部内でそれぞれが垂直方向に形成されて水平方向に周期的に配置されたｎ型ドリフト層１６６およびｐ型ドリフト層１６８をさらに備える。このような構造により、垂直方向でも水平方向と同様に、ターンオフ時にｐ型ドリフト層１６８内の正孔が排出されるので、空乏層が十分に広がり高耐圧を得ることができる。   In addition to the configuration of the semiconductor element 5 in the fifth embodiment described above, the semiconductor element 7 of this embodiment includes an insulating film 76 formed in the vertical direction in the junction termination region and a vertical direction in the junction termination region. And an n-type drift layer 166 and a p-type drift layer 168 that are periodically formed in the horizontal direction. With such a structure, holes in the p-type drift layer 168 are discharged at turn-off in the vertical direction as well as in the horizontal direction, so that the depletion layer is sufficiently spread and high breakdown voltage can be obtained.

（８）第８の実施形態
図１９は、本発明にかかる半導体素子の第８の実施の形態の概略構造を示す平面図である。図２０および図２１は、それぞれ図１９の切断線Ａ−Ａ、Ｂ−Ｂに沿った本実施形態の半導体素子の断面図である。 (8) Eighth Embodiment FIG. 19 is a plan view showing a schematic structure of an eighth embodiment of a semiconductor element according to the present invention. 20 and 21 are cross-sectional views of the semiconductor device of this embodiment taken along section lines AA and BB in FIG. 19, respectively.

本実施形態では、図１１に示す第５の実施形態と異なり、セル領域部から接合終端領域部に延在するように形成された絶縁膜７６とドリフト層２６ａ、２８ａが、垂直方向にも周期的に配置されて接合終端領域部の周縁近傍に至るまで形成される。また、接合終端領域部の表面部には、セル領域を囲むように所定幅を有するｐ−リサーフ層５２が設けられている。さらに、接合終端領域部において垂直方向に周期的に配置された各ｐ型ドリフト層２８ａ４〜２８ａ７上には電位固定用の電極７８が設けられ（図２０参照）、これらの電極７８は、相互間の間隔を維持しながらソース電極３８ａのコーナ部と中心を共有する円弧をなすように曲折してｐ型ドリフト層２８ａ１〜２８ａ３に直交するように延在して形成され、この延在部分でこれらｐ型ドリフト層２８ａ１〜２８ａ３に接続される（図２１参照）。 In the present embodiment, unlike the fifth embodiment shown in FIG. 11, the insulating film 76 and the drift layers 26 a and 28 a formed so as to extend from the cell region portion to the junction termination region portion have a period in the vertical direction as well. And is formed up to the vicinity of the periphery of the junction termination region. Further, a p - resurf layer 52 having a predetermined width is provided on the surface of the junction termination region so as to surround the cell region. Furthermore, potential fixing electrodes 78 are provided on the p-type drift layers 28a4 to 28a7 periodically arranged in the vertical direction in the junction termination region (see FIG. 20). Are bent so as to form an arc sharing the center with the corner portion of the source electrode 38a while maintaining the gap of the source electrode 38a and extending so as to be orthogonal to the p-type drift layers 28a1 to 28a3. Connected to the p-type drift layers 28a1 to 28a3 (see FIG. 21).

本実施形態の半導体素子８は、上述した構造により、ターンオフ時に垂直方向に周期的に設けられたｐ型ドリフト層３ａ４〜７内の正孔を電極７８を介して排出するので、水平方向と垂直方向の２つの方向で空乏層が均等に伸びる。これにより、高耐圧が保持される。   The semiconductor element 8 of the present embodiment discharges holes in the p-type drift layers 3a4 to 7a periodically provided in the vertical direction through the electrode 78 at the time of turn-off due to the structure described above. The depletion layer extends evenly in the two directions. Thereby, a high breakdown voltage is maintained.

（９）第９の実施形態
図２２は、本発明にかかる半導体素子の第９の実施の形態の概略構造を示す平面図である。図２３は、図２２の切断線Ａ−Ａに沿った本実施形態の半導体素子の断面図である。なお、図２２の切断線Ｂ−Ｂに沿った断面図は図３と同様である。 (9) Ninth Embodiment FIG. 22 is a plan view showing a schematic structure of a ninth embodiment of a semiconductor element according to the present invention. FIG. 23 is a cross-sectional view of the semiconductor device of this embodiment taken along section line AA of FIG. Note that the cross-sectional view along the cutting line BB in FIG. 22 is the same as FIG.

本実施形態の半導体素子９は、前述した第８の実施形態と異なり、接合終端領域部においてそれぞれの水平方向にストライプ状に形成され垂直方向に周期的に配置された絶縁膜８４とこれを周回するように形成されたｎ型ドリフト層１７２とが水平方向でそれぞれ分割されて平面視において格子形状をなすように形成され、これにより、ｐ型ドリフト層１７８の水平方向の領域が垂直方向で相互に接続されている。この垂直方向でのｐ型ドリフト層１７８の接続構造により、ターンオフ時に正孔が排出される。また、本実施形態の半導体素子９は、上述した第１の実施の形態と同様に、セル領域を囲むように形成されたｐ型ベース層３０ａに接続され、接合終端領域上に形成された絶縁膜４６上に延在して形成されたフィールド電極４８を備えるので、これにより接合終端領域部における電界が緩和される。この結果、充分な高耐圧が得られる。   Unlike the above-described eighth embodiment, the semiconductor element 9 of the present embodiment has an insulating film 84 formed in stripes in the horizontal direction and periodically arranged in the vertical direction in the junction termination region and the circuit. The n-type drift layer 172 formed in such a manner is divided in the horizontal direction so as to form a lattice shape in plan view, whereby the horizontal regions of the p-type drift layer 178 are mutually perpendicular. It is connected to the. Due to the connection structure of the p-type drift layer 178 in the vertical direction, holes are discharged at the time of turn-off. In addition, the semiconductor element 9 of this embodiment is connected to the p-type base layer 30a formed so as to surround the cell region and is insulated on the junction termination region, as in the first embodiment described above. Since the field electrode 48 formed so as to extend on the film 46 is provided, the electric field in the junction termination region is thereby reduced. As a result, a sufficiently high breakdown voltage can be obtained.

（１０）第１０の実施形態
図２４は、本発明にかかる半導体素子の第１０の実施の形態の概略構造を示す平面図である。図２５および図２６は、それぞれ図２４の切断線Ａ−Ａ、Ｂ−Ｂに沿った本実施形態の半導体素子の断面図である。 (10) Tenth Embodiment FIG. 24 is a plan view showing a schematic structure of a tenth embodiment of a semiconductor element according to the present invention. 25 and 26 are cross-sectional views of the semiconductor device of this embodiment taken along section lines AA and BB in FIG. 24, respectively.

本実施形態の半導体素子１０は、図１９に示す半導体素子８のｐ−リサーフ層５２と電極７８に代えて、セル領域を囲むように接合終端領域上に半絶縁性ポリシリコン等により形成された抵抗性フィールドプレート（Resistive Field Plate：ＲＦＰ）５０を備える。ＲＦＰ５０は、セル領域との境界近傍におけるｐ型ベース層３０ａを介して、または直接にソース電極３８ａに接続されるとともに、ｐ型ドリフト層２８ａに接続される。特に、セル領域部のｐ型ドリフト層２８を水平方向に延在した部分に該当するｐ型ドリフト層２８ａ１および２８ａ２については、それらのほぼ全長においてＲＦＰ５０にコンタクトしている（図２６参照）。また、接合終端領域部で垂直方向に周期的に形成されたｐ型ドリフト層２８ａ４〜２８ａ７は、水平方向におけるセル領域部の幅に対応する幅において離散的にＲＦＰ５０にコンタクトしている（図２５参照）。 The semiconductor element 10 of this embodiment is formed of semi-insulating polysilicon or the like on the junction termination region so as to surround the cell region, instead of the p - resurf layer 52 and the electrode 78 of the semiconductor element 8 shown in FIG. A resistive field plate (RFP) 50 is provided. The RFP 50 is connected to the source electrode 38a via the p-type base layer 30a in the vicinity of the boundary with the cell region or directly to the p-type drift layer 28a. In particular, the p-type drift layers 28a1 and 28a2 corresponding to the portion extending in the horizontal direction of the p-type drift layer 28 in the cell region are in contact with the RFP 50 in almost the entire length thereof (see FIG. 26). Further, the p-type drift layers 28a4 to 28a7 periodically formed in the vertical direction in the junction termination region portion are in discrete contact with the RFP 50 in a width corresponding to the width of the cell region portion in the horizontal direction (FIG. 25). reference).

このような構造により、ターンオフ時に正孔がｐ型ドリフト層２８ａからＲＦＰ５０を介してソース電極３８ａに排出されるので、半導体素子１０は充分な高耐圧を実現することができる。   With such a structure, holes are discharged from the p-type drift layer 28a to the source electrode 38a via the RFP 50 at the time of turn-off, so that the semiconductor element 10 can realize a sufficiently high breakdown voltage.

（１１）第１１の実施形態
図２７は、本発明にかかる半導体素子の第１１の実施の形態の概略構成を模式的に示す断面図である。 (11) Eleventh Embodiment FIG. 27 is a cross-sectional view schematically showing a schematic configuration of an eleventh embodiment of a semiconductor element according to the present invention.

図２７に示す縦型パワーＭＯＳＦＥＴ１１は、ｎ−型ベース層をなす半導体層１０２と、ｎ＋ドレイン層１００と、ドレイン電極４０と、スーパージャンクション構造をなす複数のｐ型リサーフ層１０６，１３０と、ｐ型ベース層１０８と、ｎ＋型ソース層１１０と、ゲート電極１１４およびソース電極１１６とを備える。 A vertical power MOSFET 11 shown in FIG. 27 includes a semiconductor layer 102 forming an n − type base layer, an n + drain layer 100, a drain electrode 40, and a plurality of p type RESURF layers 106 and 130 forming a super junction structure, A p-type base layer 108, an n + -type source layer 110, a gate electrode 114, and a source electrode 116 are provided.

ｎ＋ドレイン層１００は、ｎ−型ベース層１０２の一方の表面、図２７においては下面に形成され、ドレイン電極４０は、ｎ＋ドレイン層１００上に形成される。 The n + drain layer 100 is formed on one surface of the n − type base layer 102, the lower surface in FIG. 27, and the drain electrode 40 is formed on the n + drain layer 100.

ｐ型リサーフ層１０６，１３０は、ｎ−型ベース層１０２の他方の表面部、図２７においては上面部に、セル領域部だけでなく接合終端領域部にも所定方向に周期的に配置され、これによりスーパージャンクション構造が形成され、ｐ型リサーフ層１０６はｐ型ドリフト層１０６として機能し、また、ｎ−型ベース層１０２のうち、これらｐ型ドリフト層１０６に挟まれた領域部分はｎ−型ドリフト層１０２として機能する。 The p-type RESURF layers 106 and 130 are periodically arranged in a predetermined direction not only in the cell region portion but also in the junction termination region portion on the other surface portion of the n − -type base layer 102, in FIG. Thereby super junction structure is formed, p-type RESURF layer 106 functions as a p-type drift layer 106, also, n - of the type base layer 102, region portion sandwiched between the p-type drift layer 106 the n - It functions as a type drift layer 102.

ｐ型ベース層１０８は、セル領域部におけるｎ−型ベース層１０２の表面部でｐ型ドリフト層１０６に接続されるように選択的に形成される。ｎ＋型ソース層１１０は、ｐ型ベース層１０８の表面部でストライプの平面形状を有するように選択的に拡散形成される。ｐ型ベース層１０８は、例えば、約３×１０１７ｃｍ−３の不純物濃度で約２．０μｍの深さに形成され、また、ｎ＋型ソース層１１０は、例えば、約１×１０２０ｃｍ−３の不純物濃度で約０．２μｍの深さに形成される。 The p-type base layer 108 is selectively formed so as to be connected to the p-type drift layer 106 at the surface portion of the n − -type base layer 102 in the cell region portion. The n + type source layer 110 is selectively diffused so as to have a planar shape of stripes on the surface portion of the p type base layer 108. The p-type base layer 108 is formed to a depth of about 2.0 μm, for example, with an impurity concentration of about 3 × 10 17 cm −3 , and the n + -type source layer 110 is, for example, about 1 × 10 20 cm. -3 with an impurity concentration of -3 .

ゲート電極１１４は、ｎ＋型ソース層１１０およびｐ型ベース層１０８の表面からｎ−型ドリフト層１０２の表面を介して隣り合うｐ型ベース層１０８およびｎ＋型ソース層１１０の表面に至る領域上に、膜厚約０．１μｍのゲート絶縁膜、例えばＳｉ酸化膜１１２を介してストライプの平面形状をなすように形成される。ソース電極１１６は、ｐ型ベース層１０８の表面部における一方のｎ＋型ソース層１１０の表面領域、ｐ型ベース層１０８の表面領域および隣り合うｎ＋型ソース層１１０の表面領域でストライプの平面形状をなすように形成され、ゲート電極１１４を挟むように配置される。 Gate electrode 114 is a region extending from the surfaces of n + type source layer 110 and p type base layer 108 to the surfaces of adjacent p type base layer 108 and n + type source layer 110 via the surface of n − type drift layer 102. A stripe insulating planar shape is formed on a gate insulating film having a thickness of about 0.1 μm, for example, a Si oxide film 112. The source electrode 116 is a stripe plane in the surface region of one n + -type source layer 110, the surface region of the p-type base layer 108, and the surface region of the adjacent n + -type source layer 110 in the surface portion of the p-type base layer 108. It is formed so as to have a shape, and is arranged so as to sandwich the gate electrode 114.

縦型パワーＭＯＳＦＥＴ１１の接合終端領域部におけるスーパージャンクション構造の上には、金属またはポリシリコンなどの導電性膜１２８が絶縁膜１２６を介して形成され、これにより、接合終端領域におけるフィールドプレート構造を構成する。なお、素子の周縁の表面部には、ｎ層で形成され空乏化を止めるフィールドストッパ４２が設けられている。   On the super junction structure in the junction termination region of the vertical power MOSFET 11, a conductive film 128 such as metal or polysilicon is formed via an insulating film 126, thereby forming a field plate structure in the junction termination region. To do. A field stopper 42 that is formed of an n layer and stops depletion is provided on the peripheral surface of the element.

このような構造により、高電圧印加時にフィールドプレート１２８により接合終端領域部のスーパージャンクション構造部が速やかに空乏化して、接合終端領域部が等価的に低不純物濃度層となるので、接合終端領域部での電界集中が抑制され、高耐圧が保持される。なお、接合終端領域部の表面部にリサーフ層を形成しても、フィールドプレートと同様にスーパージャンクション構造部が速やかに空乏化するので、同様な効果を得ることができる。図２７において、フィールドプレート１２８はソース電極１１６と同じ電位となるような構造を有するが、これに限ることなく、ゲート電極１１４と同じ電位となるように製造しても良い。   With such a structure, when the high voltage is applied, the super junction structure portion of the junction termination region portion is quickly depleted by the field plate 128, and the junction termination region portion becomes an equivalent low impurity concentration layer. Electric field concentration is suppressed and high breakdown voltage is maintained. Even if the RESURF layer is formed on the surface portion of the junction termination region portion, the super junction structure portion is quickly depleted like the field plate, and the same effect can be obtained. In FIG. 27, the field plate 128 has a structure in which the potential is the same as that of the source electrode 116. However, the field plate 128 is not limited to this and may be manufactured to have the same potential as that of the gate electrode 114.

接合終端領域部のｐ型ドリフト層１３０の不純物量をセル領域部のｐ型ドリフト層１０６の不純物量よりも多くすることにより、接合終端領域部での耐圧低下を抑制することができる。ｐ型ドリフト層１０６，１３０の不純物量は、幅と不純物密度との積とする。   By making the impurity amount of the p-type drift layer 130 in the junction termination region portion larger than the impurity amount of the p-type drift layer 106 in the cell region portion, it is possible to suppress a decrease in breakdown voltage in the junction termination region portion. The impurity amount of the p-type drift layers 106 and 130 is the product of the width and the impurity density.

図２７では、接合終端領域部のｐ型ドリフト層１３０は、セル領域部のｐ型ドリフト層１０６よりも広い幅で形成されるが、ｐ型ドリフト層１０６と同じ不純物密度を有するように形成される。これにより、接合終端領域部でのｐ型ドーパントの不純物量が多くなり、この結果、接合終端領域部での耐圧低下を抑制することができる。   In FIG. 27, the p-type drift layer 130 in the junction termination region is formed with a width wider than the p-type drift layer 106 in the cell region, but is formed to have the same impurity density as the p-type drift layer 106. The As a result, the impurity amount of the p-type dopant in the junction termination region increases, and as a result, a decrease in breakdown voltage in the junction termination region can be suppressed.

なお、この構造に限ることなく、例えば、セル領域部のｐ型ドリフト層１０６の幅と接合終端領域部のｐ型ドリフト層１３０の幅を同じにし、不純物密度を接合終端領域部だけ高くしても同様の効果が得られる。   For example, the width of the p-type drift layer 106 in the cell region and the width of the p-type drift layer 130 in the junction termination region are made the same, and the impurity density is increased only in the junction termination region. The same effect can be obtained.

図２８は、ｐ型不純物量を変化させた時の耐圧の変化をセル領域部と接合終端領域部のそれぞれについて示すグラフである。同図の横軸は、ｎ−型ドリフト層の不純物量Ｎｎに対するｐ型ドリフト層の不純物量Ｎｐの比とした。同図に示すように、セル領域部ではｎ−型ドリフト層不純物量とｐ型ドリフト層不純物量とが等しい（アンバランスが０％）場合に最も高い耐圧が得られ、ｐ型ドリフト層の不純物量が相対的に高くなっても低くなってもその比率に応じて０％の点を中心に対称的に耐圧が低下することがわかる。この一方、接合終端領域部では、ｐ型ドリフト層不純物量を相対的に１０％高くした場合が最も高い耐圧が得られることがわかる。このように、セル領域部と接合終端領域部では、最適のｐ型ドリフト層の不純物量が異なり、セル領域部で最適のｐ型ドリフト層濃度と同一の濃度で接合終端領域部にもｐ型ドリフト層を形成すると、接合終端領域部で耐圧が低下してしまう。図２８からも明らかなように、接合終端領域部で最適の不純物量は、セル領域部より高くなっている。 FIG. 28 is a graph showing the change in breakdown voltage when the p-type impurity amount is changed for each of the cell region portion and the junction termination region portion. The horizontal axis of the figure represents the ratio of the impurity amount Np of the p-type drift layer to the impurity amount Nn of the n − -type drift layer. As shown in the figure, in the cell region portion, the highest breakdown voltage is obtained when the n − type drift layer impurity amount and the p type drift layer impurity amount are equal (unbalance is 0%), and the impurity of the p type drift layer is obtained. It can be seen that the withstand voltage decreases symmetrically around the point of 0% depending on the ratio regardless of whether the amount is relatively high or low. On the other hand, in the junction termination region, it can be seen that the highest breakdown voltage can be obtained when the p-type drift layer impurity amount is relatively increased by 10%. As described above, the optimum impurity amount of the p-type drift layer is different between the cell region portion and the junction termination region portion, and the junction termination region portion is also p-type at the same concentration as the optimum p-type drift layer concentration in the cell region portion. When the drift layer is formed, the breakdown voltage is lowered at the junction termination region. As is apparent from FIG. 28, the optimum impurity amount in the junction termination region is higher than that in the cell region.

セル領域部おけるｐ型ドリフト層不純物量は、プロセスマージンも含めると、ｎ−型ドリフト層の８０〜１２０％とすることが最適であり、接合終端領域部におけるｐ型ドリフト層不純物量は、プロセスマージンも含めると、ｎ−型ドリフト層の９０〜１３０％とすることが最適であるから、終端部のｐ型ドリフト層不純物量は、セル領域部のｐ型ドリフト層不純物量の７５〜１６３％とすることが望ましい。最も高い耐圧が得られるｐ型ドリフト層不純物量は終端部の方が高いので、終端部のｐ型ドリフト層不純物量は、セル領域部の不純物量に対して、１００〜１６３％とすることがより望ましい。 The p-type drift layer impurity amount in the cell region portion is optimal to be 80 to 120% of the n − -type drift layer including the process margin. The p-type drift layer impurity amount in the junction termination region portion is Including the margin, it is optimal that the n − type drift layer is 90 to 130%. Therefore, the p-type drift layer impurity amount in the terminal portion is 75 to 163% of the p-type drift layer impurity amount in the cell region portion. Is desirable. Since the p-type drift layer impurity amount that can provide the highest breakdown voltage is higher in the termination portion, the p-type drift layer impurity amount in the termination portion may be 100 to 163% with respect to the impurity amount in the cell region portion. More desirable.

スーパージャンクション構造の形成方法は、例えば、イオン注入と埋め込み結晶成長を繰り返す方法でも、トレンチ溝を形成して埋め込みエピを行う方法でも、トレンチ溝を形成した後に斜め方向からイオン注入を行う方法のいずれでもよい。   The method of forming the super junction structure includes, for example, either a method of repeating ion implantation and buried crystal growth, a method of forming a trench groove and performing buried epi, or a method of implanting ions from an oblique direction after forming the trench groove. But you can.

接合終端領域部のｐ型ドリフト層濃度を上げることは、スーパージャンクション構造の各形成方法に応じて可能である。   Increasing the concentration of the p-type drift layer in the junction termination region is possible depending on each formation method of the super junction structure.

イオン注入と埋め込み結晶成長を繰り返してスーパージャンクション構造を形成する方法では、セル領域部と接合終端領域部で別々にイオン注入を行っても、セル領域部と接合終端領域部でイオン注入のマスク開口幅を変えて同時にイオン注入を行ってもよい。   In the method of forming a super junction structure by repeating ion implantation and buried crystal growth, even if ion implantation is separately performed in the cell region portion and the junction termination region portion, the mask opening for ion implantation is performed in the cell region portion and the junction termination region portion. The ion implantation may be performed at the same time while changing the width.

トレンチ溝を形成した後にトレンチ溝内を結晶成長により埋め込む方法、または、斜め方向からイオン注入や気相拡散を行ってスーパージャンクション構造を形成する方法では、セル領域部と接合終端領域部とでトレンチ溝幅やメサ幅を変えてもよい。   In the method of filling the trench groove by crystal growth after forming the trench groove, or the method of forming a super junction structure by performing ion implantation or gas phase diffusion from an oblique direction, the trench is formed between the cell region portion and the junction termination region portion. The groove width and mesa width may be changed.

また、ｐ型ドリフト層不純物量をセル領域部と終端部で同じにし、接合終端領域部のｎ−型ドリフト層不純物量をセル領域部よりも下げても同様な効果が得られる。 Further, the same effect can be obtained even if the p-type drift layer impurity amount is made the same in the cell region portion and the termination portion, and the n − type drift layer impurity amount in the junction termination region portion is made lower than that in the cell region portion.

（１２）第１２の実施形態
図２９は、本発明にかかる半導体素子の第１２の実施の形態の概略構成を模式的に示す断面図である。 (12) Twelfth Embodiment FIG. 29 is a cross-sectional view schematically showing a schematic configuration of a twelfth embodiment of a semiconductor element according to the present invention.

本実施形態の半導体素子１２の特徴は、セル領域部と接合終端領域部とでセルピッチが異なるｐ型ドリフト層でスーパージャンクション構造を構成する点にある。即ち、接合終端領域部のｐ型ドリフト層１３２のセルピッチをセル領域部のｐ型ドリフト層１０６よりも狭くしている。このように、接合終端領域部でのセル幅を狭くすることにより、ターンオフ時に接合終端領域部での空乏化が速やかに進む。この結果、接合終端領域部での耐圧低下が抑制される。   A feature of the semiconductor element 12 of the present embodiment is that a super junction structure is formed by p-type drift layers having different cell pitches in the cell region portion and the junction termination region portion. That is, the cell pitch of the p-type drift layer 132 in the junction termination region is made narrower than that of the p-type drift layer 106 in the cell region. Thus, by narrowing the cell width in the junction termination region, depletion in the junction termination region proceeds rapidly at turn-off. As a result, a decrease in breakdown voltage at the junction termination region is suppressed.

図３０は、ｐ型ドリフト層とｎ−型ドリフト層の不純物量バランスに対する耐圧の変化を示すグラフである。ｎ−型ドリフト層の不純物濃度は、２．５×１０１５ｃｍ−３とした。セルピッチを１６μｍとした場合と８μｍとした場合とを比較すると、セルピッチを８μｍと狭くした方が、不純物のバランスに対して耐圧低下が小さくなっている。これより、セルピッチを狭くすることにより、不純物濃度バランスに対するマージンを大きくすることができることが分かる。 FIG. 30 is a graph showing changes in breakdown voltage with respect to the impurity amount balance of the p-type drift layer and the n − -type drift layer. The impurity concentration of the n − type drift layer was 2.5 × 10 15 cm −3 . Comparing the case where the cell pitch is 16 μm and the case where the cell pitch is 8 μm, when the cell pitch is narrowed to 8 μm, the decrease in breakdown voltage is smaller with respect to the balance of impurities. From this, it can be seen that the margin for the impurity concentration balance can be increased by narrowing the cell pitch.

さらに、ｎ−型ドリフト層とｐ型ドリフト層との不純物量バランスに注目すると、セル幅を変化させても、耐圧が最も高くなる最適のｐ型ドリフト層不純物量は、ｎ−型ドリフト層よりも高い不純物量となっている。このことから、接合終端領域部のセル幅を狭くした場合でも、接合終端領域部のｐ型ドリフト層不純物量をセル領域部よりも高くすることが望ましいことが分かる。 Further, when attention is paid to the impurity amount balance between the n − type drift layer and the p type drift layer, the optimum p type drift layer impurity amount with the highest withstand voltage even when the cell width is changed is larger than that of the n − type drift layer. The amount of impurities is also high. From this, it can be seen that even when the cell width of the junction termination region is narrowed, it is desirable that the amount of p-type drift layer impurities in the junction termination region is higher than that of the cell region.

（１３）第１３の実施形態
図３１は、本発明にかかる半導体素子の第１３の実施の形態の概略構成を模式的に示す断面図である。 (13) Thirteenth Embodiment FIG. 31 is a cross-sectional view schematically showing a schematic configuration of a thirteenth embodiment of a semiconductor element according to the present invention.

本実施形態の半導体素子１３の特徴は、接合終端領域部でのｐ型ドリフト層１３４の形状にあり、上述した各実施形態における柱状の断面形状ではなく水玉状の断面形状を有するように埋め込まれている点にある。仮に、スーパージャンクション構造を構成するｐ型ドリフト層１３４がセル領域部でこのような水玉の断面形状を有する場合は、ターンオフで一旦空乏化した後、ｐ型ドリフト層の空乏化が保持されてしまうが、本実施形態では、水玉状の断面形状のｐ型ドリフト層１３４が接合終端領域部にのみ形成されているので、半導体素子１３のオン動作に影響を及ぼすことはない。   The semiconductor element 13 of this embodiment is characterized by the shape of the p-type drift layer 134 in the junction termination region, and is embedded so as to have a polka-dot cross-sectional shape instead of the columnar cross-sectional shape in each of the above-described embodiments. There is in point. If the p-type drift layer 134 constituting the super junction structure has such a polka-dot cross-sectional shape in the cell region portion, the depletion of the p-type drift layer is maintained after being depleted once by turn-off. However, in this embodiment, since the p-type drift layer 134 having a polka-dot cross-sectional shape is formed only in the junction termination region portion, the ON operation of the semiconductor element 13 is not affected.

スーパージャンクション構造の形成にあたり、イオン注入と埋め込み結晶成長を繰り返す方法を採用する場合、接合終端領域部でスーパージャンクション構造のセルピッチを狭くすると、イオン注入するドーパントの量が終端領域で減ってしまう。本実施形態のｐ型ドリフト層１３４は、このような問題を解消するために埋め込み成長後の拡散を採用した場合に得られる構造である。即ち、埋め込み成長後の拡散によれば、埋め込まれたｐ層の濃度は、セル領域部では高く、接合終端領域部では低くなる。この結果、セル領域部では上下のｐ層が接続して柱状の断面形状をなすようにｐ型ドリフト層が形成されるが、接合終端領域部では各埋め込み層が接続されることなく水玉状の断面形状を有することになる。ただし、接合終端領域部でセルピッチを狭くしすぎると、隣り合うｐ型ドリフト層同士が接続されてしまうので、接合終端領域部のセルピッチとしては、セル領域部のセルピッチの半分以上に設定することが望ましい。   When the method of repeating ion implantation and buried crystal growth is adopted in forming the super junction structure, if the cell pitch of the super junction structure is narrowed in the junction termination region, the amount of dopant to be ion implanted is reduced in the termination region. The p-type drift layer 134 of the present embodiment has a structure obtained when diffusion after buried growth is employed in order to solve such a problem. That is, according to the diffusion after buried growth, the concentration of the buried p layer is high in the cell region portion and low in the junction termination region portion. As a result, the p-type drift layer is formed so that the upper and lower p layers are connected to form a columnar cross-sectional shape in the cell region portion, but each buried layer is not connected to each other in the junction termination region portion. It will have a cross-sectional shape. However, if the cell pitch is made too narrow in the junction termination region, adjacent p-type drift layers are connected to each other. Therefore, the cell pitch in the junction termination region can be set to more than half the cell pitch in the cell region. desirable.

（１４）第１４の実施形態
図３２は、本発明にかかる半導体素子の第１４の実施の形態の概略構成を模式的に示す断面図である。本実施形態の半導体素子１４は、接合終端領域部でのスーパージャンクション構造のセル幅がセル領域部におけるセル幅よりも狭くなるように形成され、かつ、接合終端領域部内でｐ型ドリフト層１３６のメサ幅が相対的に広くなるように形成される。これにより、接合終端領域部のｐ型ドリフト層１３６の不純物濃度をセル領域部よりも高くすることができる。このような構造により、本実施形態の半導体素子１４は、接合終端領域部での耐圧低下が抑制される。 (14) Fourteenth Embodiment FIG. 32 is a cross-sectional view schematically showing a schematic configuration of a fourteenth embodiment of a semiconductor element according to the present invention. The semiconductor element 14 of the present embodiment is formed such that the cell width of the super junction structure in the junction termination region is narrower than the cell width in the cell region, and the p-type drift layer 136 is formed in the junction termination region. The mesa width is formed to be relatively wide. Thereby, the impurity concentration of the p-type drift layer 136 in the junction termination region can be made higher than that in the cell region. With such a structure, the semiconductor element 14 of the present embodiment suppresses a decrease in breakdown voltage in the junction termination region.

（１５）第１５の実施形態
図３３は、本発明にかかる半導体素子の第１５の実施の形態の概略構成を模式的に示す断面図である。図２７に示す半導体素子１１との対比において明らかなように、本実施形態の半導体素子１５の特徴は、スーパージャンクション構造とｎ＋ドレイン層１００との間に設けられたｎ−型ドリフト層１４２をさらに備え、このｎ−型ドリフト層１４２とスーパージャンクション構造とでｎ型ドリフト層を構成する点にある。ｎ−型ドリフト層１４２は、スーパージャンクション構造におけるｎ−型ドリフト層１０２よりも低い不純物濃度を有するように形成される。このようなｎ−型ドリフト層１４２を有する場合であっても、上部のスーパージャンクション構造の空乏化により耐圧が決定されるため、上述したスーパージャンクション構造の半導体素子１〜１０と同様の接合終端領域構造を設計できる。本実施形態の半導体素子１５では、図２７に示す第１１の実施形態と同様に、接合終端領域部におけるｐ型ドリフト層１３０の幅をセル領域部のｐ型ドリフト層１０６よりも広くすることにより、接合終端領域部でのスーパージャンクション構造のｐ型不純物量をセル領域部よりも多くしている。これにより、接合終端領域部での耐圧低下を抑制することが可能になる。 (15) Fifteenth Embodiment FIG. 33 is a cross-sectional view schematically showing a schematic configuration of a fifteenth embodiment of a semiconductor element according to the present invention. As is clear from the comparison with the semiconductor element 11 shown in FIG. 27, the semiconductor element 15 of the present embodiment is characterized by an n − type drift layer 142 provided between the super junction structure and the n + drain layer 100. In addition, the n − type drift layer 142 and the super junction structure constitute an n type drift layer. N − type drift layer 142 is formed to have a lower impurity concentration than n − type drift layer 102 in the super junction structure. Even in the case of having such an n − type drift layer 142, the breakdown voltage is determined by depletion of the upper super junction structure, so that the junction termination region similar to that of the semiconductor elements 1 to 10 having the super junction structure described above is used. You can design the structure. In the semiconductor element 15 of this embodiment, as in the eleventh embodiment shown in FIG. 27, the width of the p-type drift layer 130 in the junction termination region is made wider than that of the p-type drift layer 106 in the cell region. The p-type impurity amount of the super junction structure in the junction termination region is larger than that in the cell region. Thereby, it becomes possible to suppress the pressure | voltage resistant fall in a junction termination area | region part.

（１６）第１６の実施形態
図３４は、本発明にかかる半導体素子の第１６の実施の形態の概略構成を模式的に示す断面図である。前述した第１５の実施形態と同様に、図３４に示す半導体素子１６では、ｎ−型ドリフト層１４２とスーパージャンクション構造とでｎ型ドリフト層を構成している。ｎ−型ドリフト層１４２は、スーパージャンクション構造におけるｎ−型ドリフト層１０２よりも低い不純物濃度を有する。本実施形態では、接合終端領域部構造として接合終端領域部のスーパージャンクション構造のセルピッチをセル領域部のセルピッチよりも狭くすることにより、ｐ型ドリフト層１３２とｎ−型ドリフト層１０２との濃度バランスに対するマージンを広くすることができる。さらに、接合終端領域部でのｐ型ドリフト層１３２の不純物量をセル領域部よりも多くすれば、接合終端領域部での耐圧低下をさらに抑制できる。 (16) Sixteenth Embodiment FIG. 34 is a cross-sectional view schematically showing a schematic configuration of a sixteenth embodiment of a semiconductor element according to the present invention. As in the fifteenth embodiment described above, in the semiconductor element 16 shown in FIG. 34, the n − type drift layer 142 and the super junction structure constitute an n type drift layer. N − type drift layer 142 has a lower impurity concentration than n − type drift layer 102 in the super junction structure. In this embodiment, the cell balance of the super junction structure of the junction termination region portion as the junction termination region portion structure is made narrower than the cell pitch of the cell region portion, whereby the concentration balance between the p-type drift layer 132 and the n − -type drift layer 102 is achieved. Can be widened. Furthermore, if the impurity amount of the p-type drift layer 132 in the junction termination region portion is made larger than that in the cell region portion, it is possible to further suppress the breakdown voltage drop in the junction termination region portion.

（Ｂ）半導体素子の製造方法の実施形態
図３５は、本発明にかかる半導体素子の製造方法の実施の一形態を示す略示断面図である。本実施形態は、上述した本発明の半導体素子の各実施形態におけるスーパージャンクション構造を少ない結晶成長回数で形成する方法を提供する。 (B) Embodiment of Method for Manufacturing Semiconductor Device FIG. 35 is a schematic cross-sectional view showing one embodiment of a method for manufacturing a semiconductor device according to the present invention. The present embodiment provides a method of forming the super junction structure in each of the semiconductor device embodiments of the present invention described above with a small number of crystal growths.

イオン注入と埋め込み結晶成長を繰り返す従来のプロセスでは、拡散によりｐ型リサーフ層（ｐ型ドリフト層）を形成するので、１回の結晶成長膜厚を厚くすることができず、このため５〜７回にわたってイオン注入および埋め込み結晶成長を繰り返す必要があった。また、従来の他のプロセスとしては、トレンチ溝を形成した後にトレンチ溝内を結晶成長により埋め込む方法があり、この場合は埋め込み成長回数を１回にすることが可能である。しかしながら、スーパージャンクション構造で期待されるトレンチ溝のアスペクト比は５以上と高いので、このような埋め込み結晶成長は困難であった。   In a conventional process in which ion implantation and embedded crystal growth are repeated, a p-type RESURF layer (p-type drift layer) is formed by diffusion, so that it is not possible to increase the thickness of a single crystal growth film. It was necessary to repeat ion implantation and embedded crystal growth over and over. As another conventional process, there is a method of filling the trench groove by crystal growth after forming the trench groove. In this case, it is possible to reduce the number of filling growths to one. However, since the aspect ratio of the trench groove expected in the super junction structure is as high as 5 or more, such buried crystal growth is difficult.

本実施形態の製造方法の特徴は、図３５（ａ）〜（ｆ）に示すように、アスペクト比の低いトレンチ埋め込み結晶成長を複数回繰り返す点にある。即ち、まずｎ−型半導体層１５１内に、最終的に要求されるアスペクト比の半分でトレンチ溝１５４を形成し（図３５（ａ））、このトレンチ溝１５４を埋め込むように、ｐ−型半導体層１５６をエピタキシャル成長させる（同図（ｂ））。次に、ｎ−型半導体層１５１の表面が露出するまでｐ−型半導体層１５６を後退させ、トレンチ溝に埋め込まれた半導体層１５８を得る（同図（ｃ））。その後、ｎ−型半導体層１５１およびｐ−型半導体層１５８を覆うようにｎ−型半導体層をさらにエピタキシャル成長させ、ｐ−型半導体層１５８の膜厚と同一の膜厚を有するｎ−型半導体層１６０を形成する（同図（ｄ））。続いて、トレンチ溝１５４と合致するトレンチ溝１６２をｎ−型半導体層１６０内に形成する（同図（ｅ））。さらに、ｎ−型半導体層１５３およびｐ−型半導体層１５８を覆うようにｎ−型半導体層１６４をエピタキシャル成長させる（同図（ｆ））。このように、本実施形態の半導体素子製造方法によれば、比較的容易に埋め込み成長を行うので、イオン注入と埋め込み結晶成長を繰り返す従来のプロセスよりも少ない結晶成長回数でスーパージャンクション構造を形成することができる。 A feature of the manufacturing method of this embodiment is that, as shown in FIGS. 35A to 35F, trench embedded crystal growth with a low aspect ratio is repeated a plurality of times. That is, first, a trench groove 154 is formed in the n − type semiconductor layer 151 at a half of the aspect ratio finally required (FIG. 35A), and a p − type semiconductor is formed so as to fill the trench groove 154. The layer 156 is epitaxially grown ((b) in the figure). Next, the p − type semiconductor layer 156 is retracted until the surface of the n − type semiconductor layer 151 is exposed to obtain a semiconductor layer 158 embedded in the trench (FIG. 3C). Then, n - -type semiconductor layer 151 and the p - allowed -type semiconductor layer further epitaxial growth, p - - -type semiconductor layer 158 and an n cover type n has a film same thickness as the thickness of the semiconductor layer 158 - -type semiconductor layer 160 is formed ((d) in the figure). Subsequently, a trench groove 162 coinciding with the trench groove 154 is formed in the n − type semiconductor layer 160 ((e) in the figure). Further, n - -type semiconductor layer 153 and the p - n so as to cover the type semiconductor layer 158 - -type semiconductor layer 164 is epitaxially grown (Fig. (F)). As described above, according to the semiconductor element manufacturing method of the present embodiment, since the buried growth is performed relatively easily, the super junction structure is formed with a smaller number of crystal growth times than in the conventional process in which ion implantation and buried crystal growth are repeated. be able to.

なお、本実施形態では２回のトレンチ埋め込み結晶成長でスーパージャンクション構造を形成したが、これに限ることなく、例えば一回あたりのアスペクト比を求められるアスペクト比の１／３以下に設定してトレンチ埋め込み結晶成長を３回以上繰り返すこととしても良い。また、１回目と２回目のスーパージャンクション構造をそれぞれストライプ状に形成し、相互に直交するように形成すると、位置合わせを確実に行うことができる。   In this embodiment, the superjunction structure is formed by two trench embedded crystal growths. However, the present invention is not limited to this, and for example, the trench is set to have an aspect ratio of 1/3 or less of the required aspect ratio. The embedded crystal growth may be repeated three or more times. Further, if the first and second super junction structures are formed in a stripe shape and are formed so as to be orthogonal to each other, the alignment can be reliably performed.

以上、本発明の実施の形態について説明したが、本発明は上記形態に限ることなくその技術的範囲内で種々変更して実施することができる。例えば、上述した各実施形態においては、スーパージャンクション構造、ｐ型ベース層、ｎ＋ソース層およびゲート電極をストライプ状に形成したが、格子状や千鳥状をなすように配置してもよい。また、半導体材料としてシリコン（Ｓｉ）を用いた縦型パワーＭＯＳＦＥＴについて説明したが、他の材料としては、例えばシリコンカーバイト（ＳｉＣ）や窒化ガリウム（ＧａＮ）、窒化アルミニウム（ＡｌＮ）等の化合物半導体の他、ダイアモンドを用いることもできる。 Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments and can be implemented with various modifications within the technical scope thereof. For example, in each of the embodiments described above, the super junction structure, the p-type base layer, the n + source layer, and the gate electrode are formed in a stripe shape, but may be arranged in a lattice shape or a staggered shape. Further, the vertical power MOSFET using silicon (Si) as the semiconductor material has been described, but other materials include compound semiconductors such as silicon carbide (SiC), gallium nitride (GaN), and aluminum nitride (AlN). In addition, diamond can also be used.

本発明にかかる半導体素子の第１の実施の形態の概略構造を示す平面図である。1 is a plan view showing a schematic structure of a semiconductor device according to a first embodiment of the present invention. 図１に示す半導体素子の切断線Ａ−Ａに沿った断面図である。FIG. 2 is a cross-sectional view taken along a cutting line AA of the semiconductor element shown in FIG. 1. 図１に示す半導体素子の切断線Ｂ−Ｂに沿った断面図である。FIG. 4 is a cross-sectional view taken along a cutting line BB of the semiconductor element shown in FIG. 1. 本発明にかかる半導体素子の第２の実施の形態の概略構造を示す平面図である。It is a top view which shows schematic structure of 2nd Embodiment of the semiconductor element concerning this invention. 図４に示す半導体素子の切断線Ａ−Ａに沿った断面図である。FIG. 5 is a cross-sectional view taken along a cutting line AA of the semiconductor element shown in FIG. 4. 図４に示す半導体素子の切断線Ｂ−Ｂに沿った断面図である。FIG. 5 is a cross-sectional view taken along a cutting line BB of the semiconductor element shown in FIG. 4. 本発明にかかる半導体素子の第３の実施の形態の概略構造を示す平面図である。It is a top view which shows schematic structure of 3rd Embodiment of the semiconductor element concerning this invention. 本発明にかかる半導体素子の第４の実施の形態の概略構造を示す平面図である。It is a top view which shows schematic structure of 4th Embodiment of the semiconductor element concerning this invention. 図８に示す半導体素子の切断線Ａ−Ａに沿った断面図である。FIG. 9 is a cross-sectional view taken along a cutting line AA of the semiconductor element shown in FIG. 8. 図８に示す半導体素子の一変形例を示す断面図である。It is sectional drawing which shows the modification of the semiconductor element shown in FIG. 本発明にかかる半導体素子の第５の実施の形態の概略構造を示す平面図である。It is a top view which shows schematic structure of 5th Embodiment of the semiconductor element concerning this invention. 図１１に示す半導体素子の切断線Ａ−Ａに沿った断面図である。FIG. 12 is a cross-sectional view taken along a cutting line AA of the semiconductor element shown in FIG. 11. 本発明にかかる半導体素子の第６の実施の形態の概略構造を示す平面図である。It is a top view which shows schematic structure of 6th Embodiment of the semiconductor element concerning this invention. 図１３に示す半導体素子の切断線Ａ−Ａに沿った断面図である。FIG. 14 is a cross-sectional view of the semiconductor element shown in FIG. 13 along the cutting line AA. 図１３に示す半導体素子の切断線Ｂ−Ｂに沿った断面図である。FIG. 14 is a cross-sectional view taken along the cutting line BB of the semiconductor element shown in FIG. 13. 図１３に示す半導体素子の一変形例を示す平面図である。FIG. 14 is a plan view illustrating a modified example of the semiconductor element illustrated in FIG. 13. 本発明にかかる半導体素子の第７の実施の形態の概略構造を示す平面図である。It is a top view which shows schematic structure of 7th Embodiment of the semiconductor element concerning this invention. 図１７に示す半導体素子の切断線Ａ−Ａに沿った断面図である。FIG. 18 is a cross-sectional view taken along a cutting line AA of the semiconductor element shown in FIG. 17. 本発明にかかる半導体素子の第８の実施の形態の概略構造を示す平面図である。It is a top view which shows schematic structure of 8th Embodiment of the semiconductor element concerning this invention. 図１９に示す半導体素子の切断線Ａ−Ａに沿った断面図である。FIG. 20 is a cross-sectional view taken along a cutting line AA of the semiconductor element shown in FIG. 19. 図１９に示す半導体素子の切断線Ｂ−Ｂに沿った断面図である。FIG. 20 is a cross-sectional view taken along a cutting line BB of the semiconductor element shown in FIG. 19. 本発明にかかる半導体素子の第９の実施の形態の概略構造を示す平面図である。It is a top view which shows schematic structure of 9th Embodiment of the semiconductor element concerning this invention. 図２２に示す半導体素子の切断線Ａ−Ａに沿った断面図である。FIG. 23 is a cross-sectional view taken along a cutting line AA of the semiconductor element shown in FIG. 22. 本発明にかかる半導体素子の第１０の実施の形態の概略構造を示す平面図である。It is a top view which shows schematic structure of 10th Embodiment of the semiconductor element concerning this invention. 図２４に示す半導体素子の切断線Ａ−Ａに沿った断面図である。FIG. 25 is a cross-sectional view taken along a cutting line AA of the semiconductor element shown in FIG. 24. 図２４に示す半導体素子の切断線Ｂ−Ｂに沿った断面図である。FIG. 25 is a cross-sectional view taken along a cutting line BB of the semiconductor element shown in FIG. 24. 本発明にかかる半導体素子の第１１の実施の形態の概略構成を模式的に示す断面図である。It is sectional drawing which shows typically schematic structure of 11th Embodiment of the semiconductor element concerning this invention. ｐ型ドーパント量と耐圧との関係をセル領域部と接合終端領域部のそれぞれについて示すグラフである。It is a graph which shows the relationship between the amount of p-type dopants, and a proof pressure about each of a cell region part and a junction termination region part. 本発明にかかる半導体素子の第１２の実施の形態の概略構成を模式的に示す断面図である。It is sectional drawing which shows typically schematic structure of 12th Embodiment of the semiconductor element concerning this invention. ｐ型リサーフ層とｎ−型ドリフト層の不純物量バランスに対する耐圧の変化を示すグラフである。It is a graph which shows the change of the proof pressure with respect to the impurity amount balance of a p-type RESURF layer and an n − type drift layer. 本発明にかかる半導体素子の第１３の実施の形態の概略構成を模式的に示す断面図である。It is sectional drawing which shows typically schematic structure of 13th Embodiment of the semiconductor element concerning this invention. 本発明にかかる半導体素子の第１４の実施の形態の概略構成を模式的に示す断面図である。It is sectional drawing which shows typically schematic structure of 14th Embodiment of the semiconductor element concerning this invention. 本発明にかかる半導体素子の第１５の実施の形態の概略構成を模式的に示す断面図である。It is sectional drawing which shows typically schematic structure of 15th Embodiment of the semiconductor element concerning this invention. 本発明にかかる半導体素子の第１６の実施の形態の概略構成を模式的に示す断面図である。It is sectional drawing which shows typically schematic structure of 16th Embodiment of the semiconductor element concerning this invention. 本発明にかかる半導体素子の製造方法の実施の一形態を示す略示断面図である。It is a schematic sectional drawing which shows one Embodiment of the manufacturing method of the semiconductor element concerning this invention. 従来の技術によるスーパージャンクション構造を有するパワーＭＯＳＦＥＴの概略構成を模式的に示す断面図である。It is sectional drawing which shows typically schematic structure of power MOSFET which has the super junction structure by a prior art.

符号の説明Explanation of symbols

１〜１６ 半導体素子
２０，１００ ｎ＋型ドレイン層
２６ ｎ型ドリフト層（セル領域部）
２６ａ，１３６，１６６ ｎ型ドリフト層（接合終端領域部）
２８，５４，１０６ ｐ型ドリフト層（セル領域部）
２８ａ，２９，２９’，５４ａ，１３０，１３２，１３４，１３６，１６８ ｐ型ドリフト層（接合終端領域部）
３０，１０８ ｐ型ベース層（セル領域部）
３０ａ ｐ型ベース層（接合終端領域部）
３２，１１０ ｎ＋型ソース層
３４，１１２ ゲート絶縁膜
３６，１１４ 絶縁ゲート電極
３８ ソース電極（セル領域）
３８ａ ソース電極（接合終端領域部）
４０ ドレイン電極
４２ ｎ＋型チャネルストッパ層
４４ 電極
４８，１２８ フィールド電極
５２ ｐ−型リサーフ層
６２，６２’ ｐ型ガードリング層
６６，７２，７６ 絶縁膜
６８ ｎ−型ベース層
１０２，１４２ ｎ−型ドリフト層
１５１，１５３，１６０ ｎ−型半導体層
１５６，１５８，１６４ ｐ−型半導体層 1-16 Semiconductor device 20, 100 n + type drain layer 26 n type drift layer (cell region part)
26a, 136, 166 n-type drift layer (junction termination region)
28, 54, 106 p-type drift layer (cell region part)
28a, 29, 29 ', 54a, 130, 132, 134, 136, 168 p-type drift layer (junction termination region)
30,108 p-type base layer (cell region)
30a p-type base layer (junction termination region)
32, 110 n + type source layer 34, 112 Gate insulating film 36, 114 Insulated gate electrode 38 Source electrode (cell region)
38a Source electrode (junction termination region)
40 drain electrode 42 n + type channel stopper layer 44 electrode 48, 128 field electrode 52 p − type RESURF layer 62, 62 ′ p type guard ring layers 66, 72, 76 insulating film 68 n − type base layer 102, 142 n − Type drift layers 151, 153, 160 n − type semiconductor layers 156, 158, 164 p − type semiconductor layers

Claims (4)

セル領域部と、このセル領域部を囲むように設けられた接合終端領域部とを有し、前記接合終端領域部での不純物濃度が前記セル領域部での不純物濃度よりも低くなるように形成された第１の第１導電型半導体層と、
前記第１の第１導電型半導体層の一方の表面上に形成された第２の第１導電型半導体層と、
前記第２の第１導電型半導体層に電気的に接続された第１の主電極と、
前記第１の第１導電型半導体層の前記セル領域部内で前記第１の第１導電型半導体層の一方の表面にほぼ垂直な方向でそれぞれが形成され、前記一方の表面に平行な任意の方向である第１の方向に周期的に配置された第１の第２導電型半導体層と、
前記第１の第１導電型半導体層の他方の表面部において前記第１の第２導電型半導体層に接続するように選択的に形成された第２の第２導電型半導体層と、
前記第２の第２導電型半導体層の表面部に選択的に形成された第３の第１導電型半導体層と、
前記第２の第２導電型半導体層の表面と前記第３の第１導電型半導体層の表面とに接するように形成された第２の主電極と、
前記第１の第１導電型半導体層の他方の表面のうち隣り合う前記第２の第２導電型半導体層に挟まれた領域と、前記隣り合う第２の第２導電型半導体層の表面と前記第３の第１導電型半導体層の表面の上にゲート絶縁膜を介して形成された制御電極と、
前記接合終端領域部内で前記セル領域部との境界面近傍の表面部において前記セル領域部を取り囲むように形成され、前記第２の主電極に電気的に接続される第３の第２導電型半導体層と、
を備える半導体素子。 It has a cell region portion and a junction termination region portion provided so as to surround the cell region portion, and is formed so that the impurity concentration in the junction termination region portion is lower than the impurity concentration in the cell region portion. A first first conductivity type semiconductor layer formed;
A second first conductivity type semiconductor layer formed on one surface of the first first conductivity type semiconductor layer;
A first main electrode electrically connected to the second first conductivity type semiconductor layer;
Each of the first first conductivity type semiconductor layers is formed in a direction substantially perpendicular to one surface of the first first conductivity type semiconductor layer within the cell region portion of the first first conductivity type semiconductor layer, and is arbitrary in parallel to the one surface. A first second conductivity type semiconductor layer periodically disposed in a first direction which is a direction;
A second second conductivity type semiconductor layer selectively formed so as to be connected to the first second conductivity type semiconductor layer at the other surface portion of the first first conductivity type semiconductor layer;
A third first conductivity type semiconductor layer selectively formed on a surface portion of the second second conductivity type semiconductor layer;
A second main electrode formed so as to be in contact with the surface of the second second conductivity type semiconductor layer and the surface of the third first conductivity type semiconductor layer;
Of the other surface of the first first conductivity type semiconductor layer, a region sandwiched between the adjacent second second conductivity type semiconductor layers, and the surface of the adjacent second second conductivity type semiconductor layer, A control electrode formed on the surface of the third first conductivity type semiconductor layer via a gate insulating film;
A third second conductivity type formed so as to surround the cell region portion in a surface portion in the vicinity of the boundary surface with the cell region portion in the junction termination region portion and electrically connected to the second main electrode. A semiconductor layer;
A semiconductor device comprising: 前記第１の第１導電型半導体層の前記接合終端領域部内で前記第１の第１導電型半導体層の前記一方の表面にほぼ垂直な方向で形成され、一端で前記第３の第２導電型半導体層に接して前記第３の第２導電型半導体層を介して前記第２の主電極に電気的に接続される第４の第２導電型半導体層をさらに備えることを特徴とする請求項１に記載の半導体素子。   The first second conductivity type semiconductor layer is formed in a direction substantially perpendicular to the one surface of the first first conductivity type semiconductor layer within the junction termination region of the first first conductivity type semiconductor layer, and the third second conductivity at one end. And a fourth second conductive semiconductor layer in contact with the second semiconductor electrode and in contact with the second main electrode through the third second conductive semiconductor layer. Item 2. The semiconductor element according to Item 1. 前記接合終端領域部の前記第１の第１導電型半導体層の表面部に第２導電型半導体層で形成された複数のガードリング層をさらに備えることを特徴とする請求項１または２に記載の半導体素子。   3. The device according to claim 1, further comprising a plurality of guard ring layers formed of a second conductivity type semiconductor layer on a surface portion of the first first conductivity type semiconductor layer in the junction termination region portion. Semiconductor element. アスペクト比Ｒのトレンチ溝が設けられた第１導電型半導体層と前記トレンチ溝内に埋め込まれた第２導電型半導体層とを有するスーパージャンクション構造の半導体素子の製造方法であって、
第１導電型半導体層内にＲ／Ｎ（Ｎは２以上の自然数）のアスペクト比を有するトレンチ溝を形成する第１の工程と、
前記トレンチ溝を埋め込むように第２導電型半導体層をエピタキシャル成長させる第２の工程と、
前記第１導電型半導体層の表面が露出するまで前記第２導電型半導体層を除去する第３の工程と、
前記第１導電型半導体層および前記第２導電型半導体層の上に、前記第１の工程により形成されたトレンチ溝の深さと実質的に同一の長さだけ層厚が増大するように前記第１導電型半導体層をエピタキシャル成長させる第４の工程と、
前記第１の工程により形成されたトレンチ溝に埋め込まれた前記第２導電型半導体層が露出するように前記第１導電型半導体層を選択的に除去する第５の工程と、
前記第２乃至第５の工程を（Ｎ−１）回だけ繰り返す工程と、
を備える半導体素子の製造方法。 A method for manufacturing a semiconductor device having a super junction structure having a first conductivity type semiconductor layer provided with a trench groove having an aspect ratio R and a second conductivity type semiconductor layer embedded in the trench groove,
Forming a trench groove having an aspect ratio of R / N (N is a natural number of 2 or more) in the first conductivity type semiconductor layer;
A second step of epitaxially growing a second conductivity type semiconductor layer so as to fill the trench groove;
A third step of removing the second conductive semiconductor layer until a surface of the first conductive semiconductor layer is exposed;
The thickness of the first conductive semiconductor layer and the second conductive semiconductor layer is increased by a length substantially the same as the depth of the trench formed in the first step. A fourth step of epitaxially growing the one conductivity type semiconductor layer;
A fifth step of selectively removing the first conductive type semiconductor layer so that the second conductive type semiconductor layer embedded in the trench groove formed by the first step is exposed;
Repeating the second to fifth steps (N-1) times;
A method for manufacturing a semiconductor device comprising:
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