JP2007103747A - Method of manufacturing semiconductor substrate - Google Patents

Method of manufacturing semiconductor substrate Download PDF

Info

Publication number
JP2007103747A
JP2007103747A JP2005293087A JP2005293087A JP2007103747A JP 2007103747 A JP2007103747 A JP 2007103747A JP 2005293087 A JP2005293087 A JP 2005293087A JP 2005293087 A JP2005293087 A JP 2005293087A JP 2007103747 A JP2007103747 A JP 2007103747A
Authority
JP
Japan
Prior art keywords
epitaxial layer
trenches
trench
semiconductor substrate
epitaxial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2005293087A
Other languages
Japanese (ja)
Inventor
Shoji Nogami
彰二 野上
Tomonori Yamaoka
智則 山岡
Shoichi Yamauchi
庄一 山内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumco Corp
Denso Corp
Original Assignee
Sumco Corp
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumco Corp, Denso Corp filed Critical Sumco Corp
Priority to JP2005293087A priority Critical patent/JP2007103747A/en
Priority to US12/089,497 priority patent/US20090273102A1/en
Priority to CN200680036884XA priority patent/CN101278377B/en
Priority to DE112006002626T priority patent/DE112006002626B4/en
Priority to KR1020087009941A priority patent/KR100997153B1/en
Priority to DE112006004215T priority patent/DE112006004215B4/en
Priority to PCT/JP2006/319933 priority patent/WO2007040255A1/en
Priority to CN2009102169066A priority patent/CN101853786B/en
Priority to KR1020107000759A priority patent/KR100950232B1/en
Publication of JP2007103747A publication Critical patent/JP2007103747A/en
Priority to US12/964,141 priority patent/US8835276B2/en
Priority to US14/448,370 priority patent/US20140342535A1/en
Priority to US14/448,347 priority patent/US9034721B2/en
Priority to US14/448,372 priority patent/US8956947B2/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02428—Structure
    • H01L21/0243—Surface structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Composite Materials (AREA)
  • Recrystallisation Techniques (AREA)
  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To avoid a void generated on an epitaxial layer embedded inside a trench. <P>SOLUTION: A method of manufacturing a semiconductor substrate comprises a process for growing a first epitaxial layer 11 on the surface of a substrate body 13; a process for forming a plurality of first trenches 14 on the first epitaxial layer 11; a process for growing a second epitaxial layer 12 in the entire inner part of the first trench 14; a process for polishing the second epitaxial layer 12 for flattening; a process for further growing a third epitaxial layer 16 with the same composition as that of the first epitaxial layer 11 on the upper surface of the second flattened epitaxial layer 12; a process for forming a second trench 17 on the third epitaxial layer 16 for extending the first trench 14; a process for further growing a fourth epitaxial layer 18 in the entire inner part of the second trench 17; and a process for polishing the fourth epitaxial layer 18 for flattening. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、トレンチ内部にエピタキシャル層を成長させてトレンチの内部をエピタキシャル層で埋め込む半導体基板の製造方法に関するものである。   The present invention relates to a method for manufacturing a semiconductor substrate in which an epitaxial layer is grown inside a trench and the inside of the trench is filled with the epitaxial layer.

従来、半導体基板の製造方法にあっては、トレンチ内にエピタキシャル層を埋め込み、高アスペクト比の拡散層を形成する製造方法（例えば、特許文献１参照。）が提案されている。また、縦型ＭＯＳトランジスタであって、ドリフト領域をスーパジャンクション構造（Ｐ／Ｎコラム構造）とする場合においては、トレンチ内にエピタキシャル層を埋め込み、拡散層を形成する半導体基板の製造方法（例えば、特許文献２参照。）が提案されている。
特許第３４８５０８１号公報 特開２００３−１２４４６４号公報 Conventionally, as a method for manufacturing a semiconductor substrate, a manufacturing method in which an epitaxial layer is embedded in a trench to form a diffusion layer having a high aspect ratio (see, for example, Patent Document 1) has been proposed. When the drift region has a super junction structure (P / N column structure), a semiconductor substrate manufacturing method in which an epitaxial layer is embedded in a trench and a diffusion layer is formed (for example, (See Patent Document 2).
Japanese Patent No. 3485081 JP 2003-124464 A

しかし、上記特許文献１における半導体基板の製造方法にあっては、予め形成されたトレンチ内にエピタキシャル層を複数回にわたって埋め込むことにより高アスペクト比の拡散層を形成するようになっていることから、そのアスペクト比を高くするには自ずと限界があった。そして、その限界を超えてトレンチのアスペクト比を高くすると、トレンチ内の埋め込みエピタキシャル層中に埋め込み不良（ボイド）が発生するおそれがあり、ボイドが生じるとそのボイドの上部においてフレークダウンが発生して耐圧が減少し、素子性能が低下する不具合がある。
特に、Ｎ型領域とＰ型領域とが交互にかつ電流方向に対して垂直に並んだ前述のスーパジャンクション構造（Ｐ／Ｎコラム構造）においてその耐圧を向上させるためには、トレンチ深さを深くする必要があるけれども、トレンチ深さが深くなることによって結果としてアスペクト比が高くなり、トレンチ内の埋め込みエピタキシャル層中に埋め込み不良（ボイド）が発生すると、埋め込み不良（ボイド）に起因する結晶欠陥の発生に伴い耐圧接合リーク歩留まりの低下を招いたり、トレンチでの埋め込み不良箇所においてレジストが残って工程内汚染を招くといったことが発生する。
本発明の目的は、トレンチの内部に埋め込まれたエピタキシャル層にボイドが生じることを回避し得る半導体基板の製造方法を提供することにある。 However, in the method of manufacturing a semiconductor substrate in Patent Document 1, a diffusion layer having a high aspect ratio is formed by embedding an epitaxial layer a plurality of times in a trench formed in advance. There was a natural limit to increasing the aspect ratio. If the trench aspect ratio is increased beyond that limit, a buried defect (void) may occur in the buried epitaxial layer in the trench. If a void occurs, flake-down occurs at the top of the void. There is a problem that the withstand voltage decreases and the device performance deteriorates.
In particular, in order to improve the breakdown voltage in the above-described super junction structure (P / N column structure) in which N-type regions and P-type regions are arranged alternately and perpendicular to the current direction, the trench depth is increased. However, if the trench depth is increased, the aspect ratio is increased as a result, and if a buried defect (void) occurs in the buried epitaxial layer in the trench, crystal defects caused by the buried defect (void) are eliminated. As a result, the yield of the pressure-resistant junction leakage may be reduced, or the resist may remain at the portion where the trench is poorly filled, resulting in in-process contamination.
An object of the present invention is to provide a method for manufacturing a semiconductor substrate capable of avoiding the occurrence of voids in an epitaxial layer embedded in a trench.

請求項１に係る発明は、図１に示すように、（ａ）基板本体１３表面に第１エピタキシャル層１１を成長させる工程と、（ｂ）この第１エピタキシャル層１１を部分的にエッチングして複数の第１トレンチ１４を形成する工程と、（ｃ）複数の第１トレンチ１４の内部全体及び複数の第１トレンチ１４以外の第１エピタキシャル層１１の表面に第２エピタキシャル層１２を成長させる工程と、（ｄ）第２エピタキシャル層１２を研磨して第１エピタキシャル層１１の表面を露出させるとともに複数の第１トレンチ１４の内部全体に埋め込まれた第２エピタキシャル層１２の上面を平坦にする工程と、（ｅ）平坦にされた第２エピタキシャル層１２の上面と露出した第１エピタキシャル層１１の表面に第１エピタキシャル層１１と同一組成の第３エピタキシャル層１６を更に成長させる工程と、（ｆ）この第３エピタキシャル層１６の複数の第１トレンチ１４に対応する部分をエッチングして複数の第２トレンチ１７を形成することにより複数の第１トレンチ１４を延長させる工程と、（ｇ）複数の第２トレンチ１７の内部全体及び複数の第２トレンチ１７以外の第３エピタキシャル層１６の表面に第４エピタキシャル層１８を更に成長させる工程と、（ｈ）第４エピタキシャル層１８を研磨して第３エピタキシャル層１６の表面を露出させるとともに複数の第２トレンチ１７の内部全体に埋め込まれた第４エピタキシャル層１８の上面を平坦にする工程とを含む半導体基板の製造方法である。   As shown in FIG. 1, the invention according to claim 1 includes: (a) a step of growing the first epitaxial layer 11 on the surface of the substrate body 13; and (b) a partial etching of the first epitaxial layer 11. A step of forming a plurality of first trenches 14; and (c) a step of growing the second epitaxial layer 12 on the entire interior of the plurality of first trenches 14 and on the surface of the first epitaxial layer 11 other than the plurality of first trenches 14. And (d) polishing the second epitaxial layer 12 to expose the surface of the first epitaxial layer 11 and flattening the upper surface of the second epitaxial layer 12 embedded in the entirety of the plurality of first trenches 14. (E) on the upper surface of the flattened second epitaxial layer 12 and the exposed surface of the first epitaxial layer 11, the first epitaxial layer 11 having the same composition as the first epitaxial layer 11 A step of further growing the epitaxial layer 16, and (f) etching a portion of the third epitaxial layer 16 corresponding to the plurality of first trenches 14 to form a plurality of second trenches 17, thereby forming a plurality of first trenches. (G) a step of further growing the fourth epitaxial layer 18 on the entire inside of the plurality of second trenches 17 and on the surface of the third epitaxial layer 16 other than the plurality of second trenches 17; And a step of polishing the fourth epitaxial layer 18 to expose the surface of the third epitaxial layer 16 and flattening the upper surface of the fourth epitaxial layer 18 embedded in the entire interior of the plurality of second trenches 17. A method for manufacturing a substrate.

トレンチ１４，１７の内部にボイドを生じさせることなくエピタキシャル層１２，１８で埋め込むことができるか否かに関しては、そのトレンチ１４，１７の幅Ａに対するトレンチの深さＢが浅ければ浅いほど、トレンチ１４，１７の内部にボイドを生じさせることなくエピタキシャル層１２，１８で埋め込むことができることが知られている。
この請求項１に記載された半導体基板の製造方法では、トレンチ１４，１７の形成とエピタキシャル層１２，１８の埋め込みを複数回に分けて行うので、エピタキシャル層１２，１８の埋め込みを行う際のトレンチ１４，１７の幅Ａに対するトレンチの深さＢを浅いものにすることができ、複数のトレンチ１４、１７の内部にボイドを生じさせることなくエピタキシャル層１２、１８で埋め込むことができる。 Regarding whether or not the trenches 14 and 17 can be filled with the epitaxial layers 12 and 18 without generating voids, the shallower the trench depth B with respect to the width A of the trenches 14 and 17, the smaller the depth. It is known that the trenches 14 and 17 can be filled with the epitaxial layers 12 and 18 without causing voids.
In the method of manufacturing a semiconductor substrate according to the first aspect, since the formation of the trenches 14 and 17 and the embedding of the epitaxial layers 12 and 18 are performed in a plurality of times, the trenches for embedding the epitaxial layers 12 and 18 The depth B of the trench with respect to the width A of 14 and 17 can be made shallow, and the trenches 14 and 17 can be filled with the epitaxial layers 12 and 18 without causing voids.

請求項２に係る発明は、請求項１に係る発明であって、工程（ｇ）の後に、工程（ｄ）から工程（ｇ）までを１回又は２回以上繰り返すことを特徴とする。
この請求項２に記載された半導体基板の製造方法では、工程（ｄ）から工程（ｇ）までを３回以上繰り返すことになり、最終的に得ようとするトレンチのアスペクト比が比較的大きいものであっても、１回あたりのエピタキシャル層の埋め込みを行う際のトレンチの幅Ａに対するトレンチの深さＢを浅いものにすることができ、トレンチの内部に埋め込まれたエピタキシャル層にボイドが生じることを有効に回避することができる。 The invention according to claim 2 is the invention according to claim 1, characterized in that after the step (g), the steps (d) to (g) are repeated once or twice or more.
In the method for manufacturing a semiconductor substrate according to claim 2, the steps (d) to (g) are repeated three times or more, and the aspect ratio of the trench to be finally obtained is relatively large. Even so, the depth B of the trench with respect to the width A of the trench when embedding the epitaxial layer per time can be made shallow, and voids are generated in the epitaxial layer embedded in the trench. Can be effectively avoided.

以上述べたように、本発明によれば、トレンチの形成とエピタキシャル層の埋め込みを複数回に分けて行うので、エピタキシャル層の埋め込みを行う際のトレンチの幅に対するトレンチの深さを浅いものにすることができ、複数のトレンチの内部にボイドを生じさせることなくエピタキシャル層で埋め込むことができる。特にトレンチの形成とエピタキシャル層の埋め込みを３回以上繰り返せば、最終的に得ようとするトレンチのアスペクト比が比較的大きいものであっても、エピタキシャル層の埋め込みを行う際のトレンチの幅に対するトレンチの深さを十分に浅いものにすることができ、トレンチの内部に埋め込まれたエピタキシャル層にボイドが生じることを有効に回避することができる。   As described above, according to the present invention, since the formation of the trench and the embedding of the epitaxial layer are performed in a plurality of times, the depth of the trench relative to the width of the trench when embedding the epitaxial layer is made shallow. And can be filled with an epitaxial layer without creating voids inside the plurality of trenches. In particular, if the formation of the trench and the embedding of the epitaxial layer are repeated three or more times, even if the aspect ratio of the trench to be finally obtained is relatively large, the trench with respect to the width of the trench when embedding the epitaxial layer is increased. Therefore, it is possible to effectively avoid the formation of voids in the epitaxial layer embedded in the trench.

次に本発明を実施するための最良の形態を図面に基づいて説明する。
図１に示すように、半導体基板はＮ+型の基板本体１３を備え、この基板本体１３表面にはエピタキシャル層１１，１６が形成される。基板本体１３はリン、ヒ素、アンチモン等の不純物のドープされたＮ+型のシリコン単結晶基板であり、エピタキシャル層１１，１６はリン、ヒ素、アンチモン等の不純物のドープされたＮ型シリコン単結晶層である。このエピタキシャル層１１，１６は部分的にエッチング除去され、所定の間隔をあけてリブ状の複数のエピタキシャル層１１，１６が基板本体１３の表面にそれぞれ形成され、複数のエピタキシャル層１１，１６間のトレンチ１４，１７には、ホウ素、ガリウム、インジウム等の不純物のドープされたＰ型シリコン単結晶からなるエピタキシャル層１２，１８が埋め込まれる。 Next, the best mode for carrying out the present invention will be described with reference to the drawings.
As shown in FIG. 1, the semiconductor substrate includes an N + type substrate body 13, and epitaxial layers 11 and 16 are formed on the surface of the substrate body 13. The substrate body 13 is an N + type silicon single crystal substrate doped with impurities such as phosphorus, arsenic, and antimony, and the epitaxial layers 11 and 16 are N type silicon single crystals doped with impurities such as phosphorus, arsenic, and antimony. Is a layer. The epitaxial layers 11 and 16 are partially etched away, and a plurality of rib-like epitaxial layers 11 and 16 are formed on the surface of the substrate body 13 with a predetermined interval between them. Epitaxial layers 12 and 18 made of P-type silicon single crystal doped with impurities such as boron, gallium, and indium are embedded in the trenches 14 and 17.

次に、このような半導体装置における本発明の製造方法について説明する。
先ず、図１（ａ）に示すように、Ｎ+型の基板本体１３を用意し、その上にＮ型の第１エピタキシャル層１１を形成する。具体的には、基板本体１３の表面に原料ガスとしてシランガスを供給しながら、気相成長法により４００〜１２００℃の温度範囲で第１エピタキシャル層１１を成長させる。 Next, the manufacturing method of the present invention in such a semiconductor device will be described.
First, as shown in FIG. 1A, an N + -type substrate body 13 is prepared, and an N-type first epitaxial layer 11 is formed thereon. Specifically, the first epitaxial layer 11 is grown in a temperature range of 400 to 1200 ° C. by a vapor phase growth method while supplying a silane gas as a source gas to the surface of the substrate body 13.

次に図１（ｂ）に示すように、この第１エピタキシャル層１１を部分的にエッチングして複数の第１トレンチ１４を形成する。具体的には、Ｎ型第１エピタキシャル層１１の上に図示しないシリコン酸化膜を成膜し、このシリコン酸化膜に対して所定のトレンチが得られるように所定の形状にパターニングする。そして、このパターニングされたシリコン酸化膜をマスクにしてＮ型の第１エピタキシャル層１１に対して異方性エッチング（ＲＩＥ）、又は、アルカリ性異方性エッチング液（ＫＯＨ、ＴＭＡＨ等）によるウエットエッチングを行い、複数の第１トレンチ１４を形成する。その後、マスクとして用いた図示しないシリコン酸化膜を除去する。このようにして、この基板本体１３表面に、所定の間隔をあけてリブ状の複数の第１エピタキシャル層１１をそれぞれ形成するとともに、その複数の第１エピタキシャル層１１の間に複数の第１トレンチ１４をそれぞれ形成する。   Next, as shown in FIG. 1B, the first epitaxial layer 11 is partially etched to form a plurality of first trenches 14. Specifically, a silicon oxide film (not shown) is formed on the N-type first epitaxial layer 11, and is patterned into a predetermined shape so that a predetermined trench is obtained for the silicon oxide film. Then, using this patterned silicon oxide film as a mask, the N-type first epitaxial layer 11 is subjected to anisotropic etching (RIE) or wet etching with an alkaline anisotropic etching solution (KOH, TMAH, etc.). A plurality of first trenches 14 are formed. Thereafter, a silicon oxide film (not shown) used as a mask is removed. In this manner, a plurality of rib-shaped first epitaxial layers 11 are formed on the surface of the substrate main body 13 at predetermined intervals, and a plurality of first trenches are formed between the plurality of first epitaxial layers 11. 14 are formed.

次に図１（ｃ）に示すように、複数の第１トレンチ１４の内部全体及び複数の第１トレンチ１４以外の第１エピタキシャル層１１の表面に第２エピタキシャル層１２を成長させる。具体的には、複数の第１トレンチ１４の内面を含めて第１エピタキシャル層１１の上に原料ガスを供給しながら、気相成長法により４００〜１１５０℃の温度範囲で第２エピタキシャル層１２を成膜し、その第２エピタキシャル層１２により複数の第１トレンチ１４内を埋め込む。この複数の第１トレンチ１４の内部を第２エピタキシャル層１２で埋め込む工程において、少なくとも埋め込み最終工程において、第１エピタキシャル層１１の成膜のために供給する原料ガスとして、半導体ソースガスとハロゲン化物ガスとの混合ガスを用いることが好ましい。ここで、半導体ソースガスとしては、モノシラン（ＳｉＨ4）、ジシラン（Ｓｉ2Ｈ6）、ジクロロシラン（ＳｉＨ2Ｃｌ2）、トリクロロシラン（ＳｉＨＣｌ3）、四塩化シリコン（ＳｉＣｌ4）等が挙げられる。特に、半導体ソースガスとして、ジクロロシラン（ＳｉＨ2Ｃｌ2）、トリクロロシラン（ＳｉＨＣｌ3）、四塩化シリコン（ＳｉＣｌ4）のいずれかを用いることが好ましい。ハロゲン化物ガスとしては塩化水素（ＨＣｌ）、塩素（Ｃｌ2）、フッ素（Ｆ2）、三フッ化塩素（ＣｌＦ3）、フッ化水素（ＨＦ）、臭化水素（ＨＢｒ）のいずれかを用いることが好ましく、特に塩化水素（ＨＣｌ）を用いることが好ましい。 Next, as shown in FIG. 1C, the second epitaxial layer 12 is grown on the entire interior of the plurality of first trenches 14 and on the surface of the first epitaxial layer 11 other than the plurality of first trenches 14. Specifically, the second epitaxial layer 12 is formed in a temperature range of 400 to 1150 ° C. by a vapor phase growth method while supplying a source gas onto the first epitaxial layer 11 including the inner surfaces of the plurality of first trenches 14. A film is formed, and the plurality of first trenches 14 are filled with the second epitaxial layer 12. In the step of filling the insides of the plurality of first trenches 14 with the second epitaxial layer 12, at least in the final step of filling, as source gases supplied for forming the first epitaxial layer 11, a semiconductor source gas and a halide gas are used. It is preferable to use a mixed gas. Here, examples of the semiconductor source gas include monosilane (SiH 4 ), disilane (Si 2 H 6 ), dichlorosilane (SiH 2 Cl 2 ), trichlorosilane (SiHCl 3 ), and silicon tetrachloride (SiCl 4 ). . In particular, it is preferable to use any one of dichlorosilane (SiH 2 Cl 2 ), trichlorosilane (SiHCl 3 ), and silicon tetrachloride (SiCl 4 ) as the semiconductor source gas. Any one of hydrogen chloride (HCl), chlorine (Cl 2 ), fluorine (F 2 ), chlorine trifluoride (ClF 3 ), hydrogen fluoride (HF), and hydrogen bromide (HBr) is used as the halide gas. It is particularly preferable to use hydrogen chloride (HCl).

半導体ソースガスとハロゲン化物ガスとの混合ガスを原料ガスとして供給すると、その内のハロゲン化物ガスはエッチングガスとして機能し、そのエッチングガスは供給律速であり、エッチング速度は複数の第１トレンチ１４開口部の方が複数の第１トレンチ１４の内部よりも早くなる。これにより複数の第１トレンチ１４開口部よりも深い部位での成長速度よりも遅くなり、複数の第１トレンチ１４側面上の第２エピタキシャル層１２に関して複数の第１トレンチ１４底部より複数の第１トレンチ１４開口部の膜厚が小さくなり、図２（ｃ）に示すように、複数の第１トレンチ１４の内部にボイドを生じさせることなく第２エピタキシャル層１２で埋め込むことができる。   When a mixed gas of a semiconductor source gas and a halide gas is supplied as a source gas, the halide gas therein functions as an etching gas, the etching gas is supply-controlled, and the etching rate is the opening of the plurality of first trenches 14. The portion is faster than the inside of the plurality of first trenches 14. As a result, the growth rate becomes slower than the growth rate at the deeper part than the openings of the plurality of first trenches 14, and the plurality of firsts is formed from the bottoms of the plurality of first trenches 14 with respect to the second epitaxial layer 12 on the side surfaces of the plurality of first trenches 14. The thickness of the opening of the trench 14 is reduced, and as shown in FIG. 2C, the plurality of first trenches 14 can be filled with the second epitaxial layer 12 without causing voids.

次に、図１（ｄ）に示すように、第２エピタキシャル層１２を研磨して第１エピタキシャル層１１の表面を露出させるとともに複数の第１トレンチ１４の内部全体に埋め込まれた第２エピタキシャル層１２の上面を平坦にする。この研磨は例えばＣＭＰ等により行うことができる。
次に、図１（ｅ）に示すように、平坦化された第２エピタキシャル層１２の上面と露出した第１エピタキシャル層１１の表面にその第１エピタキシャル層１１と同一組成の第３エピタキシャル層１６を更に成長させる。この第３エピタキシャル層１６の形成は上述した第１エピタキシャル層１１の形成と同一の手順により行われ、具体的には、平坦化された第２エピタキシャル層１２の上面と露出した第１エピタキシャル層１１の表面に原料ガスとしてシランガスを供給しながら、気相成長法により４００〜１２００℃の温度範囲で第３エピタキシャル層１６を成長させる。 Next, as shown in FIG. 1 (d), the second epitaxial layer 12 is polished to expose the surface of the first epitaxial layer 11, and the second epitaxial layer embedded in the entire interior of the plurality of first trenches 14. The upper surface of 12 is flattened. This polishing can be performed by, for example, CMP.
Next, as shown in FIG. 1E, a third epitaxial layer 16 having the same composition as the first epitaxial layer 11 is formed on the planarized upper surface of the second epitaxial layer 12 and the exposed surface of the first epitaxial layer 11. Grow further. The formation of the third epitaxial layer 16 is performed by the same procedure as the formation of the first epitaxial layer 11 described above. Specifically, the upper surface of the planarized second epitaxial layer 12 and the exposed first epitaxial layer 11 are formed. The third epitaxial layer 16 is grown in a temperature range of 400 to 1200 ° C. by a vapor phase growth method while supplying silane gas as a source gas to the surface.

次に、図１（ｆ）に示すように、この第３エピタキシャル層１６の複数の第１トレンチ１４に対応する部分をエッチングして複数の第２トレンチ１７を形成することにより複数の第１トレンチ１４を延長させる。具体的には、第３エピタキシャル層１６の上に図示しないシリコン酸化膜を成膜し、このシリコン酸化膜の第１トレンチ１４に対応する部分を除去して所定の形状にパターニングする。そして、このパターニングされたシリコン酸化膜をマスクにして第３エピタキシャル層１６に対して異方性エッチング（ＲＩＥ）、又は、アルカリ性異方性エッチング液（ＫＯＨ、ＴＭＡＨ等）によるウエットエッチングを行い、複数の第２トレンチ１７を形成することにより複数の第１トレンチ１４を延長させる。その後、マスクとして用いた図示しないシリコン酸化膜を除去する。   Next, as shown in FIG. 1 (f), a plurality of first trenches are formed by etching a portion corresponding to the plurality of first trenches 14 of the third epitaxial layer 16 to form a plurality of second trenches 17. 14 is extended. Specifically, a silicon oxide film (not shown) is formed on the third epitaxial layer 16, and a portion corresponding to the first trench 14 of this silicon oxide film is removed and patterned into a predetermined shape. Then, anisotropic etching (RIE) or wet etching with an alkaline anisotropic etching solution (KOH, TMAH, etc.) is performed on the third epitaxial layer 16 using the patterned silicon oxide film as a mask, The plurality of first trenches 14 are extended by forming the second trenches 17. Thereafter, a silicon oxide film (not shown) used as a mask is removed.

次に、図１（ｇ）に示すように、複数の第２トレンチ１７の内部全体及び複数の第２トレンチ１７以外の第３エピタキシャル層１６の表面に第４エピタキシャル層１８を更に成長させる。この第４エピタキシャル層１８の形成は上述した第２エピタキシャル層１２の形成と同一の手順により行われ、具体的には、複数の第２トレンチ１７の内面を含めて第３エピタキシャル層１６の上に原料ガスを供給しながら、気相成長法により４００〜１１５０℃の温度範囲で第４エピタキシャル層１８を成膜し、その第４エピタキシャル層１８により複数の第２トレンチ１７内を埋め込む。
次に、図１（ｈ）に示すように、第４エピタキシャル層１８を研磨して第３エピタキシャル層１６の表面を露出させるとともに複数の第２トレンチ１７の内部全体に埋め込まれた第４エピタキシャル層１８の上面を平坦にする。これにより、横方向にＰ型領域とＮ型領域とが交互に配置された半導体基板が得られる。 Next, as shown in FIG. 1G, a fourth epitaxial layer 18 is further grown on the entire interior of the plurality of second trenches 17 and on the surface of the third epitaxial layer 16 other than the plurality of second trenches 17. The formation of the fourth epitaxial layer 18 is performed by the same procedure as the formation of the second epitaxial layer 12 described above. Specifically, the fourth epitaxial layer 18 is formed on the third epitaxial layer 16 including the inner surfaces of the plurality of second trenches 17. While supplying the source gas, the fourth epitaxial layer 18 is formed in a temperature range of 400 to 1150 ° C. by the vapor phase growth method, and the inside of the plurality of second trenches 17 is embedded by the fourth epitaxial layer 18.
Next, as shown in FIG. 1H, the fourth epitaxial layer 18 is polished to expose the surface of the third epitaxial layer 16, and the fourth epitaxial layer embedded in the entire interior of the plurality of second trenches 17. The upper surface of 18 is flattened. As a result, a semiconductor substrate in which P-type regions and N-type regions are alternately arranged in the lateral direction is obtained.

ここで、トレンチ１４，１７の内部にボイドを生じさせることなくエピタキシャル層１２，１８で埋め込むことができるか否かに関しては、そのトレンチ１４，１７の幅Ａに対するトレンチの深さＢで表されるアスペクト比（Ｂ／Ａ）に依り、そのトレンチ１４，１７の幅Ａに対するトレンチの深さＢが浅ければ浅いほど、即ち、アスペクト比（Ｂ／Ａ）が小さいほどトレンチ１４，１７の内部にボイドを生じさせることなくエピタキシャル層１２，１８で埋め込むことができることが知られている。そして、本発明における半導体基板の製造方法に依れば、トレンチ１４，１７の形成とエピタキシャル層１２，１８の埋め込みを複数回に分けて行うので、エピタキシャル層１２，１８の埋め込みを行う際のトレンチ１４，１７のアスペクト比を小さいものにすることができる。この結果、複数のトレンチ１４、１７の内部にボイドを生じさせることなくエピタキシャル層１２、１８で埋め込むことができる。   Here, whether or not the trenches 14 and 17 can be filled with the epitaxial layers 12 and 18 without causing voids is expressed by the depth B of the trench with respect to the width A of the trenches 14 and 17. Depending on the aspect ratio (B / A), the shallower the trench depth B with respect to the width A of the trenches 14, 17, the smaller the aspect ratio (B / A), the more inside the trenches 14, 17. It is known that the epitaxial layers 12 and 18 can be filled without generating voids. According to the method for manufacturing a semiconductor substrate in the present invention, the formation of the trenches 14 and 17 and the embedding of the epitaxial layers 12 and 18 are performed in a plurality of times, so that the trenches when embedding the epitaxial layers 12 and 18 are performed. The aspect ratio of 14, 17 can be made small. As a result, the trenches 14 and 17 can be filled with the epitaxial layers 12 and 18 without generating voids.

なお、上述した実施の形態では、トレンチ１４，１７の形成とエピタキシャル層１２，１８の埋め込みを２回に分けて行う場合を説明したが、最終的に得ようとするトレンチのアスペクト比が比較的大きい場合には、上述した工程（ｇ）の後に、工程（ｄ）から工程（ｇ）までを１回又は２回以上更に繰り返しても良い。工程（ｄ）から工程（ｇ）までを３回以上繰り返す半導体基板の製造方法では、最終的に得ようとするトレンチのアスペクト比が比較的大きいものであっても、１回あたりのエピタキシャル層の埋め込みを行う際のトレンチのアスペクト比を小さいものにすることができ、トレンチの内部に埋め込まれたエピタキシャル層にボイドが生じることを有効に回避することができる。   In the above-described embodiment, the case where the formation of the trenches 14 and 17 and the embedding of the epitaxial layers 12 and 18 are performed in two steps has been described. However, the aspect ratio of the trench to be finally obtained is relatively In the case of being large, after the step (g) described above, the step (d) to the step (g) may be further repeated once or twice or more. In the method of manufacturing a semiconductor substrate in which steps (d) to (g) are repeated three or more times, even if the aspect ratio of the trench to be finally obtained is relatively large, the epitaxial layer per one time is obtained. It is possible to reduce the aspect ratio of the trench at the time of embedding, and to effectively avoid the generation of voids in the epitaxial layer embedded in the trench.

本発明実施形態の半導体基板の製造方法を示す工程図である。It is process drawing which shows the manufacturing method of the semiconductor substrate of embodiment of this invention.

符号の説明Explanation of symbols

１０ 半導体基板
１１ 第１エピタキシャル層
１２ 第２エピタキシャル層
１３ 基板本体
１４ 第1トレンチ
１６ 第３エピタキシャル層
１７ 第２トレンチ
１８ 第４エピタキシャル層
DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 11 1st epitaxial layer 12 2nd epitaxial layer 13 Substrate body 14 1st trench 16 3rd epitaxial layer 17 2nd trench 18 4th epitaxial layer

Claims (2)

（ａ）基板本体(13)表面に第１エピタキシャル層(11)を成長させる工程と、
（ｂ）この第１エピタキシャル層(11)を部分的にエッチングして複数の第１トレンチ(14)を形成する工程と、
（ｃ）前記複数の第１トレンチ(14)の内部全体及び前記複数の第１トレンチ(14)以外の前記第１エピタキシャル層(11)の表面に第２エピタキシャル層(12)を成長させる工程と、
（ｄ）前記第２エピタキシャル層(12)を研磨して前記第１エピタキシャル層(11)の表面を露出させるとともに前記複数の第１トレンチ(14)の内部全体に埋め込まれた前記第２エピタキシャル層(12)の上面を平坦にする工程と、
（ｅ）平坦にされた前記第２エピタキシャル層(12)の上面と露出した前記第１エピタキシャル層(11)の表面に前記第１エピタキシャル層(11)と同一組成の第３エピタキシャル層(16)を更に成長させる工程と、
（ｆ）この第３エピタキシャル層(16)の前記複数の第１トレンチ(14)に対応する部分をエッチングして複数の第２トレンチ(17)を形成することにより前記複数の第１トレンチ(14)を延長させる工程と、
（ｇ）前記複数の第２トレンチ(17)の内部全体及び前記複数の第２トレンチ(17)以外の前記第３エピタキシャル層(16)の表面に第４エピタキシャル層(18)を更に成長させる工程と、
（ｈ）前記第４エピタキシャル層(18)を研磨して前記第３エピタキシャル層(16)の表面を露出させるとともに前記複数の第２トレンチ(17)の内部全体に埋め込まれた前記第４エピタキシャル層(18)の上面を平坦にする工程と
を含む半導体基板の製造方法。 (A) growing a first epitaxial layer (11) on the surface of the substrate body (13);
(B) partially etching the first epitaxial layer (11) to form a plurality of first trenches (14);
(C) growing a second epitaxial layer (12) on the entire interior of the plurality of first trenches (14) and on the surface of the first epitaxial layer (11) other than the plurality of first trenches (14); ,
(D) polishing the second epitaxial layer (12) to expose the surface of the first epitaxial layer (11), and the second epitaxial layer embedded in the entire interior of the plurality of first trenches (14). Flattening the upper surface of (12);
(E) a third epitaxial layer (16) having the same composition as the first epitaxial layer (11) on the flattened upper surface of the second epitaxial layer (12) and the exposed surface of the first epitaxial layer (11); Further growing the process,
(F) A portion of the third epitaxial layer (16) corresponding to the plurality of first trenches (14) is etched to form a plurality of second trenches (17), thereby forming the plurality of first trenches (14 )
(G) A step of further growing a fourth epitaxial layer (18) on the entire interior of the plurality of second trenches (17) and on the surface of the third epitaxial layer (16) other than the plurality of second trenches (17). When,
(H) The fourth epitaxial layer (18) is polished to expose the surface of the third epitaxial layer (16) and embedded in the entire interior of the plurality of second trenches (17). And (18) a step of flattening the upper surface of the semiconductor substrate. 工程（ｇ）の後に、工程（ｄ）から工程（ｇ）までを１回又は２回以上繰り返す請求項１記載の半導体基板の製造方法。
The method of manufacturing a semiconductor substrate according to claim 1, wherein the step (d) to the step (g) are repeated once or twice or more after the step (g).
JP2005293087A 2005-10-06 2005-10-06 Method of manufacturing semiconductor substrate Pending JP2007103747A (en)

Priority Applications (13)

Application Number Priority Date Filing Date Title
JP2005293087A JP2007103747A (en) 2005-10-06 2005-10-06 Method of manufacturing semiconductor substrate
CN2009102169066A CN101853786B (en) 2005-10-06 2006-10-05 Method for manufacturing semiconductor substrate
KR1020107000759A KR100950232B1 (en) 2005-10-06 2006-10-05 Method for manufacturing semiconductor substrate
DE112006002626T DE112006002626B4 (en) 2005-10-06 2006-10-05 Semiconductor substrate and method for its production
KR1020087009941A KR100997153B1 (en) 2005-10-06 2006-10-05 Semiconductor substrate and method for manufacturing the same
DE112006004215T DE112006004215B4 (en) 2005-10-06 2006-10-05 Method for producing a semiconductor substrate
PCT/JP2006/319933 WO2007040255A1 (en) 2005-10-06 2006-10-05 Semiconductor substrate and method for manufacturing same
US12/089,497 US20090273102A1 (en) 2005-10-06 2006-10-05 Semiconductor Substrate and Method for Manufacturing the Same
CN200680036884XA CN101278377B (en) 2005-10-06 2006-10-05 Semiconductor substrate and method for manufacturing same
US12/964,141 US8835276B2 (en) 2005-10-06 2010-12-09 Method for manufacturing semiconductor substrate
US14/448,370 US20140342535A1 (en) 2005-10-06 2014-07-31 Method for manufacturing semiconductor substrate
US14/448,347 US9034721B2 (en) 2005-10-06 2014-07-31 Method for manufacturing semiconductor substrate
US14/448,372 US8956947B2 (en) 2005-10-06 2014-07-31 Method for manufacturing semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005293087A JP2007103747A (en) 2005-10-06 2005-10-06 Method of manufacturing semiconductor substrate

Publications (1)

Publication Number Publication Date
JP2007103747A true JP2007103747A (en) 2007-04-19

Family

ID=38030375

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005293087A Pending JP2007103747A (en) 2005-10-06 2005-10-06 Method of manufacturing semiconductor substrate

Country Status (2)

Country Link
JP (1) JP2007103747A (en)
CN (1) CN101278377B (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100330786A1 (en) * 2009-06-24 2010-12-30 Siltronic Ag Method For Producing An Epitaxially Coated Semiconductor Wafer
JP2015023166A (en) * 2013-07-19 2015-02-02 株式会社東芝 Semiconductor device
US9093474B2 (en) 2012-02-27 2015-07-28 Kabushiki Kaisha Toshiba Electric power semiconductor device and manufacturing method of the same
JP2016171134A (en) * 2015-03-11 2016-09-23 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method of the same

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102891093A (en) * 2011-07-19 2013-01-23 上海华虹Nec电子有限公司 Method for measuring longitudinal distribution of epitaxial layer resistors in super junction depth trenches
CN103091555A (en) * 2011-10-28 2013-05-08 上海华虹Nec电子有限公司 Method for measuring silicon epitaxy resistivity lateral distribution inside super junction deep groove
US9230917B2 (en) * 2013-05-29 2016-01-05 Infineon Technologies Dresden Gmbh Method of processing a carrier with alignment marks
CN106158626A (en) * 2015-03-30 2016-11-23 中芯国际集成电路制造(上海)有限公司 Power device and forming method thereof
CN108231742A (en) * 2017-12-29 2018-06-29 吉林华微电子股份有限公司 Photo-etching mark alignment methods and chip preparation method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003273355A (en) * 2002-03-18 2003-09-26 Toshiba Corp Semiconductor element and method for manufacturing the same
JP2005142335A (en) * 2003-11-06 2005-06-02 Fuji Electric Holdings Co Ltd Method of manufacturing semiconductor element
JP2007116190A (en) * 2006-12-12 2007-05-10 Toshiba Corp Semiconductor element and its manufacturing method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003273355A (en) * 2002-03-18 2003-09-26 Toshiba Corp Semiconductor element and method for manufacturing the same
JP2005142335A (en) * 2003-11-06 2005-06-02 Fuji Electric Holdings Co Ltd Method of manufacturing semiconductor element
JP2007116190A (en) * 2006-12-12 2007-05-10 Toshiba Corp Semiconductor element and its manufacturing method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100330786A1 (en) * 2009-06-24 2010-12-30 Siltronic Ag Method For Producing An Epitaxially Coated Semiconductor Wafer
US8551870B2 (en) * 2009-06-24 2013-10-08 Siltronic Ag Method for producing an epitaxially coated semiconductor wafer
US9093474B2 (en) 2012-02-27 2015-07-28 Kabushiki Kaisha Toshiba Electric power semiconductor device and manufacturing method of the same
US9136351B2 (en) 2012-02-27 2015-09-15 Kabushiki Kaisha Toshiba Electric power semiconductor device and manufacturing method of the same
JP2015023166A (en) * 2013-07-19 2015-02-02 株式会社東芝 Semiconductor device
JP2016171134A (en) * 2015-03-11 2016-09-23 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method of the same

Also Published As

Publication number Publication date
CN101278377A (en) 2008-10-01
CN101278377B (en) 2012-12-19

Similar Documents

Publication Publication Date Title
KR100950232B1 (en) Method for manufacturing semiconductor substrate
JP4865290B2 (en) Manufacturing method of semiconductor substrate
JP2007103747A (en) Method of manufacturing semiconductor substrate
JP5015440B2 (en) Manufacturing method of semiconductor substrate
KR100844481B1 (en) Method for manufacturing semiconductor device
JP4879545B2 (en) Manufacturing method of semiconductor substrate
JP5636203B2 (en) Semiconductor substrate, semiconductor device, and method for manufacturing semiconductor substrate
JP5556851B2 (en) Manufacturing method of semiconductor device
JP4788519B2 (en) Manufacturing method of semiconductor substrate
JP2005142335A (en) Method of manufacturing semiconductor element
JP5397253B2 (en) Manufacturing method of semiconductor substrate
JP5566987B2 (en) Manufacturing method of semiconductor substrate
JP2009231308A (en) Method of manufacturing semiconductor device having super junction structure

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080624

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20120417