JP5397253B2 - Manufacturing method of semiconductor substrate - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor substrate in which a cavity used as an alignment mark is provided in a desired region.

  Conventionally, a super junction MOSFET (hereinafter referred to as SJ-MOSFET) having a PN column structure is known as a power device that achieves both high breakdown voltage and low on-resistance. The SJ-MOSFET can reduce the on-resistance by reducing the PN column pitch width, and as an effective manufacturing method thereof, a PN column structure is formed by growing a buried epitaxial layer after forming a trench in the substrate. There is a method of forming.

  However, in this manufacturing method, since the single crystal semiconductor layer is embedded without leaving a shape in the trench formed in the substrate, it is difficult to form an alignment mark with a PN column pattern required in the device manufacturing process. is there. For this reason, it is necessary to separately add a dedicated process for forming the alignment mark, and there is a problem that the manufacturing process of the semiconductor substrate is complicated and the cost is increased.

  Therefore, the buried epitaxial layer is formed in the trench of the PN column region while making the trench width of the alignment mark region smaller than that of the PN column region so that voids (cavities) remain in the trench of the alignment mark region. Japanese Patent Application Laid-Open No. H10-228707 proposes a method for performing this.

  As another method, Patent Document 2 proposes a method in which the trench width of the alignment mark region is made larger than that of the PN column region to leave a deep groove shape in the alignment mark region.

JP 2008-41942 A JP 2007-288213 A

  However, in Patent Document 1, since the trench width of the alignment mark region is made smaller than the trench width of the PN column region, the width of the alignment mark thus produced is inevitably smaller than ½ of the PN column pitch width. For this reason, the width of the alignment mark cannot be designed freely. Along with this, there is a restriction that alignment marks suitable for the manufacturing apparatus cannot be freely formed.

  Accordingly, it is conceivable to increase the trench width of the alignment mark region. However, since the trench width of the PN column region is wider than the trench width of the alignment mark region, if the trench width of the alignment mark region is widened, the PN column region becomes a meaningless wide region.

  Further, in Patent Document 2, since a deep groove-shaped alignment mark remains on the substrate, there is a concern that resist coating spots and resist residues may be generated in the device manufacturing process due to the deep groove-shaped alignment mark.

  In view of the above points, the present invention eliminates the need for a separate process for forming an alignment mark, allows the size of the alignment mark to be set freely, and further causes defects such as resist coating spots and resist residues in the device manufacturing process. It is an object of the present invention to provide a method for manufacturing a semiconductor substrate that does not generate the problem.

  In order to achieve the above object, according to the first aspect of the present invention, there is provided a step of preparing a substrate (19) made of a single crystal semiconductor, and a thickness direction of the substrate (19) from the surface (20) of the substrate (19). A method for manufacturing a semiconductor substrate, comprising: a step of forming a trench (14, 16) extending in a trench; and a step of epitaxially growing a single crystal semiconductor layer (21) in the trench (14, 16). 14 and 16), different trenches are simultaneously formed in the desired region (15) of the surface (20) of the substrate (19) and the region (13) other than the desired region.

  In the epitaxial growth step, a part of the single crystal semiconductor layer (21) is completely buried in the trench (14) in the region (13) other than the desired region, and at the same time, in the trench (16) in the desired region (15). A first epitaxial growth step embedded in the trench (16) so that the space outside the trench (16) in the desired region (15) is connected, and after the first epitaxial growth step, the desired region (15) A two-stage epitaxial growth process including a second epitaxial growth process in which a remaining portion of the single crystal semiconductor layer (21) is formed so that a cavity (22) as an alignment mark remains in the trench (16) is characterized. And

  According to this, first, since different trenches (14, 16) are simultaneously formed in each region (13, 15), a dedicated process for forming the cavity (22) serving as an alignment mark is not added separately. Can be good. In this case, the size of the cavity (22) to be formed later in the trench (16) can be freely designed by adjusting the width of the trench (16) formed in the desired region (15).

  Further, since the trench (16) in the desired region (15) is not completely filled in the first epitaxial growth step, the thickness of the single crystal semiconductor layer (21) formed on the wall surface of the trench (16) is adjusted. By doing so, the size of the cavity (22) formed in a later step can be freely adjusted.

  Further, since the second epitaxial growth step is performed so that the cavity (22) remains in the trench (16) of the desired region (15) in the second epitaxial growth step, the growth condition of the single crystal semiconductor layer (21) is increased. The size of the cavity (22) can be adjusted accordingly.

  In addition, since the single crystal semiconductor layer (21) is buried in each trench (14, 16) by the second epitaxial growth process, problems such as resist coating spots and resist residues are not generated by the recesses in the trench (14, 16). Can be.

  As in the second aspect of the invention, in the step of forming the trenches (14, 16), the desired region (15) is used as the alignment mark region, and the region (13) other than the desired region is used as the surface ( The trenches (14, 16) may be formed as PN column regions in which the substrates (19) and the single crystal semiconductor layers (21) are alternately arranged in the plane direction 20).

  Then, as in the third aspect of the invention, in the step of forming the trench (14, 16), the trench width (16) formed in the desired region (15) as a different trench (14, 16) ( It is preferable to form trenches (14, 16) where W1) is wider than the trench width (W2) of the trench (14) formed in the region (13) other than the desired region.

  In the step of forming the trench (14, 16) as in the invention described in claim 4, the trench depth of the trench (16) formed in the desired region (15) as a different trench (14, 16) is formed. It is also possible to form trenches (14, 16) deeper than the trench depth of trench (14) formed in region (13) other than the desired region.

  On the other hand, in the step of forming the trench (14, 16) as in the invention described in claim 5, as the different trench (14, 16), of the wall surfaces of the trench (16) formed in the desired region (15) The growth rate of the single crystal semiconductor layer (21) on the side surface (24) perpendicular to the surface (20) of the substrate (19) is such that the substrate (of the wall surface of the trench (14) formed in the region (13) other than the desired region ( It is also possible to form trenches (14, 16) slower than the growth rate of the single crystal semiconductor layer (21) on the side surface (25) perpendicular to the surface (20) of 19).

  On the other hand, as in the invention according to claim 6, in the step of forming the trench (14, 16), among the wall surfaces of the trench (16) formed in the desired region (15) as different trenches (14, 16). The surface orientation of the side surface (24) perpendicular to the surface (20) of the substrate (19) is the surface (20) of the substrate (19) among the wall surfaces of the trench (14) formed in the region (13) other than the desired region. A trench (14, 16) different from the plane orientation of the right side surface (25) may be formed.

  In the epitaxial growth step, the growth rate of the single crystal semiconductor layer (21) in the second epitaxial growth step is the same as that of the single crystal semiconductor layer (21) in the first epitaxial growth step. It is preferably faster than the growth rate.

  In the invention according to claim 8, in the epitaxial growth step, the growth temperature of the single crystal semiconductor layer (21) in the second epitaxial growth step is higher than the growth temperature of the single crystal semiconductor layer (21) in the first epitaxial growth step. Is preferably high.

  In addition, the code | symbol in the bracket | parenthesis of each means described in this column and the claim shows the correspondence with the specific means as described in embodiment mentioned later.

1 is a plan view of a semiconductor substrate according to a first embodiment of the present invention. It is the A section enlarged view of FIG. It is the B section enlarged view of FIG. FIG. 4 is a cross-sectional view taken along the line C-C ′ of FIG. 3. It is the figure which showed the manufacturing process of the semiconductor substrate shown by FIGS. It is the figure which showed the manufacturing process following FIG. It is the figure which showed the manufacturing process of the semiconductor substrate which concerns on 2nd Embodiment of this invention. FIG. 8 is a diagram illustrating a manufacturing process subsequent to FIG. 7. It is a top view of the semiconductor substrate which concerns on 3rd Embodiment of this invention. It is the D section enlarged view of FIG. It is the E section enlarged view of FIG. It is F-F 'sectional drawing of FIG. It is the figure which showed the manufacturing process of the semiconductor substrate shown by FIGS. It is the figure which showed the manufacturing process following FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a plan view of a semiconductor substrate 10 according to the present embodiment. FIG. 2 is an enlarged view of a portion A in FIG.

  As shown in FIG. 1, the semiconductor substrate 10 has a plate shape configured as a semiconductor wafer. A plurality of chips 11 are formed on the single semiconductor substrate 10. The chip 11 is a unit that is divided into individual parts by dicing and cutting the semiconductor substrate 10.

  Further, as shown in FIG. 2, each chip 11 is partitioned by a scribe line 12. The scribe line 12 extends in an arbitrary x direction and a y direction perpendicular to the x direction on one surface of the semiconductor substrate 10. A rectangular area surrounded by such scribe lines 12 is an area of one chip 11, and a PN column area 13 is provided in the area of this one chip 11. A plurality of trenches 14 are formed in the PN column region 13.

  The scribe line 12 is provided with an alignment mark region 15 in which an alignment mark for recognizing the position of the PN column region 13 is formed. In the present embodiment, alignment mark regions 15 are provided on both the scribe line 12 extending in the x direction and the scribe line 12 extending in the y direction. This alignment mark region 15 is a region to be diced, and a plurality of trenches 16 are formed.

  FIG. 3 is an enlarged view of a portion B in FIG. As shown in this figure, the PN column region 13 is provided with a plurality of trenches 14 extending in the x direction in the y direction. The alignment mark region 15 provided in the scribe line 12 extending in the y direction is provided with a plurality of trenches 16 extending in the x direction in the y direction.

  When the trench width of the trench 16 formed in the alignment mark region 15 is W1, and the trench width of the trench 14 formed in the PN column region 13 is W2, W1> W2. That is, the trench width W 1 of the trench 16 formed in the alignment mark region 15 is wider than the trench width W 2 of the trench 14 formed in the PN column region 13.

  The “trench width” refers to the length in the direction perpendicular to the longitudinal direction of each of the trenches 14 and 16 in the surface direction of the surface of the semiconductor substrate 10. In addition, in the alignment mark region 15 provided in the scribe line 12 extending in the x direction, a plurality of trenches 16 extending in the y direction are provided in the x direction. Also in this case, the trench width W 1 of the trench 16 formed in the alignment mark region 15 is wider than the trench width W 2 of the trench 14 formed in the PN column region 13.

  4 is a cross-sectional view taken along the line C-C ′ of FIG. 3. As shown in this figure, the semiconductor substrate 10 is formed based on a substrate 19 in which an N type layer 18 made of single crystal silicon is formed on an N + type substrate 17 made of, for example, single crystal silicon. ing. The surface of the N-type layer 18 becomes the surface 20 of the substrate 19 (that is, the semiconductor substrate 10). Each trench 14, 16 extends from the surface 20 of the substrate 19 in the thickness direction of the substrate 19 so as to reach the N + type substrate 17.

  In the alignment mark region 15, a P-type single crystal semiconductor made of single crystal silicon so that a space inside the trench 16 and a space outside the trench 16 are separated in each trench 16 having a trench width W 1. Layer 21 is embedded. For this reason, a cavity 22 is provided in the trench 16. The cavity 22 functions as an alignment mark in an infrared mask aligner or the like.

  On the other hand, in the PN column region 13, the P-type single crystal semiconductor layer 21 is completely buried in each trench 14 having a trench width W2. Thus, in the PN column region 13, the column-shaped N-type layers 18 and the column-shaped P-type single crystal semiconductor layers 21 are alternately arranged on the N + -type substrate 17 in the plane direction of the N + -type substrate 17. SJ (Super Junction) structure. That is, the substrate 19 (N-type layer 18) and the P-type single crystal semiconductor layer 21 are alternately arranged in the plane direction of the surface 20 of the substrate 19. The above is the overall configuration of the semiconductor substrate 10 according to the present embodiment.

  Next, a method for manufacturing the semiconductor substrate 10 will be described with reference to FIGS. First, in the step shown in FIG. 5A, a wafer-like substrate 19 is prepared. The substrate 19 is obtained by epitaxially growing an N-type layer 18 made of single crystal silicon on an N + type substrate 17 made of single crystal silicon and flattening the surface.

Subsequently, in the step shown in FIG. 5B, a mask 23 such as SiO ₂ is formed on the N-type layer 18. This mask 23 can be formed, for example, by heat-treating the surface of the N-type layer 18 in an oxygen atmosphere. Then, a part of the mask 23 is opened so that the regions where the trenches 14 and 16 are to be formed in the N-type layer 18 are exposed from the mask 23.

  At this time, by adjusting the opening width of the mask 23 in the alignment mark region 15 and the opening width of the mask 23 in the PN column region 13, the widths of the trenches 14 and 16 in the regions 13 and 15 are adjusted. As described above, a part of the mask 23 is opened so that the trench width W1 of the trench 16 in the alignment mark region 15 is wider than the trench width W2 of the trench 14 in the PN column region 13.

  Thereafter, in the step shown in FIG. 5C, the substrate 19 is etched using the mask 23. As a result, different trenches 14 and 16 are simultaneously formed in the substrate 19 in the alignment mark region 15 and the PN column region 13. Each trench 14, 16 reaches the N + type substrate 17. “Different trenches 14, 16” refers to trenches 14, 16 having different trench widths. As described above, the trench width W 1 of the trench 16 in the alignment mark region 15 is larger than the trench width W 2 of the trench 14 in the PN column region 13. It means wide.

  The steps shown in FIGS. 5B and 5C correspond to the steps of forming the trenches 14 and 16.

  6A, a part of the single crystal semiconductor layer 21 is completely embedded in the trench 14 in the PN column region 13, and at the same time, the space in the trench 16 in the alignment mark region 15 and the trench 16 A first epitaxial growth step of burying a part of the single crystal semiconductor layer 21 in the trench 16 is performed so as to be connected to the outside space.

  In the first epitaxial growth step, the P-type single crystal semiconductor layer 21 is formed under a reaction law condition of, for example, 950 ° C. or lower. The reaction law condition is that the single crystal semiconductor layer 21 grows on the walls of the trenches 14 and 16 by reducing the supply of the reaction gas for forming the single crystal semiconductor layer 21 and lowering the growth temperature to 950 ° C. or lower. It is an easy condition.

  Specifically, a substrate 19 having trenches 14 and 16 formed therein is disposed in the chamber of the epitaxial growth apparatus. In addition, the temperature in the chamber of the epitaxial growth apparatus is raised, the halide gas and the silicon source gas are supplied in necessary amounts, the inside of the chamber is set to a reduced pressure environment, and the hydrogen gas is supplied into the chamber.

Here, for example, SiH ₂ Cl ₂ (dichlorosilane: DCS) is used as a silicon source gas, and a gas mixed with, for example, hydrogen chloride (HCl) is used as a halide gas, and low-pressure epitaxial growth is performed. The growth temperature is 950 ° C. or less, the growth pressure is, for example, 40 Torr, the flow rate of DCS = 0.1 slm, the flow rate of hydrogen gas (H ₂ ) = 30 slm, and the flow rate of hydrogen chloride gas (HCl) = 0.5 slm. The growth rate on the main surface of the substrate 19 under these conditions is about several tens to 100 nm / min. As a result, chlorine atoms (Cl atoms) adhere to the silicon surface in the openings of the trenches 14 and 16, so that silicon grows in the trenches 14 and 16 without closing the openings of the trenches 14 and 16.

  By performing the first epitaxial growth step under this reaction rule condition, a part of the single crystal semiconductor layer 21 is completely buried in the trench 14 having the trench width W2 narrower than the trench width W1 in the alignment mark region 15. On the other hand, since the trench width W1 in the alignment mark region 15 is wider than the trench width W2 in the PN column region 13, the embedding of the single crystal semiconductor layer 21 is incomplete.

  “Incomplete burying” refers to a state in which a gap remains in the trench 16 even if a part of the single crystal semiconductor layer 21 is formed. In other words, it can be said that the single crystal semiconductor layer 21 formed in the trench 16 in the alignment mark region 15 is open, and indicates a state in which the space inside and outside the trench 16 is connected.

  6A, the single crystal semiconductor layer 21 is formed on the wall surface of the trench 16 in the alignment mark region 15, the entire interior of the trench 14 in the PN column region 13, and the surface 20 of the substrate 19. As shown in FIG. Form part.

  Next, in the step shown in FIG. 6B, a second epitaxial growth step of forming the remaining portion of the single crystal semiconductor layer 21 so that the cavity 22 as the alignment mark remains in the trench 16 in the alignment mark region 15 is performed. Do.

  In this second epitaxial growth step, for example, the P-type single crystal semiconductor layer 21 is formed under a supply rule condition of 1000 ° C. or higher. The supply rule condition is that the supply of the reaction gas for forming the single crystal semiconductor layer 21 is increased and the growth temperature is set to 1000 ° C. or higher so that the single crystal semiconductor layer 21 grows on the surface 20 side of the substrate 19. It is a condition to make it faster.

  Specifically, the growth temperature is set higher than that in the first epitaxial growth step (950 ° C. or lower), the halide gas flow rate is lower than that in the first epitaxial growth step, the growth pressure and the DCS flow rate. Or higher than during the first epitaxial growth step. Therefore, the growth rate on the surface 20 side of the substrate 19 can be high.

  As a result, a large amount of growth gas is supplied to the surface 20 side of the substrate 19, so that the growth rate of the single crystal semiconductor layer 21 on the surface 20 side of the substrate 19 is higher than the growth rate of the single crystal semiconductor layer 21 on the bottom side in the trench 16. The rate goes up. For this reason, since the opening part of the trench 16 is closed by the single crystal semiconductor layer 21 before the space in the trench 16 is completely filled, the cavity 22 is left in the trench 16. This cavity 22 is used as an alignment mark.

  Thus, since the growth rate on the surface 20 side of the substrate 19 is increased, the single crystal semiconductor layer 21 is also grown on the surface 20 of the substrate 19. In this case, the recess due to the trench 14 of the single crystal semiconductor layer 21 formed in the trench 14 of the PN column region 13 by the first epitaxial growth process is planarized. In addition, for the trench 16 that was opened in the first epitaxial growth step, the opening of the trench 16 is closed by the single crystal semiconductor layer 21. Accordingly, the entire single crystal semiconductor layer 21 on the surface 20 of the substrate 19 is planarized.

  The steps shown in FIGS. 6A and 6B correspond to the step of epitaxially growing the single crystal semiconductor layer 21 in the trenches 14 and 16.

  In the step shown in FIG. 6C, the single crystal semiconductor layer 21 on the surface 20 of the substrate 19 is removed by a planarization polishing method such as CMP polishing so that the surface 20 of the substrate 19 is exposed. Thus, the semiconductor substrate 10 shown in FIGS. 1 to 4 is completed. The wafer-like semiconductor substrate 10 manufactured in this way is divided into individual devices by forming devices such as MOSFETs in the respective regions of the chip 11 and dicing cut along the scribe lines 12.

  As described above, in this embodiment, the trenches 14 and 16 in which the trench width W1 of the alignment mark region 15 is wider than the trench width W2 of the PN column region 13 are simultaneously formed in the alignment mark region 15 and the PN column region 13. It is a feature. Thereby, when manufacturing the semiconductor substrate 10, the process for exclusive use for forming the cavity 22 used as an alignment mark can be made unnecessary.

  Then, a first epitaxial growth step of forming a part of the single crystal semiconductor layer 21 so that a gap remains in the trench 16 of the alignment mark region 15 while completely embedding the single crystal semiconductor layer 21 in the trench 14 of the PN column region 13. After that, a second epitaxial growth step is performed in which the trench 16 is closed with the single crystal semiconductor layer 21 so that the cavity 22 remains in the trench 16 in the alignment mark region 15.

  Thereby, the size of the cavity 22 can be freely adjusted by adjusting the thickness of the single crystal semiconductor layer 21 formed on the wall surface of the trench 16 so that a gap remains in the trench 16 of the alignment mark region 15. In addition, a cavity 22 serving as an alignment mark can be left in the trench 16 in the alignment mark region 15.

  For example, the size of the cavity 22 in the direction parallel to the surface 20 of the substrate 19 is W3. Further, at the position where the cavity 22 is formed in the trench 16, the film thickness (growth amount) of the single crystal semiconductor layer 21 in the first epitaxial growth step is set to W4, and the film thickness of the single crystal semiconductor layer 21 in the second epitaxial growth step. Let (growth amount) be W5. In this case, the size W3 of the cavity 22 is W3 = W1-W4-W5. That is, the size of the completed cavity 22 (alignment mark) can be freely designed from the trench width W1 and the epitaxial growth amounts W4 and W5.

  Here, the “size of the cavity 22” can be defined as a length in a direction parallel to the surface 20 of the substrate 19 (semiconductor substrate 10), a spatial volume of the cavity 22, or the like.

  Since the trench width W1 of the trench 16 is wider than the trench width W2 of the trench 14 in the PN column region 13, the width of the cavity 22 is necessarily smaller than ½ of the PN column pitch width. There is no restriction on the size design. Further, it is not necessary to increase the trench width W2 of the trench 14 in the PN column region 13 in order to increase the size of the cavity 22. Therefore, alignment marks suitable for the device manufacturing apparatus can be freely formed.

  Since the single crystal semiconductor layer 21 is buried in each of the trenches 14 and 16 by the second epitaxial growth process, resist coating spots and resist residues are generated in the device manufacturing process due to the recesses in the trenches 14 and 16. You can avoid it.

  As for the correspondence between the description of the present embodiment and the description of the claims, the alignment mark area 15 corresponds to the “desired area” in the claims, and the PN column area 13 corresponds to “ This corresponds to “an area other than the desired area”. Further, the substrate 19 in which the N-type layer 18 is formed on the N + -type substrate 17 corresponds to “a substrate made of a single crystal semiconductor” in the claims.

(Second Embodiment)
In the present embodiment, parts different from the first embodiment will be mainly described. This embodiment is characterized in that the trench depth of the trench 16 formed in the alignment mark region 15 is deeper than the trench depth of the trench 14 formed in the PN column region 13. Hereinafter, the manufacturing process of the semiconductor substrate 10 according to the present embodiment will be described with reference to FIGS.

  First, in the step shown in FIG. 7A, the substrate 19 is prepared as in the step shown in FIG. In the step shown in FIG. 7B, a mask 23 is formed on the surface 20 of the substrate 19 as in the step shown in FIG.

  Subsequently, in the step shown in FIG. 7C, trenches 14 and 16 are formed in the regions 13 and 15, respectively. In this step, the substrate 19 is etched by anisotropic etching (RIE) or the like using the difference in etching rate depending on the opening width of the mask 23. Thereby, the trench 16 in the alignment mark region 15 having a wide opening width, that is, a wide trench width W1, reaches the N + type substrate 17, while the trench 14 in the PN column region 13 having a narrow opening width, that is, a narrow trench width W2, is formed in the N + type substrate. It is shallower than the trench 16 without reaching 17.

  Therefore, in this step, trenches 14 and 16 in which the trench depth of trench 16 formed in alignment mark region 15 is deeper than the trench depth of trench 14 formed in PN column region 13 are formed.

  Thereafter, in the step shown in FIG. 8A, the first epitaxial growth step is performed in the same manner as the step shown in FIG. 6A. In the step shown in FIG. 8B, the step shown in FIG. Similar to the step, the second epitaxial growth step is performed. 8C, the single crystal semiconductor layer 21 on the surface 20 is polished so that the surface 20 of the substrate 19 is exposed, as in the step shown in FIG. 6C. Thus, the semiconductor substrate 10 according to this embodiment is completed.

  As described above, the trench 16 in the alignment mark region 15 can be formed deeper than the trench 14 in the PN column region 13.

(Third embodiment)
In the present embodiment, parts different from the first and second embodiments will be mainly described. In each of the above embodiments, the growth temperature and growth rate of the second epitaxial growth step are set higher than the growth temperature and growth rate of the first epitaxial growth step. However, in this embodiment, the side surface of the trench 16 in the alignment mark region 15 is used. Is slower than the growth rate of the side surface of the trench 14 in the PN column region 13 so that the single crystal semiconductor layer 21 is not completely buried in the trench 16 in the alignment mark region 15. .

  Therefore, in this embodiment, the plane orientation of the semiconductor substrate 10 is an important parameter. Therefore, as shown in FIG. 9, the orientation flat plane orientation of the semiconductor substrate 10 according to the present embodiment is the (111) plane, and the plane orientation of one surface of the semiconductor substrate 10 is the (110) plane. .

  FIG. 10 is an enlarged view of a portion D in FIG. As shown in this figure, in the present embodiment, alignment mark regions 15 are provided on the scribe lines 12 extending in the y direction. That is, this is an example in the case where there is one alignment mark for one chip 11. A plurality of trenches 16 extending in the x direction are formed in the alignment mark region 15.

  Since the direction in which the trench 16 in the alignment mark region 15 extends on the surface 20 of the substrate 19 is parallel to the orientation flat, the side surface 24 perpendicular to the surface 20 of the substrate 19 among the wall surfaces of the trench 16 in the alignment mark region 15 is 111) plane.

  Here, since there are four side surfaces of the wall surface of the trench 16 in the x direction and the y direction, the “side surface 24 of the trench 16” is parallel to the longitudinal direction of the trench 16 on the surface 20 of the substrate 19. A surface perpendicular to the surface 20 is indicated.

  On the other hand, in the PN column region 13, a plurality of trenches 14 are formed to be inclined at a predetermined angle with respect to the x direction. The predetermined angle is 126 ° with respect to the x-axis as shown in FIG. For this reason, the side surface 25 perpendicular to the surface 20 of the substrate 19 among the wall surfaces of the trench 14 in the PN column region 13 is a (100) surface. The “side surface 25 of the trench 14” corresponds to a surface parallel to the longitudinal direction of the trench 14 on the surface 20 of the substrate 19 and perpendicular to the surface 20, as described above.

  As described above, when the plane orientations of the side surfaces 24 and 25 of the trenches 14 and 16 are different, the growth rate of the single crystal semiconductor layer 21 on the side surfaces 24 and 25 is different. Specifically, the growth rate of the (100) plane is faster than the growth rate of the (111) plane. Therefore, even if the trench 14 in the PN column region 13 is completely filled with the single crystal semiconductor layer 21, the trench 16 in the alignment mark region 15 is not completely filled.

  In this embodiment, the trench width W1 of the trench 16 formed in the alignment mark region 15 and the trench width W2 of the trench 14 formed in the PN column region 13 have the same width (W1 = W2). .

  12 is a cross-sectional view taken along the line F-F ′ of FIG. 11. When the above plane orientation is expressed as a cross-sectional view, as shown in FIG. 12, the surface 20 of the substrate 19 is a (110) plane. Further, the side surface 24 of the trench 16 in the alignment mark region 15 is a (111) plane, and the side surface 25 of the trench 14 in the PN column region 13 is a (100) plane. The semiconductor substrate 10 has the same structure as that shown in FIG. 4 except that the relationship of the trench width is W1 = W2 and the plane orientation.

  Next, a method for manufacturing the semiconductor substrate 10 according to the present embodiment will be described with reference to FIGS.

  First, in the step shown in FIG. 13A, a wafer-like substrate 19 is prepared. In this step, the N-type layer 18 is epitaxially grown so that the surface of the N-type layer 18, that is, the surface 20 of the substrate 19 is a (110) plane.

  In the step shown in FIG. 13B, a mask 23 is formed on the N-type layer 18 as in the step shown in FIG. Here, the predetermined region of the mask 23 is opened so that the side surface 24 of the trench 16 in the alignment mark region 15 becomes the (111) plane and the side surface 25 of the trench 14 in the PN column region 13 becomes the (100) surface. The trench widths W1 and W2 of the trenches 14 and 16 are the same.

  In the step shown in FIG. 13C, the substrate 19 is etched using the mask 23 as in the step shown in FIG. Thereby, trenches 14 and 16 having the same trench width but different plane orientations are formed in alignment mark region 15 and PN column region 13.

  In the step shown in FIG. 14A, the first epitaxial growth step is performed as in the step shown in FIG. As described above, since the growth rate of the single crystal semiconductor layer 21 differs according to the plane orientation, the trench 14 in the PN column region 13 is completely filled with the single crystal semiconductor layer 21, while the single crystal is formed in the trench 16 in the alignment mark region 15. Since the growth rate of the semiconductor layer 21 is slow, the single crystal semiconductor layer 21 is not completely filled in the trench 16 and becomes incomplete as described above.

  Thereafter, in the step shown in FIG. 14B, the second epitaxial growth step is performed as in the step shown in FIG. 6B. As a result, a cavity 22 is left in the trench 16 in the alignment mark region 15. 14C, the single crystal semiconductor layer 21 on the surface 20 of the substrate 19 is removed so that the surface 20 of the substrate 19 is exposed, as in the step shown in FIG. 6C. Thus, the semiconductor substrate 10 shown in FIGS. 9 to 12 is completed.

  As described above, by designating the plane orientations of the side surfaces 24 and 25 of the trenches 14 and 16, respectively, the trench 14 in the PN column region 13 is completely filled in the first epitaxial growth step, and the alignment mark region 15 It is possible to prevent the trench 16 from being completely filled. In this case, since the difference in growth rate between the side surfaces 24 and 25 is used, the trench widths may be the same, or W1> W2 as in the first embodiment.

(Other embodiments)
The method of manufacturing a semiconductor substrate shown in each of the above embodiments is an example, and the methods of the respective embodiments may be combined. In order to form the single crystal semiconductor layer 21 so that the cavity 22 remains in the trench 16 in the alignment mark region 15 in the second epitaxial growth step, the growth temperature of the single crystal semiconductor layer 21 in the second epitaxial growth step is set. In addition to raising the growth temperature of the single crystal semiconductor layer 21 in the first epitaxial growth step, the growth rate of the single crystal semiconductor layer 21 in the second epitaxial growth step is higher than the growth rate of the single crystal semiconductor layer 21 in the first epitaxial growth step. May be faster.

  In each of the above embodiments, the alignment mark region 15 is provided on the scribe line 12. However, this is an example, and the alignment mark region 15 may be located at another position of the scribe line 12. Further, the alignment mark region 15 may be located in the region of the chip 11. For example, as shown in FIG. 2, a PN column region 13 is provided in the region of the chip 11, but nothing is formed in the region around the PN column region 13. The region 15 may be provided. Furthermore, the extending direction of the trench 16 in the alignment mark region 15 shown in the above embodiments is also an example, and the extending direction can be freely set.

  In the above, the size of the cavity 22 functioning as the alignment mark is adjusted by the growth amount of the single crystal semiconductor layer 21. However, if the finished alignment mark has a desired size (especially width), the initial trench is determined from the epitaxial growth amount. What is necessary is just to determine the width.

  In each of the above embodiments, since the surface 20 of the substrate 19 is flattened by final polishing after the second epitaxial growth step, resist coating spots and resists are formed in the device manufacturing process using the semiconductor substrate 10. There is no fear of generating the rest. As described above, the surface 20 side of the substrate 19 is polished, but if the single crystal semiconductor layer 21 is formed thick on the surface 20 of the substrate 19 in the second epitaxial growth step, the trench on the surface of the single crystal semiconductor layer 21 is formed. The influence of the dents 14 and 16 can be reduced, and also in this case, there is no concern about the resist in the device process.

  Further, in each of the above embodiments, the polishing is performed after the second epitaxial growth step, but this polishing step may be necessary or unnecessary depending on how the semiconductor substrate 10 is used. Therefore, the polishing step is not essential and may not be performed.

  In the third embodiment, the plane orientation of the side surfaces 24 and 25 of the trenches 14 and 16 may be any plane orientation as long as the magnitude relationship of the epitaxial growth rate of the single crystal semiconductor layer 21 is established. It doesn't have to be limited.

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 13 PN column region 14, 16 Trench 15 Alignment mark region 19 Substrate 20 Surface of substrate 21 Single crystal semiconductor layer 22 Cavity

Claims (8)

Preparing a substrate (19) composed of a single crystal semiconductor;
Forming trenches (14, 16) extending from the surface (20) of the substrate (19) in the thickness direction of the substrate (19);
And a step of epitaxially growing a single crystal semiconductor layer (21) in the trench (14, 16).
In the step of forming the trenches (14, 16), different trenches are simultaneously formed in a desired region (15) of the surface (20) of the substrate (19) and a region (13) other than the desired region,
In the epitaxial growth step, a part of the single crystal semiconductor layer (21) is completely embedded in the trench (14) in the region (13) other than the desired region, and at the same time, the trench (16 in the desired region (15)). ) And a space outside the trench (16) in the desired region (15) so that the space outside the trench (16) is connected, and after the first epitaxial growth step, the desired epitaxial growth step is performed. And a second epitaxial growth step of forming a remaining portion of the single crystal semiconductor layer (21) so that a cavity (22) as an alignment mark remains in the trench (16) of the region (15). A method for manufacturing a semiconductor substrate, comprising:   In the step of forming the trenches (14, 16), the desired region (15) is used as an alignment mark region, and the region (13) other than the desired region is arranged in the plane direction of the surface (20) of the substrate (19). The method of manufacturing a semiconductor substrate according to claim 1, wherein the trench (14, 16) is formed as a PN column region in which the substrate (19) and the single crystal semiconductor layer (21) are alternately arranged. .   In the step of forming the trenches (14, 16), as the different trenches (14, 16), the trench width (W1) of the trench (16) formed in the desired region (15) is a region other than the desired region ( The method of manufacturing a semiconductor substrate according to claim 1 or 2, wherein a trench (14, 16) wider than a trench width (W2) of the trench (14) formed in 13) is formed.   In the step of forming the trench (14, 16), the trench (16) formed in the desired region (15) has a trench depth other than the desired region (13) as the different trench (14, 16). 4. The method of manufacturing a semiconductor substrate according to claim 1, wherein trenches (14, 16) deeper than a trench depth of the trench (14) to be formed are formed.   In the step of forming the trench (14, 16), the surface (20) of the substrate (19) among the wall surfaces of the trench (16) formed in the desired region (15) as the different trench (14, 16). The growth rate of the single crystal semiconductor layer (21) on the side surface (24) perpendicular to the surface of the substrate (19) of the wall surface of the trench (14) formed in the region (13) other than the desired region (20 5. A trench (14, 16) that is slower than the growth rate of the single-crystal semiconductor layer (21) on the side surface (25) perpendicular to) is formed according to claim 1. A method for manufacturing a semiconductor substrate.   In the step of forming the trench (14, 16), the surface (20) of the substrate (19) among the wall surfaces of the trench (16) formed in the desired region (15) as the different trench (14, 16). Of the side surface (25) perpendicular to the surface (20) of the substrate (19) among the wall surfaces of the trench (14) formed in the region (13) other than the desired region. 6. The method of manufacturing a semiconductor substrate according to claim 1, wherein trenches (14, 16) having different plane orientations are formed.   In the epitaxial growth step, the growth rate of the single crystal semiconductor layer (21) in the second epitaxial growth step is faster than the growth rate of the single crystal semiconductor layer (21) in the first epitaxial growth step. A method for manufacturing a semiconductor substrate according to any one of claims 1 to 6.   In the epitaxial growth step, the growth temperature of the single crystal semiconductor layer (21) in the second epitaxial growth step is higher than the growth temperature of the single crystal semiconductor layer (21) in the first epitaxial growth step. A method for manufacturing a semiconductor substrate according to any one of claims 1 to 7.

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