JP5541069B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device using an SON (Silicon-On-Nothing) structure as an alignment mark.

  In manufacturing a semiconductor device, there are a plurality of photolithography processes. In that case, various patterning alignments are performed based on the alignment marks of the recesses formed on the surface of the silicon wafer as the semiconductor substrate.

  As shown in FIG. 30, when an element having an arbitrary device structure (for example, a horizontal MOS transistor 104 surrounded by a diffusion isolation layer 105) is formed on the cavity 103 of the SON structure 102, a recess (trench 112a) is formed. ) Alignment mark 112 must be formed on the surface of the silicon wafer 101. Normally, the trench 112a of the alignment mark 112 is formed simultaneously with a fine hole trench (not shown) for forming the SON structure 102. In the figure, 105 is a diffusion separation layer, 106 is a silicon layer, 107 is a source layer, 108 is a drain layer, 109 is a gate electrode, 110 is a source electrode, and 111 is a drain electrode.

  FIG. 31 is a main part process diagram explaining the method for forming the SON structure. A fine hole trench 113 is formed in the silicon wafer 101 (FIG. 31A). Next, by annealing in a hydrogen atmosphere (reducing atmosphere) in an atmosphere of high temperature and reduced pressure, silicon on the surface of the hole trench 113 flows so as to minimize the surface energy, and the internal space 114 of the hole trench 113 is spherical. Transforms into Thereby, the silicon layer 115 is formed so as to gradually close the opening of the hole trench 113 (FIG. 31B). Furthermore, one large cavity 103 is formed by coupling the internal spaces 114 of the adjacent hole trenches 113 to each other. The SON structure 102 is formed by the cavity 103 and the silicon layer 116 closed on the cavity 103 (FIG. 31C). This closed silicon layer 116 is supported at a boundary portion 117 with the surrounding bulk substrate (silicon wafer 101 in which no cavity is formed). It is known that the SON structure 102 is formed in this way (see Patent Document 1).

  Simultaneously with the formation of the SON structure 102, the concave alignment mark 112 shown in FIG. 30 is formed on the surface of the silicon wafer 101. At this time, the trench 112a to be the alignment mark 112 is formed wide so that the surface thereof is not blocked.

Further, in recent years, attention has been focused on SJ (Super Junction) -MOSFET, which can improve the trade-off between on-resistance and breakdown voltage.
FIG. 32 is a cross-sectional view of a principal part of the SJ-MOSFET. The SJ-MOSFET 120 is formed by repeatedly performing film formation 122 by epitaxial growth and patterning for forming a column 123 by ion implantation on the silicon wafer 121 after the alignment mark 130 is formed. A dotted line on the side is an alignment mark 130 of a recess formed on the silicon wafer 121. In the figure, reference numeral 124 denotes a well layer, 125 denotes a source layer, 126 denotes a gate electrode, 127 denotes a source electrode, 128 denotes a drain layer, and 129 denotes a drain electrode.

  Further, in Patent Document 2, in a method of detecting an alignment mark formed on a substrate by reflected diffracted light of a laser beam, a sensor unit that detects detected light reflected by an edge of the alignment mark, and adjacent to the sensor unit A sensor unit that detects noise light in a direction perpendicular to the direction of the detected light, and either a noise signal of the sensor unit that detects the noise light or a detection signal of the sensor unit that detects the detected light It is described that one of them is inverted and added to reduce alignment errors that occur in the color filter manufacturing process.

  Further, in Patent Document 3, an element isolation insulating film formed on both upper sides of a silicon substrate, a gate insulating film and a gate electrode formed in order on the silicon substrate surface between the element isolation insulating films, a gate insulating film and an element isolation insulation A source region and a drain region formed on the silicon substrate between the films, a blister formed inside the silicon substrate below the gate insulating film, and a silicon channel inside the silicon substrate surrounded by the blister and the source region and the drain region; A MOSFET using a SON structure that can simultaneously improve the shortcomings of a bulk structure and an SOI structure by forming a blister with hydrogen or helium ions and a method for manufacturing the same are described.

  Further, in Patent Document 4, in a method of manufacturing a semiconductor memory device, a plurality of trenches are formed in a semiconductor substrate, and the semiconductor substrate is heat-treated in a hydrogen atmosphere, thereby closing the plurality of trenches while opening the plurality of trenches. The space under the trench is coupled to each other, a semiconductor layer provided on the cavity is formed, the semiconductor layer in the element isolation formation region is etched, an insulating film is formed on the side surface and the bottom surface of the semiconductor layer, and the semiconductor layer Conventionally, by filling the lower cavity with an electrode material, forming an element isolation by forming an insulating film on the electrode material in the element isolation formation region, and forming a memory element MC on the semiconductor layer, It is described that a semiconductor memory device and a method for manufacturing the same can be provided.

  Non-Patent Document 1 describes that a transistor is formed on a SON structure and the SON structure is used as a part of a separation layer.

JP 2007-273993 A JP-A-6-94422 JP 2006-261667 A JP 2008-21727 A

IEICE Technical Report, ED, Electronic Device 102 (175) pp. 99104

  However, the alignment mark 112 of the element of the SON structure 102 is somewhat distorted after SON formation. For this reason, the recognizability on the exposure machine side is deteriorated, and high-accuracy alignment becomes difficult.

  FIG. 33 is a cross-sectional view of a main part including an alignment marker of an element having a SON structure. FIG. 33A shows a main part of a recess (trench 112a) for the alignment marker and a hole trench having an SON structure arranged immediately below the element. FIG. 4B is a fragmentary cross-sectional view of the main part after annealing at high temperature and reduced pressure in a hydrogen atmosphere. As shown in FIG. 5B, pattern collapse occurs in the alignment mark after annealing.

  FIG. 34 is a cross-sectional view of the main part of the alignment mark in the epitaxial growth process of the SJ-MOSFET. FIG. 34 (a) shows the alignment mark before epitaxial growth, and FIG. 34 (b) shows the alignment mark after epitaxial growth. FIG. 6C is a diagram in which alignment marks are formed again.

  As shown in FIG. 34B, the shape of the alignment mark 130 is lost every time epitaxial growth occurs, and the alignment accuracy is deteriorated, or the alignment mark 130 disappears and the alignment cannot be performed. For this reason, it is necessary to suppress the epitaxial growth rate in order to suppress mark collapse or disappearance, or to re-form the alignment mark 130a as shown in FIG. In the figure, reference numeral 121 denotes a silicon wafer, and 131 denotes an epitaxial layer.

Further, in the conventional recess alignment mark, the resist may remain in the recess during the photolithography process, thereby reducing the reliability of the element.
Neither Patent Documents 1 to 4 nor Non-Patent Document 1 describes that the SON structure is used as an alignment mark in a photolithography process.

  An object of the present invention is to provide a method for manufacturing a semiconductor device that solves the above-described problems and does not need to consider that a resist remains on an alignment mark in a recess in a photolithography process.

  Another object of the present invention is to provide a method for manufacturing a semiconductor device in which an element is formed on a SON structure and the SON structure and an element on the SON structure can be accurately aligned.

  In addition, in a method for manufacturing a semiconductor device such as SJ-MOSFET, which is manufactured by repeating patterning and epitaxial growth, a method for manufacturing a semiconductor device capable of performing accurate alignment without taking into account pattern collapse or disappearance of alignment marks. It is to provide.

Another object of the present invention is to provide a method of manufacturing a semiconductor device using a transmission laser that transmits a silicon wafer for the detection of the alignment mark.

  In order to achieve the above object, according to the first aspect of the present invention, a process of forming a large number of fine hole trenches in an ineffective region of a semiconductor wafer, and an upper portion of the hole trenches by an annealing process. Forming a SON structure which is one large cavity by bonding the spaces of the hole trenches together while closing the substrate, and forming a semiconductor element on the semiconductor wafer using the SON structure as an alignment mark for photolithography And a method of manufacturing a semiconductor device.

  According to the invention described in claim 2 of the claims, in the invention described in claim 1, the invalid area is a portion of a dicing line or a dead space of the semiconductor wafer outside the dicing line. Good.

  According to a third aspect of the present invention, the alignment mark may be detected by a laser having a wavelength that transmits the semiconductor wafer.

According to the invention described in claim 4 of the claims, in the invention described in claim 3, the laser may be a red laser or an infrared laser.
According to the invention described in claim 5 of the claims, in the invention described in claim 1, the SON structure serving as the alignment mark may be formed simultaneously with the SON structure forming the semiconductor element. .

  According to the invention described in claim 6, the SON structure serving as the alignment mark in the invention described in claim 1 is formed between columns formed in a multistage epitaxial growth layer of a superjunction element. It may be used for alignment and alignment of the column and a well layer connected to the column.

  Further, according to the invention described in claim 7 of the claims, in the invention described in claim 1, the annealing treatment is performed in a 100% hydrogen atmosphere, the temperature is in the range of 1000 ° C. to 1200 ° C., and the pressure is It may be performed in the range of 133 Pa to 2660 Pa.

  According to the present invention, it is not necessary to consider that the resist remains on the alignment mark as in the prior art in the photolithography process, and the reliability of the element can be improved.

  In addition, an SON structure alignment mark is formed inside an ineffective area such as a dicing line of a silicon wafer, and an element is formed on the SON structure by recognizing the alignment mark with a red laser (transmission type laser). When an element is formed by repeated epitaxial growth, accurate alignment can be performed.

  In addition, by using the SON structure as an alignment mark, it is not necessary to consider the shape deformation of the alignment mark that has conventionally occurred during epitaxial growth, the epitaxial growth rate can be improved, and the throughput in the manufacturing process can be improved. .

  Further, a process such as re-formation of the alignment mark as in the prior art becomes unnecessary, and the manufacturing process can be shortened.

It is principal part manufacturing process sectional drawing of the semiconductor device of 1st Example of this invention. FIG. 2 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the first embodiment of the invention, following FIG. 1; FIG. 3 is a main part manufacturing step sectional view showing the method of manufacturing the semiconductor device in the first embodiment of the invention following FIG. 2; FIG. 4 is a main-portion manufacturing process cross-sectional view of the semiconductor device according to the first embodiment of the invention, following FIG. 3; FIG. 5 is a cross-sectional view of the essential part manufacturing process of the semiconductor device according to the first embodiment of the invention, following FIG. 4. It is the figure shown about the hole trench 5, (a) is a top view of the silicon wafer 1 which showed the dicing line 4, (b) is an enlarged view of the dicing line 4 shown to the A section of (a), (c) is It is an arrangement plan of hole trench 5 formed in B section of (b). FIG. 4 is a plan view of a main part of an example of an alignment mark, where (a) is a layout diagram of hole trenches before annealing, and (b) is a diagram in which a SON structure is formed after annealing. It is principal part manufacturing process sectional drawing of the semiconductor device of 2nd Example of this invention. FIG. 9 is a main-portion manufacturing process cross-sectional view of the semiconductor device according to the second embodiment of the invention, following FIG. 8; FIG. 10 is a cross-sectional view of the main part manufacturing process of the semiconductor device according to the second embodiment of the invention, following FIG. 9; FIG. 11 is a cross-sectional view showing the main part manufacturing process of the semiconductor device according to the second embodiment of the invention, following FIG. 10; FIG. 12 is a main-portion manufacturing process cross-sectional view of the semiconductor device according to the second embodiment of the invention, following FIG. 11; FIG. 13 is a cross-sectional view of the main part manufacturing process of the semiconductor device according to the second embodiment of the invention, following FIG. 12. FIG. 14 is a main-portion manufacturing process cross-sectional view of the semiconductor device according to the second embodiment of the invention, following FIG. 13; FIG. 15 is a main-portion manufacturing process cross-sectional view of the semiconductor device according to the second embodiment of the invention, following FIG. 14; FIG. 16 is a cross-sectional view of the main part manufacturing process of the semiconductor device according to the second embodiment of the invention, following FIG. 15; FIG. 17 is a main-portion manufacturing process cross-sectional view of the semiconductor device according to the second embodiment of the invention, following FIG. 16; 4 is a cross-sectional view of a main part of a lateral MOSFET in which a side surface formed on an SOI substrate 50 is surrounded by a diffusion separation layer. FIG. It is principal part manufacturing process sectional drawing of the semiconductor device of 3rd Example of this invention. FIG. 20 is a cross-sectional view of the main part manufacturing process of the semiconductor device according to the third embodiment of the invention, following FIG. 19. FIG. 21 is a main-portion manufacturing process cross-sectional view of the semiconductor device according to the third embodiment of the invention, following FIG. 20; FIG. 22 is a principal part manufacturing step sectional view of the semiconductor device in the third embodiment of the invention, following FIG. 21; FIG. 23 is a main-portion manufacturing process sectional view of the semiconductor device according to the third embodiment of the invention, following FIG. 22; FIG. 24 is a cross-sectional view of the main part manufacturing process of the semiconductor device according to the third embodiment of the invention, following FIG. 23. FIG. 25 is a cross-sectional view of the main part manufacturing process of the semiconductor device according to the third embodiment of the invention, following FIG. 24; FIG. 26 is a cross-sectional view showing the main part manufacturing process of the semiconductor device according to the third embodiment of the invention, following FIG. 25; 27 is a fragmentary manufacturing step sectional view of the semiconductor device according to the third embodiment of the present invention continued from FIG. 26; FIG. FIG. 28 is a cross-sectional view of the main part manufacturing process of the semiconductor device according to the third embodiment of the invention, following FIG. 27; FIG. 29 is a cross-sectional view showing the main part manufacturing process of the semiconductor device according to the third embodiment of the invention, following FIG. 28; It is a figure which shows the alignment mark of the element formed on the SON structure. It is a principal part process drawing explaining the formation method of SON structure. It is principal part sectional drawing of SJ-MOSFET. It is principal part sectional drawing containing the alignment marker of the element of SON structure, (a) is principal part sectional drawing of the hole trench used as the SON structure arrange | positioned directly under the recessed part (trench 112a) for alignment markers, (b) ) Is a fragmentary cross-sectional view after annealing in a hydrogen atmosphere at high temperature and reduced pressure. It is principal part sectional drawing of the alignment mark in the epitaxial growth process of SJ-MOSFET, (a) is the figure of the alignment mark before epitaxial growth, (b) is the figure of the alignment mark after epitaxial growth, (c) is the alignment mark again FIG.

  Embodiments will be described in the following examples.

  1 to 5 are process diagrams showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention, and are cross-sectional views of main part manufacturing processes shown in the order of steps. This method for manufacturing a semiconductor device describes a method for forming an alignment mark having a SON structure and a method for recognizing the alignment mark.

  First, as shown in FIG. 1, an oxide film 2 having a thickness of, for example, about 1 μm is formed on a silicon wafer 1 (semiconductor substrate) having a (001) principal surface 1a. Here, the main surface 1a is the (001) plane, but it may be in a different plane orientation.

  Next, as shown in FIG. 2, a resist mask 3 is coated on the oxide film 2, and the oxide film 2 is etched and patterned by the resist mask 3, thereby forming an oxide film mask 2a for forming the alignment mark 9. To do.

  Next, as shown in FIG. 3, the surface layer of the dicing line 4 of the silicon wafer 1 is selectively etched by the oxide film mask 2a, so that a large number of hole trenches 5 that become the alignment marks 9 of the SON structure 11 are formed. Form.

  6A and 6B are diagrams showing the hole trench 5, in which FIG. 6A is a plan view of the silicon wafer 1 showing the dicing line 4, and FIG. 6B is a dicing shown in part A of FIG. An enlarged view of the line 4 and FIG. 5C are layout diagrams of the hole trenches 5 formed in the portion B of FIG. In the figure, reference numeral 7 denotes an active region in the chip, and 8 denotes a hole trench formed in the active region 7. The dimensions of one hole trench 5 and 8 are, for example, vertical L1 = 1 μm, horizontal L2 = 1 μm, depth T = 5 μm (see FIG. 3), and interval Q = 0.5 μm. The shape of the hole trenches 5 and 8 is a quadrilateral or more polygon or circle. In addition, for example, in the case of a square or a circle, the dimensions are vertical L1, horizontal L2, or a diameter in the range of about 0.4 μm to 1.5 μm, the interval Q is in the range of about 0.4 μm to 1.5 μm, and the depth T Is preferably in the range of about 5 μm to 10 μm. Further, the hole trenches 5 and 8 are preferably a square arrangement (arrangement of FIG. 6C) in which the arrangement of the lattice points is a square or an equilateral triangle arrangement in which the arrangement of the positions of the lattice points is an equilateral triangle.

Further, the hole trench 5 may be formed at a location off the dicing line 4, for example, at a location (dead space 6) that is not required in the chip as shown in FIG. 6 (a).
Further, the hole trench 8 of the SON structure 23 (see, for example, FIG. 8) formed in the active region 7 that forms the element is formed simultaneously with the same dimension as the hole trench 5 of the SON structure 11 that becomes the alignment mark 9.

  Next, as shown in FIG. 4, the annealing treatment is performed in a treatment furnace 11a in a 100% hydrogen atmosphere under a high temperature and reduced pressure range of a temperature of 1000 ° C. to 1200 ° C. and a pressure of 133 Pa (1 Torr) to 2660 Pa (20 Torr). Aligning the spaces of the hole trenches 5 with each other while closing the upper part of the hole trenches 5, the alignment mark 9 of the SON structure 11 that is one large cavity 10 is formed. Further, the hole trench 8 formed under the active region 7 shown in FIG. 6 is also annealed at the same time, so that the SON structure 23 composed of one cavity 22 as shown in FIG. 8 is formed.

  FIG. 7 is a plan view of the main part of an example of an alignment mark, where FIG. 7A is a layout diagram of hole trenches before annealing, and FIG. 7B is a diagram in which a SON structure is formed after annealing. In FIG. 9A, a dotted line 9a indicates a region where the hole trench 5 to be the alignment mark 9 in FIG. The hole trench 5 is arranged in the whole area inside the cross dotted line 9a, but a part thereof is shown here.

  As the alignment mark 9, as shown in FIG. 7, a pattern with a cross is taken as an example. The size of the alignment mark 9 formed after the annealing process is, for example, a pattern width W = about 4 μm to 6 μm, a cross arm length L = about 10 μm to 15 μm, and a cavity depth P = 1 μm to 2 μm ( 4), which is substantially the same size as the alignment mark of the recess formed on the surface of a normal silicon wafer. Of course, the size and shape of the alignment mark 9 can be arbitrarily set. In FIG. 7A, only a part of the hole trench 5 is shown.

  Further, if the temperature range and pressure range of the annealing process at the time of forming the SON structures 11 and 23 are out of the range, the formation of the SON structure 11 becomes difficult. When the temperature is lower than 1000 ° C., the deformation amount of the silicon wall sandwiched between the hole trenches 5 (location indicated by the interval Q in FIG. 6C) is reduced, and the upper space of each hole trench 5 is difficult to be blocked. Further, when the temperature is higher than 1200 ° C., the cavity 10 may not be crushed and formed. Further, although the pressure is preferably reduced, the pressure is less than 133 Pa is a limit in the current processing apparatus. When the pressure exceeds 2660 Pa, the deformation amount of the silicon wall sandwiched between the hole trenches 5 is reduced, and it takes too much time to close the upper space of each hole trench 5. However, the inventors have confirmed that the SON structure 11 is formed even at normal pressure with respect to the pressure during annealing. In this embodiment, an annealing process in a 100% hydrogen atmosphere is shown, but an atmosphere composed of a rare gas and hydrogen or a reducing atmosphere containing hydrogen may be used. Even if other hydrogen-free materials are used, the SON structure can be formed if the atmosphere during the annealing treatment is an ultra-high vacuum, a rare gas atmosphere, or a reducing atmosphere.

  Next, as shown in FIG. 5, the alignment mark 18 formed on the reticle mask 17 set on the exposure machine 12 and the silicon wafer 1 using a laser (for example, red laser) having a wavelength that transmits the silicon wafer 1. Alignment with the alignment mark 9 formed in (1) is performed.

  In this alignment, when the silicon wafer 1 is positioned, the elements formed on the silicon wafer 1 are also automatically positioned by the exposure machine 12. In FIG. 5, the alignment mark 9 of the SON structure 11 is detected as follows.

  The outgoing light 14 emitted from the red laser emitting portion 13 having a wavelength of about 670 μm installed in the exposure machine 12 is incident on the surface of the silicon wafer 1. A part of the incident light 14 is reflected on the cavity 10 of the SON structure 11 to be the alignment mark 9 and becomes reflected light 16. Others pass through the silicon wafer 1 below the cavity 10 as transmitted light 114a. The reflected light 16 is captured by the detection unit 15 installed in the exposure machine 11. The alignment mark 9 is detected from the change in reflection intensity of the captured reflected light 16. In some cases, the red laser is incident from the back surface of the silicon wafer 1 and the alignment mark 9 is detected from the change in the reflection intensity. In some cases, the change in the transmission intensity of the red laser is utilized.

  Further, an infrared laser, a red LED (light emitting diode), or the like may be used instead of the red laser. In this case, the emission unit 13 and the detection unit 15 are changed so as to correspond to them.

  By using the alignment mark 9 of the SON structure 11, it is not necessary to consider the shape collapse or disappearance of the alignment mark in a manufacturing process for forming elements on the SON structure or a manufacturing process for performing epitaxial growth many times.

As a result, in the manufacturing process in which epitaxial growth is performed many times, the epitaxial growth rate can be improved, and the throughput in the manufacturing process can be improved.
In addition, a manufacturing process such as re-formation of an alignment mark as in the prior art becomes unnecessary, and the manufacturing process can be shortened.

  Further, it is not necessary to consider that the resist remains on the alignment mark in the photolithography process. By using the alignment mark 9 of the SON structure 11 in a photolithography process when manufacturing an element other than the elements of Example 2 and Example 3 to be described later, the resist residue can be eliminated and the reliability of the element can be eliminated. Can be increased.

  Next, an embodiment in which an element such as a MOS transistor having a SON structure or a multistage epitaxial layer SJ-MOSFET is formed using the alignment mark 9 will be described below.

  8 to 17 are process diagrams showing a method of manufacturing a semiconductor device according to the second embodiment of the present invention, and are cross-sectional views of main part manufacturing processes shown in the order of steps. This semiconductor device is an example of a lateral MOS transistor having an insulating isolation structure composed of a SON structure and a diffusion isolation layer. This is an example of a semiconductor device having an insulating isolation structure in which the SON structure is used in place of an SOI (Silicon On Insulator) structure.

  First, as shown in FIG. 8, an alignment mark 9 of the SON structure 11 and an n-type silicon wafer 21 in which the SON structure 23 is simultaneously formed under the element formation site are prepared. By simultaneously forming the SON structure 11 to be the alignment mark 9 and the SON structure 23 formed immediately below the element, the manufacturing cost can be reduced. 8A and 8B are cross-sectional views of the main part of the silicon wafer 21 on which the SON structures 11 and 23 are formed. FIG. 8A is an overall view, and FIG. 8B is an enlarged cross-sectional view of a portion C in FIG. FIG. In the figure, reference numeral 10 denotes a cavity serving as the alignment mark 9, and 22 denotes a cavity of the SON structure 23. .

  Next, as shown in FIG. 9, a single-crystal n-type and low-concentration silicon layer 24 having a lower concentration than the silicon wafer 21 is formed on the silicon wafer 21 by epitaxial growth. A p-type diffusion separation layer 25 (high-concentration diffusion layer) that penetrates the silicon layer 24 on the cavity 22 of the SON structure 23 and reaches the cavity 22 is formed. The diffusion separation layer 25 is aligned with the alignment mark 9 so as to surround the silicon layer 24 on the cavity 22 and the silicon layer 26 (thin film) of the SON structure 23. The alignment mark 9 is recognized by the red laser as described above. FIG. 10 and subsequent figures are cross-sectional views of relevant parts corresponding to FIG.

Next, as shown in FIG. 10, an oxide film 27 and a selective oxide film 28 to be a gate oxide film are formed on the upper surface of the silicon layer 24 surrounded by the diffusion separation layer 25.
Next, as shown in FIG. 11, polysilicon 29 to be a gate electrode is formed on the entire surface.

  Next, as shown in FIG. 12, a silicon wafer 21 is set on a spinner table 30 of a resist coating apparatus, a resist 31 is coated on polysilicon 29, and then the resist 31 is cured.

  Next, as shown in FIG. 13, the silicon wafer 1 covered with the resist 31 is set in the exposure machine 32. Subsequently, the alignment mark 9 of the SON structure 11 formed on the silicon wafer 21 is irradiated from the exposure machine 32 with, for example, incident light 33 of a red laser having a wavelength of 670 nm, and a change in the reflection intensity of the reflected light 34 is caused. Then, the alignment mark 36 of the reticle mask 35 set in the exposure device 32 and the alignment mark 9 of the SON structure 11 of the silicon wafer 21 are positioned. This positioning is for positioning the silicon wafer 21 so that elements can be reliably formed on the silicon layer 24 on the SON structure 23. The red laser is incident from the surface of the silicon wafer 21, and this positioning is performed by changing the reflection intensity. Of course, irradiation may be performed from the back side and positioning may be performed by changing the reflection intensity.

  Next, as shown in FIG. 14, the resist 31 on the positioned silicon wafer 21 is irradiated with exposure light 37 emitted from an exposure machine 32 through a reticle mask 35 to expose the resist 31. The pattern 35 a formed on the reticle mask 35 by this exposure is projected onto the resist 31. As the exposure machine 32, for example, a stepper device in which an exposure location moves for each shot is used. Here, the resist 31 shows a case of a negative resist (the resist remains at the place where the light hits). Of course, a body resist may be used.

Next, as shown in FIG. 15, the exposed silicon wafer 21 is taken out, and the resist on the silicon wafer is patterned by etching to form a resist mask 38.
Next, as shown in FIG. 16, after the polysilicon 29 is etched by the resist mask 38 to form the gate electrode 39, the resist mask 38 is removed.

  Next, as shown in FIG. 17, an n-type impurity such as phosphorus or arsenic is ion-implanted using the gate electrode 39 and the selective oxide film 28 as a mask, and then thermally diffused to form a source layer 41 and a drain layer 42. To do. Thereafter, the gate oxide film 27 is removed except under the gate electrode 39, and a source electrode 43 and a drain electrode 44 are formed. Subsequently, the silicon wafer 21 is cut along a dicing line 45 indicated by a dotted line to form a chip, and a lateral MOS transistor having an insulating isolation layer whose side is surrounded by a diffusion isolation layer 25 and whose bottom is a cavity 22 of the SON structure 23 Is formed. Although one MOS transistor is formed in the figure, in an actual device, a large number of elements are formed on the silicon layer 24 surrounded by the diffusion isolation layer 25 to constitute an IC (integrated circuit).

  Thus, as shown in FIG. 17, when the SON structure 23 is used as the bottom of the insulating separation layer, since the separation of the bottom is the cavity 22, the SOI substrate 50 (insulation by the oxide film 52 is used) as shown in FIG. Compared with the lateral MOSFET formed in the isolation layer), the isolation capacitance can be reduced. As a result, by forming an element on the SON structure 23, the high-speed performance of the semiconductor device can be improved. In FIG. 18, reference numeral 51 denotes a silicon substrate, 53 denotes a silicon layer, 54 denotes a diffusion separation layer, 55 denotes a selective oxide film, 56 denotes a gate insulating film, 57 denotes a gate electrode, 58 denotes a source layer, and 59 denotes a drain. Layer 58a is a source electrode and 59a is a drain electrode.

  Here, an example of a horizontal MOS transistor has been described as an element, but the present invention is not limited to this, and a plurality of arbitrary elements can be formed on the silicon layer 24 on the SON structure 23. The silicon layer 24 is a single crystal layer, but may be a polysilicon layer.

  FIGS. 19 to 29 are process diagrams showing a method of manufacturing a semiconductor device according to a third embodiment of the present invention, and are cross-sectional views of main part manufacturing processes shown in the order of steps. This semiconductor device is an example of a 600V withstand voltage SJ-MOSFET having a planar gate structure.

  First, as shown in FIG. 19, an n-type silicon layer 62 serving as a buffer layer is formed on an n-type silicon wafer 61 on which the alignment mark 9 of the SON structure 11 is formed. This silicon layer 61 is an epitaxial layer having an impurity concentration lower than that of the silicon wafer 61. In the figure, reference numeral 10 denotes a cavity of the SON structure 11, and 22 denotes a cavity of the SON structure 23. 19 is a cross-sectional view showing the alignment mark 9 of the silicon wafer 61. FIG. 19 (a) is an overall view, and FIG. 19 (b) is an enlarged view of a portion D in FIG. 19 (a).

Next, as shown in FIG. 20, after forming and patterning an epitaxial layer 63 having a lower concentration than the silicon layer 62 on the silicon layer 62, for example, a dose column is formed in order to form a p-column structure. An ion implantation 70 of boron ions 71 (p-type impurities) is performed with a resist mask 69 in an amount of 1.0 × 10 ¹³ cm ⁻² . In the patterning process of the resist mask 69, the alignment mark 9 of the SON structure 11 is used, and, for example, a 670 nm red laser 72 having a wavelength that transmits the silicon wafer 61 is used to form a reticle mask (not shown) and the silicon wafer 61. The alignment mark 9 of the SON structure 11 is aligned. At this time, the incident light 72 a of the red laser 72 is emitted from the surface of the silicon wafer 61. Of course, it may be performed from the back side. Incidentally, reference numeral 72b in the figure denotes reflected light.

  Next, in FIG. 21, the epitaxial growth process, the patterning process using the alignment mark 9 of the SON structure 11, and the ion implantation 70 of boron ions 71 are repeated a plurality of times. Here, although the example of 5 times (epitaxial layers 63-67) was shown, it does not restrict to this. Although not shown, phosphorus ions are implanted into the entire surfaces of the epitaxial layers 63 to 67 before the boron ions 71 are implanted 70. The formation and removal of the resist mask 69 is repeated each time an epitaxial layer is formed, and alignment with the alignment mark 9 is performed each time.

  Next, as shown in FIG. 22, the uppermost epitaxial layer 75 is formed on the epitaxial layer 67. At this stage, epitaxial growth is performed seven times. The number of times depends on the element breakdown voltage as described later.

  Next, as shown in FIG. 23, a p-type column structure 73 and an n-type column structure 74 are formed by heat treatment. Here, the n-type semiconductor layer in contact with the p-type column structure 73 is referred to as an n-type column structure 74. The p-type column structure 73 has a column shape surrounded by the n-type column structure 74 and is formed inside the n-type column structure 74. This is like the “pillar” of the p-type column structure 73 stands in the “sea” of the n-type column structure 74. The depth S of the p-type column structure 74 is about 50 μm here. Further, in the p-type column structure 73 and the n-type column structure 74 formed by stacking, the vertical pn junction where the column structures 73 and 74 are in contact uses the alignment mark 9 of the SON structure 11. By this, it is formed accurately.

  The depth S (50 μm) of the p-type column structure 73 described above is a case of a withstand voltage of 600 V, and the depth S of the p-type column structure 73 becomes deeper as the device withstand voltage increases. In this case, the n-type epitaxial layer is formed more frequently, and the thickness of the entire n-type epitaxial layer is further increased.

The p-type column structure 73 is formed by biting into the silicon layer 62 and the n-type epitaxial layer 75 by the heat treatment.
Next, as shown in FIG. 24, an oxide film 76 serving as a gate oxide film is formed on the uppermost n-type epitaxial layer 75, and polysilicon 77 serving as a gate electrode is formed on these oxide films 76. To do.

  Next, as shown in FIG. 25, a resist mask 78 is formed using the alignment mark 9 of the SON structure 11, and the polysilicon 77 is patterned using the resist mask 78 to form a gate electrode 79.

  Next, as shown in FIG. 26, using the gate electrode 79 and the resist 80 as a mask, the p-type well layer 81 connected to the p-type column structure 73 on the p-type column structure is implanted with boron ions and heat. It is formed by diffusion. By using the alignment mark 9 of the SON structure 11, the position of the gate electrode 79, the position of the p-type column structure 73, and the position of the p-type well structure 81 can be accurately determined. By the heat treatment for forming the p-type well layer 81, the p-type column structure 73 extends to the uppermost epitaxial layer 75 and is connected to the p-type well layer 81.

Next, as shown in FIG. 27, an n-type source layer 83 is formed using the gate electrode 79 and the resist 82 as a mask.
Next, as shown in FIG. 28, an interlayer insulating film 84 (BPSG), an insulating film 85, a source surface electrode 86, and a surface protective film 87 are formed. Thereafter, the back surface 61a of the silicon wafer 61 is back-ground (back surface grinding) to reduce the thickness R of the silicon wafer 61 including the epitaxial layer from about 675 μm to about 280 μm.

  Next, as shown in FIG. 29, after an n-type drain layer 88 and a drain back electrode 89 are formed on the back surface 61a of the silicon wafer 61, the silicon wafer 61 is cut along the dicing line 90 into chips, and 600V The withstand voltage SJ-MOSFET is completed. By this cutting, the position of the alignment mark of the SON structure 11 is cut off from the chip 91. A pressure-resistant structure portion (not shown) is formed in a range 93 indicated by an arrow on the outer peripheral portion 92 of the chip 91. Further, when the silicon wafer 61 has a high concentration, the silicon wafer 61 serves as a drain layer. In that case, in order to reduce the contact resistance with the drain back electrode 89, a high concentration contact layer may be formed instead of the drain layer 88.

  As described above, by using the alignment mark 9 of the SON structure 11, even when an epitaxial layer is formed a plurality of times and an impurity diffusion layer is selectively formed in each epitaxial layer, the alignment mark 9 is deformed or lost. There is no need to consider. As a result, the epitaxial growth rate can be improved as compared with the prior art, and the throughput in the manufacturing process can be improved.

In addition, since a manufacturing process such as re-formation of an alignment mark is not required as in the prior art, the manufacturing process can be shortened.
In the third embodiment, an example of a planar SJ-MOSFET has been described. However, it is needless to say that the present invention can also be applied to a trench SJ-MOSFET (not shown).

1, 21, 61 Silicon wafer 1a Main surface 2 Oxide film 2a Oxide film mask 3 Resist mask 4, 45, 90 Dicing line 5 Hole trench (formed at alignment mark)
6 Dead space 7 Active region 8 Hole trench (formed in the active region)
9 Alignment mark 9a Dotted line (cross)
10 cavity (alignment mark)
11 SON structure (alignment mark)
DESCRIPTION OF SYMBOLS 11a Processing furnace 12 Exposure machine 13 Emitting part 14, 33, 72a Incident light 14a Transmitted light 15 Detection part 16, 34, 72b Reflected light 17, 35 Reticle mask 18 Alignment mark (reticle mask)
22 Cavity (SON structure of active region)
23 SON structure (active region)
24, 62 Silicon layer 25 Diffusion separation layer 26 Silicon layer (silicon thin film on cavity of SON structure)
27 Oxide film 28 Selective oxide film 29, 77 Polysilicon 30 Spinner table 31, 80, 82 Resist 32 Exposure machine 35a Pattern (reticle mask)
36 Alignment mark (reticle mask)
37 Light for exposure 38, 69, 78 Resist mask 39, 79 Gate electrode 40, 84 Interlayer insulating film 41 Source layer 42 Drain layer 43 Source electrode 44 Drain electrode 61a Back surface 63-67, 75 Epitaxial layer 70 Ion implantation 71 Boron ion 72 red laser 73 p-type column structure 74 n-type column structure 76 gate oxide film 81 p-type well layer 83 n-type source layer 85 insulating film 86 source surface electrode 87 surface protective film 88 n-type drain layer 89 drain Back electrode 91 Chip 92 Outer periphery 93 Range

Claims (7)

Forming a large number of fine hole trenches in the ineffective region of the semiconductor wafer;
A step of forming an SON (Silicon On Notifying) structure which is one large cavity by combining the spaces of the hole trenches with each other while closing the upper portion of the hole trenches by an annealing process;
Using the SON structure as an alignment mark for photolithography and forming a semiconductor element on the semiconductor wafer;
A method for manufacturing a semiconductor device, comprising: 2. The method of manufacturing a semiconductor device according to claim 1, wherein the invalid area is a portion of a dicing line or a dead space of the semiconductor wafer outside the dicing line. The method of manufacturing a semiconductor device according to claim 1, wherein the alignment mark is detected by a laser having a wavelength that transmits the semiconductor wafer. The method of manufacturing a semiconductor device according to claim 3, wherein the laser is a red laser or an infrared laser. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the SON structure to be the alignment mark is formed simultaneously with the SON structure constituting the semiconductor element. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the SON structure serving as the alignment mark is used for alignment of an impurity diffusion layer formed in a multi-stage epitaxial growth layer of a super junction element. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the annealing treatment is performed in a 100% hydrogen atmosphere at a temperature in a range of 1000 ° C. to 1200 ° C. and a pressure in a range of 133 Pa to 2660 Pa. 3.

Images