JP2009081352A - Manufacturing method for semiconductor substrate, and semiconductor substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To manufacture a high-quality SiC substrate by reducing crystal defect on a seed layer. <P>SOLUTION: The manufacturing method for a semiconductor substrate is intended for manufacturing a semiconductor substrate 1 having an SiC layer 30 on an insulating layer 20. The manufacturing method has an Si part segmentation step to form a groove part 40 exposing the insulating layer 20 on an Si layer 50 on a base substrate 100 comprising the insulating layers 20 and the Si layers 50 that are sequentially formed on a support substrate 10 and to segment the Si layer 50 into many island-shaped Si parts 55 using the groove part 40, a seed layer formation step to form island-shaped seed parts 65 by carbonizing the Si parts 55 and to form a seed layer 60 comprising the seed parts 65, and an SiC layer formation step to form island-shaped SiC parts 35 through the epitaxial growth of the seed parts 65 and to form the SiC layer 30 comprising the SiC parts 35. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor substrate manufacturing method and a semiconductor substrate.

  In recent years, SiC (silicon carbide) has attracted attention as a semiconductor material. Since SiC has a higher breakdown electric field than Si, it can have a high breakdown voltage, and since the resistance value when the FET is on is small, power loss can be reduced. In addition, it has features such as stable operation at high temperatures and a low diffusion rate of impurity ions. Such SiC is considered to be applied to high voltage power devices such as rectifiers and inverters, and is expected to save energy.

  In order to efficiently manufacture a device using SiC, it is extremely important to increase the diameter of a substrate (wafer) having a single crystal SiC layer. At present, a 6-inch 4H—SiC substrate has been put into practical use, but it is considered effective to reduce crystal defects in order to further increase the substrate diameter and improve the yield.

  As a method for manufacturing an SiC substrate, Patent Document 1 discloses a method using an SOI substrate. As a method for suppressing crystal defects, Patent Literature 2 discloses a method for relaxing internal stress of a single crystal film.

  In the method of Patent Document 1, the Si layer of an SOI substrate having an Si layer on an insulating layer is thinned and carbonized to form a SiC seed layer. Then, the SiC substrate is manufactured by epitaxially growing the seed layer. Since the thinned Si layer is completely carbonized, the remaining Si is prevented from diffusing into the SiC layer during epitaxial growth or the like to cause crystal defects. In addition, when carbonizing the Si layer, since the lattice constants of Si and SiC are different, stress is generated between Si and SiC and deformation due to strain occurs. However, since the Si layer is thinned, the thickness direction The strain is reduced and crystal defects are suppressed.

In the method of Patent Document 2, when a nitride single crystal film is grown on a silicon substrate, a growth space for a crystal growing in the plane direction is secured. As a result, it is possible to relieve internal stress caused by the crystal growing while pressing each other, and to prevent tilting of the crystal axis.
JP 2003-224248 A Japanese Patent Laid-Open No. 2002-11069

  However, the method of Patent Document 1 may not be able to cope with an increase in the diameter of the SiC substrate. That is, the stress between Si and SiC caused by the difference in lattice constant also acts in the surface direction of the SiC substrate, so that the larger the area for carbonizing Si, that is, the larger the diameter of the manufactured SiC substrate The greater the amount, the greater the deformation between Si and SiC. When the seed layer is thus deformed, crystal defects are generated in the seed layer. When the seed layer is epitaxially grown, crystal growth occurs on the upper layer based on the crystal structure of the lower layer, so that crystal defects are generated in a chain on the crystal defect portion.

  Further, the method of Patent Document 2 is a method for satisfactorily growing a nitride single crystal film on a silicon substrate, and it is difficult to directly apply it to seed layer formation when manufacturing a SiC substrate. That is, since the seed layer is formed not by crystal growth but by carbonization of the Si layer, the effect of suppressing crystal defects in the seed layer cannot be expected from the gist of Patent Document 2 to secure a crystal growth space. It is.

  This invention is made | formed in view of said situation, and it aims at providing the method of reducing the crystal defect of a seed layer and manufacturing a good quality SiC substrate.

The method for producing a semiconductor substrate of the present invention is a method for producing a semiconductor substrate having a SiC layer on an insulating layer,
A groove portion exposing the insulating layer is formed in the Si layer of the base substrate in which the insulating layer and the Si layer are sequentially formed on the support substrate, and the Si layer is partitioned into a plurality of island-shaped Si portions by the groove portion. Si section partitioning process,
A seed layer forming step of carbonizing the Si portion to form an island-shaped seed portion and forming a seed layer comprising the seed portion;
An SiC layer forming step of forming an island-shaped SiC portion by epitaxially growing the seed portion and forming an SiC layer made of the SiC portion.

  In this way, crystal defects in the seed part can be suppressed. Specifically, in the middle of the seed layer forming step, there is a state in which SiC with Si and Si carbonized is mixed in the Si portion, and a stress in the plane direction due to a difference in lattice constant acts between Si and SiC. To do. The amount of deformation of Si and SiC due to this stress increases as the area where the stress acts, that is, the contact area between Si and SiC increases. In the method of the present invention, a groove (space) is formed between the Si parts, and the Si parts are not in direct contact with each other. Therefore, the stress at each Si part when carbonizing the Si part is affected by the adjacent Si. It does not propagate to the part. Therefore, the deformation amount of Si and SiC in each Si part is defined by the contact area between Si and SiC in each Si part, that is, the area of each Si part. Since the area of each Si part is smaller than the area of the Si layer that is not partitioned into Si parts, the amount of deformation of Si and SiC in each Si part becomes small, and crystal defects are caused in the seed part due to the deformation of Si and SiC. The probability of occurrence is reduced.

  In addition, since the seed portion having a good crystal structure is formed by reducing the probability of occurrence of crystal defects, the SiC portion having a good crystal structure can be formed by epitaxially growing the seed portion having a good crystal structure. it can. In this way, it is possible to manufacture a semiconductor substrate having an SiC layer with very few crystal defects.

  Further, as described above, since the deformation amount of Si and SiC due to the difference in lattice constant is a value corresponding to the area of the Si portion, even when a large-diameter substrate is used as the base substrate, crystal defects are similarly reduced. Therefore, a large-diameter semiconductor substrate can be manufactured with a good yield. By forming a chip using such a large-diameter semiconductor substrate, the chip can be efficiently manufactured.

Moreover, it is preferable to have the process of filling the said groove part with an insulating material after the said SiC layer formation process.
In this way, when an element or the like is formed on the manufactured semiconductor substrate, the element material or the like is prevented from being embedded or flowing into the groove to become a foreign substance.

The semiconductor substrate is a semiconductor substrate for forming a plurality of chips, and has a plurality of chip formation regions corresponding to one of the formed chips,
In the Si part partitioning step, the groove part may be formed so that one Si part corresponds to one chip formation region.
In this case, when the SiC portion is carbonized and epitaxially grown to form the SiC portion, the same region as one Si portion becomes one SiC portion, so that the SiC portion corresponding to the chip formation region is formed. Can do. Therefore, even if the physical properties of the semiconductor substrate, such as temperature characteristics and strength, are locally changed due to the formation of the groove, the plurality of chip formation regions have the same physical properties, so that chips of the same quality can be formed. it can. In addition, when forming a plurality of chips using a silicon wafer or the like, usually, a plurality of chip formation areas are designed on a silicon wafer, elements are formed in each chip formation area, and then the chips are separated into individual chips. Form. Therefore, if one Si portion and one chip formation region are made to correspond to each other, an existing method can be diverted to partition the Si layer, and the process of partitioning the Si layer is facilitated.

  The chip formation region in the present invention refers to a design section on a semiconductor substrate corresponding to one of the chips in consideration of a chip size, a margin of misalignment in a formation process, and the like. In addition, in the intermediate body in the process of manufacturing the base substrate and the semiconductor substrate, a region corresponding to the chip formation region of the manufactured semiconductor substrate may be referred to as a chip formation region.

The semiconductor substrate is a semiconductor substrate for forming a plurality of chips, and has a plurality of chip formation regions corresponding to one of the formed chips,
In the Si part partitioning step, the groove part may be formed so that one chip forming region includes two or more Si parts.
In this way, since the same region as one Si portion becomes one SiC portion as described above, two or more SiC portions are included in one chip formation region. Therefore, when a chip is formed using the semiconductor substrate, the element can be well separated if the element is formed in each of two or more SiC parts included in the chip formation region. In particular, if the groove is filled with an insulating material as described above, the insulating portion buried in the groove can function as an element isolation region, and complete element isolation can also be achieved.

The semiconductor substrate is a semiconductor substrate for forming a plurality of chips, and has a plurality of chip formation regions corresponding to one of the formed chips,
In the Si part partitioning step, the groove part may be formed so that two or more chip forming regions are included in one Si part.
In this way, for example, when a chip formed using a semiconductor substrate is fine, the alignment when forming the groove portion is divided rather than dividing the Si layer into the Si portion corresponding to each chip formation region. The margin can be increased. Therefore, it is possible to suppress a decrease in chip yield due to misalignment.

The semiconductor substrate of the present invention is
A support substrate;
An insulating layer provided on the support substrate;
An SiC layer provided on the insulating layer and having a plurality of SiC portions that are partitioned by grooves and formed in an island shape;
In the SiC part, an Si layer provided on the insulating layer is partitioned by the groove part to form an island-like Si part, and the Si part is carbonized, and then the carbonized Si part is a seed part. And formed by epitaxial growth.
In this way, since the seed part has very few crystal defects as described above, the SiC part obtained by epitaxial growth of the seed part also has very few crystal defects. Therefore, the SiC layer having the SiC portion with very few crystal defects has very few crystal defects, and the semiconductor substrate provided with this has a good quality.

The groove is preferably embedded with an insulating material.
In this way, when an element or the like is formed on the semiconductor substrate, it is possible to prevent the element material or the like from being embedded in or flowing into the groove to become a foreign substance.

  Hereinafter, although one embodiment of the present invention is described, the technical scope of the present invention is not limited to the following embodiment. In the following description, various structures are illustrated using drawings, but in order to show the characteristic parts of the structures in an easy-to-understand manner, the structures in the drawings are shown in different sizes and scales from the actual structures. There is.

  In addition, SiC has a crystal structure in which double layers composed of Si (silicon) and C (carbon) are stacked, but the crystal structure changes the way of stacking depending on the temperature of the crystallization process, and more than one hundred types There is a crystal structure called polymorphism. Typical crystal structures include 4H—SiC, 2H—SiC, 3C—SiC, etc., and the following embodiments are examples of crystallizing 3C—SiC capable of single crystallization at a relatively low process temperature. The explanation will be given. Hereinafter, after describing a configuration of a semiconductor substrate (SiC substrate) according to an embodiment of the present invention, an embodiment of a manufacturing method thereof will be described.

  FIG. 1A is a plan view showing a configuration of a semiconductor substrate (SiC substrate) 1 of the present embodiment. As shown in FIG. 1A, in the SiC substrate 1 of this embodiment, the groove portions 40 are formed at equal intervals in the vertical and horizontal directions, and a rectangular portion (square shape in the present embodiment) surrounded by the groove portions 40 is an island shape. The SiC part 35 is formed. Thus, as for the SiC substrate 1 of this embodiment, the surface layer part is divided into the some island-like SiC part 35 by the groove part 40. FIG. In addition, the SiC substrate 1 of the present embodiment is for forming a plurality of chips, and each of the rectangular portions of the SiC portion 35 excluding those located on the peripheral portion of the SiC substrate 1 forms a chip. It corresponds to each of the chip formation regions.

  FIG. 1B is a cross-sectional view taken along line Ib-Ib in FIG. As shown in FIG. 1B, the SiC substrate 1 of this embodiment includes a silicon substrate 10, an insulating layer 20 provided thereon, and a plurality of SiC portions 35 formed on the insulating layer 20. SiC layer 30. Further, the SiC substrate 1 of the present embodiment is configured to include an insulating part 45 in which an insulating material is embedded in the groove part 40.

  Next, an embodiment of a method for manufacturing a semiconductor substrate according to the present invention will be described using an example applied to the method for manufacturing the SiC substrate 1.

2A to 2F are cross-sectional process diagrams illustrating a method for manufacturing SiC substrate 1.
First, as shown in FIG. 2A, a base substrate 100 in which an insulating layer 20 and an Si layer 50 are sequentially formed on a support substrate 10 is prepared. In the present embodiment, a silicon substrate is used as the support substrate 10, the insulating layer 20 is made of SiO ₂ formed by a thermal oxidation method or the like, and the Si layer is made of single crystal silicon. . The SOI substrate (base substrate) 100 can be formed and used by a SIMOX method, a bonding method, or the like. Since the formed substrate has been commercialized, it can also be used.

  In the SIMOX method, high-energy oxygen ions are implanted into a silicon substrate (not shown), and the portion into which oxygen ions are implanted is thermally oxidized at a temperature of about 1400 ° C. to form an insulating layer, thereby forming an SOI substrate. Is the method. The bonding method is, for example, bonding a silicon substrate (not shown) whose both surfaces are thermally oxidized and a normal silicon substrate (not shown), and then polishing the exposed side of the thermally oxidized surfaces. Then, an SOI substrate is formed by exposing the Si layer. According to the SIMOX method, an insulating layer can be provided at a uniform depth from the surface, but crystal defects may occur in the surface layer on which oxygen ions have been implanted, that is, the Si layer. In this embodiment, from the viewpoint of reducing crystal defects, the SOI substrate 100 is formed by a bonding method and used in the subsequent steps.

  Next, as shown in FIG. 2B, the Si layer 50 of the SOI substrate 100 is thinned. The thickness of the thinned Si layer 50 is preferably about 3 to 10 nm, and in this embodiment is about 5 nm.

  Next, as shown in FIG. 2C, a groove 40 exposing the insulating layer 20 is formed in the Si layer 50 using a known resist method and etching technique, and the Si layer 50 is formed by the groove 40. A plurality of island-shaped Si portions 55 are partitioned. As will be described in detail later, if the number of the groove portions 40 is one or more, that is, if the Si layer 50 is partitioned into two or more Si portions 55, the effect of the present invention can be obtained, and the Si layer 50 can be finely divided. The higher the effect, the higher the effect. Therefore, it is preferable to finely partition the Si layer 50 to such an extent that no inconvenience occurs when forming chips or elements on the manufactured SiC substrate 1. In the present embodiment, the groove 40 is formed and the Si layer 50 is partitioned so that one chip formation region corresponds to one Si portion 55.

  Next, as shown in FIG. 2D, the Si portion 55 is carbonized to form a seed portion 65, and a seed layer 60 composed of the seed portion 65 is formed. Specifically, the intermediate body of the SiC substrate 1 having the Si portion 55 (see FIG. 2C) is left in a chamber where the atmospheric temperature can be controlled, for example, and hydrogen gas and silicon carbide-based gas are contained in the chamber. And the inside of the chamber is maintained at an atmospheric temperature of about 1200 ° C to 1500 ° C. The Si portion 55 is formed into a seed portion 65 made of SiC by carbonizing Si from the surface side thereof to form SiC, and through a state where Si and SiC obtained by carbonizing the Si are laminated. .

  In the state where Si and SiC carbonized with this are laminated (mixed state), the lattice constant is different between Si and SiC, so that stress acts in the thickness direction and the surface direction between Si and SiC. is doing. The amount of deformation in the thickness direction of SiC due to these stresses is small because the Si layer 50 is thinned as described above, and it is extremely rare that a crystal defect occurs in SiC due to this deformation. On the other hand, the deformation amount in the surface direction of Si and SiC is an amount corresponding to the area where the stress in the surface direction acts, that is, the contact area between Si and SiC.

  In the method of the present invention, since the Si layer 50 is partitioned into a plurality of island-like Si portions 55 by the groove portions 40, the Si portions 55 are not in direct contact with each other. Since the stress does not propagate beyond the space such as the groove 40, the stress in the surface direction between Si and SiC in each Si portion 55 does not propagate to the neighboring Si portion 55. Therefore, the amount of deformation in the surface direction of Si and SiC is an amount corresponding to the contact area between Si and SiC in each Si portion 55, that is, the area of each Si portion 55. Since the area of each Si portion 55 is smaller than the area of the undivided Si layer 50, the amount of deformation in the surface direction of Si and SiC in each Si portion 55 is smaller than that in the case where the Si layer 50 is not partitioned. SiC crystal defects due to the are suppressed. In this way, the seed portion 65 with very few SiC crystal defects can be formed.

  Next, as shown in FIG. 2 (e), the seed portion 65 is epitaxially grown to form the SiC portion 35, and the SiC layer 30 composed of the SiC portion 35 is formed. Specifically, for example, the intermediate body of the SiC substrate 1 on which the seed portion 65 is formed (see FIG. 2D) is left as it is in the chamber described above, and hydrogen gas and silicon carbide-based gas are left in the chamber. And the inside of the chamber is maintained at an atmospheric temperature of about 500 ° C to 1500 ° C. The SiC in the mixed gas can be crystallized on the SiC of the seed portion 65, and the SiC portion 35 can be formed by epitaxially growing the seed portion 65. As described above, since the seed part 65 is formed in a good crystal structure with few crystal defects, the SiC part 35 epitaxially grown based on the seed part 65 can also be formed in a good crystal structure.

  Next, as shown in FIG. 2F, in this embodiment, an insulating material 45 is embedded in the groove 40 to form an insulating part 45. Specifically, an insulating liquid material is applied to the intermediate body of the SiC substrate 1 on which the SiC layer 30 is formed (see FIG. 2E) by a liquid phase method such as a spin coat method, and the liquid material is applied. Pour into the groove 40. Then, after solidifying the liquid material, the intermediate body of the SiC substrate 1 on which the SiC layer 30 is formed is planarized by a CMP method or the like. As described above, SiC substrate 1 is obtained.

  According to the manufacturing method of the present invention as described above, since the Si layer 50 is partitioned into the plurality of Si portions 55, the amount of deformation of Si and SiC becomes small when the Si portion 55 is carbonized. Therefore, the seed part 65 with very few SiC crystal defects can be formed, and the seed part 65 can be epitaxially grown with a good crystal structure. Therefore, it is possible to form the SiC portion 35 having a good crystal structure with very few crystal defects, and it is possible to manufacture a high-quality SiC substrate 1 including the SiC layer 30 having a good crystal structure.

  Further, since the deformation amounts of Si and SiC are defined by the area of the Si portion 55, a high-quality SiC substrate can be manufactured similarly when a large-diameter SOI substrate is used. Therefore, an increase in crystal defects accompanying an increase in the diameter of the SiC substrate can be suppressed, and the SiC substrate can be manufactured with a good yield.

  Since the semiconductor substrate (SiC substrate) of the present invention manufactured as described above includes the SiC layer 30 having an extremely good crystal structure, an element having good characteristics can be formed on the SiC layer 30. Therefore, it is possible to manufacture a high-quality chip or device having an element with good characteristics. Moreover, since it can be set as a large-diameter and cheap SiC substrate, a chip | tip, a device, etc. can be manufactured efficiently using this, and the manufacturing cost of the manufactured chip | tip or device can also be reduced. it can.

  Further, as in the present embodiment, in the SiC substrate 1 for forming a plurality of chips, if the groove 40 is formed so that the chip formation region becomes the Si portion 55, the Si portion 55 is included in the chip formation region. Is carbonized and epitaxially grown SiC portion 35 is formed. Therefore, when the chip is formed on the manufactured SiC substrate 1, the step of partitioning the SiC layer 30 is omitted. Moreover, when partitioning the Si layer 50, the existing partition method can be diverted and used, and the process of partitioning the Si layer 50 is facilitated. Even if physical properties such as temperature characteristics and strength of the SiC substrate 1 are locally changed due to the formation of the groove portion 40 or the insulating portion 45, these influences are caused by a plurality of chip formation regions corresponding to each of the plurality of chip formation regions. It becomes uniform in the SiC part. Therefore, variation in the quality of the formed chip is prevented, and the chip can be formed satisfactorily.

  Further, as in the present embodiment, if the insulating portion 45 is formed by pouring (embedding) an insulating material into the groove portion 40, a chip is formed by forming elements, wirings, or the like on the manufactured SiC substrate 1. Further, it is possible to prevent a material such as an element or a wiring from flowing into or embedded in the groove portion 40. Therefore, these do not become foreign matters, and a chip can be formed satisfactorily.

In this embodiment, the insulating part 45 is formed by applying a liquid material by a liquid phase method. However, the insulating part 45 is formed by depositing an insulating material in the groove part 40 by a vapor phase method such as an evaporation method. Also good. Further, when the insulating portion 45 is formed, it may be flattened by an etch back method or the like instead of flattening by the CMP method. Further, in forming the groove 40, without using the resist method, and an etching pattern made of SiO ₂ or SiN as a mask may be etched. As the base substrate, an SOS substrate whose insulating layer is made of sapphire, an SOQ substrate whose insulating layer is made of quartz, or the like may be used, and a support substrate made of a material other than silicon may be used. In any case, the effect of the present invention can be obtained by using a base substrate in which an insulating layer and a Si layer are sequentially formed on a supporting substrate.

(Modification)
In the embodiment, the groove portion 40 is formed so that one Si portion 55 corresponds to one chip formation region. However, the number and arrangement of the groove portions 40 are designed according to the configuration of the chip, and the like. It is also possible to adopt a Si portion having a section different from the form. Hereinafter, some examples will be described for the Si portion in a section different from the embodiment.

FIGS. 3A and 3B are plan views showing a modification in which the section of the Si portion is modified.
FIG. 3A shows an example of an SiC substrate manufactured in the same manner as in the embodiment after forming a groove so that two or more Si portions are included in one chip formation region. In this modification, the chip formation region 80 includes two SiC portions 35A and 35B. Further, as in the above embodiment, an insulating portion is also formed in the groove portion 40 of this modification. For example, if an element is formed in each of the SiC portions 35A and 36B, the insulating portion becomes an element isolation region. It is supposed to function as. Further, an existing method for forming the element isolation region can be diverted. For example, since the groove portion can be formed by diverting the method of forming the trench, the process of forming the groove portion is facilitated and highly reliable.

  FIG. 3B shows an example of an SiC substrate manufactured in the same manner as in the above embodiment after forming a groove so that two or more chip forming regions are included in one Si portion. In this modification, one SiC part 35 includes four chip formation regions 81, 82, 83, and 84. In this way, the alignment margin can be made larger than in the case where the groove portion is formed so as to partition the Si portion corresponding to each of the chip formation regions 81, 82, 83, 84. Therefore, for example, it is not necessary to form a fine groove portion in order to form a fine chip, and it is possible to suppress a decrease in yield due to misalignment when manufacturing the chip.

  Note that the number and arrangement of the groove portions 40 are not limited to those in the above-described embodiment and the modified examples, and can be variously changed according to the size, forming method, application, and the like of the chip. A SiC substrate can also be manufactured by dividing the Si layer into a plurality of different sizes, whereby a SiC substrate having a plurality of different sizes of SiC portions can be obtained. Further, when one SiC portion is made to correspond to one chip formation region, for example, a linear groove portion is not formed so that a larger number of chip formation regions are included in the semiconductor substrate. These grooves may be formed and partitioned into staggered Si portions.

(A), (b) is a figure which shows the structure of the semiconductor substrate of this invention. (A)-(f) is sectional process drawing for demonstrating the manufacturing method of this invention. (A), (b) is a figure which shows the modification of the semiconductor substrate of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... SiC substrate (semiconductor substrate), 20 ... Insulating layer, 30 ... SiC layer, 35 ... SiC part,
40 ... groove, 45 ... insulating part, 50 ... Si layer, 55 ... Si part, 60 ... seed layer, 65 ... seed part, 100 ... SOI substrate (base substrate) )

Claims (7)

A method of manufacturing a semiconductor substrate having a SiC layer on an insulating layer,
A groove portion exposing the insulating layer is formed in the Si layer of the base substrate in which the insulating layer and the Si layer are sequentially formed on the support substrate, and the Si layer is partitioned into a plurality of island-shaped Si portions by the groove portion. Si section partitioning process,
A seed layer forming step of carbonizing the Si portion to form an island-shaped seed portion and forming a seed layer comprising the seed portion;
A method of manufacturing a semiconductor substrate, comprising: forming an island-like SiC portion by epitaxially growing the seed portion, and forming an SiC layer formed of the SiC portion.   The method of manufacturing a semiconductor substrate according to claim 1, further comprising a step of filling the groove with an insulating material after the SiC layer forming step. The semiconductor substrate is a semiconductor substrate for forming a plurality of chips, and has a plurality of chip formation regions corresponding to one of the formed chips,
3. The method of manufacturing a semiconductor substrate according to claim 1, wherein in the Si section partitioning step, a groove is formed so that one chip formation region corresponds to one Si section. The semiconductor substrate is a semiconductor substrate for forming a plurality of chips, and has a plurality of chip formation regions corresponding to one of the formed chips,
3. The method of manufacturing a semiconductor substrate according to claim 1, wherein in the Si part partitioning step, the groove part is formed so that two or more Si parts are included in one chip formation region. The semiconductor substrate is a semiconductor substrate for forming a plurality of chips, and has a plurality of chip formation regions corresponding to one of the formed chips,
3. The method of manufacturing a semiconductor substrate according to claim 1, wherein in the Si part partitioning step, the groove part is formed so that two or more chip formation regions are included in one Si part. A support substrate;
An insulating layer provided on the support substrate;
An SiC layer provided on the insulating layer and having a plurality of SiC portions that are partitioned by grooves and formed in an island shape;
In the SiC portion, an Si layer provided on the insulating layer is partitioned by the groove portion to form an island-shaped Si portion, and the Si portion is carbonized, and then the carbonized Si portion is a seed portion. And a semiconductor substrate formed by epitaxial growth.   The semiconductor substrate according to claim 6, wherein the groove is embedded with an insulating material.

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