JP2006222144A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device wherein a MOS transistor, having a strained silicon region, can be made high in its performance, and to provide its manufacturing method. <P>SOLUTION: The manufacturing method includes a step of forming a first SiGe layer (12) whose Ge concentration has a concentration gradient on a semiconductor substrate (11), a step of forming a second SiGe layer (13) with released strain on the first SiGe layer, a step of forming a groove (22) in the second SiGe layer as well as at least in a part of the first SiGe layer, and a step of heating the substrate entirely, after the groove has been finished and before the groove is embedded. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having a strained silicon region and a method for manufacturing the same.

  Conventionally, for the purpose of improving the performance of MOS transistors, a SiGe layer having a concentration gradient related to a germanium composition is formed on a silicon substrate, and a SiGe layer having a strain relaxation is formed, followed by forming a Si layer having a tensile stress. The method is used. By using the substrate formed by this method, the mobility of the MOS transistor can be improved.

  However, a problem with this method is that the dislocation density on the surface of the strained Si layer is extremely high. Without reducing this dislocation density, even if an LSI is formed on a strained Si layer, for example, only a transistor inferior in terms of leakage current or the like can be realized, and therefore cannot be put into practical use as a substrate for forming an LSI. .

In Patent Document 1, the SiGe layer is patterned with a photoresist, plasma etched, a trench is formed around the region, the substrate and the SiGe layer are thermally annealed in an inert atmosphere, and the SiGe layer is relaxed. A method for manufacturing a semiconductor substrate is disclosed.
JP 2003-229361 A

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can improve the performance of a MOS transistor having a strained silicon region.

  According to one embodiment of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a first SiGe layer having a Ge concentration gradient on a semiconductor substrate; and a second step of relaxing strain on the first SiGe layer. A step of forming a SiGe layer, a step of forming a groove in at least a part of the second SiGe layer and the first SiGe layer, and a step of embedding the groove after the formation of the groove. And heat treating the whole.

According to one embodiment of the present invention, a semiconductor device includes a semiconductor substrate, a first SiGe layer having a concentration gradient of Ge formed on the semiconductor substrate, and a strain relaxation formed on the first SiGe layer. A dislocation penetrating the surface of the second SiGe layer in a region of the partitioned second SiGe layer and at least a part of the first SiGe layer. Is a density of 1 × 10 ³ cm ⁻² or less.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which aims at the performance enhancement of the MOS transistor which has a distortion silicon area | region, and its manufacturing method can be provided.

  Hereinafter, embodiments will be described with reference to the drawings.

(First embodiment)
1 to 5 are diagrams showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention. Hereinafter, the manufacturing process of the semiconductor device according to the first embodiment will be described with reference to FIGS.

First, as shown in FIG. 1, on a single crystal silicon (Si) substrate 11, a single crystal SiGe graded layer 12 having a thickness of 2 μm and having a concentration gradient in which the Ge concentration continuously increases from 0% to 25%, It is formed by epitaxial growth using SiH ₄ and GeH ₄ as source gases. Further, on the single crystal SiGe graded layer 12, a SiGe epitaxial layer 13 having a thickness of 0.5 μm and containing a uniform concentration of Ge having a Ge concentration of 25% is formed.

  At this time, dislocations 21 are formed due to the difference in lattice constant between single crystal Si and single crystal SiGe. The dislocation 21 starts from the single-crystal SiGe graded layer 12 where the lattice constant changes, but the dislocation line (21) terminates at the surface of the crystal, and thus penetrates to the surface of the SiGe epitaxial layer 13. .

  Thereafter, the surface of the SiGe epitaxial layer 13 is smoothed by CMP. Further, after forming a mask (not shown) on the SiGe epitaxial layer 13 and patterning it, as shown in FIG. 2, a part of the SiGe epitaxial layer 13 and the SiGe graded layer 12 is formed by the RIE method. A plurality of grooves 22 are formed by etching up to the middle region of the dead layer 12. Thereafter, the mask is peeled off. Here, the area of the island-like SiGe region 20 divided by etching is 5 mm × 5 mm. Further, the groove 22 at the time of etching has a width of 0.5 μm. Here, the depth of the groove 22 may reach the silicon substrate 11.

  By heat-treating the entire substrate at, for example, 950 ° C. for 30 minutes in a hydrogen or nitrogen atmosphere, the dislocation lines (21) move toward a state of low energy as shown in FIG. Specifically, the dislocation line (21) penetrating to the surface of the SiGe epitaxial layer 13 changes to a state where it is terminated at the side surface of the region of the SiGe graded layer 12 partially removed by the RIE method. In this process, the driving force is to reduce the lattice distortion and shorten the dislocation lines in an energy disadvantageous state as much as possible. Since the surface may be roughened by this heat treatment, CMP may be performed after this heat treatment.

  Thereafter, as shown in FIG. 4, a 1 μm-thick SiGe layer 14 containing 25% Ge and having a relaxed strain is deposited on the entire surface, and the groove 22 formed by the RIE method is buried. At this time, a recess is formed immediately above the groove of the SiGe layer 14. Further, as shown in FIG. 5, a single-crystal Si layer 15 having a thickness of 50 nm and containing no Ge is deposited as an active layer on the SiGe layer 14. As a result, single-crystal Si is deposited on SiGe containing 25% Ge whose strain has been relaxed, so that a Si layer having tensile stress can be formed.

When the threading dislocation density observed on the surface of the strained Si layer formed by this method was measured, it was found to be in the range of 1 × 10 ⁰ to 1 × 10 ³ cm ⁻² . This dislocation density varies depending on the heat treatment conditions described later, the layout for forming the grooves, and the like, and can be 1 × 10 ¹ cm ⁻² or less. On the other hand, the threading dislocation density observed on the surface of the strained Si layer formed by the conventional method in the case where the groove was not formed was 1 × 10 ⁵ cm ⁻² . This is because, as long as the conventional method is used, a strained Si layer exists on the entire surface of the wafer, and the only place where the dislocation line can be terminated without penetrating the surface is the end portion (bevel region) of the wafer. It is done.

  In the first embodiment, the dislocations formed in individual islands do not spread to other islands by forming the SiGe region in which the strain is relaxed into an island shape by the grooves. In comparison, the dislocation density can be dramatically reduced.

  In the first embodiment, the size (area) of the SiGe region 20 divided into island shapes is 5 mm × 5 mm. However, the appropriate size can be defined in relation to the heat treatment conditions.

  FIG. 6 is a diagram showing the relationship of the dislocation density with respect to the length of one side of the square island region. In FIG. 6, when the shape of the island region is fixed to a square and its size is changed, the result of examining how the dislocation density changes depending on the heat treatment in the state of being processed into an island. Is shown. Here, the heat treatment atmosphere was fixed at hydrogen, the pressure was 10 Torr, and the time was 30 minutes. It can be seen that the larger the size of the island, the higher the temperature required to reduce the dislocation density. In an actual device, since the groove pattern is made to correspond to the device layout, various patterns of grooves can be used.

(Second Embodiment)
FIG. 7 is a cross-sectional view showing the configuration of the semiconductor device according to the second embodiment of the present invention. In the second embodiment, an LSI including a MOSFET having a strained channel is formed on the strained SiGe layer formed in the island shape shown in the first embodiment. In FIG. 7, the same parts as those in FIGS. In FIG. 7, 31 is a gate insulating film, 32 is a gate electrode, 33 is a sidewall insulating film, 34 is a diffusion layer, and 35 is an element isolation region.

  In this LSI manufacturing process, as shown in FIG. 7, the position where the trench 22 is formed coincides with the element isolation region 35, that is, the region where the MOSFET is formed is terminated by the RIE method. By making it not coincide with the region to be formed, it is possible to create a MOSFET in which no dislocation line penetrates the surface of the strained SiGe layer. In this MOSFET, the SiGe layer 14 in which the trench is buried does not finally remain.

  As a method for forming an island region, there are a method of matching a region where a groove is formed by the RIE method with a device isolation region, or a method of matching a dicing line region for dividing an LSI chip. That is, the position of the trench and the active region of the semiconductor element is not matched. Since the size of the island region differs depending on how the groove is taken, dislocations can be prevented from reaching the MOSFET by performing heat treatment according to each way.

In the island region formed by this method, the dislocation density was 1 × 10 ³ cm ⁻² or less. Moreover, in the SiGe layer having a concentration gradient, dislocations for relaxing the strain exist at high density, but 95% or more of them are terminated at the end of the island without penetrating the surface of the SiGe layer. It was confirmed that

  Compared with a MOSFET formed on a normal strained Si layer, the MOSFET produced in this way has a gate insulating film defective rate of 1/10 or less and a junction leakage current of 1/100 or less. I was able to.

  As described above, in this embodiment, after forming a SiGe layer having a concentration gradient and further forming a strain-relieved SiGe layer, the SiGe layer having at least the concentration gradient is reached by a lithography process and a dry etching process. By forming a groove having a depth, the substrate surface is processed into an island shape. Here, the shape of the island can be matched with the chip size of the LSI to be formed. After removing the resist, heat treatment is performed to move the end of the dislocation loop formed in the SiGe layer from the substrate surface to the end of the island, and thereafter, the strain of the SiGe layer is relaxed by CMP. Etch part to smooth the surface. Thereafter, a strain-reduced SiGe layer and strained Si layer are formed.

  As a result, a strained Si wafer having a low dislocation density existing on the substrate surface can be formed. As a result, a semiconductor device having a good gate insulating film breakdown voltage and low junction leakage can be realized.

  In addition, this invention is not limited only to the said embodiment, In the range which does not change a summary, it can deform | transform suitably and can be implemented.

The figure which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. The figure which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. The figure which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. The figure which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. The figure which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. The figure which shows the relationship of the dislocation density with respect to the length of one side of the square island area | region which concerns on the 1st Embodiment of this invention. Sectional drawing which shows the structure of the semiconductor device which concerns on the 2nd Embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Si substrate 12 ... SiGe layer with concentration gradient 13 ... Strain relaxation SiGe layer 14 ... SiGe layer 15 ... Strain Si layer 20 ... Island-like SiGe region 21 ... Dislocation 22 ... Groove 31 ... Gate insulating film 32 ... Gate electrode 33 ... sidewall insulating film 34 ... diffusion layer 35 ... element isolation region

Claims (5)

Forming a first SiGe layer having a Ge concentration gradient on a semiconductor substrate;
Forming a strain-relieved second SiGe layer on the first SiGe layer;
Forming a groove in the second SiGe layer and at least a portion of the first SiGe layer;
After the groove is formed, a step of heat treating the whole before the step of filling the groove;
A method for manufacturing a semiconductor device, comprising: Forming a strain-relaxed third SiGe layer on the second SiGe layer;
Forming a Si layer on the third SiGe layer;
The method of manufacturing a semiconductor device according to claim 1, wherein:   2. The method of manufacturing a semiconductor device according to claim 1, wherein the groove and the active region of the semiconductor element are not located at the same position. A semiconductor substrate;
A first SiGe layer having a concentration gradient of Ge formed on the semiconductor substrate;
A strain-relaxed second SiGe layer formed on the first SiGe layer,
In the divided region of the second SiGe layer and at least a part of the first SiGe layer, the density of dislocations penetrating the surface of the second SiGe layer is 1 × 10 ³ cm ⁻² or less. A semiconductor device characterized by the above.   The semiconductor device according to claim 4, wherein 95% or more of the dislocations are terminated at an end portion of the divided region.

Images