WO2013117153A1

WO2013117153A1 - Semiconductor structure and method for forming same

Info

Publication number: WO2013117153A1
Application number: PCT/CN2013/071388
Authority: WO
Inventors: Lei Guo; Yuan Li
Original assignee: Lei Guo; Yuan Li
Priority date: 2012-02-08
Filing date: 2013-02-05
Publication date: 2013-08-15

Abstract

A method for forming a semiconductor structure is provided. The method comprises steps of: providing a substrate (100); forming a first single crystal semiconductor layer (200) on the substrate (100); etching the first single crystal semiconductor layer (200) to form a plurality of holes or trenches extending to a top surface of the substrate (100), or etching the first single crystal semiconductor layer (200) and the substrate (100) to form a plurality of holes or trenches extending into the substrate (100); etching the substrate (100) through the plurality of holes or trenches to form a plurality of supporting structures (1001) in a region under the top surface of the substrate (100), thus forming a patterned structure; and depositing a single crystal semiconductor material to form a second single crystal semiconductor layer (300) on the patterned structure.

Description

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and benefits of the following applications:

( 1 ) Chinese Patent Application Serial No. 201210027899.7, filed with the State Intellectual Property Office of P. R. China on Feb. 8, 2012; and

( 2 ) Chinese Patent Application Serial No. 201210027900.6, filed with the State Intellectual Property Office of P. R. China on Feb. 8, 2012.

The entire contents of which are incorporated herein by reference.

FIELD

The present disclosure relates to semiconductor design and fabrication field, and more particularly to a semiconductor structure and a method for forming the same.

BACKGROUND

Recently, with a development of semiconductor technique, an integration of different types of heterogeneous semiconductor materials on one substrate has attracted more attentions, such as GaN on Si, GaAs on Si, Ge on Si, etc. Different applications such as a power semiconductor device, a photoelectric device or a high speed logic device, generally need different semiconductor materials. For example, taking into account of a breakdown voltage, a large band gap semiconductor material such as SiC or GaN is required by the power semiconductor device, a direct band gap semiconductor material such as GaAs or GaN is required by the photoelectric device, a semiconductor material such as SiGe is required by the high speed logic device.

In order to enable more complex functions on one chip, high quality heterogeneous semiconductor materials are required to be obtained on a single substrate. However, these materials are significantly different from a material of the substrate in characteristics. For example, a difference of a lattice structure or a lattice constant may result in a high dislocation density which seriously affects a device performance; a difference of thermal expansion coefficient may result in a crack of a heterogeneous material film on the substrate, even of the whole wafer, during a cooling stage of an epitaxy process. To this end, a technique for forming heterogeneous semiconductor materials on a single substrate is urgently needed. SUMMARY

The present disclosure is aimed to solve at least one of the defects.

According to an aspect of the present disclosure, a method for forming a semiconductor structure is provided. The method comprises steps of: providing a substrate; forming a first single crystal semiconductor layer on the substrate; etching the first single crystal semiconductor layer to form a plurality of holes or trenches extending to a top surface of the substrate, or etching the first single crystal semiconductor layer and the substrate to form a plurality of holes or trenches extending into the substrate; etching the substrate through the plurality of holes or trenches to form a plurality of supporting structures in a region under the top surface of the substrate, thus forming a patterned structure; and depositing a single crystal semiconductor material to form a second single crystal semiconductor layer on the patterned structure.

In one embodiment, depositing a single crystal semiconductor material to form a second single crystal semiconductor layer on the patterned structure comprises: epitaxially laterally growing a single crystal semiconductor material on a lateral surface of the first single crystal semiconductor layer exposed in the plurality of holes or trenches.

In one embodiment, after epitaxially laterally growing a single crystal semiconductor material on a lateral surface of the first single crystal semiconductor layer exposed in the plurality of holes or trenches, the method further comprises: epitaxially longitudinally growing and then epitaxially laterally over-growing the single crystal semiconductor material on a top surface of the first single crystal semiconductor layer to form the second single crystal semiconductor layer. By such an epitaxial lateral overgrowth (ELOG) process, a dislocation density is significantly reduced.

In one embodiment, the substrate has a patterned surface.

In one embodiment, before forming a first single crystal semiconductor layer on the substrate, the method further comprises: forming a buffer layer on the substrate.

In one embodiment, the buffer layer has a single-layer structure, a multi-layer superlattice structure or a multi- layer interlaced structure.

In one embodiment, etching the first single crystal semiconductor layer to form a plurality of holes or trenches extending to a top surface of the substrate, or etching the first single crystal semiconductor layer and the substrate to form a plurality of holes or trenches extending into the substrate comprises: forming a mask layer on the first single crystal semiconductor layer; etching the mask layer to form a plurality of openings; and etching the first single crystal semiconductor layer to form a plurality of holes or trenches extending to a top surface of the substrate, or etching the first single crystal semiconductor layer and the substrate to form a plurality of holes or trenches extending into the substrate.

In one embodiment, a material of the substrate comprises any one of Si, SiGe, SiC, GaAs, Ge, GaN, GaP, InP, Ga₂0₃, A1₂0₃, A1N, ZnO, LiGa0₂ and LiA10₂.

In one embodiment, etching the substrate through the plurality of holes or trenches to form a plurality of supporting structures in a region under the top surface of the substrate comprises: etching the substrate by a wet etch, a dry etch or an electrochemical etch when the substrate is conductive; and etching the substrate by a wet etch or a dry etch when the substrate is nonconductive.

In one embodiment, the method further comprises: implanting different types and/or different concentrations of doping elements in different regions of the substrate to selectively etch redundant parts of the substrate and thus remaining a plurality of supporting structures.

In one embodiment, the method further comprises: implanting different types and/or different concentrations of doping elements into the substrate to form a plurality of etch resistant structures below a top surface of the substrate, which enables a lateral etching during a process of forming the plurality of supporting structures.

In one embodiment, a material of the first single crystal semiconductor layer comprises any one of group IV semiconductors Ge, SiGe, SiC; group III-V semiconductors GaN, InGaN, A1N, AlGaN, InN, AlGalnN, GaAs, GaP, AlGalnP; group II- VI semiconductors ZnO, Ga₂0₃, ZnS, ZnSe, PbSe, CdS, CdTe; and a combination thereof.

In one embodiment, the method further comprises: if a material of the substrate is Si, after etching the substrate through the plurality of holes or trenches to form a plurality of supporting structures, processing the substrate in a nitrogenous and/or oxygenous ambience to enable each supporting structure to react with the nitrogenous and/or the oxygenous ambience to form an isolation structure. In this embodiment, a material of the isolation structures is Si0₂, SiON or SiN. In one aspect, single crystal Si becomes amorphous oxide or nitride, which is more advantageous for releasing a thermal mismatch stress; in another aspect, the isolation structures may be helpful to separate the Si substrate from the first single crystal semiconductor layer during a late fabrication process of a device (such as an LED) so that the Si substrate can be recycled. In one embodiment, the first single crystal semiconductor layer and/or the second single crystal semiconductor layer have a multi- layer compound semiconductor structure.

In one embodiment, the method further comprises: dividing the substrate into a plurality of blocks by deep trench etching to prevent a stress accumulation in a large scale.

With the method according to embodiments of the present disclosure, the substrate may use a low cost rough material (such as a Si wafer), a high quality heterogeneous thin film may be obtained, and a process is simple and realizable. Moreover, a stress resulted from thermal mismatch may be effectively released by the plurality of supporting structures, which is advantageous for further fabricating a large size single crystal semiconductor layer thereon, such as the second single crystal semiconductor layer with a very large thickness (above dozens of microns) and a large diameter (a basic size may be up to 8-12 inches even 18 inches). What is more important, the plurality of supporting structures are formed subsequent to forming the first single crystal semiconductor layer, and thus many unfavorable factors resulted from a direct epitaxy of heterogeneous materials on the plurality of supporting structures are avoided. Therefore, a perfect interface between the plurality of supporting structures and the first single crystal semiconductor layer can be ensured. Meanwhile, a growth quality of the first single crystal semiconductor layer and the second single crystal semiconductor layer can be ensured.

According to another aspect of the present disclosure, a semiconductor structure is provided. The semiconductor structure comprises: a substrate; a plurality of supporting structures formed on a top surface of the substrate; a first single crystal semiconductor layer formed on the plurality of supporting structures, a plurality of holes or trenches buried in the first single crystal semiconductor layer and extending to the top surface of the substrate; and a second single crystal semiconductor layer formed on the first single crystal semiconductor layer, covering and extending to the plurality of holes or trenches.

In one embodiment, the substrate has a patterned surface.

In one embodiment, the semiconductor structure further comprises a buffer layer formed on the substrate.

In one embodiment, the semiconductor structure further comprises a mask layer formed on the first single crystal semiconductor layer, wherein the mask layer is divided into a plurality of discrete masks by the plurality of holes or trenches.

In one embodiment, a material of the substrate comprises any one of Si, SiGe, SiC, GaAs, Ge, GaN, GaP, InP, Ga₂0₃, A1₂0₃, A1N, ZnO, LiGa0₂, and LiA10₂.

In one embodiment, the plurality of supporting structures are formed by a wet etch, a dry etch or an electrochemical etch when the substrate is conductive; and the plurality of supporting structures are formed by a wet etch or a dry etch when the substrate is nonconductive.

In one embodiment, the semiconductor structure further comprises a plurality of etch resistant structures formed below the top surface of the substrate by implanting different types and/or different concentrations of doping elements in the substrate.

In one embodiment, the semiconductor structure further comprises an isolation structure formed by a reaction of each supporting structure with a nitrogenous and/or oxygenous ambience, if a material of the substrate is Si.

In one embodiment, the first single crystal semiconductor layer and/or the second single crystal semiconductor layer have a multi- layer compound semiconductor structure.

In one embodiment, the substrate further comprises a plurality of deep trenches, by which the substrate is divided into a plurality of blocks to prevent a stress accumulation in a large scale.

The semiconductor structure according to embodiments of the present disclosure has advantages of low dislocation density, high quality thin film and low material cost. Moreover, a stress resulted from thermal mismatch may be effectively released by the plurality of supporting structures.

Additional aspects and advantages of the embodiments of the present disclosure will be given in part in the following descriptions, become apparent in part from the following descriptions, or be learned from the practice of the embodiments of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other aspects and advantages of the disclosure will become apparent and more readily appreciated from the following descriptions taken in conjunction with the drawings in which:

Figs. 1-12 are schematic cross-sectional views of intermediate statuses of a semiconductor structure formed in steps of a method for fabricating a semiconductor structure according to a first embodiment of the present disclosure;

Figs. 13-23 are schematic cross-sectional views of intermediate statuses of a semiconductor structure formed in steps of a method for fabricating a semiconductor structure according to a second embodiment of the present disclosure;

Fig. 24 is a schematic cross-sectional view of the semiconductor structure according to the first embodiment of the present disclosure;

Fig. 25a is a schematic cross-sectional view of the semiconductor structure according to another embodiment of the present disclosure;

Fig. 25b is a schematic top view of the semiconductor structure according to the another embodiment of the present disclosure; and

Fig. 26 is a schematic cross-sectional view of the semiconductor structure according to the second embodiment of the present disclosure.

DETAILED DESCRIPTION

Embodiments of the present disclosure will be described in detail in the following descriptions, examples of which are shown in the accompanying drawings, in which the same or similar elements and elements having same or similar functions are denoted by like reference numerals throughout the descriptions. The embodiments described herein with reference to the accompanying drawings are explanatory and illustrative, which are used to generally understand the present disclosure. The embodiments shall not be construed to limit the present disclosure.

It is to be understood that phraseology and terminology used herein with reference to device or element orientation (such as, terms like "longitudinal", "lateral", "front", "rear", "right", "left", "lower", "upper", "horizontal", "vertical", "above", "below", "up", "top", "bottom" as well as derivative thereof such as "horizontally", "downwardly", "upwardly", etc.) are only used to simplify description of the present invention, and do not alone indicate or imply that the device or element referred to must have or operated in a particular orientation.

In addition, terms such as "first" and "second" are used herein for purposes of description and are not intended to indicate or imply relative importance or significance or imply a number of technical features indicated. Therefore, a "first" or "second" feature may explicitly or implicitly comprise one or more features. Further, in the description, unless indicated otherwise, "a plurality of refers to two or more.

Terms concerning attachments, coupling and the like, such as "connected" and "interconnected", refer to a relationship wherein structures are secured or attached to one another either directly or indirectly through intervening structures, as well as both movable or rigid attachments or relationships, unless expressly described otherwise.

A semiconductor structure is provided according to the present disclosure. Figs. 1-12 are schematic cross-sectional views of intermediate statuses of the semiconductor structure formed in steps of the method for forming the semiconductor structure according to a first embodiment.

As shown in Figs. 1-12, the method for forming the semiconductor structure comprises following steps.

In step S101, as shown in Fig. 1, a substrate 100 is provided.

The substrate 100 may have a patterned surface. For example, the substrate 100 may be a patterned Si substrate or a patterned sapphire substrate. Such patterned substrate may be favorable for a reduction of a dislocation density of an epitaxial layer formed thereon, as well as for an emission of LED light.

A material of the substrate 100 comprises any one of Si, SiGe, SiC, GaAs, Ge, GaN, GaP, InP, Ga₂0₃, A1₂0₃, A1N, ZnO, LiGa0₂ and LiA10₂. Preferably, the substrate 100 is a Si substrate, which is not only low-cost and easy to be doped, but also easy to react to form a hetero isolation structure.

In step S102, as shown in Figs. 2-4, different types and/or different concentrations of doping elements are implanted in different regions under a top surface of the substrate to form a plurality of supporting structures 1001 and a plurality of etch regions 1002 alternately distributed. There is an etch resistant structure 1003 under a bottom surface of each etch region 1002, while a bottom region 1000 of the substrate remaining unchanged.

Specifically, as shown in Fig. 2, taking a Si substrate as example, firstly, a plurality of regions under the top surface of the substrate 100 are lightly doped or non-doped to form the plurality of resistant structures 1003. Secondly, as shown in Fig. 3, the substrate 100 is heavily doped at a smaller depth below the top surface of the substrate 100 to form the plurality of separated etch regions 1002. Thirdly, as shown in Fig. 4, a region between every two adjacent etch regions 1002 is lightly doped or non-doped to form the plurality of supporting structures 1001. In a preferred embodiment, a lightly doped or non-doped Si wafer is used as a substrate. The plurality of separated etch regions 1002 may be heavily doped by using lithography and ion implantation. The bigger the doping dose is, the higher the etching rate is. It should be noted that, this embodiment is explanatory and illustrative, but not construed to limit the present disclosure. Other doping processes may be adopted in practice, provided that when etching different regions, respective etching rate satisfies "Vioo2>Vioo3

It should be noted that, it will be easy to realize a selective etching in a following process for the substrate 100 processed by step SI 02. However, if step SI 02 is skipped, in order to form the plurality of supporting structures, a precise control is required in the following etch process.

Alternatively, an area of each etch region 1002 is larger than that of each supporting structure 1001. Preferably, the area of each etch region 1002 is twice larger than that of each supporting structure 1001.

In step SI 03, as shown in Fig. 5, a first single crystal semiconductor layer 200 is formed on the substrate 100.

A material of the first single crystal semiconductor layer 200 comprises any one of group IV semiconductors Ge, SiGe, SiC; group III-V semiconductors GaN, InGaN, A1N, AlGaN, InN, AlGalnN, GaAs, GaP, AlGalnP; group II- VI semiconductors ZnO, Ga₂0₃, ZnS, ZnSe, PbSe, CdS, CdTe; and a combination thereof, such as a combination of a AIN/GaN layer and a GaAs/AlGaAs layer.

The first single crystal semiconductor layer 200 may have a multi-layer compound structure. In this embodiment, the multi-layer compound structure may be a superlattice structure, a compound structure with gradient distribution (gradually increasing) of composition (such as a SiGe layer with gradient distribution of Ge), or a compound structure with different compositions distributed alternatively (such as GaN and A1N distributed alternatively).

In step S104, as shown in Fig. 6, the first single crystal semiconductor layer 200 is etched to form a plurality of openings. The plurality of openings are in alignment with the plurality of etch resistant structures 1002 in a vertical direction respectively. By this means, the first single crystal semiconductor layer 200 becomes a plurality of first single crystal semiconductor structures (still denoted as 200).

Then the substrate 100 is etched from the plurality of openings to form a plurality of holes or trenches extending into the substrate 100. Preferably, a depth of each hole or trench is greater than a width of each hole or trench. Alternatively, this step may be skipped. In this case, the plurality of openings formed in step S103 are equal to the plurality of holes or trenches, that is, the plurality of holes or trenches extends to the top surface of the substrate 100.

In step S105, as shown in Figs. 7 and 8, the substrate 100 is etched through the plurality of holes or trenches to form a plurality of supporting structures 1001 in a region under the top surface of the substrate 100, thus forming a patterned structure.

When the substrate 100 is conductive, the substrate 100 may be etched by a wet etch, a dry etch or an electrochemical etch, and a selective etch or remaining may be realized according to different doping dose and/or type of respective material. For example, for the Si substrate, the plurality of supporting structures 1001 are formed by the electrochemical etch with HF as an etching regent. Since the smaller a resistivity is, the higher the etching rate is, by controlling the resistivity and/or the doping type of the first single crystal semiconductor layer 200, the plurality of supporting structures 1001 can be formed while the first single crystal semiconductor layer 200 is hardly etched. Specifically, as shown in Fig. 7, an anodic oxidation may be adopted so as to selectively remove the p-type heavily doped etch regions 1002 and remain the n-type doped supporting structures 1001. In this case, the n- typed etch resistant structures 1003 are used for preventing an over deep electrochemical etch. Then as shown in Fig. 8, the etch regions 1002 are etched, while remaining the supporting structures 1001.

In a preferred embodiment, a lightly doped or non-doped Si wafer is used as a substrate. The plurality of separated etch regions 1002 may be heavily doped by using lithography and ion implantation. A precisely controlled wet etch process may be adopted to selectively remove the etch regions 1002, by using HF/HNO₃/H₂O as etchant.

When the substrate 100 is nonconductive, the substrate 100 may be etched by a wet etch or a dry etch, and the selective etch or remaining may be realized by controlling etch time. By controlling the resistivity of the first single crystal semiconductor layer 200, the plurality of supporting structures 1001 can be formed while the first single crystal semiconductor layer 200 is hardly etched. Specifically, as shown in Fig. 8, in the substrate 100, the etch regions 1002 are etched, while remaining the supporting structures 1001. If the wet etch is adopted, firstly, the substrate may be processed by an ion implantation so that a crystal structure of the etch regions 1002 of the substrate is damaged, which is favorable for the formation of the plurality of supporting structures.

Preferably, an area of each supporting structure 1001 is less than that of etch first single crystal semiconductor structure 200 so that a follow-up grown single crystal semiconductor film (i.e., the second single crystal semiconductor layer 300) is easy to be separated from the bottom region 1000 of the substrate by the plurality of supporting structures 1001.

In order to better release an stress of an epitaxial film, an lateral size of etch supporting structure is generally less than a micron order. Preferably, a length and/or a width is less than lOOnm.

In step SI 06, as shown in Fig. 9, if the material of the substrate is Si, after etching the substrate through the plurality of holes or trenches to form the plurality of supporting structures, under a high temperature condition or in a plasma ambiance with a relative high temperature, the substrate is processed in a nitrogenous and/or oxygenous ambience (such as any one of 0₂, H₂0, NH₃, N₂, O3, oxygen plasma, nitrogen plasma and a combination thereof) to enable each supporting structure to react with the nitrogenous and/or the oxygenous ambience to form an isolation structure (arrows shown in Fig. 9 represent inputting a reaction gas). In this embodiment, exposed parts of the supporting structures (Si or SiGe) react with the nitrogenous and/or the oxygenous ambience to form the isolation structure (Si0₂, SiON or SiN). Preferably, NH₃ is input to react with Si or SiGe (the material of the supporting structures) to form amorphous SiN, while the first single crystal semiconductor layer (such as GaN or AIN) remaining unchanged. Each supporting structure thus becomes the hetero isolation structure.

It should be noted that, the step SI 06 is an optional step, which can be skipped when the material of the substrate 100 is not Si or SiGe. The isolation layer formed in this step is different from the substrate in material. Moreover, the amorphous isolation layer (such as amorphous SiN), in one aspect, is more favorable for a release of the thermal mismatch stress, in another aspect, may be as served a lift-off layer to separate the substrate from the first single crystal semiconductor layer, thus conveniently realizing a transfer of an epitaxial film and a recycling of the substrate. In step S107, as shown in Figs. 10-12, a single crystal semiconductor material is deposited to form a second single crystal semiconductor layer 300 on the patterned structure. The single crystal semiconductor material may be firstly epitaxially laterally grown on a lateral surface of the first single crystal semiconductor layer 200 exposed in the plurality of holes or trenches. After a while, the plurality of holes or trenches are filled with the single crystal semiconductor material, and the single crystal semiconductor material may be epitaxially longitudinally grown and then continuously epitaxially laterally over-grown until the second single crystal semiconductor layer 300 is formed on the patterned structure. In Figs. 10-12, bold-faced arrows represent a flow of a gas source of the single crystal semiconductor material, while light-faced arrows represent a growth direction of the single crystal semiconductor material.

A material of the second single crystal semiconductor layer 300 may also comprise any one of group IV semiconductors Ge, SiGe, SiC; group III-V semiconductors GaN, InGaN, A1N, AlGaN, InN, AlGalnN, GaAs, GaP, AlGalnP; group II- VI semiconductors ZnO, Ga₂0₃, ZnS, ZnSe, PbSe, CdS, CdTe; and a combination thereof. Alternatively, the second single crystal semiconductor layer 300 may have a multi- layer compound structure.

For the semiconductor of diamond structure (such as Ge, SiGe or SiC) or semiconductor of sphalerite structure (such as GaAs, GaP), as shown in Fig. 12, the single crystal semiconductor material may be directly deposited on the patterned structure. By this means, the plurality of openings are covered by a thick epitaxial layer, thus forming the whole second single crystal semiconductor layer 300.

For the semiconductor of wurtzite structure (such as GaN, InGaN or A1N), as shown in Figs. 10-12, the second single crystal semiconductor layer 300 may be formed based on a characteristic that a lateral growth rate is greater than a longitudinal growth rate in a special process. Specifically, during the deposition of GaN, InGaN or A1N, the single crystal semiconductor material is firstly epitaxially laterally grown on a lateral surface of the first single crystal semiconductor layer 200 exposed in the plurality of holes or trenches. After a while, the plurality of holes or trenches are filled with the single crystal semiconductor material, and the single crystal semiconductor material is first epitaxially longitudinally grown and then epitaxially laterally over-grown, until the whole second single crystal semiconductor layer 300 is formed on the patterned structure, in which an epitaxial lateral overgrowth (ELOG) process is adopted. Because the second single crystal semiconductor layer 300 is mainly formed by lateral growth, the second single crystal semiconductor layer 300 has a very low dislocation density, thus improving a growth quality thereof. Alternatively, the ELOG process may be replaced by a one-step epitaxial growth or other deposition process.

Preferably, except all above steps, the method may further comprise: dividing the substrate into a plurality of blocks by deep trench etching to prevent a stress accumulation in a large scale. This step may be performed prior to any of the above steps. Preferably, this step is performed accompany with step SI 03 and step SI 04. Because deep trenches are wide, the second single crystal semiconductor layer 300 is disconnected at each deep trench to reduce the stress accumulation.

Figs. 13-23 are schematic cross-sectional views of intermediate statuses of the semiconductor structure formed in steps of the method for forming the semiconductor structure according to a second embodiment.

As shown in Figs. 13-23, the method for forming the semiconductor structure comprises following steps.

In step S201, as shown in Fig. 13, a substrate 100 is provided.

In step S202, as shown in Figs. 14-16, different types and/or different concentrations of doping elements are implanted in different regions under a top surface of the substrate to form a plurality of supporting structures 1001 and a plurality of etch regions 1002 alternately distributed. There is an etch resistant structure 1003 under a bottom surface of each etch region 1002, while a bottom region 1000 of the substrate remaining unchanged.

Specifically, as shown in Fig. 14, taking a Si substrate as example, firstly, a plurality of regions under the top surface of the substrate 100 are lightly doped or non-doped to form the plurality of resistant structures 1003. Secondly, as shown in Fig. 15, the substrate 100 is heavily doped at a smaller depth below the top surface of the substrate 100 to form the plurality of separated etch regions 1002. Thirdly, as shown in Fig. 16, a region between every two adjacent etch regions 1002 is lightly doped or non-doped to form the plurality of supporting structures 1001. In a preferred embodiment, a lightly doped or non-doped Si wafer is used as a substrate. The plurality of separated etch regions 1002 may be heavily doped by using lithography and ion implantation. The bigger the doping dose is, the higher the etching rate is. It should be noted that, this embodiment is explanatory and illustrative, but not construed to limit the present disclosure. Other doping processes may be adopted in practice, provided that when etching different regions, respective etching rate satisfies "Vioo2>Vioo₃

In step S203, as shown in Fig. 17, a buffer layer 110, a first nitride semiconductor layer 200 and a mask layer 210 are sequentially formed on the substrate 100.

Specifically, the buffer layer 110 may have a single-layer low temperature structure (such as an A1N layer), a multi- layer super lattice structure (such as an AIN/AlGaN multi- layer) or a multi-layer interlaced structure (such as a multi-layer combination of AlN/GaN). A material of the first nitride semiconductor layer 200 comprises any one of GaN, InGaN, A1N, AlGaN, InN, AlGalnN and a combination thereof (such as a multi-layer combination of AIN/AlGaN or AlN/GaN). In a preferred embodiment, the first nitride semiconductor layer 200 is the A1N layer or the double-layer combination of AlN/GaN. A material of the mask layer 210 comprises any one of Si0₂, Si_xNi-_x, Hf0₂, Zr0₂, A1₂0₃ and a photo resist.

It should be noted that, a provision of the buffer layer 110 or the mask layer 210 is optional. Alternatively, step S202 may comprise: sequentially forming a first nitride semiconductor layer 200 and a mask layer 210 on the substrate 100.

In step S204, also as shown in Fig. 17, a plurality of openings are formed by etching the mask layer 210. The plurality of openings are in alignment with the plurality of etch resistant structures 1001 in a vertical direction respectively, By this means, the mask layer 210 becomes a plurality of discrete masks.

In step S205, as shown in Fig. 18, the first nitride semiconductor layer 200, the buffer layer 110 and the substrate 100 are etched from the plurality of openings to form a plurality of holes or trenches extending into the substrate 100 (that is, extending into the etch regions 1002). Preferably, a depth of each hole or trench is greater than a width of each hole or trench. Alternatively, the first nitride semiconductor layer 200 and the buffer layer 110 are etched from the plurality of openings to form a plurality of holes or trenches extending to the top surface of the substrate 100.

In step S206, as shown in Fig. 19, the substrate 100 is etched through the plurality of holes or trenches to form a plurality of supporting structures in a region under the top surface of the substrate 100, thus forming a patterned structure, that is, the etch region 1002 becomes the plurality of supporting structures 1001. Specifically, the substrate 100 may be etched by any one of an electrochemical etch, a wet etch, a dry etch and a combination thereof.

In step S207, as shown in Fig. 20, if the material of the substrate is Si, after step S206, under a high temperature condition or in a plasma ambiance with a relative high temperature, the substrate is processed in a nitrogenous and/or oxygenous ambience (such as any one of 0₂, H₂0, NH₃, N₂, O3, oxygen plasma, nitrogen plasma and a combination thereof) to enable etch supporting structure to react with the nitrogenous and/or the oxygenous ambience to form an isolation structure (arrows shown in Fig. 20 represent inputting a reaction gas). In this embodiment, exposed parts of the supporting structures (Si or SiGe) react with the nitrogenous and/or the oxygenous ambience to form the isolation structure (Si0₂ or SiN). Preferably, NH₃ is input to react with Si or SiGe (the material of the supporting structures) to form amorphous SiN, while the first nitride semiconductor layer (such as GaN or A1N) remaining unchanged. Etch supporting structure thus becomes the hetero isolation structure.

It should be noted that, the step S207 is an optional step, which can be skipped when the material of the substrate 100 is not Si or SiGe. The isolation layer formed in this step is different from the substrate in material. Moreover, the amorphous isolation layer (such as amorphous SiN), in one aspect, is more favorable for a release of the thermal mismatch stress, in another aspect, may be as a lift-off layer to separate the substrate from the first single crystal semiconductor layer, thus conveniently realizing a transfer of an epitaxial film and a recycling of the substrate.

In step S208, as shown in Figs. 21-23, a nitride semiconductor material is deposited to form a second nitride semiconductor layer 300 on the patterned structure. The nitride semiconductor material is firstly epitaxially laterally grown on a lateral surface of the first nitride semiconductor layer 200 exposed in the plurality of holes or trenches. After a while, the plurality of holes or trenches are filled with the nitride semiconductor material, and the nitride semiconductor material may be epitaxially longitudinally grown and then continuously epitaxially laterally over-grown until the second nitride semiconductor layer 300 is formed on the patterned structure. Because the second nitride semiconductor layer 300 is formed by a lateral growth, the second nitride semiconductor layer 300 has a very low dislocation density, thus improving a growth quality thereof.

A material of the second nitride semiconductor layer 300 may also comprise any one of GaN, InGaN, A1N, AlGaN, InN, AlGalnN and a combination thereof (such as a multi-layer combination of AlGaN/InGaN, AlGaN/GaN, AlGaN/GaN/InGaN or InGaN/GaN). Preferably, the second nitride semiconductor layer 300 is a GaN layer.

It should be noted that, when the mask layer 210 is a photo resist layer, it needs to be removed after step S206. In step S208, alternatively, the second nitride semiconductor layer 300 may be directly formed on the first nitride semiconductor layer 300 by the ELOG process.

In this embodiment, the lateral epitaxial growth of the second nitride semiconductor layer 300 may be realized by controlling a growth condition. In Figs. 21-23, bold-faced arrows represent a flow of a gas source of the nitride semiconductor material, while light-faced arrows represent a growth direction of the nitride semiconductor material. Taking GeN as an example, a growth mode of GaN mainly depends on a growth temperature and a pressure in a growth chamber. The higher the growth temperature is and the lower the pressure is, the more dominant the lateral growth is. Contrarily, the longitudinal growth is more dominant. A preferred growth condition of GaN may be as follows: the growth temperature is 1100 °C , the pressure in the growth chamber is lOOTorr, trimethylg allium is as a gallium source, and NH₃ is as a nitrogen source. If GaN needs to be doped, a certain amount of S1H₄ may be used as an n-type doping source, and a certain amount of Cp₂Mg may be used as a p-type doping source. As shown in Fig. 21, since the lateral growth rate of GaN in the holes or trenches is greater than the longitudinal growth rate of GaN in the holes or trenches, and the depth of the holes or trenches is greater than a width of the openings, upper parts of the holes or trenches are filled with GaN by the lateral growth, while lower parts of the holes or trenches remaining unfilled or semi-filled. As shown in Fig. 22, after depositing for a while, both upper parts of the holes or trenches are filled and the openings are sealed with GaN, and then GaN is further epitaxially grown to form a lug boss on each opening. As shown in Fig. 23, GaN is continuously grown on the plurality of discrete masks by the ELOG process to form the whole second nitride semiconductor layer 300. In this embodiment, the lateral growth is favorable for a reduction of a dislocation density of GaN, thus improving a thickness and a growth quality of the film.

The method according to embodiments of the present disclosure has following advantages.

(1) For the semiconductor of wurtzite structure, the second single crystal semiconductor layer may be formed on the first single crystal semiconductor layer by the lateral growth. The dislocation density of the epitaxial film can be reduced, and the film quality is improved. More importantly, since a surface of the first single crystal semiconductor layer is different from that of the supporting structure and is more suitable for growing the second single crystal semiconductor layer, an epitaxial growth quality of the second single crystal semiconductor layer is further improved.

(2) The plurality of holes or trenches and the micro/nano-size supporting structures are advantageous for releasing the thermal mismatch stress resulted from the film growth process, thus preventing the film from cracking when the epitaxial thickness of the film is larger, and improving the epitaxial thickness and growth quality of the film. It means that it is possible to use the low cost but high thermal mismatch material (such as Si) as the substrate, and it is also favorable for an LED vertical structure. More importantly, since the plurality of holes or trenches and the supporting structures are formed after a formation of the first single crystal semiconductor layer, the growth quality of the first single crystal semiconductor layer is not affected by a surface problem of the plurality of holes or trenches and the supporting structures. Thus, the high quality first single crystal semiconductor layer may be obtained. Accordingly, the high quality second single crystal semiconductor layer may be obtained.

(3) The etch regions are removed and the supporting structures are remained so that the semiconductor structure obtained is easy to be separated from the substrate. Particularly for the Si or SiGe substrate, each supporting structure reacts to form the hetero isolation structure to further release stress. Moreover, the isolation structure is favorable for the separation of the substrate. (4) The substrate is divided into a plurality of blocks by deep trench etching, which in one aspect, prevents the stress accumulation in the large scale, and in another aspect, is favorable for division of device.

(5) The low cost material (such as Si) is used as the substrate material. The process is simple and the fabrication cost is low.

Fig. 24 is a schematic cross-sectional view of the semiconductor structure according to the first embodiment of the present disclosure.

As shown in Fig. 24, the semiconductor structure comprises: a substrate 100, a first single crystal semiconductor layer 200, a plurality of supporting structures 1001, a second single crystal semiconductor layer 300 and a plurality of holes or trenches. The plurality of supporting structures are formed on a top surface of the substrate 100 for reducing a thermal stress resulted from a growth process of semiconductor materials. The first single crystal semiconductor layer 200 is formed on the plurality of supporting structures. The plurality of holes or trenches are buried in the first single crystal semiconductor layer 200 and extend to the top surface of the substrate. The second single crystal semiconductor layer 300 is formed on the first single crystal semiconductor layer 200, covering and extending to the plurality of holes or trenches.

A material of the substrate 100 may comprise any one of Si, SiGe, SiC, GaAs, Ge, GaN, GaP, InP, Ga₂0₃, A1₂0₃, A1N, ZnO, LiGa0₂ and LiA10₂.

The plurality of supporting structures are formed by a wet etch or a dry etch or an electrochemical etch when the substrate 100 is conductive; and the supporting structure is formed by a wet etch or a dry etch when the substrate 100 is nonconductive.

Materials of the first single crystal semiconductor layer 200 and the second single crystal semiconductor layer 300 may comprise any one of group IV semiconductors Ge, SiGe, SiC; group III-V semiconductors GaN, InGaN, A1N, AlGaN, InN, AlGalnN, GaAs, GaP, AlGalnP; group II- VI semiconductors ZnO, Ga₂0₃, ZnS, ZnSe, PbSe, CdS, CdTe; and a combination thereof, such as a combination of a AIN/GaN layer and a GaAs/AlGaAs layer.

Optionally, a plurality of etch resistant structures 1003 are formed below the top surface of the substrate 100 by implanting different types and/or different concentrations of doping elements in the substrate 100 for preventing an over deep electrochemical etch. Preferably, if a material of the substrate is Si or SiGe, under a high temperature condition or in a plasma ambiance with a relative high temperature, an isolation structure is formed by a reaction of each supporting structure with a nitrogenous and/or oxygenous ambience (such as any one of 0₂, H₂0, NH₃, N₂, 0₃, oxygen plasma, nitrogen plasma and a combination thereof). The isolation structures are favorable for the separation of the substrate in a following process.

Preferably, the substrate 100 further comprises a plurality of deep trenches, by which the substrate 100 is divided into a plurality of blocks. Figs. 25a and 25b are a schematic cross-sectional view and a top view of the semiconductor structure respectively according to an embodiment of the present disclosure. As shown in Fig. 25a, the substrate 100 is divided into a plurality of blocks. It can be seen from Fig. 25b, besides the second single crystal semiconductor layer 300 which is exposed at a top layer, the substrate 100 is also exposed from the deep trenches. When the substrate 100 is a Si substrate and there are hetero isolation structures on the top surface of the substrate 100, the hetero isolation structures are exposed from the deep trenches. The semiconductor structure with a deep trench isolation prevents the stress accumulation in the large scale, prevents the film from cracking when the epitaxial thickness of the film is larger, and is also favorable for division of device.

As shown in Fig. 26, the semiconductor structure comprises: a substrate 100, a buffer layer 110, a first nitride semiconductor layer 200, a mask layer 210, a plurality of supporting structures 1001, a second nitride semiconductor layer 300 and a plurality of holes or trenches. The plurality of supporting structures 1001 or the plurality of supporting structures with hetero isolation structures are formed on a top surface of the substrate 100. The buffer layer 110 is formed on the substrate 100, and an interface between the substrate 100 and the buffer layer 110 may be a plane or a patterned structure. The first nitride semiconductor layer 200 is formed on the buffer layer 110. The mask layer 210 is formed on the first nitride semiconductor layer 200 and has a plurality of openings, by which the mask layer 210 is divided into a plurality of discrete masks. The plurality of holes or trenches are buried in the first nitride semiconductor layer 200 and extend to the plurality of supporting structures. The second nitride semiconductor layer 300 is formed on the mask layer 210, covering and extending to the plurality of holes or trenches.

The substrate 100 has a patterned surface. For example, the substrate 100 may be a patterned Si substrate or a patterned sapphire substrate. Such patterned substrate may be favorable for a reduction of a dislocation density of an epitaxial layer formed thereon, as well as for an emission of LED light.

A material of the substrate 100 comprises any one of Si, SiGe, SiC, GaAs, Ge, GaN, GaP, InP, Ga₂0₃, A1₂0₃, A1N, ZnO, LiGa0₂ and LiA10₂.

Specifically, the buffer layer 110 may have a single-layer low temperature structure (such as an A1N layer), a multi- layer super lattice structure (such as an AIN/AlGaN multi- layer) or a multi- layer interlaced structure (such as a multi- layer combination of AIN/GaN). Materials of the first nitride semiconductor layer 200 and the second nitride semiconductor layer 300 comprise any one of GaN, InGaN, A1N, AlGaN, InN, AlGalnN and a combination thereof (such as a multi-layer combination of AlGaN/InGaN, AlGaN/GaN, AlGaN/GaN/InGaN or InGaN/GaN). A material of the mask layer 210 comprises any one of Si0₂, Si_xN_1-x, Hf0₂, Zr0₂, amorphous A1₂0₃ and a photo resist.

It should be noted that, the buffer layer 110 or the mask layer 210 is optional. Alternatively, the semiconductor structure may comprise: a substrate 100, a first nitride semiconductor layer 200, a mask layer 210, a second nitride semiconductor layer 300 and a plurality of holes or trenches. Yet alternatively, the semiconductor structure may comprise: a substrate 100, a buffer layer 110, a first nitride semiconductor layer 200, a second nitride semiconductor layer 300 and a plurality of holes or trenches. The semiconductor structure according to embodiments of the present disclosure has following advantages.

(1) For the semiconductor of wurtzite structure, the second single crystal semiconductor layer may be formed on the first single crystal semiconductor layer by the lateral growth. The dislocation density of the epopitaxial film can be reduced, and the film quality is improved. More importantly, since a surface of the first single crystal semiconductor layer is different from that of the supporting structure and is more suitable for growing the second single crystal semiconductor layer, the epitaxial growth quality of the second single crystal semiconductor layer is further improved.

(2) The plurality of holes or trenches and the micro/nano-size supporting structures are advantageous for releasing the thermal mismatch stress resulted from the film growth process, thus preventing the film from cracking when the epitaxial thickness of the film is larger, and improving the epitaxial thickness and growth quality of the film. It means that it is possible to use the low cost but high thermal mismatch material (such as Si) to be as the substrate, and it is also favorable for an LED vertical structure. More importantly, since the plurality of holes or trenches and the supporting structures are formed after a formation of the first single crystal semiconductor layer, the growth quality of the first single crystal semiconductor layer is not affected by a surface problem of the plurality of holes or trenches and the supporting structures. Thus, the high quality first single crystal semiconductor layer may be obtained. Accordingly, the high quality second single crystal semiconductor layer may be obtained.

(3) The etch regions are removed and the supporting structures are remained so that the semiconductor structure obtained is easy to be separated from the substrate. Particularly for the Si or SiGe substrate, each supporting structure reacts to form the hetero isolation structure to further release stress. Moreover, the isolation structure is favorable for the separation of the substrate.

(4) The substrate is divided into a plurality of blocks by deep trench etching, which in one aspect, prevents the stress accumulation in the large scale, and in another aspect, is favorable for division of device.

Reference throughout this specification to "an embodiment", "some embodiments", "one embodiment", "an example", "a specific examples", or "some examples" means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the disclosure. Thus, the appearances of the phrases such as "in some embodiments", "in one embodiment", "in an embodiment", "an example", "a specific examples", or "some examples" in various places throughout this specification are not necessarily referring to the same embodiment or example of the disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

Although explanatory embodiments have been shown and described, it would be appreciated by those skilled in the art that changes, alternatives, and modifications may be made in the embodiments without departing from spirit and principles of the disclosure. Such changes, alternatives, and modifications all fall into the scope of the claims and their equivalents.

Claims

WHAT IS CLAIMED IS:

1. A method for forming a semiconductor structure, comprising steps of:

providing a substrate;

forming a first single crystal semiconductor layer on the substrate;

etching the first single crystal semiconductor layer to form a plurality of holes or trenches extending to a top surface of the substrate, or etching the first single crystal semiconductor layer and the substrate to form a plurality of holes or trenches extending into the substrate;

etching the substrate through the plurality of holes or trenches to form a plurality of supporting structures in a region under the top surface of the substrate, thus forming a patterned structure; and

depositing a single crystal semiconductor material to form a second single crystal semiconductor layer on the patterned structure.

2. The method for forming a semiconductor structure according to claim 1, wherein depositing a single crystal semiconductor material to form a second single crystal semiconductor layer on the patterned structure comprises:

epitaxially laterally growing a single crystal semiconductor material on a lateral surface of the first single crystal semiconductor layer exposed in the plurality of holes or trenches.

3. The method for forming a semiconductor structure according to claim 2, after epitaxially laterally growing a single crystal semiconductor material on a lateral surface of the first single crystal semiconductor layer exposed in the plurality of holes or trenches, further comprising:

epitaxially longitudinally growing and then epitaxially laterally over-growing the single crystal semiconductor material on a top surface of the first single crystal semiconductor layer to form the second single crystal semiconductor layer.

4. The method for forming a semiconductor structure according to any one of claims 1-3, wherein the substrate has a patterned surface.

5. The method for forming a semiconductor structure according to any one of claims 1-4, before forming a first single crystal semiconductor layer on the substrate, further comprising: forming a buffer layer on the substrate.

6. The method for forming a semiconductor structure according to claim 5, wherein the buffer layer has a single-layer structure, a multi-layer superlattice structure or a multi-layer interlaced structure.

7. The method for forming a semiconductor structure according to any one of claims 1-6, wherein etching the first single crystal semiconductor layer to form a plurality of holes or trenches extending to a top surface of the substrate, or etching the first single crystal semiconductor layer and the substrate to form a plurality of holes or trenches extending into the substrate comprises: forming a mask layer on the first single crystal semiconductor layer;

etching the mask layer to form a plurality of openings; and

etching the first single crystal semiconductor layer to form a plurality of holes or trenches extending to a top surface of the substrate, or etching the first single crystal semiconductor layer and the substrate to form a plurality of holes or trenches extending into the substrate.

8. The method for forming a semiconductor structure according to any one of claims 1-7, wherein a material of the substrate comprises any one of Si, SiGe, SiC, GaAs, Ge, GaN, GaP, InP, Ga₂0₃, A1₂0₃, A1N, ZnO, LiGa0₂ and LiA10₂.

9. The method for forming a semiconductor structure according to any one of claims 1-8, wherein etching the substrate through the plurality of holes or trenches to form a plurality of supporting structures in a region under the top surface of the substrate comprises:

etching the substrate by a wet etch, a dry etch or an electrochemical etch when the substrate is conductive; and

etching the substrate by a wet etch or a dry etch when the substrate is nonconductive.

10. The method for forming a semiconductor structure according to claim 9, wherein etching the substrate by a wet etch, a dry etch or an electrochemical etch when the substrate is conductive comprises:

implanting different types and/or different concentrations of doping elements in different regions of the substrate to selectively etch redundant parts of the substrate and thus remaining a plurality of supporting structures.

11. The method for forming a semiconductor structure according to any one of claims 1-10, further comprising:

implanting different types and/or different concentrations of doping elements in the substrate to form a plurality of etch resistant structures below the top surface of the substrate.

12. The method for forming a semiconductor structure according to any one of claims 1-11, wherein a material of the first single crystal semiconductor layer comprises any one of group IV semiconductors Ge, SiGe, SiC; group III-V semiconductors GaN, InGaN, A1N, AlGaN, InN, AlGalnN, GaAs, GaP, AlGalnP; group II-VI semiconductors ZnO, Ga₂0₃, ZnS, ZnSe, PbSe, CdS, CdTe; and a combination thereof.

13. The method for forming a semiconductor structure according to any one of claims 1-12, further comprising:

if a material of the substrate is Si, after etching the substrate through the plurality of holes or trenches to form a plurality of supporting structures, processing the substrate in a nitrogenous and/or oxygenous ambience to enable each supporting structure to react with the nitrogenous and/or the oxygenous ambience to form an isolation structure.

14. The method for forming a semiconductor structure according to any one of claims 1-13, wherein the first single crystal semiconductor layer and/or the second single crystal semiconductor layer have a multi-layer compound semiconductor structure.

15. The method for forming a semiconductor structure according to any one of claims 1-14, further comprising: dividing the substrate into a plurality of blocks by deep trench etching.

16. A semiconductor structure, comprising:

a substrate;

a plurality of supporting structures formed on a top surface of the substrate;

a first single crystal semiconductor layer formed on the plurality of supporting structures, a plurality of holes or trenches buried in the first single crystal semiconductor layer and extending to the top surface of the substrate; and

a second single crystal semiconductor layer formed on the first single crystal semiconductor layer, covering and extending to the plurality of holes or trenches.

17. The semiconductor structure according to claim 16, wherein the substrate has a patterned surface.

18. The semiconductor structure according to claim 16 or 17, further comprising a buffer layer formed on the substrate.

19. The semiconductor structure according to claim 18, wherein the buffer layer has a single-layer structure, a multi-layer superlattice structure or a multi-layer interlaced structure.

20. The semiconductor structure according to one of claims 16-19, further comprising a mask layer formed on the first single crystal semiconductor layer, wherein the mask layer is divided into a plurality of discrete masks by the plurality of holes or trenches.

21. The semiconductor structure according to one of claims 16-20, wherein a material of the substrate comprises any one of Si, SiGe, SiC, GaAs, Ge, GaN, GaP, InP, Ga₂0₃, A1₂0₃, AIN, ZnO, LiGa0₂, and LiA10₂.

22. The semiconductor structure according to one of claims 16-21, wherein

the plurality of supporting structures are formed by a wet etch, a dry etch or an electrochemical etch when the substrate is conductive; and

the plurality of supporting structures are formed by a wet etch or a dry etch when the substrate is nonconductive.

23. The semiconductor structure according to one of claims 16-22, further comprising a plurality of etch resistant structures formed below the top surface of the substrate by implanting different types and/or different concentrations of doping elements in the substrate.

24. The semiconductor structure according to one of claims 16-23, wherein a material of the first single crystal semiconductor layer comprises any one of group IV semiconductors Ge, SiGe, SiC; group III-V semiconductors GaN, InGaN, AIN, AlGaN, InN, AlGalnN, GaAs, GaP, AlGalnP; group II- VI semiconductors ZnO, Ga₂0₃, ZnS, ZnSe, PbSe, CdS, CdTe; and a combination thereof.

25. The semiconductor structure according to one of claims 16-24, further comprising an isolation structure formed by a reaction of each supporting structure with a nitrogenous and/or oxygenous ambience, if a material of the substrate is Si.

26. The semiconductor structure according to one of claims 16-25, wherein the first single crystal semiconductor layer and/or the second single crystal semiconductor layer have a multi-layer compound semiconductor structure.

27. The semiconductor structure according to one of claims 16-26, wherein the substrate further comprises a plurality of deep trenches, by which the substrate is divided into a plurality of blocks.