WO2012065536A1 - Semiconductor structure and method for forming the same - Google Patents

Semiconductor structure and method for forming the same Download PDF

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Publication number
WO2012065536A1
WO2012065536A1 PCT/CN2011/082174 CN2011082174W WO2012065536A1 WO 2012065536 A1 WO2012065536 A1 WO 2012065536A1 CN 2011082174 W CN2011082174 W CN 2011082174W WO 2012065536 A1 WO2012065536 A1 WO 2012065536A1
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Prior art keywords
layer
porous layer
porous
substrate
semiconductor
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PCT/CN2011/082174
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French (fr)
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Chuwen Wang
Dongjing Zhao
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Chuwen Wang
Dongjing Zhao
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Priority claimed from CN 201010546347 external-priority patent/CN102064186A/en
Priority claimed from CN 201010546357 external-priority patent/CN102104060B/en
Priority claimed from CN201110021061.2A external-priority patent/CN102122691B/en
Application filed by Chuwen Wang, Dongjing Zhao filed Critical Chuwen Wang
Publication of WO2012065536A1 publication Critical patent/WO2012065536A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02502—Layer structure consisting of two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02513—Microstructure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound

Abstract

A semiconductor structure and a forming method thereof are provided. The semiconductor structure comprises: a substrate (1100), a first porous layer (1200) formed on the substrate (1100), a second porous layer (1300) formed on the first porous layer (1200), and a first semiconductor layer (1400) formed on the second porous layer (1300). A porosity of the second porous layer (1300) is smaller than that of the first porous layer (1200), and a pore size of the second porous layer (1300) is smaller than that of the first porous layer (1200).

Description

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME FIELD
The present disclosure relates to a semiconductor manufacture and design, and more particularly to a semiconductor structure and a method for forming the same.
BACKGROUND
Recently, an LED (light emitting diode) has been widely used in display screens, backlights, special lighting, etc., because of its long life, high luminescent efficiency, small volume, good durability and rich colors. A core structure in the LED is an LED epitaxial wafer, which mainly comprises a substrate, a buffer layer, an N-type semiconductor layer, an active light-emitting layer and a P-type semiconductor layer. As a core layer of the LED epitaxial wafer, the active light-emitting layer is formed between the N-type semiconductor layer and the P-type semiconductor layer, thus forming a PN junction at an interface between the P-type semiconductor layer and the N-type semiconductor layer. GaN (gallium nitride) is a commonly used material for forming an LED epitaxial film for a blue LED. Because a thermal expansion coefficient of the substrate is different from that of the LED epitaxial film and a conventional GaN epitaxy is a high temperature process, after the LED epitaxial film is formed, an internal stress will be generated in the epitaxial film due to a thermal mismatch. For example, for an AI2O3 (sapphire) substrate and a Si (silicon) substrate, because the thermal mismatch between AI2O3 and GaN is small, a small stress will be generated in the GaN epitaxial wafer formed on the AI2O3 substrate, while because the thermal mismatch between Si and GaN is large, a large stress will be generated in a GaN epitaxial wafer formed on the Si substrate. However, the sapphire substrate is very expensive, and a large diameter sapphire wafer is difficult to be fabricated, so that the conventional LED is very expensive. Because Si wafers are very cheap and a Si wafer with a large diameter is convenient to be fabricated, researches and applications on heteroepitaxy based on the Si substrate have been carried out widely, for example, lll-V compound semiconductor materials such as GaN are formed on the Si substrate by epitaxy. However, due to a large thermal mismatch between Si and GaN, the thermal mismatch stress may cause cracks on the epitaxial film when the epitaxial film is thick, and consequently a quality of the epitaxial film is poor, thus limiting a thickness of the film. Meanwhile, a large lattice mismatch between Si and most lll-V compound semiconductor materials such as GaN may cause a lot of dislocations to be generated in the epitaxial film, thus affecting a quality of the film and deteriorating a performance of an LED device.
SUMMARY
The present disclosure is aimed to solve at least one of the above mentioned technical problems. Accordingly, a semiconductor structure and a method for forming the same are provided.
According to an aspect of the present disclosure, a semiconductor structure is provided. The semiconductor structure comprises: a substrate; a first porous layer formed on the substrate; a second porous layer formed on the first porous layer, in which a porosity of the second porous layer is smaller than that of the first porous layer, and a pore size of the second porous layer is smaller than that of the first porous layer; and a first semiconductor layer formed on the second porous layer.
In one embodiment, the semiconductor structure further comprises: a second semiconductor layer with a patterned structure formed between the second porous layer and the first semiconductor layer.
In one embodiment, the first semiconductor layer is a buffer layer, in which the semiconductor structure further comprises an LED structure formed on the buffer layer, and the LED structure at least comprises a first conductivity type semiconductor layer, a light-emitting layer, and a second conductivity type semiconductor layer.
In one embodiment, the substrate comprises a Si substrate, a SiGe substrate with low
Ge content, or a combination thereof.
In one embodiment, each of the first and second porous layers is a porous Si layer or a porous SiGe layer. In one embodiment, the semiconductor structure further comprises: a third porous layer formed between the first porous layer and the substrate, in which the third porous layer is a porous Si layer or a porous SiGe layer, a porosity of the third porous layer is smaller than that of the first porous layer, and a pore size of the third porous layer is smaller than that of the first porous layer.
In one embodiment, the first porous layer comprises a plurality of first regions and a plurality of second regions, in which each second region is formed between two adjacent first regions, a porosity of each first region is greater than that of each second region, and a pore size of each first region is greater than that of each second region.
In one embodiment, the porosity of the first porous layer increases gradually from an interface between the first porous layer and the substrate to an interface between the first porous layer and the second porous layer.
In one embodiment, the first semiconductor layer comprises a lll-V compound semiconductor layer.
According to another aspect of the present disclosure, a method for forming a semiconductor structure is provided. The method comprises steps of: providing a substrate; forming a first porous layer and a second porous layer on the substrate, in which a porosity of the second porous layer is smaller than that of the first porous layer, and a pore size of the second porous layer is smaller than that of the first porous layer; and forming a first semiconductor layer on the second porous layer.
In one embodiment, the method further comprises: forming a second semiconductor layer on the second porous layer; and forming a patterned structure on the second semiconductor layer.
In one embodiment, the first semiconductor layer is a buffer layer, in which the method further comprises: forming an LED structure on the buffer layer, in which the LED structure at least comprises a first conductivity type semiconductor layer, a light-emitting layer, and a second conductivity type semiconductor layer. In one embodiment, the substrate comprises a Si substrate, a SiGe substrate with low Ge content, or a combination thereof.
In one embodiment, the step of forming a first porous layer and a second porous layer on the substrate comprises: anodizing the substrate with a varied anode current density so as to form the first porous layer and the second porous layer on the substrate, in which the first porous layer and the second porous layer are a porous Si layer or a porous SiGe layer.
In one embodiment, before anodizing, the method further comprises: forming a heavily-doped buried layer by implanting a dopant into the substrate, in which the buried layer is converted into the first porous layer and a layer of the substrate on the buried layer is converted into the second porous layer after anodizing.
In one embodiment, the step of forming a first porous layer and a second porous layer on the substrate comprises: anodizing the substrate to form a first porous layer; and annealing the first porous layer to convert a top layer of the first porous layer into a second porous layer.
In one embodiment, the method further comprises: forming a third porous layer between the substrate and the first porous layer by anodizing, in which the third porous layer is a porous Si layer or a porous SiGe layer, a porosity of the third porous layer is smaller than that of the first porous layer, and a pore size of the third porous layer is smaller than that of the first porous layer.
In one embodiment, the first porous layer comprises a plurality of first regions and a plurality of second regions, in which each second region is formed between two adjacent first regions, a porosity of each first region is greater than that of each second region, and a pore size of each first region is greater than that of each second region.
In one embodiment, the porosity of the first porous layer increases gradually from an interface between the first porous layer and the substrate to an interface between the first porous layer and the second porous layer. According to an embodiment of the present disclosure, during cooling stage in an epitaxial process, a thermal mismatch stress may be released by elastic deformation or fracture of the first porous layer, thus avoiding cracking of a lll-V or a ll-VI compound semiconductor film growing epitaxially. Therefore, a lll-V compound semiconductor layer with a large thickness may be formed, and especially when there is a larger thermal mismatch between a material for forming the substrate and epitaxial materials, a Si substrate and a GaN film may be formed epitaxially. In addition, a second porous layer with smaller porosity and smaller pore size may also be formed on the first porous layer, thus inhibiting a dislocation formed as a result of a lattice mismatch between the substrate and the first semiconductor layer and reducing a dislocation density. Preferably, the third porous layer with smaller porosity and smaller pore size may also be formed between the substrate and the first porous layer, and consequently a shear stress between different porous layers with different porosities may be used for conveniently removing the first porous layer, and consequently stripping the substrate. According to an embodiment of the present disclosure, through the first and second porous layers, the thermal mismatch stress between Si and epitaxial materials such as GaN may be released, the cracking of the epitaxial film with a larger thickness may be prevented, and a crystal quality of the epitaxial film may be improved. Therefore, an eptaxial layer such as a GaN layer having a large thickness may be formed on the Si substrate, in which there is a large thermal mismatch stress between epitaxial materials and Si. Moreover, porous Si materials may be removed during subsequent processes, which may not have an influence on subsequent device fabricating processes.
According to an embodiment of the present disclosure, by epitaxially growing the first semiconductor layer on the first porous layer with a large porosity, in which there is a large thermal mismatch stress between epitaxial materials and Si, the thermal mismatch stress during cooing process may be released by partial deformation of the first porous layer, thus ensuring an integrity of the epitaxial film and epitaxially growing an epitaxial layer with a larger thickness. Moreover, a patterned porous layer (i.e., a porous layer having a plurality of first regions and a plurality of second regions) may be used for controlling the releasing of the thermal mismatch stress and providing good mechanical support, thus further improving the quality of the epitaxial film.
Additional aspects and advantages of the embodiments of the present disclosure will be given in part in the following descriptions, become apparent in part from the following descriptions, or be learned from the practice of the embodiments of the present disclosure.
BRIEF DESCRIPTION OF THE DRAWINGS
These and other aspects and advantages of the disclosure will become apparent and more readily appreciated from the following descriptions taken in conjunction with the drawings in which:
Fig. 1 is a cross-sectional view of a semiconductor structure according to a first embodiment of the present disclosure;
Fig. 2 is a flow chart of a method for forming a semiconductor structure according to a first embodiment of the present disclosure;
Fig. 3 is a cross-sectional view of a semiconductor structure according to a second embodiment of the present disclosure;
Fig. 4 is a flow chart of a method for forming a semiconductor structure according to a second embodiment of the present disclosure;
Fig. 5 is a cross-sectional view of a semiconductor structure according to a third embodiment of the present disclosure;
Fig. 6 is a cross-sectional view of a semiconductor structure according to a fourth embodiment of the present disclosure; and
Fig. 7 is a cross-sectional view of a semiconductor structure according to a fifth embodiment of the present disclosure.
DETAILED DESCRIPTION
Embodiments of the present disclosure will be described in detail in the following descriptions, examples of which are shown in the accompanying drawings, in which the same or similar elements and elements having same or similar functions are denoted by like reference numerals throughout the descriptions. The embodiments described herein with reference to the accompanying drawings are explanatory and illustrative, which are used to generally understand the present disclosure. The embodiments shall not be construed to limit the present disclosure.
Various embodiments and examples are provided in the following description to implement different structures of the present disclosure. In order to simplify the present disclosure, certain elements and settings will be described. However, these elements and settings are only examples and are not intended to limit the present disclosure. In addition, reference numerals may be repeated in different examples in the disclosure. This repeating is for the purpose of simplification and clarity and does not refer to relations between different embodiments and/or settings. Furthermore, examples of different processes and materials are provided in the present disclosure. However, it would be appreciated by those skilled in the art that other processes and/or materials may be also applied. Moreover, a structure in which a first feature is "on" a second feature may include an embodiment in which the first feature directly contacts the second feature and may include an embodiment in which an additional feature is prepared between the first feature and the second feature so that the first feature does not directly contact the second feature.
According to an embodiment of the present disclosure, a first porous layer with a larger porosity and a larger pore size is used for releasing a thermal mismatch stress introduced during subsequent processes, and then is removed when a device is formed, thus avoiding an influence of a thermal mismatch of different semiconductor materials on the device.
Fig. 1 is a cross-sectional view of a semiconductor structure according to a first embodiment of the present disclosure. The semiconductor structure comprises a substrate 1 100, a first porous layer 1200 formed on the substrate 1 100, a second porous layer 1300 formed on the first porous layer 1200, and a first semiconductor layer 1400 formed on the second porous layer 1300. In one embodiment, a porosity of the second porous layer 1300 is smaller than that of the first porous layer 1200, a pore size of the second porous layer 1300 is smaller than that of the first porous layer 1200, and the porosity of the first porous layer 1200 is greater than 30%. A material for forming the substrate 1 100 is different from that for forming the first semiconductor layer 1400. For example, the substrate 1 100 may comprise a Si substrate, a SiGe substrate with low Ge content, or a combination thereof, and the first semiconductor layer 1400 may comprise a lll-V compound semiconductor layer or a ll-VI compound semiconductor layer. The lll-V compound semiconductor layer may be an InP layer, a GaN layer, a GaSb layer, or a GaAs layer. The ll-VI compound semiconductor layer may be a ZnO layer, a SnO layer, a ZnS layer, a CdS layer, or a CdTe layer. In this way, according to an embodiment of the present disclosure, because of its larger porosity and larger pore size, the first porous layer 1200 may be used for releasing the thermal mismatch stress introduced during subsequent processes. In addition, the second porous layer 1300 with smaller porosity and smaller pore size may help to improve a quality of the first semiconductor layer 1400 formed thereon. In one embodiment, the first porous layer 1200 is a porous Si layer or a porous SiGe layer, and a content of Ge in the first porous layer 1200 varies gradually. The second porous layer 1300 is a very thin layer, so that a stress in the first semiconductor layer 1400 may be transferred to the first porous layer 1200. In one embodiment, the porosity of the first porous layer 1200 is greater than 20%. In one embodiment, the porosity and the pore size of the second porous layer 1300 may be very small, for example, the porosity and the pore size of the second porous layer 1300 may be zero after annealing, that is, the second porous layer 1300 may become an imporous layer.
In one embodiment, the substrate 1 100 is a Si substrate or a SiGe substrate with low Ge content, and each of the first and second porous layers 1200, 1300 is a porous Si layer or a porous SiGe layer, preferably, a porous Si layer. A thickness of the first porous layer 1200 is greater than that of the second porous layer 1300. For example, the thickness of the first porous layer 1200 is between tens of nanometers and tens of microns, and the thickness of the second porous layer 1300 is between several nanometers and tens of nanometers, thus conveniently removing the first porous layer 1200 for releasing the thermal mismatch stress during subsequent processes.
Fig. 2 is a flow chart of a method for forming a semiconductor structure according to a first embodiment of the present disclosure. The method comprises the following steps.
Step S201 , a substrate 1 100 is provided. The substrate 1 100 may comprise a Si substrate, a SiGe substrate with low Ge content, or a combination thereof.
Step S202, a first porous layer 1200 and a second porous layer 1300 are formed on the substrate 1 100. In some embodiments, the first porous layer 1200 and the second porous layer 1300 may be formed on the substrate 1 100 through various modes. Some exemplary modes are as follows.
Mode 1
The substrate 1 100 is anodized, and an anode current with varied current density is applied to the substrate 1 100 so as to form the first and second porous layers 1200, 1300 on the substrate 1 100.
Mode 2
Before the substrate 1 100 is anodized, a heavily-doped buried layer is formed by implanting a dopant into the substrate 1 100. In some embodiments, various dopants such as P or B may be used. Then, the substrate 1 100 is anodized, so that the buried layer is converted into the first porous layer 1200 and a layer of the substrate 1 100 on the buried layer is converted into the second porous layer 1300. This mode needs to be used in combination with Mode 1 .
Mode 3
The substrate 1 100 is anodized to form the first porous layer 1200, and the first porous layer 1200 is annealed so that a top layer of the first porous layer 1200 is converted into the second porous layer 1300.
Mode 4
In one embodiment, the porosity of the first porous layer 1200 increases gradually from an interface between the first porous layer 1200 and the substrate 1 100 to an interface between the first porous layer 1200 and the second porous layer 1300, thus releasing the thermal mismatch stress. The first porous layer 1200 is formed by: implanting a dopant into the substrate 1 100, anodizing the substrate 1 100, and applying an anode current to the substrate 1 100. The anode current density increases rapidly at the beginning of the anodizing process and decreases gradually. That is, the anode current density increases rapidly to a maximum value, is maintained at the maximum value for a predetermined time, and then falls gradually.
Step S203, a first semiconductor layer 1400 is formed on the second porous layer 1300. The first semiconductor layer 1400 may comprise a lll-V compound semiconductor layer or a ll-VI compound semiconductor layer. The lll-V compound semiconductor layer may be an InP layer, a GaN layer, a GaSb layer, or a GaAs layer. The ll-VI compound semiconductor layer may be a ZnO layer, a SnO layer, a ZnS layer, a CdS layer, or a CdTe layer.
Fig. 3 is a cross-sectional view of a semiconductor structure according to a second embodiment of the present disclosure. The semiconductor structure comprises a substrate 3100, a third porous layer 3200 formed on the substrate 3100, a first porous layer 3300 and a second porous layer 3400 formed on the third porous layer 3200, and a first semiconductor layer 3500 formed on the second porous layer 3400.
In one embodiment, a porosity of each of the second porous layer 3400 and the third porous layer 3200 is smaller than that of the first porous layer 3300, and a pore size of each of the second porous layer 3400 and the third porous layer 3200 is smaller than that of the first porous layer 3300. A material for forming the substrate 3100 is different from that for forming the first semiconductor layer 3500. For example, the substrate 3100 may comprise a Si substrate, a SiGe substrate with low Ge content, or a combination thereof, and the first semiconductor layer 3500 may comprise a lll-V compound semiconductor layer or a ll-VI compound semiconductor layer. The lll-V compound semiconductor layer may be an InP layer, a GaN layer, a GaSb layer, or a GaAs layer. The ll-VI compound semiconductor layer may be a ZnO layer, a SnO layer, a ZnS layer, a CdS layer, or a CdTe layer. In this way, according to an embodiment of the present disclosure, because of its larger porosity and larger pore size, the first porous layer 3300 may be used for releasing the thermal mismatch stress introduced during subsequent processes. In addition, the second porous layer 3400 with smaller porosity and smaller pore size may alleviate a dislocation between the substrate 3100 and the first semiconductor layer 3500. Moreover, a thickness of the third porous layer 3200 is greater than that of the first porous layer 3300. For example, the thickness of the first porous layer 3300 is between tens of nanometers and hundreds of microns, the thickness of the second porous layer 3400 is between several nanometers and tens of nanometers, and the thickness of the third porous layer 3200 is between tens of nanometers and tens of microns. Because the porosities of the third porous layer 3200 and the first porous layer 3300 are different, which may result in an internal stress at the interface between the third porous layer 3200 and the first porous layer 3300, the third porous layer 3200 and the first porous layer 3300 may be easily separated by cutting, and thus the substrate 3100 may be conveniently removed during subsequent processes.
In one embodiment, the substrate 3100 is a Si substrate or a SiGe substrate with low Ge content, and each of the first, second and third porous layers 3300, 3400, 3200 is a porous Si layer or a porous SiGe layer.
Fig. 4 is a flow chart of a method for forming a semiconductor structure according to a second embodiment of the present disclosure. The method comprises the following steps.
Step S401 , a substrate 3100 is provided. The substrate 3100 may comprise a Si substrate, a SiGe substrate with low Ge content, or a combination thereof.
Step S402, a third porous layer 3200, a first porous layer 3300 and a second porous layer 3400 are formed on the substrate 3100. In one embodiment, a porosity of each of the second porous layer 3400 and the third porous layer 3200 is smaller than that of the first porous layer 3300, and a pore size of each of the second porous layer 3400 and the third porous layer 3200 is smaller than that of the first porous layer 3300. A thickness of the third porous layer 3200 is greater than that of the first porous layer 3300. For example, the thickness of the first porous layer 3300 is between tens of nanometers and hundreds of microns, the thickness of the second porous layer 3400 is between several nanometers and tens of nanometers, and the thickness of the third porous layer 3200 is between tens of nanometers and tens of microns. In some embodiments, the first porous layer 1200 and the second porous layer 1300 may be formed on the substrate 1 100 through various modes. Some exemplary modes are as follows.
Mode 1
The substrate 3100 is anodized, and a varied anode current density is applied to the substrate 3100 so as to form the third, first and second porous layers 3200, 3300, 3400 on the substrate 3100. In this embodiment, the varied anode current density refers to the anode current density increasing and decreasing in two or more steps. The higher the current density, the larger the porosity is, and the bigger the pore size is. Therefore, the porosity of the first porous layer 3300 is greater than that of each of the second porous layer 3400 and the third porous layer 3200, and a pore size of the first porous layer 3300 is greater than that of each of the second porous layer 3400 and the third porous layer 3200.
Mode 2
In order to facilitate a formation of the first porous layer 3300, before the substrate 3100 is anodized, a heavily-doped buried layer is formed by implanting a dopant into the substrate 3100, and a thickness of heavily-doped buried layer is controlled to equal to that of the first porous layer 3300. In this way, after the substrate 3100 is anodized, the heavily-doped buried layer may be converted to form the first porous layer 3300.
Step S403, a first semiconductor layer 3500 is formed on the second porous layer 3400. The first semiconductor layer 3500 may comprise a lll-V compound semiconductor layer or a ll-VI compound semiconductor layer. The lll-V compound semiconductor layer may be an InP layer, a GaN layer, a GaSb layer, or a GaAs layer. The ll-VI compound semiconductor layer may be a ZnO layer, a SnO layer, a ZnS layer, a CdS layer, or a CdTe layer. Fig. 5 is a cross-sectional view of a semiconductor structure according to a third embodiment of the present disclosure. The semiconductor structure comprises a substrate 5100, a first porous layer 5200 formed on the substrate 5100, a second porous layer 5300 formed on the first porous layer 5200, and a first semiconductor layer 5400 formed on the second porous layer 5300. In this embodiment, the first porous layer 5200 comprises a plurality of first regions 6100 and a plurality of second regions 6200, in which each second region 6200 is formed between two adjacent first regions 6100, a porosity of each first region 6100 is greater than that of each second region 6200, and a pore size of the first region 6100 is greater than that of each second region 6200. The first porous layer 5200 may be formed through the following method. For example, a mask layer is firstly formed on the substrate 5100, the mask layer is etched to form a plurality of openings, the substrate 5100 is implanted through the openings to form a plurality of first implanted regions at the openings, and then the plurality of first implanted regions are anodized. Due to a damage caused by implanting, after anodized, the first implanted regions may be converted into the first regions. In this way, the porosity and the pore size of the first regions may be larger, thus facilitating a releasing of the stress; meanwhile, because the second regions with smaller porosity and smaller pore size are formed between the first regions, the first porous layer may not collapse as a result of the releasing of the stress.
Fig. 6 is a cross-sectional view of a semiconductor structure according to a fourth embodiment of the present disclosure. The semiconductor structure comprises a substrate 6100, a first porous layer 6200 formed on the substrate 6100, a second porous layer 6300 formed on the first porous layer 6200, a second semiconductor layer 6400 with a patterned structure formed on the second porous layer 6300, and a first semiconductor layer 6500 formed on the second semiconductor layer 6400 with a patterned structure. In one embodiment, a porosity of the second porous layer 6300 is smaller than that of the first porous layer 6200, a pore size of the second porous layer 6300 is smaller than that of the first porous layer 6200, and the porosity of the first porous layer 6200 is greater than 30%. A material for forming the substrate 6100 is different from that for forming the first semiconductor layer 6500. For example, the substrate 6100 may comprise a Si substrate, a SiGe substrate with low Ge content, or a combination thereof, and the first semiconductor layer 6500 may comprise a lll-V compound semiconductor layer or a ll-VI compound semiconductor layer. The lll-V compound semiconductor layer may be an InP layer, a GaN layer, a GaSb layer, or a GaAs layer. The ll-VI compound semiconductor layer may be a ZnO layer, a SnO layer, a ZnS layer, a CdS layer, or a CdTe layer. In this way, according to an embodiment of the present disclosure, because of its larger porosity and larger pore size, the first porous layer 6200 may be used for releasing the thermal mismatch stress introduced during subsequent processes. In addition, the second porous layer 6300 with smaller porosity and smaller pore size may help to improve a quality of the first semiconductor layer 6500 formed thereon. Moreover, the second semiconductor layer 6400 with a patterned structure may alleviate a dislocation between the substrate 6100 and the first semiconductor layer 6500, thus further improving the quality of the first semiconductor layer 6500. The patterned structure may be an array with regular geometrical structures such as a semisphere, a cuboid or a cube formed by Si, SiGe with low Ge content, or a combination thereof. When lll-V compound semiconductor materials such as GaN grow epitaxially on the second semiconductor layer 6400 with a patterned structure, transversal and longitudinal epitaxial growth modes of the lll-V compound semiconductor materials may be controlled through a suitable technology, thus reducing a dislocation density in an eptaxial layer. In one embodiment, the porosity of the first porous layer 6200 is greater than 20%. In one embodiment, the porosity and the pore size of the second porous layer 6300 may be very small, for example, the porosity and the pore size of the second porous layer 6300 may be zero after annealing, that is, the second porous layer 6300 may become an imporous layer.
In one embodiment, the first porous layer 6200 is a porous SiGe layer, and a content of Ge in the first porous layer 6200 varies gradually. The second porous layer 6300 and the second semiconductor layer 6400 with a patterned structure are very thin layers, so that a stress in the first semiconductor layer 6500 may be transferred to the first porous layer 6200.
In one embodiment, the substrate 6100 may comprise a Si substrate or a SiGe substrate with low Ge content, and each of the first and second porous layers 6200, 6300 is a porous Si layer or a porous SiGe layer, preferably, a porous Si layer. A thickness of the first porous layer 6200 is greater than that of the second porous layer 6300. For example, the thickness of the first porous layer 6200 is between tens of nanometers and tens of microns, and the thickness of each of the second porous layer 6300 and the second semiconductor layer 6400 with a patterned structure is between several nanometers and tens of nanometers, thus conveniently removing the first porous layer 6200 for releasing the thermal mismatch stress during subsequent processes.
A method for forming the semiconductor structure according to the fourth embodiment of the present disclosure may be similar to the above method for forming the semiconductor structure according to the first embodiment of the present disclosure, but further comprise steps of: forming a second semiconductor layer on the second porous layer 6300; and forming a patterned structure on the second semiconductor layer to form the second semiconductor layer 6400 with a patterned structure.
Fig. 7 is a cross-sectional view of a semiconductor structure according to a fifth embodiment of the present disclosure. The semiconductor structure is an LED epitaxial wafer according to an embodiment of the present disclosure. The LED epitaxial wafer comprises a substrate 7100, a first porous layer 7200, a second porous layer 7300, and an LED structure 7400. The LED structure 7400 comprises a first conductivity type semiconductor layer 7410, a light-emitting layer 7420, and a second conductivity type semiconductor layer 7430. In one embodiment, the substrate 7100 may be a Si-containing substrate, for example, a Si substrate, a SiGe substrate with low Ge content, or a SOI (silicon on insulator) substrate. A porosity of the second porous layer 7300 is smaller than that of the first porous layer 7200, and a pore size of the second porous layer 7300 is smaller than that of the first porous layer 7200. In this way, the first porous layer 7200 may be used for releasing the thermal mismatch stress, and the second porous layer 7300 may help to improve an epitaxial crystal quality such as a surface roughness and a defect density of the LED structure 7400. In one embodiment, the first conductivity type semiconductor layer 7410 may be an N-type GaN layer, the light-emitting layer 7420 may be an InGaN/GaN multi quantum well light-emitting layer, and the second conductivity type semiconductor layer 7430 may be a P-type GaN layer. In some embodiments, the semiconductor structure may also comprise a P-type AIGaN layer formed between the light-emitting layer 7420 and the second conductivity type semiconductor layer 7430, and the P-type AIGaN layer may be used as a barrier layer. In one embodiment, the second porous layer 7300 may be a Si layer formed after the first porous layer 7200 is annealed. In one embodiment, a buffer layer (not shown in Fig.7) may be formed between the second porous layer 7300 and the LED structure 7400. In one embodiment, the buffer layer may be an AIN layer, a GaN layer, or a GaAs layer. Usually, a thickness of the second porous layer 7300 is within about 10nm, thus facilitating a transfer of the stress.
A method for forming the semiconductor structure according to the fifth embodiment of the present disclosure may be similar to the above method for forming the semiconductor structure according to the first embodiment of the present disclosure. The LED structure 7400 may be formed on the buffer layer, and the LED structure 7400 may also be formed on the second porous layer 7300. The LED structure 7400 at least comprises the first conductivity type semiconductor layer 7410, the light-emitting layer 7420, and the second conductivity type semiconductor layer 7430.
According to an embodiment of the present disclosure, during a cooling stage in an epitaxial process, a thermal mismatch stress may be released by elastic deformation or fracture of the first porous layer, thus avoiding cracking of a lll-V or a ll-VI compound semiconductor film grown epitaxially. Therefore, a lll-V or a ll-VI compound semiconductor layer with a large thickness may be formed, and especially when there is a larger thermal mismatch between a material for forming the substrate and epitaxial materials, a Si substrate and a GaN film may be formed epitaxially. In addition, a second porous layer with smaller porosity and smaller pore size may also be formed on the first porous layer, thus inhibiting a dislocation formed as a result of a lattice mismatch between the material for forming the substrate and a material for forming the first semiconductor layer and reducing a dislocation density. More preferably, the third porous layer with smaller porosity and smaller pore size may also be formed between the substrate and the first porous layer, and consequently a shear stress between different porous layers with different porosities may be used for conveniently removing the first porous layer, thus stripping the substrate. According to an embodiment of the present disclosure, through the first and second porous layers, the thermal mismatch stress between Si and epitaxial materials such as GaN may be released, the cracking of the epitaxial film with a larger thickness may be prevented, and a crystal quality of the epitaxial film may be improved. Therefore, an eptaxial layer such as a GaN layer having a large thickness may be formed on the Si substrate, in which there is a large thermal mismatch stress between epitaxial materials and Si. Moreover, porous Si materials may be removed during subsequent processes, which may not have an influence on subsequent device fabricating processes.
According to an embodiment of the present disclosure, by epitaxially forming the first semiconductor layer on the first porous layer with a large porosity, in which there is a large thermal mismatch stress between epitaxial materials and Si, the thermal mismatch stress during a cooing process may be released by partial deformation of the first porous layer, thus ensuring an integrity of the epitaxial film and epitaxially forming an epitaxial layer with a larger thickness. Moreover, a patterned porous layer (i.e., a porous layer having a plurality of first regions and a plurality of second regions) may be used for controlling the releasing of the thermal mismatch stress and providing good mechanical support, thus further improving the quality of the epitaxial film.
Although explanatory embodiments have been shown and described, it would be appreciated by those skilled in the art that changes, alternatives, and modifications all falling into the scope of the claims and their equivalents may be made in the embodiments without departing from spirit and principles of the disclosure.

Claims

WHAT IS CLAIMED IS:
1 . A semiconductor structure, comprising:
a substrate;
a first porous layer formed on the substrate;
a second porous layer formed on the first porous layer, wherein a porosity of the second porous layer is smaller than that of the first porous layer, and a pore size of the second porous layer is smaller than that of the first porous layer; and
a first semiconductor layer formed on the second porous layer.
2. The semiconductor structure according to claim 1 , further comprising:
a second semiconductor layer with a patterned structure formed between the second porous layer and the first semiconductor layer.
3. The semiconductor structure according to claim 1 , wherein the first semiconductor layer is a buffer layer, in which the semiconductor structure further comprises an LED structure formed on the buffer layer, and the LED structure at least comprises a first conductivity type semiconductor layer, a light-emitting layer, and a second conductivity type semiconductor layer.
4. The semiconductor structure according to claim 1 , wherein the substrate comprises a Si substrate, a SiGe substrate with low Ge content, or a combination thereof.
5. The semiconductor structure according to claim 4, wherein each of the first and second porous layers is a porous Si layer or a porous SiGe layer.
6. The semiconductor structure according to claim 5, further comprising:
a third porous layer formed between the first porous layer and the substrate, wherein the third porous layer is a porous Si layer or a porous SiGe layer, a porosity of the third porous layer is smaller than that of the first porous layer, and a pore size of the third porous layer is smaller than that of the first porous layer.
7. The semiconductor structure according to claim 1 , wherein the first porous layer comprises a plurality of first regions and a plurality of second regions, in which each second region is formed between two adjacent first regions, a porosity of each first region is greater than that of each second region, and a pore size of each first region is greater than that of each second region.
8. The semiconductor structure according to claim 1 , wherein the porosity of the first porous layer increases gradually from an interface between the first porous layer and the substrate to an interface between the first porous layer and the second porous layer.
9. The semiconductor structure according to claim 1 , wherein the first semiconductor layer comprises a lll-V compound semiconductor layer.
10. A method for forming a semiconductor structure, comprising steps of:
providing a substrate;
forming a first porous layer and a second porous layer on the substrate, wherein a porosity of the second porous layer is smaller than that of the first porous layer, and a pore size of the second porous layer is smaller than that of the first porous layer; and
forming a first semiconductor layer on the second porous layer.
1 1 . The method according to claim 10, further comprising:
forming a second semiconductor layer on the second porous layer; and
forming a patterned structure on the second semiconductor layer.
12. The method according to claim 10, wherein the first semiconductor layer is a buffer layer, in which the method further comprises:
forming an LED structure on the buffer layer, in which the LED structure at least comprises a first conductivity type semiconductor layer, a light-emitting layer, and a second conductivity type semiconductor layer.
13. The method according to claim 10, wherein the substrate comprises a Si substrate, a SiGe substrate with low Ge content, or a combination thereof.
14. The method according to claim 10, wherein the step of forming a first porous layer and a second porous layer on the substrate comprises:
anodizing the substrate with a varied anode current density so as to form the first porous layer and the second porous layer on the substrate, in which the first porous layer and the second porous layer are a porous Si layer or a porous SiGe layer.
15. The method according to claim 14, before anodizing, further comprising:
forming a heavily-doped buried layer by implanting a dopant into the substrate, wherein the buried layer is converted into the first porous layer and a layer of the substrate on the buried layer is converted into the second porous layer after anodizing.
1 6. The method according to claim 10, wherein the step of forming a first porous layer and a second porous layer on the substrate comprises:
anodizing the substrate to form a first porous layer; and
annealing the first porous layer to convert a top layer of the first porous layer into a second porous layer.
17. The method according to claim 1 6, further comprising: forming a third porous layer between the substrate and the first porous layer by anodizing, wherein the third porous layer is a porous Si layer or a porous SiGe layer, a porosity of the third porous layer is smaller than that of the first porous layer, and a pore size of the third porous layer is smaller than that of the first porous layer.
18. The method according to claim 10, wherein the first porous layer comprises a plurality of first regions and a plurality of second regions, in which each second region is formed between two adjacent first regions, a porosity of each first region is greater than that of each second region, and a pore size of each first region is greater than that of each second region.
19. The method according to claim 10, wherein the porosity of the first porous layer increases gradually from an interface between the first porous layer and the substrate to an interface between the first porous layer and the second porous layer.
PCT/CN2011/082174 2010-11-15 2011-11-14 Semiconductor structure and method for forming the same WO2012065536A1 (en)

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CN201010546357.1 2010-11-15
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