CN102104060A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN102104060A CN102104060A CN2010105463571A CN201010546357A CN102104060A CN 102104060 A CN102104060 A CN 102104060A CN 2010105463571 A CN2010105463571 A CN 2010105463571A CN 201010546357 A CN201010546357 A CN 201010546357A CN 102104060 A CN102104060 A CN 102104060A
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Abstract
The invention provides a semiconductor structure comprising a first semiconductor material substrate, a first porous structure layer, a second porous structure layer and a second semiconductor material layer, wherein the first porous structure layer is formed on the first semiconductor material substrate; the second porous structure layer is formed on the first porous structure layer; the porosity and the aperture of the second porous structure layer are both less than the porosity and the aperture of the first porous structure layer; and the second semiconductor material layer is formed on the second porous structure layer. The invention can release the thermal mismatch stress of Si materials and epitaxial materials through the porous structure layers, prevent the problems of cracking and the like of an epitaxial film with larger thickness and enhance the quality of an epitaxial film crystal, thereby extending an epitaxial material layer (such as GaN and the like) which has large thickness and higher thermal mismatch stress with the Si materials on a Si substrate; and in addition, the porous Si materials can be removed in a subsequent process, therefore a subsequent device process can not be influenced.
Description
Technical field
The present invention relates to semiconductor manufacturing and design field, particularly a kind of semiconductor structure and forming method thereof.
Background technology
In recent years, light-emitting diode (light emitting diode, LED) long with its life-span, luminous efficiency is high, volume is little, sturdy and durable, color abundant, is widely used in fields such as display screen, backlight, special lighting.The core of LED is the LED epitaxial wafer, and its primary structure comprises: substrate, resilient coating, n type semiconductor layer, active area luminescent layer, electronic barrier layer, p type semiconductor layer.As the active area luminescent layer of LED epitaxial wafer core between n type semiconductor layer and p type semiconductor layer, the PN junction that the interface of p type semiconductor layer and n type semiconductor layer is constituted.Because the substrate thermal coefficient of expansion different, and the restriction of deposition process with rete, therefore caused behind coating growth, can be because thermal mismatching and in rete, can produce internal stress, for example for the Al in LED field
2O
3(sapphire) substrate is at Al
2O
3Substrate Grown GaN epitaxial wafer will produce tension stress, if for example can produce compression at SiC substrate Grown GaN epitaxial wafer again.Yet Sapphire Substrate is very expensive, and wafer is not easy to do greatly, therefore causes very costliness of present LED.Because the Si material is cheap, therefore technical maturity, and diameter wafers is arranged, has occurred much using different materials based on the application of Si material as application needs such as photoelectricity, microwaves at present, as GaN etc.
But there are very big thermal stress mismatch in Si and these III-V group iii v compound semiconductor materials, and the thermal stress mismatch will can cause that be full of cracks (Crack) appears in film when big epitaxial thickness, and the film quality that extension is come out is not good, has therefore limited the thickness of film.
Summary of the invention
Purpose of the present invention is intended to solve at least one of above-mentioned technological deficiency, has particularly proposed a kind of semiconductor structure and forming method thereof.
For achieving the above object, one aspect of the present invention proposes a kind of semiconductor structure, comprising: first semiconductive material substrate; Be formed on first porous structure layer on the described first semiconductive material substrate top layer; Be formed on second porous structure layer on described first porous structure layer, wherein, porosity in described second porous structure layer and aperture are all less than porosity and aperture in described first porous structure layer; With second semiconductor material layer that is formed on described second porous structure layer.
In one embodiment of the invention, described first semiconductive material substrate comprises Si, low Ge component S iGe or its combination.
In one embodiment of the invention, described first porous structure layer and second porous structure layer are porous silicon structure sheaf or porous germanium silicon structure layer.
In one embodiment of the invention, also comprise: be formed on the 3rd porous structure layer between described first porous structure layer and described first semiconductive material substrate, wherein, described the 3rd porous structure layer is porous silicon structure sheaf or porous germanium silicon structure layer, and the porosity in described the 3rd porous structure layer and aperture are all less than porosity and aperture in described first porous structure layer.
In one embodiment of the invention, between described the 3rd porous structure layer and described first porous structure layer, cut and peel off.
In one embodiment of the invention, comprise a plurality of first areas and the interval second area between described two first areas in described first porous structure layer, wherein, the porosity of described first area and aperture are all greater than the porosity and the aperture of described second area.
In one embodiment of the invention, porosity in described first porous structure layer is gradual change, and from described first porous structure layer with the improving gradually at the interface to described first porous structure layer and described second porous structure layer at the interface of described first semiconductive material substrate.
In one embodiment of the invention, described second semiconductor material layer comprises the III-V group iii v compound semiconductor material.
The present invention has also proposed a kind of formation method of semiconductor structure on the other hand, may further comprise the steps: first semiconductive material substrate is provided; Form first porous structure layer and second porous structure layer on the described first semiconductive material substrate top layer, wherein, porosity in described second porous structure layer and aperture are all less than porosity and aperture in described first porous structure layer; With formation second semiconductor material layer on described second porous structure layer.
In one embodiment of the invention, described substrate comprises Si, low Ge component S iGe or its combination.
In one embodiment of the invention, describedly on the first semiconductive material substrate top layer, form first porous structure layer and second porous structure layer further comprises: described first semiconductive material substrate is carried out anodic oxidation, while forms first porous structure layer and second porous structure layer to the anode current that described first semiconductive material substrate applies impulse form with the top in described first semiconductive material substrate, wherein, described first porous structure layer and second porous structure layer are porous silicon structure sheaf or porous germanium silicon structure layer.
In one embodiment of the invention, also comprise before the anodic oxidation carrying out: described first semiconductive material substrate is injected to form implanted layer, and described implanted layer forms described first porous structure layer after anodic oxidation.
In one embodiment of the invention, describedly on the first semiconductive material substrate top layer, form first porous structure layer and second porous structure layer further comprises: described first semiconductive material substrate is carried out anodic oxidation to form first porous structure layer; Described first porous structure layer annealed form second porous structure layer with top at described first porous structure layer.
In one embodiment of the invention, also comprise: between described first semiconductive material substrate top layer and described first porous structure layer, form the 3rd porous structure layer by anodic oxidation, wherein, described the 3rd porous structure layer is porous silicon structure sheaf or porous germanium silicon structure layer, and the porosity in described the 3rd porous structure layer and aperture are all less than porosity and aperture in described first porous structure layer.
In one embodiment of the invention, between described the 3rd porous structure layer and described first porous structure layer, cut and peel off.
In one embodiment of the invention, described formation the 3rd porous structure layer, described first porous structure layer and described second porous structure layer further comprise: described first semiconductive material substrate is carried out anodic oxidation, and the while forms described the 3rd porous structure layer, described first porous structure layer and described second porous structure layer to the anode current that described first semiconductive material substrate applies the multistage pulses form with the top in described first semiconductive material substrate.
In one embodiment of the invention, comprise a plurality of first areas and the interval second area between described two first areas in described first porous structure layer, wherein, the porosity of described first area and aperture are all greater than the porosity and the aperture of described second area.This first porous structure layer forms by following steps: form mask layer on described first semiconductive material substrate; The described mask layer of etching is to form a plurality of openings; By described opening described first semiconductive material substrate is injected to form first injection zone at described opening part, described first injection zone is forming described first area through after the anodic oxidation.
In one embodiment of the invention, porosity in described first porous structure layer is gradual change, and from described first porous structure layer with the improving gradually at the interface to described first porous structure layer and described second porous structure layer at the interface of described first semiconductive material substrate.Concrete formation method is: described first semiconductive material substrate is injected, and described first semiconductive material substrate carried out anodic oxidation, simultaneously apply anode current, the trailing edge that described anode current has the rising edge of fast lifting and progressively reduces to described first semiconductive material substrate.
In one embodiment of the invention, described second semiconductor material layer comprises the III-V group iii v compound semiconductor material.
In the present invention, after follow-up epitaxy technique cooling, mechanical deformation or fracture by above-mentioned porous structure layer can discharge thermal mismatch stress, thereby can make the III-V family film of generation avoid the Crack phenomenon, therefore can the thicker III-V family material of growth fraction by the present invention.In addition, also can on porous structure layer, form the more porous structure layer in low porosity and aperture of one deck in the present invention again, thereby can eliminate the dislocation between first semi-conducting material and second semi-conducting material.More preferably, also can between first semiconductive material substrate and above-mentioned porous structure layer, form the more porous structure layer in low porosity and aperture of one deck again, thus convenient removal to porous structure layer.The present invention can discharge the thermal mismatch stress of Si material and epitaxial material by porous structure layer, prevents the generation of problem such as epitaxial film be full of cracks under the bigger thickness, improves the epitaxial film crystal mass.Therefore by the present invention can be on the Si substrate the big thickness of extension have greatly the epitaxial material layer of thermal mismatch stress (as GaN etc.) with the Si material, and porous Si material can be removed in subsequent technique, therefore also can not impact subsequent device technology.
The present invention adopts extension and the big semiconductor material layer of Si material thermal mismatching on the big porous silicon of porosity, can partial deformation take place in cooling procedure by the porous silicon layer of fragility discharge thermal mismatch stress, guarantee the intact of epitaxial thin film material layer, can the thicker epitaxial material layer of extension.Secondly, can control the release of thermal mismatch stress, provide favorable mechanical to support, further improve the quality of epitaxial film by patterned porous silicon (being the porous silicon structure of a plurality of first areas and second area).
Aspect that the present invention adds and advantage part in the following description provide, and part will become obviously from the following description, or recognize by practice of the present invention.
Description of drawings
Above-mentioned and/or additional aspect of the present invention and advantage are from obviously and easily understanding becoming the description of embodiment below in conjunction with accompanying drawing, wherein:
Fig. 1 is the semiconductor structure schematic diagram of the embodiment of the invention one;
Fig. 2 is the formation method flow diagram of the semiconductor structure of the embodiment of the invention one;
Fig. 3 is the semiconductor structure schematic diagram of the embodiment of the invention two;
Fig. 4 is the formation method flow diagram of the semiconductor structure of the embodiment of the invention two;
Fig. 5 is the semiconductor junction composition of the embodiment of the invention three.
Embodiment
Describe embodiments of the invention below in detail, the example of described embodiment is shown in the drawings, and wherein identical from start to finish or similar label is represented identical or similar elements or the element with identical or similar functions.Below by the embodiment that is described with reference to the drawings is exemplary, only is used to explain the present invention, and can not be interpreted as limitation of the present invention.
Disclosing hereinafter provides many different embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter parts and the setting to specific examples is described.Certainly, they only are example, and purpose does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and purpose clearly, itself not indicate the relation between various embodiment that discuss of institute and/or the setting.In addition, various specific technology and the examples of material that the invention provides, but those of ordinary skills can recognize the property of can be applicable to of other technologies and/or the use of other materials.In addition, first feature described below second feature it " on " structure can comprise that first and second features form the embodiment of direct contact, can comprise that also additional features is formed on the embodiment between first and second features, such first and second features may not be direct contacts.
The present invention mainly discharges the thermal mismatch stress that subsequent technique is introduced by the porous structure layer than macroporosity and aperture, and when forming subsequent device, this porous structure layer being removed, thereby the influence of having avoided the thermal mismatching of different semi-conducting materials to produce to device.
As shown in Figure 1, be the semiconductor structure schematic diagram of the embodiment of the invention one.This semiconductor structure comprises first semiconductive material substrate 1100, is formed on first porous structure layer 1200 and second porous structure layer 1300 on first semiconductive material substrate 1100, and is formed on second semiconductor material layer 1400 on second porous structure layer 1300.In an embodiment of the present invention, all less than porosity and aperture in first porous structure layer 1200, the porosity of first porous structure layer 1200 is greater than 30% porosity in second porous structure layer 1300 and aperture.Wherein, first semiconductive material substrate 1100 is different with the material of second semiconductor material layer 1400, for example, first semiconductive material substrate 1100 can comprise Si, low Ge component S iGe or its combination etc., and second semiconductor material layer 1400 can comprise III-V group iii v compound semiconductor material etc.Like this, in embodiments of the present invention,, therefore can follow-up thermal mismatch stress be discharged by above-mentioned first porous structure layer 1200 because the porosity and the aperture of first porous structure layer 1200 are all bigger.In addition, in an embodiment of the present invention, can help to improve the quality of growth second semiconductor material layer 1400 thereon by the second all less porous structure layer 1300 of porosity and aperture.Wherein, in one embodiment of the invention, first porous structure layer 1200 is a porous germanium silicon structure layer, and the Ge component in first porous structure layer 1200 is gradual change.The thinner thickness of second porous structure layer 1300, thus can be so that the stress of top second semiconductor material layer 1400 conducts to first porous structure layer 1200.In one embodiment of the invention, the porosity in first porous structure layer 1200 is greater than 20%.In one embodiment of the invention, the porosity in first porous structure layer 1200 is greater than 20%.Wherein, in one embodiment of the invention, the porosity and the aperture of second porous structure layer 1300 can be very little, and the porosity of this second porous structure layer 1300 and aperture can be changed into zero after annealing, promptly become the structure of atresia.
In one embodiment of the invention, first semiconductive material substrate 1100 is the germanium silicon substrate of silicon substrate or low germanium component, first porous structure layer 1200 and second porous structure layer 1300 are porous silicon structure sheaf or porous germanium silicon structure layer, are preferably the porous silicon structure sheaf in the present invention.Wherein, the thickness of first porous structure layer 1200 is greater than the thickness of second porous structure layer 1300, for example the thickness of first porous structure layer 1200 is about tens nm between the tens μ m, and the thickness of second porous structure layer 1300 is about several nm between tens nm, thereby makes things convenient for first porous structure layer 1200 that will discharge thermal mismatch stress in the subsequent technique to remove.
As shown in Figure 2, the formation method flow diagram for the semiconductor structure of the embodiment of the invention one may further comprise the steps:
Step S201 provides first semiconductive material substrate, 1100, the first semiconductive material substrate 1100 can comprise Si, low Ge component S iGe or its combination etc.
Step S202 forms first porous structure layer 1200 and second porous structure layer 1300 on first semiconductive material substrate 1100.In an embodiment of the present invention, can on first semiconductive material substrate 1100, form first porous structure layer 1200 and second porous structure layer 1300 in several ways, for example:
Mode one,
First semiconductive material substrate 1100 is carried out anodic oxidation, and the while forms first porous structure layer 1200 and second porous structure layer 1300 to the anode current that first semiconductive material substrate 1100 applies impulse form with the top in first semiconductive material substrate 1100.
Mode two,
Before carrying out anodic oxidation, earlier first semiconductive material substrate 1100 is injected to form implanted layer, wherein, in an embodiment of the present invention, can adopt multiple impurity, for example P, B etc.Then, to first implanted layer with second implanted layer carries out anodic oxidation so that implanted layer forms first porous structure layer 1200, and on first porous structure layer 1200, form second porous structure layer 1300.Wherein, this mode needs to combine with mode one.
Mode three,
First semiconductive material substrate 1100 is carried out anodic oxidation to form first porous structure layer 1200, and first porous structure layer 1200 is annealed forms second porous structure layer 1300 with the top at first porous structure layer 1200.
Mode four,
In one embodiment of the invention, porosity in first porous structure layer 1200 is gradual change, and from first porous structure layer 1200 with the improving gradually at the interface to first porous structure layer 1200 and second porous structure layer 1300 at the interface of first semiconductive material substrate 1100, so not only can discharge thermal mismatch stress, also can be used as the cutting peel ply.First porous structure layer 1200 forms by following steps: first semiconductive material substrate 1100 is injected, and first semiconductive material substrate 1100 carried out anodic oxidation, simultaneously apply anode current to first semiconductive material substrate 1100, wherein, the trailing edge that this anode current has the rising edge of fast lifting and progressively reduces, promptly this anode current slowly reduces after certain hour is kept in rising suddenly step by step.
Step S203 forms second semiconductor material layer 1400 on second porous structure layer 1300.Wherein, second semiconductor material layer 1400 can comprise III-V group iii v compound semiconductor material etc.
As shown in Figure 3, be the semiconductor structure schematic diagram of the embodiment of the invention two.This semiconductor structure 3000 comprises first semiconductive material substrate 3100, be formed on the 3rd porous structure layer 3200 on first semiconductive material substrate 3100, be formed on first porous structure layer 3300 and second porous structure layer 3400 on the 3rd porous structure layer 3200, and is formed on second semiconductor material layer 3500 on second porous structure layer 3400.
In an embodiment of the present invention, porosity in second porous structure layer 3400 and the 3rd porous structure layer 3200 and aperture are all less than porosity and aperture in first porous structure layer 3300.Wherein, first semiconductive material substrate 3100 is different with the material of second semiconductor material layer 3500, for example, first semiconductive material substrate 3100 can comprise Si, low Ge component S iGe or its combination etc., and second semiconductor material layer 3500 can comprise the III-V group iii v compound semiconductor material.Like this, in embodiments of the present invention,, therefore can follow-up thermal mismatch stress be discharged by above-mentioned first porous structure layer 3300 because the porosity and the aperture of first porous structure layer 3300 are all bigger.In addition, in an embodiment of the present invention, can improve dislocation between first semiconductive material substrate 3100 and second semiconductor material layer 3500 by the second all less porous structure layer 3400 of porosity and aperture.Secondly, in an embodiment of the present invention, the thickness of the 3rd porous structure layer 3200 is greater than the thickness of first porous structure layer 3300, for example the thickness of first porous structure layer 3300 is about tens nm between the hundreds of nm, and the thickness of second porous structure layer 3400 is about several nm between tens nm, the thickness of the 3rd porous structure layer 3200 is about tens nm between the tens μ m, because porosity difference, can between the 3rd porous structure layer 3200 and first porous structure layer 3300, cut easily like this and peel off, remove porous structure layer in the subsequent technique thereby make things convenient for.
In one embodiment of the invention, first semiconductive material substrate 3100 is the germanium silicon layer of silicon substrate or low germanium component, and the 3rd porous structure layer 3200, first porous structure layer 3300 and second porous structure layer 3400 are porous silicon structure sheaf or porous germanium silicon structure layer.
As shown in Figure 4, the formation method flow diagram for the semiconductor structure of the embodiment of the invention two may further comprise the steps:
Step S401 provides first semiconductive material substrate, 3100, the first semiconductive material substrate 3100 can comprise Si, low Ge component S iGe or its combination etc.
Step S402 forms the 3rd porous structure layer 3200, first porous structure layer 3300 and second porous structure layer 3400 on first semiconductive material substrate 3100.Wherein, the porosity of the 3rd porous structure layer 3200 and second porous structure layer 3400 and aperture are all less than porosity and aperture in first porous structure layer 3300.The thickness of the 3rd porous structure layer 3200 is greater than the thickness of first porous structure layer 3300, for example the thickness of first porous structure layer 3300 is about tens nm between the hundreds of nm, and the thickness of second porous structure layer 3400 is about several nm between tens nm, and the thickness of the 3rd porous structure layer 3200 is about tens nm between the tens μ m.In an embodiment of the present invention, can on first semiconductive material substrate 3100, form the 3rd porous structure layer 3200, first porous structure layer 3300 and second porous structure layer 3400 in several ways, for example:
Mode one,
First semiconductive material substrate 3100 is carried out anodic oxidation, and the while forms the 3rd porous structure layer 3200, first porous structure layer 3300 and second porous structure layer 3400 to the anode current that first semiconductive material substrate 3100 applies the multistage pulses form with the top in first semiconductive material substrate 3100.Wherein, the anode current of multistage pulses form is meant branch two-stage or the multistage amplitude that improves electric current gradually in this embodiment, thereby reaches the porosity of first porous structure layer 3300 and aperture all greater than the porosity of the 3rd porous structure layer 3200 and second porous structure layer 3400 and the purpose in aperture.
Mode two,
The formation of first porous structure layer 3300 before carrying out anodic oxidation, also needs first semiconductive material substrate 3100 is injected for convenience, and the controllable thickness of injecting the implanted layer of the degree of depth is made as the thickness of first porous structure layer 3300.Be first porous structure layer 3300 carrying out after the anodic oxidation that implanted layer just can be corroded like this.
Step S403 forms second semiconductor material layer 3500 on second porous structure layer 3400.Wherein, second semiconductor material layer 3500 can comprise III-V group iii v compound semiconductor material etc.
As shown in Figure 5, be the semiconductor junction composition of the embodiment of the invention three.This semiconductor structure comprises first semiconductive material substrate 1100, is formed on first porous structure layer 5200 and second porous structure layer 5300 on first semiconductive material substrate 5100, and is formed on second semiconductor material layer 5400 on second porous structure layer 5300.In this embodiment, comprise a plurality of first areas 6100 and the second area 6200 between two first areas 6100 at interval in first porous structure layer, wherein, the porosity of first area 6100 and aperture are all greater than the porosity and the aperture of second area 6200.Can form the first such porous structure layer by the following method.As on first semiconductive material substrate, forming mask layer earlier, this mask layer of etching is to form a plurality of openings afterwards, by these openings first semiconductive material substrate is injected to form first injection zone at opening part, then carry out anodic oxidation, owing to inject the damage that causes, therefore first injection zone just can form the first area through after the anodic oxidation.Like this, that just the porosity in the first area and aperture can be done is bigger, more helps discharging stress, simultaneously owing to be provided with the less second area in porosity and aperture between the first area as support, thereby can not cause subsiding because of discharging stress.
In the present invention, after follow-up epitaxy technique cooling, mechanical deformation by above-mentioned porous structure layer can discharge thermal mismatch stress, thereby can make the III-V family film of generation avoid the Crack phenomenon, therefore can the thicker III-V family material of growth fraction by the present invention.In addition, also can on porous structure layer, form the more porous structure layer in low porosity and aperture of one deck in the present invention again, thereby can eliminate the dislocation between first semi-conducting material and second semi-conducting material.More preferably, also can between first semiconductive material substrate and above-mentioned porous structure layer, form the more porous structure layer in low porosity and aperture of one deck again, thus convenient removal to porous structure layer.The present invention can discharge the thermal mismatch stress of Si material and epitaxial material by porous structure layer, prevents the generation of problem such as epitaxial film be full of cracks under the bigger thickness, improves the epitaxial film crystal mass.Therefore by the present invention can be on the Si substrate the big thickness of extension have greatly the epitaxial material layer of thermal mismatch stress (as GaN etc.) with the Si material, and porous Si material can be removed in subsequent technique, therefore also can not impact subsequent device technology.
The present invention adopts extension and the big semiconductor material layer of Si material thermal mismatching on the big porous silicon of porosity, can partial deformation take place in cooling procedure by the porous silicon layer of fragility discharge thermal mismatch stress, guarantee the intact of epitaxial thin film material layer, can the thicker epitaxial material layer of extension.Secondly, can control the release of thermal mismatch stress, provide favorable mechanical to support, further improve the quality of epitaxial film by patterned porous silicon (being the porous silicon structure of a plurality of first areas and second area).
Although illustrated and described embodiments of the invention, for the ordinary skill in the art, be appreciated that without departing from the principles and spirit of the present invention and can carry out multiple variation, modification, replacement and modification that scope of the present invention is by claims and be equal to and limit to these embodiment.
Claims (21)
1. a semiconductor structure is characterized in that, comprising:
First semiconductive material substrate;
Be formed on first porous structure layer on the described first semiconductive material substrate top layer;
Be formed on second porous structure layer on described first porous structure layer, wherein, porosity in described second porous structure layer and aperture are all less than porosity and aperture in described first porous structure layer; With
Be formed on second semiconductor material layer on described second porous structure layer.
2. semiconductor structure as claimed in claim 1 is characterized in that, described first semiconductive material substrate comprises Si, low Ge component S iGe or its combination.
3. semiconductor structure as claimed in claim 2 is characterized in that, described first porous structure layer and second porous structure layer are porous silicon structure sheaf or porous germanium silicon structure layer.
4. semiconductor structure as claimed in claim 3 is characterized in that, also comprises:
Be formed on the 3rd porous structure layer between described first porous structure layer and described first semiconductive material substrate, wherein, described the 3rd porous structure layer is porous silicon structure sheaf or porous germanium silicon structure layer, and the porosity in described the 3rd porous structure layer and aperture are all less than porosity and aperture in described first porous structure layer.
5. semiconductor structure as claimed in claim 4 is characterized in that, cuts between described the 3rd porous structure layer and described first porous structure layer and peels off.
6. semiconductor structure as claimed in claim 1, it is characterized in that, comprise a plurality of first areas and the interval second area between described two first areas in described first porous structure layer, wherein, the porosity of described first area and aperture are all greater than the porosity and the aperture of described second area.
7. semiconductor structure as claimed in claim 1, it is characterized in that, porosity in described first porous structure layer is gradual change, and from described first porous structure layer with the improving gradually at the interface to described first porous structure layer and described second porous structure layer at the interface of described first semiconductive material substrate.
8. semiconductor structure as claimed in claim 1 is characterized in that, described second semiconductor material layer comprises the III-V group iii v compound semiconductor material.
9. the formation method of a semiconductor structure is characterized in that, may further comprise the steps:
First semiconductive material substrate is provided;
Form first porous structure layer and second porous structure layer on the described first semiconductive material substrate top layer, wherein, porosity in described second porous structure layer and aperture are all less than porosity and aperture in described first porous structure layer; With
On described second porous structure layer, form second semiconductor material layer.
10. the formation method of semiconductor structure as claimed in claim 9 is characterized in that, described substrate comprises Si, low Ge component S iGe or its combination.
11. the formation method of semiconductor structure as claimed in claim 10 is characterized in that, describedly forms first porous structure layer and second porous structure layer further comprises on the first semiconductive material substrate top layer:
Described first semiconductive material substrate is carried out anodic oxidation, while forms first porous structure layer and second porous structure layer to the anode current that described first semiconductive material substrate applies impulse form with the top in described first semiconductive material substrate, wherein, described first porous structure layer and second porous structure layer are porous silicon structure sheaf or porous germanium silicon structure layer.
12. the formation method of semiconductor structure as claimed in claim 11 is characterized in that, also comprises before the anodic oxidation carrying out:
Described first semiconductive material substrate is injected to form implanted layer, and described implanted layer forms described first porous structure layer after anodic oxidation.
13. the formation method of semiconductor structure as claimed in claim 10 is characterized in that, describedly forms first porous structure layer and second porous structure layer further comprises on the first semiconductive material substrate top layer:
Described first semiconductive material substrate is carried out anodic oxidation to form first porous structure layer;
Described first porous structure layer annealed form second porous structure layer with top at described first porous structure layer.
14. the formation method of semiconductor structure as claimed in claim 13 is characterized in that, also comprises:
Between described first semiconductive material substrate top layer and described first porous structure layer, form the 3rd porous structure layer by anodic oxidation, wherein, described the 3rd porous structure layer is porous silicon structure sheaf or porous germanium silicon structure layer, and the porosity in described the 3rd porous structure layer and aperture are all less than porosity and aperture in described first porous structure layer.
15. the formation method of semiconductor structure as claimed in claim 14 is characterized in that, cuts between described the 3rd porous structure layer and described first porous structure layer and peels off.
16. the formation method of semiconductor structure as claimed in claim 14 is characterized in that, described formation the 3rd porous structure layer, described first porous structure layer and described second porous structure layer further comprise:
Described first semiconductive material substrate is carried out anodic oxidation, and the while forms described the 3rd porous structure layer, described first porous structure layer and described second porous structure layer to the anode current that described first semiconductive material substrate applies the multistage pulses form with the top in described first semiconductive material substrate.
17. the formation method of semiconductor structure as claimed in claim 9, it is characterized in that, comprise a plurality of first areas and the interval second area between described two first areas in described first porous structure layer, wherein, the porosity of described first area and aperture are all greater than the porosity and the aperture of described second area.
18. the formation method of semiconductor structure as claimed in claim 17 is characterized in that, described first porous structure layer forms by following steps:
On described first semiconductive material substrate, form mask layer;
The described mask layer of etching is to form a plurality of openings;
By described opening described first semiconductive material substrate is injected to form first injection zone at described opening part, described first injection zone is forming described first area through after the anodic oxidation.
19. the formation method of semiconductor structure as claimed in claim 9, it is characterized in that, porosity in described first porous structure layer is gradual change, and from described first porous structure layer with the improving gradually at the interface to described first porous structure layer and described second porous structure layer at the interface of described first semiconductive material substrate.
20. the formation method of semiconductor structure as claimed in claim 19, it is characterized in that, described first porous structure layer forms by following steps: described first semiconductive material substrate is injected, and described first semiconductive material substrate carried out anodic oxidation, simultaneously apply anode current, the trailing edge that described anode current has the rising edge of fast lifting and progressively reduces to described first semiconductive material substrate.
21. the formation method of semiconductor structure as claimed in claim 9 is characterized in that, described second semiconductor material layer comprises the III-V group iii v compound semiconductor material.
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| PCT/CN2011/082174 WO2012065536A1 (en) | 2010-11-15 | 2011-11-14 | Semiconductor structure and method for forming the same |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012065536A1 (en) * | 2010-11-15 | 2012-05-24 | Chuwen Wang | Semiconductor structure and method for forming the same |
| WO2012109797A1 (en) * | 2011-02-18 | 2012-08-23 | 晶元光电股份有限公司 | Photoelectric element and manufacturing method thereof |
| CN105428481A (en) * | 2015-12-14 | 2016-03-23 | 厦门市三安光电科技有限公司 | Nitride bottom layer and manufacturing method thereof |
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| EP4300541A1 (en) * | 2022-06-29 | 2024-01-03 | GlobalFoundries U.S. Inc. | Device over patterned buried porous layer of semiconductor material |
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| WO2012065536A1 (en) * | 2010-11-15 | 2012-05-24 | Chuwen Wang | Semiconductor structure and method for forming the same |
| WO2012109797A1 (en) * | 2011-02-18 | 2012-08-23 | 晶元光电股份有限公司 | Photoelectric element and manufacturing method thereof |
| CN105428481A (en) * | 2015-12-14 | 2016-03-23 | 厦门市三安光电科技有限公司 | Nitride bottom layer and manufacturing method thereof |
| CN113782457A (en) * | 2021-08-20 | 2021-12-10 | 长江存储科技有限责任公司 | Manufacturing method of bonded wafer and wafer bonding machine |
| CN113782457B (en) * | 2021-08-20 | 2023-11-21 | 长江存储科技有限责任公司 | Method for manufacturing bonding wafer and wafer bonding machine |
| EP4300541A1 (en) * | 2022-06-29 | 2024-01-03 | GlobalFoundries U.S. Inc. | Device over patterned buried porous layer of semiconductor material |
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| CN102104060B (en) | 2013-03-20 |
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