CN102104060B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN102104060B CN102104060B CN 201010546357 CN201010546357A CN102104060B CN 102104060 B CN102104060 B CN 102104060B CN 201010546357 CN201010546357 CN 201010546357 CN 201010546357 A CN201010546357 A CN 201010546357A CN 102104060 B CN102104060 B CN 102104060B
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Abstract
The invention provides a semiconductor structure comprising a first semiconductor material substrate, a first porous structure layer, a second porous structure layer and a second semiconductor material layer, wherein the first porous structure layer is formed on the first semiconductor material substrate; the second porous structure layer is formed on the first porous structure layer; the porosity and the aperture of the second porous structure layer are both less than the porosity and the aperture of the first porous structure layer; and the second semiconductor material layer is formed on the second porous structure layer. The invention can release the thermal mismatch stress of Si materials and epitaxial materials through the porous structure layers, prevent the problems of cracking and the like of an epitaxial film with larger thickness and enhance the quality of an epitaxial film crystal, thereby extending an epitaxial material layer (such as GaN and the like) which has large thickness and higher thermal mismatch stress with the Si materials on a Si substrate; and in addition, the porous Si materials can be removed in a subsequent process, therefore a subsequent device process can not be influenced.
Description
Technical field
The present invention relates to semiconductor manufacturing and design field, particularly a kind of semiconductor structure and forming method thereof.
Background technology
In recent years, light-emitting diode (light emitting diode, LED) is long with its life-span, luminous efficiency is high, volume is little, sturdy and durable, color abundant, is widely used in the fields such as display screen, backlight, special lighting.The core of LED is the LED epitaxial wafer, and its primary structure comprises: substrate, resilient coating, n type semiconductor layer, active area luminescent layer, electronic barrier layer, p type semiconductor layer.As the active area luminescent layer of LED epitaxial wafer core between n type semiconductor layer and p type semiconductor layer, the PN junction that the interface of p type semiconductor layer and n type semiconductor layer is consisted of.Because the substrate thermal coefficient of expansion different with rete, and the restriction of deposition process, therefore caused behind coating growth, can be because thermal mismatching and in rete, can produce internal stress, for example for the Al in LED field
2O
3(sapphire) substrate is at Al
2O
3The GaN epitaxial wafer of substrate growth will produce tension stress, if the GaN epitaxial wafer of for example growing at the SiC substrate again can produce compression.Yet Sapphire Substrate is very expensive, and wafer is not easy to do greatly, therefore causes present LED very expensive.Because the Si material is cheap, therefore technical maturity, and diameter wafers is arranged, has occurred much need to using different materials based on the application of Si material such as application such as photoelectricity, microwaves at present, such as GaN etc.
But, there are very large thermal stress mismatch in Si and these III-V group iii v compound semiconductor materials, the thermal stress mismatch will can cause when larger epitaxial thickness that be full of cracks (Crack) appears in film, and extension film quality out is not good, therefore limit the thickness of film.
Summary of the invention
Purpose of the present invention is intended to solve at least one of above-mentioned technological deficiency, has particularly proposed a kind of semiconductor structure and forming method thereof.
For achieving the above object, one aspect of the present invention proposes a kind of semiconductor structure, comprising: the first semiconductive material substrate; Be formed on the first porous structure layer on described the first semiconductive material substrate top layer; Be formed on the second porous structure layer on described the first porous structure layer, wherein, the porosity in described the second porous structure layer and aperture are all less than porosity and aperture in described the first porous structure layer; With the second semiconductor material layer that is formed on described the second porous structure layer.
In one embodiment of the invention, described the first semiconductive material substrate comprises Si, low Ge component S iGe or its combination.
In one embodiment of the invention, described the first porous structure layer and the second porous structure layer are porous silicon structure sheaf or porous germanium silicon structure layer.
In one embodiment of the invention, also comprise: be formed on the 3rd porous structure layer between described the first porous structure layer and described the first semiconductive material substrate, wherein, described the 3rd porous structure layer is porous silicon structure sheaf or porous germanium silicon structure layer, and the porosity in described the 3rd porous structure layer and aperture are all less than porosity and aperture in described the first porous structure layer.
In one embodiment of the invention, between described the 3rd porous structure layer and described the first porous structure layer, cut and peel off.
In one embodiment of the invention, comprise a plurality of first areas and the interval second area between described two first areas in described the first porous structure layer, wherein, the porosity of described first area and aperture are all greater than porosity and the aperture of described second area.
In one embodiment of the invention, porosity in described the first porous structure layer is gradual change, and from described the first porous structure layer with at the interface the improving gradually at the interface to described the first porous structure layer and described the second porous structure layer of described the first semiconductive material substrate.
In one embodiment of the invention, described the second semiconductor material layer comprises the III-V group iii v compound semiconductor material.
The present invention has also proposed a kind of formation method of semiconductor structure on the other hand, may further comprise the steps: the first semiconductive material substrate is provided; Form the first porous structure layer and the second porous structure layer on described the first semiconductive material substrate top layer, wherein, the porosity in described the second porous structure layer and aperture are all less than porosity and aperture in described the first porous structure layer; With formation the second semiconductor material layer on described the second porous structure layer.
In one embodiment of the invention, described substrate comprises Si, low Ge component S iGe or its combination.
In one embodiment of the invention, describedly on the first semiconductive material substrate top layer, form the first porous structure layer and the second porous structure layer further comprises: described the first semiconductive material substrate is carried out anodic oxidation, while forms the first porous structure layer and the second porous structure layer to the anode current that described the first semiconductive material substrate applies impulse form with the top in described the first semiconductive material substrate, wherein, described the first porous structure layer and the second porous structure layer are porous silicon structure sheaf or porous germanium silicon structure layer.
In one embodiment of the invention, also comprise before the anodic oxidation carrying out: described the first semiconductive material substrate is injected to form implanted layer, and described implanted layer forms described the first porous structure layer after anodic oxidation.
In one embodiment of the invention, describedly on the first semiconductive material substrate top layer, form the first porous structure layer and the second porous structure layer further comprises: described the first semiconductive material substrate is carried out anodic oxidation to form the first porous structure layer; Described the first porous structure layer annealed form the second porous structure layer with the top at described the first porous structure layer.
In one embodiment of the invention, also comprise: between described the first semiconductive material substrate top layer and described the first porous structure layer, form the 3rd porous structure layer by anodic oxidation, wherein, described the 3rd porous structure layer is porous silicon structure sheaf or porous germanium silicon structure layer, and the porosity in described the 3rd porous structure layer and aperture are all less than porosity and aperture in described the first porous structure layer.
In one embodiment of the invention, between described the 3rd porous structure layer and described the first porous structure layer, cut and peel off.
In one embodiment of the invention, described formation the 3rd porous structure layer, described the first porous structure layer and described the second porous structure layer further comprise: described the first semiconductive material substrate is carried out anodic oxidation, and the while forms described the 3rd porous structure layer, described the first porous structure layer and described the second porous structure layer to the anode current that described the first semiconductive material substrate applies the multistage pulses form with the top in described the first semiconductive material substrate.
In one embodiment of the invention, comprise a plurality of first areas and the interval second area between described two first areas in described the first porous structure layer, wherein, the porosity of described first area and aperture are all greater than porosity and the aperture of described second area.This first porous structure layer forms by following steps: form mask layer on described the first semiconductive material substrate; The described mask layer of etching is to form a plurality of openings; By described opening described the first semiconductive material substrate is injected to form the first injection zone at described opening part, described the first injection zone is forming described first area through after the anodic oxidation.
In one embodiment of the invention, porosity in described the first porous structure layer is gradual change, and from described the first porous structure layer with at the interface the improving gradually at the interface to described the first porous structure layer and described the second porous structure layer of described the first semiconductive material substrate.Concrete formation method is: described the first semiconductive material substrate is injected, and described the first semiconductive material substrate carried out anodic oxidation, simultaneously apply anode current to described the first semiconductive material substrate, the trailing edge that described anode current has the rising edge of fast lifting and progressively reduces.
In one embodiment of the invention, described the second semiconductor material layer comprises the III-V group iii v compound semiconductor material.
In the present invention, after follow-up epitaxy technique cooling, mechanical deformation by above-mentioned porous structure layer or fracture can the releasing heat mismatch stress, thereby can make the III-V family film of generation avoid the Crack phenomenon, therefore can the thicker III-V family material of growth fraction by the present invention.In addition, also can on porous structure layer, form again in the present invention the more porous structure layer in low porosity and aperture of one deck, thereby can eliminate the dislocation between the first semi-conducting material and the second semi-conducting material.More preferably, also can between the first semiconductive material substrate and above-mentioned porous structure layer, form again the more porous structure layer in low porosity and aperture of one deck, thus convenient removal to porous structure layer.The present invention can discharge the thermal mismatch stress of Si material and epitaxial material by porous structure layer, prevents the generation of the problem such as epitaxial film be full of cracks under the larger thickness, improves the epitaxial film crystal mass.Therefore by the present invention can be on the Si substrate the large thickness of extension with the epitaxial material layer larger thermal mismatch stress of Si material existence (such as GaN etc.), and porous Si material can be removed in subsequent technique, therefore also can not impact subsequent device technique.
The present invention adopts extension and the larger semiconductor material layer of Si material thermal mismatching on the large porous silicon of porosity, can partial deformation occur in cooling procedure by the porous silicon layer of fragility discharge thermal mismatch stress, guarantee the intact of epitaxial thin film material layer, can the thicker epitaxial material layer of extension.Secondly, can control the release of thermal mismatch stress by patterned porous silicon (being the porous silicon structure of a plurality of first areas and second area), good mechanical support is provided, further improve the quality of epitaxial film.
The aspect that the present invention adds and advantage in the following description part provide, and part will become obviously from the following description, or recognize by practice of the present invention.
Description of drawings
Above-mentioned and/or the additional aspect of the present invention and advantage are from obviously and easily understanding becoming the description of embodiment below in conjunction with accompanying drawing, wherein:
Fig. 1 is the semiconductor structure schematic diagram of the embodiment of the invention one;
Fig. 2 is the formation method flow diagram of the semiconductor structure of the embodiment of the invention one;
Fig. 3 is the semiconductor structure schematic diagram of the embodiment of the invention two;
Fig. 4 is the formation method flow diagram of the semiconductor structure of the embodiment of the invention two;
Fig. 5 is the semiconductor junction composition of the embodiment of the invention three.
Embodiment
The below describes embodiments of the invention in detail, and the example of described embodiment is shown in the drawings, and wherein identical or similar label represents identical or similar element or the element with identical or similar functions from start to finish.Be exemplary below by the embodiment that is described with reference to the drawings, only be used for explaining the present invention, and can not be interpreted as limitation of the present invention.
Disclosing hereinafter provides many different embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter parts and the setting of specific examples are described.Certainly, they only are example, and purpose does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and purpose clearly, itself not indicate the relation between the various embodiment that discuss of institute and/or the setting.In addition, the various specific technique that the invention provides and the example of material, but those of ordinary skills can recognize the property of can be applicable to of other techniques and/or the use of other materials.In addition, First Characteristic described below Second Characteristic it " on " structure can comprise that the first and second Characteristics creations are the direct embodiment of contact, also can comprise the embodiment of other Characteristics creation between the first and second features, such the first and second features may not be direct contacts.
The present invention mainly discharges the thermal mismatch stress that subsequent technique is introduced by the porous structure layer than macroporosity and aperture, and when forming subsequent device, this porous structure layer being removed, thereby the impact on device of having avoided the thermal mismatching of different semi-conducting materials to produce.
As shown in Figure 1, be the semiconductor structure schematic diagram of the embodiment of the invention one.This semiconductor structure comprises the first semiconductive material substrate 1100, is formed on the first porous structure layer 1200 and the second porous structure layer 1300 on the first semiconductive material substrate 1100, and is formed on the second semiconductor material layer 1400 on the second porous structure layer 1300.In an embodiment of the present invention, all less than porosity and aperture in the first porous structure layer 1200, the porosity of the first porous structure layer 1200 is greater than 30% the porosity in the second porous structure layer 1300 and aperture.Wherein, the first semiconductive material substrate 1100 is different from the material of the second semiconductor material layer 1400, for example, the first semiconductive material substrate 1100 can comprise Si, low Ge component S iGe or its combination etc., and the second semiconductor material layer 1400 can comprise III-V group iii v compound semiconductor material etc.Like this, in embodiments of the present invention, because porosity and the aperture of the first porous structure layer 1200 are all larger, therefore can follow-up thermal mismatch stress be discharged by above-mentioned the first porous structure layer 1200.In addition, in an embodiment of the present invention, can help to improve the quality of growth the second semiconductor material layer 1400 thereon by the second all less porous structure layer 1300 of porosity and aperture.Wherein, in one embodiment of the invention, the first porous structure layer 1200 is porous germanium silicon structure layer, and the Ge component in the first porous structure layer 1200 is gradual change.The thinner thickness of the second porous structure layer 1300, thus can be so that the stress of top the second semiconductor material layer 1400 conducts to the first porous structure layer 1200.In one embodiment of the invention, the porosity in the first porous structure layer 1200 is greater than 20%.In one embodiment of the invention, the porosity in the first porous structure layer 1200 is greater than 20%.Wherein, in one embodiment of the invention, porosity and the aperture of the second porous structure layer 1300 can be very little, and the porosity of this second porous structure layer 1300 and aperture can be changed into zero after annealing, namely become the structure of atresia.
In one embodiment of the invention, the first semiconductive material substrate 1100 is the germanium silicon substrate of silicon substrate or low germanium component, the first porous structure layer 1200 and the second porous structure layer 1300 are porous silicon structure sheaf or porous germanium silicon structure layer, are preferably in the present invention the porous silicon structure sheaf.Wherein, the thickness of the first porous structure layer 1200 is greater than the thickness of the second porous structure layer 1300, for example the thickness of the first porous structure layer 1200 is about tens nm between the tens μ m, and the thickness of the second porous structure layer 1300 is about several nm between tens nm, thereby make things convenient in the subsequent technique the first porous structure layer 1200 of releasing heat mismatch stress is removed.
As shown in Figure 2, the formation method flow diagram for the semiconductor structure of the embodiment of the invention one may further comprise the steps:
Step S201 provides the first semiconductive material substrate 1100, the first semiconductive material substrate 1100 can comprise Si, low Ge component S iGe or its combination etc.
Step S202 forms the first porous structure layer 1200 and the second porous structure layer 1300 on the first semiconductive material substrate 1100.In an embodiment of the present invention, can on the first semiconductive material substrate 1100, form in several ways the first porous structure layer 1200 and the second porous structure layer 1300, for example:
Mode one,
The first semiconductive material substrate 1100 is carried out anodic oxidation, and the while forms the first porous structure layer 1200 and the second porous structure layer 1300 to the anode current that the first semiconductive material substrate 1100 applies impulse form with the top in the first semiconductive material substrate 1100.
Mode two,
Before carrying out anodic oxidation, first the first semiconductive material substrate 1100 is injected to form implanted layer, wherein, in an embodiment of the present invention, can adopt multiple impurity, such as P, B etc.Then, to the first implanted layer with the second implanted layer carries out anodic oxidation so that implanted layer forms the first porous structure layer 1200, and on the first porous structure layer 1200, form the second porous structure layer 1300.Wherein, this mode needs to combine with mode one.
Mode three,
The first semiconductive material substrate 1100 is carried out anodic oxidation to form the first porous structure layer 1200, and the first porous structure layer 1200 is annealed forms the second porous structure layer 1300 with the top at the first porous structure layer 1200.
Mode four,
In one embodiment of the invention, porosity in the first porous structure layer 1200 is gradual change, and from the first porous structure layer 1200 with at the interface the improving gradually at the interface to the first porous structure layer 1200 and the second porous structure layer 1300 of the first semiconductive material substrate 1100, so not only can the releasing heat mismatch stress, also can be used as the cutting peel ply.The first porous structure layer 1200 forms by following steps: the first semiconductive material substrate 1100 is injected, and the first semiconductive material substrate 1100 carried out anodic oxidation, simultaneously apply anode current to the first semiconductive material substrate 1100, wherein, the trailing edge that this anode current has the rising edge of fast lifting and progressively reduces, namely this anode current slowly reduces after certain hour is kept in rising suddenly step by step.
Step S203 forms the second semiconductor material layer 1400 on the second porous structure layer 1300.Wherein, the second semiconductor material layer 1400 can comprise III-V group iii v compound semiconductor material etc.
As shown in Figure 3, be the semiconductor structure schematic diagram of the embodiment of the invention two.This semiconductor structure 3000 comprises the first semiconductive material substrate 3100, be formed on the 3rd porous structure layer 3200 on the first semiconductive material substrate 3100, be formed on the first porous structure layer 3300 and the second porous structure layer 3400 on the 3rd porous structure layer 3200, and is formed on the second semiconductor material layer 3500 on the second porous structure layer 3400.
In an embodiment of the present invention, the porosity in the second porous structure layer 3400 and the 3rd porous structure layer 3200 and aperture are all less than porosity and aperture in the first porous structure layer 3300.Wherein, the first semiconductive material substrate 3100 is different from the material of the second semiconductor material layer 3500, for example, the first semiconductive material substrate 3100 can comprise Si, low Ge component S iGe or its combination etc., and the second semiconductor material layer 3500 can comprise the III-V group iii v compound semiconductor material.Like this, in embodiments of the present invention, because porosity and the aperture of the first porous structure layer 3300 are all larger, therefore can follow-up thermal mismatch stress be discharged by above-mentioned the first porous structure layer 3300.In addition, in an embodiment of the present invention, can improve dislocation between the first semiconductive material substrate 3100 and the second semiconductor material layer 3500 by the second all less porous structure layer 3400 of porosity and aperture.Secondly, in an embodiment of the present invention, the thickness of the 3rd porous structure layer 3200 is greater than the thickness of the first porous structure layer 3300, for example the thickness of the first porous structure layer 3300 is about tens nm between the hundreds of nm, and the thickness of the second porous structure layer 3400 is about several nm between tens nm, the thickness of the 3rd porous structure layer 3200 is about tens nm between the tens μ m, because porosity is different, can between the 3rd porous structure layer 3200 and the first porous structure layer 3300, cut easily like this and peel off, remove porous structure layer in the subsequent technique thereby make things convenient for.
In one embodiment of the invention, the first semiconductive material substrate 3100 is the germanium silicon layer of silicon substrate or low germanium component, and the 3rd porous structure layer 3200, the first porous structure layer 3300 and the second porous structure layer 3400 are porous silicon structure sheaf or porous germanium silicon structure layer.
As shown in Figure 4, the formation method flow diagram for the semiconductor structure of the embodiment of the invention two may further comprise the steps:
Step S401 provides the first semiconductive material substrate 3100, the first semiconductive material substrate 3100 can comprise Si, low Ge component S iGe or its combination etc.
Step S402 forms the 3rd porous structure layer 3200, the first porous structure layer 3300 and the second porous structure layer 3400 on the first semiconductive material substrate 3100.Wherein, the porosity of the 3rd porous structure layer 3200 and the second porous structure layer 3400 and aperture are all less than porosity and aperture in the first porous structure layer 3300.The thickness of the 3rd porous structure layer 3200 is greater than the thickness of the first porous structure layer 3300, for example the thickness of the first porous structure layer 3300 is about tens nm between the hundreds of nm, and the thickness of the second porous structure layer 3400 is about several nm between tens nm, and the thickness of the 3rd porous structure layer 3200 is about tens nm between the tens μ m.In an embodiment of the present invention, can on the first semiconductive material substrate 3100, form in several ways the 3rd porous structure layer 3200, the first porous structure layer 3300 and the second porous structure layer 3400, for example:
Mode one,
The first semiconductive material substrate 3100 is carried out anodic oxidation, and the while forms the 3rd porous structure layer 3200, the first porous structure layer 3300 and the second porous structure layer 3400 to the anode current that the first semiconductive material substrate 3100 applies the multistage pulses form with the top in the first semiconductive material substrate 3100.Wherein, the anode current of multistage pulses form refers to minute two-stage or the multistage amplitude that improves gradually electric current in this embodiment, thereby reaches the porosity of the first porous structure layer 3300 and aperture all greater than the porosity of the 3rd porous structure layer 3200 and the second porous structure layer 3400 and the purpose in aperture.
Mode two,
Formation for convenient the first porous structure layer 3300 before carrying out anodic oxidation, also needs the first semiconductive material substrate 3100 is injected, and the thickness that injects the implanted layer of the degree of depth can be controlled to be the thickness of the first porous structure layer 3300.Be the first porous structure layer 3300 carrying out after the anodic oxidation that implanted layer just can be corroded like this.
Step S403 forms the second semiconductor material layer 3500 on the second porous structure layer 3400.Wherein, the second semiconductor material layer 3500 can comprise III-V group iii v compound semiconductor material etc.
As shown in Figure 5, be the semiconductor junction composition of the embodiment of the invention three.This semiconductor structure comprises the first semiconductive material substrate 1100, is formed on the first porous structure layer 5200 and the second porous structure layer 5300 on the first semiconductive material substrate 5100, and is formed on the second semiconductor material layer 5400 on the second porous structure layer 5300.In this embodiment, comprise a plurality of first areas 6100 and the interval second area 6200 between two first areas 6100 in the first porous structure layer, wherein, the porosity of first area 6100 and aperture are all greater than porosity and the aperture of second area 6200.Can form by the following method the first such porous structure layer.As on the first semiconductive material substrate, forming mask layer first, this mask layer of etching is to form a plurality of openings afterwards, by these openings the first semiconductive material substrate is injected to form the first injection zone at opening part, then carry out anodic oxidation, owing to inject the damage that causes, therefore the first injection zone just can form the first area through after the anodic oxidation.Like this, that just the porosity in the first area and aperture can be done is larger, more is conducive to discharge stress, simultaneously owing to be provided with the less second area in porosity and aperture between the first area as support, thereby can not cause subsiding because of discharging stress.
In the present invention, after follow-up epitaxy technique cooling, mechanical deformation by above-mentioned porous structure layer can the releasing heat mismatch stress, thereby can make the III-V family film of generation avoid the Crack phenomenon, therefore can the thicker III-V family material of growth fraction by the present invention.In addition, also can on porous structure layer, form again in the present invention the more porous structure layer in low porosity and aperture of one deck, thereby can eliminate the dislocation between the first semi-conducting material and the second semi-conducting material.More preferably, also can between the first semiconductive material substrate and above-mentioned porous structure layer, form again the more porous structure layer in low porosity and aperture of one deck, thus convenient removal to porous structure layer.The present invention can discharge the thermal mismatch stress of Si material and epitaxial material by porous structure layer, prevents the generation of the problem such as epitaxial film be full of cracks under the larger thickness, improves the epitaxial film crystal mass.Therefore by the present invention can be on the Si substrate the large thickness of extension with the epitaxial material layer larger thermal mismatch stress of Si material existence (such as GaN etc.), and porous Si material can be removed in subsequent technique, therefore also can not impact subsequent device technique.
The present invention adopts extension and the larger semiconductor material layer of Si material thermal mismatching on the large porous silicon of porosity, can partial deformation occur in cooling procedure by the porous silicon layer of fragility discharge thermal mismatch stress, guarantee the intact of epitaxial thin film material layer, can the thicker epitaxial material layer of extension.Secondly, can control the release of thermal mismatch stress by patterned porous silicon (being the porous silicon structure of a plurality of first areas and second area), good mechanical support is provided, further improve the quality of epitaxial film.
Although illustrated and described embodiments of the invention, for the ordinary skill in the art, be appreciated that without departing from the principles and spirit of the present invention and can carry out multiple variation, modification, replacement and modification to these embodiment that scope of the present invention is by claims and be equal to and limit.
Claims (21)
1. a semiconductor structure is characterized in that, comprising:
The first semiconductive material substrate;
Be formed on the first porous structure layer on described the first semiconductive material substrate top layer;
Be formed on the second porous structure layer on described the first porous structure layer; With
Be formed on the second semiconductor material layer on described the second porous structure layer, wherein, porosity in described the second porous structure layer and aperture are all less than porosity and aperture in described the first porous structure layer, discharging the thermal mismatch stress between described the first semiconductive material substrate and described the second semiconductor material layer, and improve the dislocation between described the first semiconductive material substrate and described the second semiconductor material layer.
2. semiconductor structure as claimed in claim 1 is characterized in that, described the first semiconductive material substrate comprises Si, low Ge component S iGe or its combination.
3. semiconductor structure as claimed in claim 2 is characterized in that, described the first porous structure layer and the second porous structure layer are porous silicon structure sheaf or porous germanium silicon structure layer.
4. semiconductor structure as claimed in claim 3 is characterized in that, also comprises:
Be formed on the 3rd porous structure layer between described the first porous structure layer and described the first semiconductive material substrate, wherein, described the 3rd porous structure layer is porous silicon structure sheaf or porous germanium silicon structure layer, and the porosity in described the 3rd porous structure layer and aperture are all less than porosity and aperture in described the first porous structure layer.
5. semiconductor structure as claimed in claim 4 is characterized in that, cuts between described the 3rd porous structure layer and described the first porous structure layer and peels off.
6. semiconductor structure as claimed in claim 1, it is characterized in that, comprise a plurality of first areas and the interval second area between described two first areas in described the first porous structure layer, wherein, the porosity of described first area and aperture are all greater than porosity and the aperture of described second area.
7. semiconductor structure as claimed in claim 1, it is characterized in that, porosity in described the first porous structure layer is gradual change, and from described the first porous structure layer with at the interface the improving gradually at the interface to described the first porous structure layer and described the second porous structure layer of described the first semiconductive material substrate.
8. semiconductor structure as claimed in claim 1 is characterized in that, described the second semiconductor material layer comprises the III-V group iii v compound semiconductor material.
9. the formation method of a semiconductor structure is characterized in that, may further comprise the steps:
The first semiconductive material substrate is provided;
On described the first semiconductive material substrate top layer, form the first porous structure layer and the second porous structure layer; With
On described the second porous structure layer, form the second semiconductor material layer, wherein, porosity in described the second porous structure layer and aperture are all less than porosity and aperture in described the first porous structure layer, discharging the thermal mismatch stress between described the first semiconductive material substrate and described the second semiconductor material layer, and improve the dislocation between described the first semiconductive material substrate and described the second semiconductor material layer.
10. the formation method of semiconductor structure as claimed in claim 9 is characterized in that, described substrate comprises Si, low Ge component S iGe or its combination.
11. the formation method of semiconductor structure as claimed in claim 10 is characterized in that, describedly forms the first porous structure layer and the second porous structure layer further comprises on the first semiconductive material substrate top layer:
Described the first semiconductive material substrate is carried out anodic oxidation, while forms the first porous structure layer and the second porous structure layer to the anode current that described the first semiconductive material substrate applies impulse form with the top in described the first semiconductive material substrate, wherein, described the first porous structure layer and the second porous structure layer are porous silicon structure sheaf or porous germanium silicon structure layer.
12. the formation method of semiconductor structure as claimed in claim 11 is characterized in that, also comprises before the anodic oxidation carrying out:
Described the first semiconductive material substrate is injected to form implanted layer, and described implanted layer forms described the first porous structure layer after anodic oxidation.
13. the formation method of semiconductor structure as claimed in claim 10 is characterized in that, describedly forms the first porous structure layer and the second porous structure layer further comprises on the first semiconductive material substrate top layer:
Described the first semiconductive material substrate is carried out anodic oxidation to form the first porous structure layer;
Described the first porous structure layer annealed form the second porous structure layer with the top at described the first porous structure layer.
14. the formation method of semiconductor structure as claimed in claim 13 is characterized in that, also comprises:
Between described the first semiconductive material substrate top layer and described the first porous structure layer, form the 3rd porous structure layer by anodic oxidation, wherein, described the 3rd porous structure layer is porous silicon structure sheaf or porous germanium silicon structure layer, and the porosity in described the 3rd porous structure layer and aperture are all less than porosity and aperture in described the first porous structure layer.
15. the formation method of semiconductor structure as claimed in claim 14 is characterized in that, cuts between described the 3rd porous structure layer and described the first porous structure layer and peels off.
16. the formation method of semiconductor structure as claimed in claim 14 is characterized in that, described formation the 3rd porous structure layer, described the first porous structure layer and described the second porous structure layer further comprise:
Described the first semiconductive material substrate is carried out anodic oxidation, and the while forms described the 3rd porous structure layer, described the first porous structure layer and described the second porous structure layer to the anode current that described the first semiconductive material substrate applies the multistage pulses form with the top in described the first semiconductive material substrate.
17. the formation method of semiconductor structure as claimed in claim 9, it is characterized in that, comprise a plurality of first areas and the interval second area between described two first areas in described the first porous structure layer, wherein, the porosity of described first area and aperture are all greater than porosity and the aperture of described second area.
18. the formation method of semiconductor structure as claimed in claim 17 is characterized in that, described the first porous structure layer forms by following steps:
On described the first semiconductive material substrate, form mask layer;
The described mask layer of etching is to form a plurality of openings;
By described opening described the first semiconductive material substrate is injected to form the first injection zone at described opening part, described the first injection zone is forming described first area through after the anodic oxidation.
19. the formation method of semiconductor structure as claimed in claim 9, it is characterized in that, porosity in described the first porous structure layer is gradual change, and from described the first porous structure layer with at the interface the improving gradually at the interface to described the first porous structure layer and described the second porous structure layer of described the first semiconductive material substrate.
20. the formation method of semiconductor structure as claimed in claim 19, it is characterized in that, described the first porous structure layer forms by following steps: described the first semiconductive material substrate is injected, and described the first semiconductive material substrate carried out anodic oxidation, simultaneously apply anode current to described the first semiconductive material substrate, the trailing edge that described anode current has the rising edge of fast lifting and progressively reduces.
21. the formation method of semiconductor structure as claimed in claim 9 is characterized in that, described the second semiconductor material layer comprises the III-V group iii v compound semiconductor material.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010546357 CN102104060B (en) | 2010-11-15 | 2010-11-15 | Semiconductor structure and forming method thereof |
| PCT/CN2011/082174 WO2012065536A1 (en) | 2010-11-15 | 2011-11-14 | Semiconductor structure and method for forming the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN 201010546357 CN102104060B (en) | 2010-11-15 | 2010-11-15 | Semiconductor structure and forming method thereof |
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| CN102104060A CN102104060A (en) | 2011-06-22 |
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| DE112011104913T5 (en) * | 2011-02-18 | 2013-12-24 | Epistar Corp. | Optoelectronic device and method for producing the same |
| CN105428481B (en) * | 2015-12-14 | 2018-03-16 | 厦门市三安光电科技有限公司 | Nitride bottom and preparation method thereof |
| CN113782457B (en) * | 2021-08-20 | 2023-11-21 | 长江存储科技有限责任公司 | Method for manufacturing bonding wafer and wafer bonding machine |
| US20240006524A1 (en) * | 2022-06-29 | 2024-01-04 | Globalfoundries U.S. Inc. | Device over patterned buried porous layer of semiconductor material |
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| US5350599A (en) * | 1992-10-27 | 1994-09-27 | General Electric Company | Erosion-resistant thermal barrier coating |
| US6376859B1 (en) * | 1998-07-29 | 2002-04-23 | Texas Instruments Incorporated | Variable porosity porous silicon isolation |
| US6375738B1 (en) * | 1999-03-26 | 2002-04-23 | Canon Kabushiki Kaisha | Process of producing semiconductor article |
| CN1795538A (en) * | 2003-05-30 | 2006-06-28 | S.O.I探测硅绝缘技术公司 | Substrate for stressed systems and method for growing crystal on the substrate |
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| US5350599A (en) * | 1992-10-27 | 1994-09-27 | General Electric Company | Erosion-resistant thermal barrier coating |
| US6376859B1 (en) * | 1998-07-29 | 2002-04-23 | Texas Instruments Incorporated | Variable porosity porous silicon isolation |
| US6375738B1 (en) * | 1999-03-26 | 2002-04-23 | Canon Kabushiki Kaisha | Process of producing semiconductor article |
| CN1795538A (en) * | 2003-05-30 | 2006-06-28 | S.O.I探测硅绝缘技术公司 | Substrate for stressed systems and method for growing crystal on the substrate |
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