GB2514268A

GB2514268A - Silicon carbide epitaxy

Info

Publication number: GB2514268A
Application number: GB1410481.4A
Authority: GB
Inventors: Peter John Ward
Original assignee: Anvil Semiconductors Ltd
Current assignee: Anvil Semiconductors Ltd
Priority date: 2011-10-26
Filing date: 2011-10-26
Publication date: 2014-11-19
Anticipated expiration: 2031-10-26
Also published as: HK1201637A1; GB2514268B; GB201410481D0

Abstract

A semiconductor device comprises: a monocrystalline silicon substrate 41 having a principal surface and a perimeter 42, the silicon substrate comprising an outer, annular region 44 running adjacent to the perimeter of the substrate and an inner region 43 disposed inside the outer region; a monocrystalline silicon carbide layer 31 disposed directly on the principal surface of the substrate 41 on the inner region 43 but not on or over the outer region 44 of the substrate 41; and a polycrystalline and/or amorphous silicon carbide layer 32 disposed on the outer region 44 but not on the inner region 43.

Description

Silicon carbide epitaxy

Field of the Invention

The present invention relates to silicon carbide epitaxy.

Background

Silicon carbide is a promising material for future power electronics applications because it can sustain much higher voltages than silicon and has a thermal conductivity similar to copper.

Silicon carbide exists in several different crystal forms (or "polytypes") depending on the sequence in which bilayers of silicon and carbon stack.

The most commonly-used polytype of silicon carbide is four-step hexagonal stacking sequence silicon carbide (4TT-SiC) because it is possible to grow this in single crystal form and produce wafers of the semiconductor material. However, these crystals arc produced by physical vapour transport PVT) process in which a powder of silicon carbide is sublimed at about 2,200 °C producing a vapour which travels and then condenses on a seed crystal. This process is very energy intensive and so silicon carbide wafers are much more expensive to produce than silicon wafers.

Another poytype of silicon carbide. 3-step cubic silicon carbide (3C-SiC), can in principle be grown epitaxially on silicon wafers because they share a cubic crystal form. In this case, a layer of silicon carbide for device fabrication could be realised more cheaply than fabricating a 4H-SiC wafer. However, there are two significant challenges to epitaxially growing a layer of 3-step cubic silicon carbide on silicon, i.e. 3C-SiC/Si heteroepitaxy.

Firstly. there is a httice mismatch het\veen 3-step cubic silicon carbide and the silicon wafer seed.

Secondly, silicon carbide and silicon have different coefficients of thermal expansion. When a layer of silicon carbide is grown on silicon at elevated temperatures and then cooled to room temperature, the silicon carbide contracts at a faster rate than silicon, thus the resulting structure bows.

When growing indium gallium aluminiun nitride (InGaA1N) on a sapphire or silicon carbide substrate, warping or cracking can he reduced by forming a layer of silicon dioxide on the substrate and selectively growing TnGaAIN through openings in the silicon dioxide layer on the exposed parts of the substrate, as described in JP 10 /0 135140 A. InGaA1N is generally grown at temperatures of no more than about 600 °C which is well below the melting point of the substrate. However, silicon carbide is generally grown at temperatures in excess of 1200 °f Furthermore, silicon carbide is grown using gas mixtures which etch silicon dioxide at such high temperatures.

Attempts have been made to address the problem of cracking in layers of silicon carbide by growing silicon carbide on a single-crystal silicon-germanium substrate having a Ge content of between 5 and 20%, as described in WO 03069657 A. Sum mary The present invention seeks to address the problem of water how and/or other mechanical deficiencies when growing silicon carbide on silicon.

\Ve described herein a method comprising providing a rnonocrystafline sihcon wafer having a principal surface which supports a masking layer having windows which expose corresponding regions of the silicon wafer, forming silicon carbide seed regions on the exposed regions of the wafer and growing monocrysta]]ine silicon carbide on the silicon carbide seed regions. the terni "silicon wafer" is intended to exclude a silicon-germanium wafer.

This method can help to reduce how-causing Forces across the silicon wafer resulting from differences in thermal expansion for silicon carbide and silicon.

Furthermore, regions of polycrystalline and/or amorphous silicon carbide may he formed between the monocrystalline silicon carbide layers which can help to reduce stress and, thus, contribute to reducing bow-causing forces.

Forming the silicon carbide seed regions preferably comprises forming a respective silicon carbide seed layer on each exposed region. Forming the silicon carbide layers preferably comprises growing a respective monocrystalline silicon carbide layer on each silicon carbide seed region.

Providing the silicon wafer having a principal surface which supports a masking layer may comprise providing the silicon wafer, forming a masking layer on the silicon wafer such that the masking layer directly overlies the principal surface, providing an etch mask having windows on the masking layer and etching the naasking layer through the windows in the etch mask to reach the principal surface of the wafer.

The masking layer i-nay comprise a dielectric layer. The dielectric layer may he a silicon dioxide layer. the silicon dioxide layer may be a thermal oxide layer or a deposited silicon dioxide layer. the masking layer may comprise a bilayer comprising first and second hilayer layers, for example, a layer of silicon dioxide (closest to the wafer) and a layer of silicon nitride (furthest from the water). The masking layer may have a thickness in a range between 2,000 and 10,000 A, for example, in a range between 4,000 and 6,000 A. The principal surface may he a first principal surface and the masking layer may he a first masking layer and the silicon wafer may have a second, opposite principal surface which supports a second masking layer. The second masking layer preferably is not patterned. The presence of a masking layer on the back of the wafer can help to stiffen the wafer. The first masking layer and the second masking layer may comprise the same material, fir e.xanaple silicon dioxide. the masking layer may conaprise a senaiconductor layer.

the semiconductor may he polycrystalline silicon.

The masking layer may he subsequently partially or fully etched by feed gases at elevated temperatures while in a reactor chamber. Even though the masking layer may be partially or Fully consumed, the masking layer can still serve to prevent or inhibit nonocrystalline silicon carbide from being grown on an underlying region of silicon, for example, by causing polycrystalline and/or amorphous silicon carbide to be forned between the inonocrystalline silicon carbide layers.

the nonocrystalline silicon carbide layers and the polycrystalline and/or amorphous silicon carbide region(s) naay he coplanar (i.e. fornaed in the same layer).

The monocrystalline silicon carbide layers and the polycrystalline and/or amorphous silicon carbide regions may lie in different planes due to the polycrystalline and/or amorphous silicon carbide region(s) being formed on the masking layer.

/\s mentioned earlier, polycrystalline and/or amorphous silicon carbide regions can help to reduce stress.

Forming the silicon carbide seed regions may comprise depositing carbon on the exposed regions of the wafer and converting the carbon into silicon carbide, for example, by reaction of carbon with underlying silicon. Growing monocrystalline silicon carbide may comprise growing silicon carbide having a thickness of at least 0.3 mm, at least 1 pm. at least 2 am or at least 3 na. Growing silicon carbide may comprise growing silicon carbide having a thickness of no more than 2 km. no more than 5 m or no more than 10 km. Growing the silicon carbide layers may comprise growing 3-step cubic silicon carbide.

Thc silicon wafer may have a diameter of at least 4 inches (101.6 mm) or 100 mm.

Thc wafer may havc a thickncss of at lcast 300 am. A silicon-on-insulator wafcr can be used. The silicon wafer may include an cpitaxially-grown silicon layer. The silicon wafer and/or epitaxially-grown silicon layer (if presett) may be doped, fir example, n-type or p-type.

Ihe method naay further comprise processing the silicon carbide layer to form semiconductor devices. The method may further comprise cutting the masking layer and the silicon wafer between the windows to form dies.

We describe herein a silicon semiconductor structure comprising a rnonocrystalline silicon wafer having a principal surface and spaced apart monocrystalline silicon carbide layers disposed directly on the principal surface of the wafer.

Each inonocrystalline silicon carbide layer may comprise a silicon carbide seed region formed directly on the principal surface of the silicon wafer and a silicon carbide layer disposed directly on the silicon carbide seed region.

The monocrystalline silicon carbide layers may comprise 3-step cubic silicon cart) ide.

/\ccording to a first aspect of the present invention there is provided a senuconductor device comprising a monocrystalline silicon substrate having a principal surface and a perimeter (or "edge") the silicon substrate comprising an outer region running adjacent to the perimeter and an inner region disposed inside the outer region, a monocrystalline silicon carbide layer disposed directly on the principal surface of the substrate on the inner region, but not on the outer region of the substrate.

The monocrystalline silicon carbide layer may comprise a silicon carbide seed region formed directly on the principal surface of the silicon substrate and a silicon carbide layer disposed direcdy on the silicon carbide seed region.

The monocrystai]inc silicon carbide aycr may comprise 3-step cubic silicon carbide.

-I-

Brief Description of the Drawings

Certain embodiments of the present invention will now he described, by way of example, with reference to the accompanying drawings, in which: Figures la to Ic illustrates stages during a first process of heteroepitaxy; Figures 2a to 2j illustrate stages during a method of fabricating silicon carbide semiconductor devices including a second ie of heteroepitaxy; Figure 3 is a flow diagram of a method of fabrication shown in Figures 2a to 2j; Figure 4a shows a first semiconductor device die formed by the method of fabrication shown in Figures 2a to 2j; Figure 4h shows a second semiconductor device die in which a masking layer is fully consumed; and Figure 3 schematically illustrates a silicon carbide semiconductor device.

Detailed Description

Before describing embodiments of the present invention, a silicon carbide/silicon heteroepitaxy process will be described with reference to Figures Ia to le which may be useful for understanding the present invention.

Figure la shows a monocrystalline silicon wafer 1 at a room temperature (about 25 °C). The silicon wafer 1 serves asa seed wafer on which a layer of three-step cubic silicon carbide (3C -SiC) can he epitaxially grown. The silicon wafer 1 has a diameter, d.

The silicon wafer 1 is placed in a silicon carbide epitaxial reactor (not shown) and is heated to about 1350 °C As shown (in highly schematic Form) in Figure Ib, the silicon wafer 1 expands when heated. The heated wafer has a diameter, d', greater than diameter, d, of the \vafer at room temperature.

Referring to Figure ic, the heated silicon wafer 1 is exposed to a vapour 2 of silicon and carbon reactive species in a chemical vapour deposition (cvi)) process. The vapour 2 adsorbs on the silicon wafer 1 forming three-step cubic silicon carbide.

Although, the lattice constants of silicon carbide and silicon normally differ, an epitaxial layer 3 of three-step cubic silicon carbide grotvs on the silicon substrate 1 matching the lattice constant of silicon by means of lattice dislocations (not shown) and forming a composite structure 4, as shown in Figure id.

Tjowever, as shown in Figure 1 e, when the composite structure 4 is aflowed to coo], the silicon carbide epitaxia] layer 3 shrinks at a faster rate than the underlying silicon wafer 3 and so the structure 4 bows.

For a silicon wafer I having a diameter of 150 mm, the edges ot the wafer can be raised by a distance.. 5. relative, to the centre of the wafer by about 10 nina.

The present invention seeks to address this problem.

Referring to Figures 2a to 2j and also to Figure 3, an embodiment of a method of /5 fabricating silicon carbide semiconductor devices which includes silicon carbide/silicon heteroepitaxy in accordance with the present invention will he described.

Figure 2a shows a monocrystalline silicon wafer 11 at a room temperature.

The silicon wafer 11 max have an off-axis, 11111 crystal orientation and may he polished on one or both sides 12, 13. The sides 12, 13 may also he referred to as "surfaces" or "faces". Other crystal orientations may he used, such as 11001 on or off axis. the silicon wafer ii has a thickness, t1, and a diameter, d1 (not shown). In this example. t = 500 am and d1 = 100 i-nm. The silicon wafer Ii has a wafer how less than 25 tm and so can he considered to have substantially no how.

The silicon wafer 11 serves as a crystal matrix on which a layer of monocrystalline three-step cubic silicon carbide. can be epitaxially grown on a first side 12 of the wafer 11 (hereinafter referred to as the cupper surface") on a monocrystalline silicon surface region 14. In some embodiments, silicon-on-insulator may he used and so the monocrystalline silicon surface region 14 can take the form of a monocrystalline silicon layer, for example having a thickness of about 50 to 200 nm, disposed on a layer of silicon dii xide. However, other wafers having different layer structures, hut which is mostly or predominantly comprised or made up of silicon can he used. For example, a wafer which mostly comprises silicon hut which has one or a few layers of non-silicon material embedded in it may he used. Thus, the tcta] thickness (or volume) of non-silicon material used in layers or regions of the wafer may make up no more about 1%, 0.1% or even 0.01 % of the wafer.

Before heteroepitaxy, the silicon wafer 11 may he processed, for example, by patterning and etching the upper surface 12 and/or the lower surface 13.

/0 Referring in particular to Figure 21), first and second masking layers 13, 16 are formed at the tipper and lower surfaces 12, 13 (Figure 2a) of the silicon wafer 11 (step S2).

The masking layers 13, 16 do not comprise monocrystalline silicon. The masking layers 15, 16 may comprise a dielectric material. however, a non-dielectric material (i.e. a semiconductor or conductive material) can be used. Moreover, silicon can be used, but in the form of polycrystalline silicon.

Each masking layer 15, 16 takes the form of a layer of thermal oxide and has a thickness of about 0.3 am. The thernial oxide layers 15, 16 may he grown by wet oxidation at a temperature between about 800 and 1200 °C. During thermal oxidation, silicon is sacrificially converted and so new first and second silicon surfaces 17, 18 are formed. Herein, the new first and second silicon surfaces 17, 18 are referred to as "principal surfaces".

Other dielectric materials, such silicon nitride (Si3N4), can he used. The layers 15, 16 can he formed using other processes, such as chemical vapour deposition (CYD).

It will he appreciated that if the dielectric materials are deposited and silicon is not sacrificially consumed, then the (original) silicon surfaces 12, 13 form the principal surfaces 17, 18 of the wafer 11. The masking layers 15, 16 may each comprise two layers (i.e. may each be bilayers) comprising, for example, a silicon dioxide layer and an overlying silicon nitride layer. the masking layers 15, 16 need not be the same -10-thickness and can he thinner or thicker. Suitable layer thicknesses can he found by routine experiment.

Thc presence of the second masking laycr 16 can help to stiffen the wafer 11.

Furthermore, the sccond masking layer 15 can help "balance" the first masking layer in a way which helps reduce wafer bow during subsequent proccssing stcps.

Referring to Figure 2c, an etch mask 19 is formed on an upper layer 20 of the first masking layer 15. The. etch mask 19 takes the form of a photoresist. The etch mask /0 17 takes the form of a rectangular grid defining an array of rectangular windows 21 which expose the. upper surface 20 of the masking layer 15.

Referring in particular to Figure 2d, unmasked regions 22 of the first masking layer IS are etched so as to transfer the pattern of the etch mask 19 into the first masking layer 15 (step 53). the masking layer 15 may be etched using a dry etch, such as a reactive ion etch (RIE) based on, for example, CIIF3 or a wet etch using buffered hydrofluoric acid (BIIF). After etching, the mask 19 is removed.

Referring in particular to Figure 2e, the resulting patterned wafer 23 includes a silicon wafer 11 supporting a patterned masking layer 24 on the upper surface 17 of the wafer 11.

The masking layer 24 takes the form of a grid defining an array of windows 25 which expose the upper surface 17 of the wafer 11. The windows 25 are generally rectangular (e.g. square) having a width w1 and (in an perpendicular direction) a length l (not shown) in a range between about 5 mm to 20 mm. The windows 25 are spaced apart by strips 26 of masking layer material 24 having a width w of about 100 gm which may later define scribe lanes.

The patterned wafer 23 is cleaned, e.g. using a Piranha etch, and is placed in a reactor @ot shown), such as an ACiS M10 marketed by EPE SpA., Baran2ate, italy.

the reactor chamber (not shown) is subjected to a high-vacuum bake out at about -11 - 500 °C and is re-filled with hydrogen at about 100 mhar. The patterned wafer 23 is heated via inductive heating of a susceptor (not shown).

The patterned wafer 23 may be cleaned in situ with hydrogen (IL) at a temperature, T of about 1100 °C fir about 2 minutes.

The patterned wafer 23 is heated as quickly as possible to a temperature, T, of 1370 °C in a flow of a carbon-containing gas, such as ethylene (C2IT.I), diluted in hydrogen (H2). /0

Referring in particular to Figure 2f. during ramping. a thin (i.e.. one, two or a few monolayers thickness) layers 29 of carbon are deposited directly on the upper surface 17 of the silicon wafer 11 in the windows 25. Carbon may also he deposited on the masking layer 24.

Referring also to Figure 2g, the thin layers 29 (Figure 2f of carbon are converted into corresponding thin layers 30 of silicon carbide (SiC) by reacting the carbon with underlying silicon in the wafer ii (step S5). the resulting thin silicon carbon layers 30 provide seed layers for subsequent deposition of silicon carbide.

The masking layer 24 may survive or may he consumed or partially-consumed by the hydrogen-rich atmosphere at the elevated temperatures.

During or after temperature ramping, the feed gases are changed from those used for carbonization to those used for silicon carbide epitaxy.

Referring to Figures 2h. silicon carbide is grown using a suitable silicon-carrying gas, such as trichlorosilane, SiHCI3, and a suitable carbon-carrying gas, such as ethylene C,114, at the elevated temperature, T2, of 1370 °C resulting in layers 31 of monocrystalline 3-step cubic silicon carbide in the windows 25 and a layer 32 of polycrystalline, mixed polytype silicon carbide on the thermal oxide layer 24 (step So). the carbon-carrying gas may be ethylene, propane (C3II) or other similar gas.

The silicon-carrying gas naay a silane. such as (mono)silane (SiH4) , a chlorosilane. -12-

such as trichiorosilane, SiHCI3, or another suitable silicon-carrying gas. Silicon carbide growth may he achieved using a more complex precursor gas which includes silicon and carbon.

As explained earher, the masking layer 24 may be (partially or fully) consumed by the hydrogen-rich atmosphere. Even if the masking lay er 24 does not survive, it can still serve to inhibit epitaxy (i.e. monocrystallinc growth) of silicon carbide on the silicon wafer 11 in the regions between the windows 25. For example, deposition of silicon carbide may result in fornaation of polycrystalline silicon carbide on the /0 silicon wafer ii in the regions beiwe.en the windows 25.

The silicon carbide layer 31 may he undoped (e.g. with a background doping of the order of 1011 cm I), lightly-doped or doped il-type with nitrogen (N) or phosphorus (P), or p-type with aluminium (Al) or l3oron (13).

Ihe reactor chamber (not shown) is purged and temperature is ramped down. When the processed wafer 33 cools, it does not bow (or at least bow excessively) because the thermal stresses only act over the dimensions of the window 25, not the whole wafer diameter. Furthern ore, the epitaxial layers 31 and underlying silicon wafer ii do not delaminate. The epitaxial layers 31 exhibit a low density of defects, for example, less than 100 mm2.

\Vith out wishing to he bound by theory, the overgrown wafer 33 does not how for one or more reasons. Firstly, forces caused by differences thermal expansion for silicon and silicon carbide act over smaller distances, i.e. windows 25, rather than over the whole wafer. Secondly, the presence of polycrystalline silicon carbide 32 can help to relax strain.

The silicon carbide layers 31 can he processed to form semiconductor devices, for example, power electronic devices or micro/nano electro-mechanical systems (MEMS/NRN'IS) devices. -13-

Processing may include high-temperature processing steps such as gate oxidation, implant annealing etc. and low-temperature processing such as thin film deposition, lithography, dry etching and so on (step S7) .A processed water 34 is shown in Figure 2i.

As shown in Figure 2j, after processing has been completed, the processed wafer 34 can be divided into dies 35 by cutting along the scribe lanes 26 (step S8).

the dies 35 are then packaged and wires bonded to the dies (not shown).

Referring to Figure 4a, a die 35 includes a substrate 41 having a perimeter 42. the die 35 and the substrate 41 are rectangular in plan view (i.e. rectangular in the x-y plane). The substrate 41 includes inner, core portion 43 and an outer, annular portion 44. The outer portion 44 runs adjacent to the perimeter 43 of the substrate 41 and has an annular width of at least 50 pm, typically about 100 gm (i.e. about half a scribe lane width). Any silicon carbide 32' formed over the outer portion 44 of the substrate 41 is polycrystaHine and/or amorphous. however, silicon carbide 31 forned on the inner portion 43 of die substrate 41 is nonocrystalline.

As explained earlier, the masking layer 24 may he etched during ramping.

carbonizing, C-to-SiC converting and/or SiC growing stages.

Referring to Figure 4h, a die 35 is shown in which polycrystalline and/or amorphous silicon carbide 32' is fornied directly on the outer portion 44 of the substrate 41. Thus, monocrystalline and polycrystalline and/or amorphous silicon carbide is formed in the same layer 45, hut an inner region 31 of the layer 45 is monocrystalline and an outer, annular region 32' is polycrystalhne and/or amorphous. Thus, the rnonocrystalline and polycrystalline carbide regions are laterally spaced.

Referring to Figure 5, an example of a semiconductor device 51 iii the form of a insulated gate bipolar transistor (IGBI) is shown. -14-

The device 51 has first and second 3-step cubic silicon carbide epitaxial layers 52a, 52h grown using the process hereinhefore described. The silicon carbide epitaxial layers 52a, 52h include a heavily-doped p-type layer 52a which is supported on a p-type silicon substrate 53 and which provides a 1)-type collector, and a lightly-doped n-type layer 521) which provides a drift region and which is supported on the p-type silicon carbide layer 52a. P-type wells 54 at the sLirface 55 of the epitaxial layer 52 provide body regions 54. N-type wells 56 within the p-type wells 54 previde contact regions. A channel 57 is formed beneath a gate 58 which separated using a gate dielectric layer 59.

Ihe 1G Bt shown in Figure 5 is able to support much greater breakdown voltages due to the use of silicon carbide in the epitaxial drift region 31.

It will he appreciated that many modiFications may he made to the embodiments hereinbefore described.

Different wafer diameters and thicknesses can be used. For example, wafers having diameters of 150 nun, 200 turn, 300 mm or more can be used.

The growth conditions, for instance temperature. pressure and/or precursors, can he varied and optirnised.

A material other than silicon can he used for the seed wafer. Thus, wafers made up of (or predominantly of) an inorganic semiconductor can he used.

The process need not involve growing a monocrystalline layer of semiconductor naaterial (i.e. heteroepitaxy), hut can involve growing non-monocrystalline layers, e.g. polycrystalline layers of semiconductor material.

/\n upper surface or face of a wafer may he referred to as a "front surface", "front face", "top surface" or "top face" of the wafer. Likewise, a lower surface or face may be referred to a "back surface", "rear surface", "back face", "rear face", bottom surface", bottom face'' of the wafer. -15-

Claims

Claims 1. A semiconductor device comprising: a tnonocrystalhne silicon substrate having a principal surface and a perimeter, the silicon substrate comprising an outer, annular region running adjacent to the perimeter of the sul strate and an inner region disposed inside the outer region; a monocrystalhne silicon carbide layer dispesed directly on the pritcipal surface of the substrate on the inner region but not on or over the outer region of the substrate; and a polycrystalline and/or aniorphous silicon carbide laye.r disposed on the outer region hut not on the inner region.
2. A semiconductor device according to claim 2, wherein the silicon carbide layer comprises: a monocrystalline silicon carbide seed region formed directly on the principal surface of the silicon substrate; and a monocrystalline silicon carbide layer disposed directly on the silicon carbide seed region.
3. A semiconductor device according to claim 1 or 2, wherein the silicon carbide layer comprises 3-step cubic silicon carbide.
4. A semiconductor device according to any one of claims 1 to 3. further comprising: a masking layer supported on the principal surface of the silicon substrate on the outer region hut not on the inner region
5. A semiconductor device according to any preceding claim, further comprising: polycrystalline silicon carbide layer disposed on the outer region but not on the inner region. -16-6. A semiconductor device according to claim 3, wherein polycrystalline monocrystalline silicon carbide layers are formed in different regions of a single silicon carbide layer.7. A scnflconductor device hercinbefore described with reference to the accotnpanying drawings.