JP5135719B2 - Trench type insulated gate semiconductor device - Google Patents

Description

  The present invention relates to a power semiconductor device having a trench gate structure.

  As power consumption of power converters is reduced, there is a great expectation for power consumption of power semiconductor devices (switching devices) that play a central role in the power conversion devices. In recent years, power semiconductor devices having a trench gate structure with a greatly improved channel density have been put to practical use as a measure that can greatly contribute to such low power consumption. The power semiconductor device having this trench gate structure is expanding its application range to IGBTs, thyristors, and diodes with a focus on power MOSFETs.

  Furthermore, in bipolar semiconductor devices such as IGBTs, a trench gate structure is applied to increase the channel density, and further, a structure in which holes injected from the collector side are difficult to escape to the emitter electrode, that is, an emitter region that is conductively connected to the emitter electrode. The area ratio is reduced (in other words, the area of the floating region portion insulated from the emitter electrode or connected with high resistance is relatively increased). As a result, the effect of accumulating carriers on the emitter side of the drift region can also be obtained. Therefore, even when the resistance component of the drift region is large and the on-voltage tends to increase as in a general high voltage semiconductor device, the low on-state There is an advantage that voltage and low steady loss can be achieved. However, in the trench gate type IGBT having a structure in which the floating region portion insulated from the emitter electrode is relatively increased with respect to the conductively connected emitter region, the on-voltage is reduced as described above. Since the gate-collector capacitance (mirror capacitance) increases, there is a problem that the switching loss tends to increase.

  To further explain this point, when the normal IGBT is turned on in the conventional structure, when the voltage between the gate and the emitter is increased, the gate-emitter capacitance is charged first (the former), and then the gate is turned on. The capacity between collectors (mirror capacity) is charged (the latter). However, in an IGBT having a floating region portion insulated from the emitter electrode, all the capacitance between the gate electrode is a gate-collector capacitance (mirror capacitance), and according to the resistance value in the floating region portion resistance-connected to the emitter electrode. The mirror capacity becomes a large size.

Here, an IGBT is taken up as such a trench gate type semiconductor device, and a sectional view thereof is shown in FIG. FIG. 8A is a plan view of a trench gate type IGBT having a surface pattern of a striped trench, and FIG. 8B is a cross-sectional view taken along the line H-H. In FIG. 8, the surface of a laminated semiconductor substrate of p-type collector layer 100 and n-type drift layer 101 or a p-type collector layer 100, and a three-layer laminated semiconductor substrate of an n ⁺ -type buffer layer and n-type drift layer 101 (not shown). p-type channel layer 102 is formed on the layer, further, that of the p-type channel layer 102, ^{n +} -type emitter region 103 is formed on the surface layer of the p-type channel region portion 102-1, as required ^{n +} A p ⁺ region (not shown) may be formed in a surface exposed portion of the p-type channel region portion 102-1 sandwiched between the type emitter regions 103. A trench 104 having a depth reaching the n-type drift layer 101 from the surface of the n ⁺ -type emitter region 103 through the p-type channel layer 102 is formed by anisotropic etching. A gate electrode 106 made of conductive polycrystalline silicon is filled with a gate oxide film 105 formed on the inner surface thereof. A structure in which the gate electrode 106 is provided in the trench 104 and a channel is formed by applying a predetermined gate voltage to the p-type channel region portion 102-1 along the side wall surface of the trench 104 is referred to as a trench gate structure. The gate electrode 106 made of conductive polycrystalline silicon is connected in contact with a gate runner 110 made of conductive polycrystalline silicon provided around the chip, and is not shown through a contact region 111 with the aluminum gate electrode. Focused on aluminum gate pad. together on the surface of the n ⁺ -type emitter region 103 contacts in common with the surface of the p-type channel region portion 102-1 adjacent to the ^{n +} -type emitter region 103, and further over to above the floating region portions 102-2 An emitter electrode 107 is provided. In FIG. 8A, the emitter electrode 107 is omitted for easy understanding.

  On the other hand, in this trench gate type IGBT, the p-type channel layer 102 is not directly in contact with the emitter electrode 107 but on the surface via the interlayer insulating film 108 in addition to the channel region portion indicated by the reference numeral 102-1. A region in contact, that is, a region portion called a floating region portion 102-2 is provided. A collector electrode 109 is provided on the back surface on the p-type collector layer 100 side. Further, FIG. 8 is only a plan view and a cross-sectional view of the main part of the trench gate type IGBT chip. Actually, the necessary number of annular trench gate patterns are connected to each other. Is formed with a breakdown voltage structure region (not shown), and a gate pad portion formed of an aluminum film is provided on a part of the chip surface.

  Like the above-described trench-type insulated gate IGBT shown in FIG. 8, the p-type channel layer 102 is directly in contact with the emitter electrode 107 and the p-type channel region portion 102-1 in direct conductive contact with the trench 104. When the area of the p-type channel region portion 102-1 that is divided into the floating region portion 102-2 and is in direct contact with the emitter electrode 107 is relatively narrow with respect to the floating region portion 102-2, As described above, since holes injected from the back collector layer 100 are difficult to escape to the emitter electrode 107, carriers are accumulated in the drift layer 101. As a result, the voltage drop in the drift layer 101 is reduced and the on-voltage between the collector electrode 109 and the emitter electrode 107 is reduced.

  However, although the on-voltage is reduced as described above, on the other hand, all the capacitance between the floating region portion 102-2 and the gate electrode 106 which is insulated without being in direct contact with the emitter electrode 107 is the gate-collector capacitance. Since (mirror capacitance) increases, turn-on loss increases and high-speed switching characteristics deteriorate. In addition, when a reverse bias voltage is applied between the collector and the emitter, the potential in this region becomes higher than the potential of the emitter electrode 107, so that the reverse blocking voltage between the collector and the emitter is lowered. Therefore, as a countermeasure against this, by connecting the floating region portion 102-2 to the emitter electrode 107 through a high resistance, the gate-collector capacitance is reduced without increasing the on-voltage, and A technology capable of improving the blocking voltage in the reverse direction has been developed and reported (see Patent Document 1, Patent Documents 2, 3, and 4 for descriptions of related technologies). According to this technique, the floating region portion and the emitter electrode are locally connected via a resistor (that is, a resistance connection). Specifically, for example, a process using a diffusion layer in the floating region portion as a sheet resistance is used. A power semiconductor device having a trench gate structure in which the gate-collector capacitance can be reduced without increasing the step and without increasing the on-voltage can be obtained.

  On the other hand, in the conventional IGBT having no floating region portion before the patent document, switching noise is easily generated when a high dV / dt including a high frequency component is applied between the collector and the emitter during switching. The charge / discharge time of the gate capacitance is adjusted to be large, dV / dt is reduced to reduce the main current increasing rate dIc / dt at turn-on, and switching noise is reduced.

However, if the gate resistance is increased, the turn-on loss of the IGBT increases. FIG. 9 shows the turn-on characteristics of the IGBTs switched with different gate resistances. As shown in FIG. 9, when the gate resistance is increased, the current slope (di / dt) at the turn-on time is reduced. This is preferable in terms of suppression of switching noise, but on the other hand, it increases voltage tail and increases switching loss. Therefore, in trench gate type IGBT, low di / dt is realized without increasing gate resistance as much as possible. Is preferred.
JP 2001-308327 A JP 2002-534811 A JP 2003-101020 A JP 2005-175425 A

  However, the trench gate type IGBT having a structure connected to the emitter electrode 107 via a high resistance locally with respect to the floating region described above can reduce the gate-collector capacitance without increasing the on-voltage. However, if a large current flows through the floating region at turn-on, the potential of the floating region may rise significantly due to the voltage drop caused by the sheet resistance provided in the floating region. is there. In addition, in that case, the displacement current generated thereby charges the capacitance between the gate and the emitter regardless of the gate resistance, and the turn-on di / dt is increased to increase the radiation noise.

  In the invention described in Patent Document 4, a low on-voltage is reduced by narrowing the pitch of the plurality of emitter electrode contact regions provided in the interlayer insulating film on the surface of the floating region part to some extent and adjusting the sheet resistance therebetween. In this structure, when the gate-emitter capacitance is charged regardless of the gate resistance and the turn-on dIc / dt is increased to a large current, the gate-collector capacitance is reduced. In order to further reduce the sheet resistance, it is necessary to reduce the pitch of the emitter electrode contact regions and further increase the number of contact regions. Then, the amount of holes extracted increases, the carrier accumulation effect decreases, and the on-voltage increases, so there is a limit to cope with the above-mentioned large current, and it is difficult to adjust the sheet resistance beyond that There's a problem.

  The present invention has been made in view of the above points, and an object of the present invention is to charge the capacitance between the gate and the emitter regardless of the gate resistance without reducing the reverse breakdown voltage between the collector and the emitter. To provide a trench type insulated gate semiconductor device capable of suppressing an increase in turn-on di / dt and having a low on-voltage and a small mirror capacitance even when the current is large enough to increase the turn-on dIc / dt. It is.

According to the first aspect of the present invention, the first semiconductor layer made of a semiconductor substrate of one conductivity type and the second semiconductor layer of another conductivity type formed on one main surface layer of the semiconductor substrate. A third semiconductor layer of another conductivity type formed on the other main surface layer of the semiconductor substrate, a fourth semiconductor region of one conductivity type selectively formed on the surface layer of the second semiconductor layer, A trench that penetrates the second semiconductor layer from the surface of the semiconductor region and reaches the first semiconductor layer, and a surface that is common to both surfaces of the second semiconductor layer and the fourth semiconductor region sandwiched between the trenches on the surface of the second semiconductor layer. A first electrode that is in contact; a polysilicon gate electrode provided in the trench via an insulating film; and a surface of the second semiconductor layer, wherein the first electrode is in contact with the first electrode via an interlayer insulating film . Conductive contact is made between the fifth semiconductor region and the surface of the third semiconductor layer. In the insulated gate semiconductor device comprising a second electrode, the surface layer of the fifth high concentration at the surface concentration than the impurity concentration of the semiconductor region is 10 ¹⁹ cm ^-3 other conductivity type sixth region of the is more than the fifth semiconductor region formed in the at least 20μm distance is connected before Symbol conductive and the first electrode to form a contact region in the interlayer insulating film of the fifth semiconductor region surface to keep the between the sixth region, said sixth region The object can be achieved by providing a trench type insulated gate semiconductor device comprising a structure having a sheet resistance function of a predetermined size by the fifth semiconductor region between the contact regions .

According to a second aspect of the present invention, the trench type insulated gate semiconductor device according to the first aspect of the present invention is preferably such that the sixth region is formed deeper than the trench.
According to the invention of claim 3, the trench type insulated gate semiconductor device according to claim 1, wherein the fifth semiconductor region is divided into a plurality of regions by a trench. It is desirable.

According to the present invention, the turn-on di at the time of a large current such that the gate-emitter capacitance is charged regardless of the gate resistance and the turn-on dIc / dt is increased without reducing the reverse breakdown voltage between the collector and the emitter. It is possible to provide a trench type insulated gate semiconductor device that can suppress an increase in / dt and can have a low on-state voltage and a small mirror capacitance.
In short, the present invention provides a contact region as small as possible to electrically connect the floating region portion and the emitter electrode, and is separated from this contact region by a distance corresponding to the sheet resistance necessary to keep a low on-voltage. By forming an impurity layer with a higher impurity concentration than the floating region ahead, the potential rise in the floating region due to large current flowing through the sheet resistance is minimized, and a low on-voltage and low mirror capacitance Therefore, a trench type insulated gate semiconductor device can be realized.

Hereinafter, a trench type insulated gate semiconductor device according to the present invention will be described in detail with reference to the drawings. The present invention is not limited to the description of the examples described below unless it exceeds the gist described in the claims.
FIGS. 1-1 to 7 are a plan view and a sectional view of a trench type insulated gate semiconductor device according to the present invention. FIG. 9 is a relationship diagram by simulation of the resistance value of the IGBT and the reduction rate of the peak current according to the present invention. FIG. 10 is a relationship diagram of the resistance value and the on-voltage of the IGBT according to the present invention by simulation.

  As an embodiment according to the present invention, a trench type insulated gate IGBT is shown in FIGS. 1-1 and 1-2. 1-1 (a) is a top view, FIG. 1-2 (b) is an AA cross-sectional view of FIG. 1-1, and FIG. 1-2 (c) is a BB cross-section of FIG. 1-1. The figure is shown. In order to facilitate understanding in the top view (a) of FIG. 1-1, the upper emitter electrode 7 and the interlayer insulating film 8 depicted in the cross-sectional view (b) of FIG. 1-2 are removed. The difference from FIG. 8 is that in FIGS. 1-1 and 1-2, the contact region 11 between the emitter electrode 7 provided on the interlayer insulating film 8 and the floating region portion 2-2, and the floating region portion 2-2. In other words, a high impurity region 2-3 of the same conductivity type provided therein is additionally formed.

In the IGBT according to the example 1, the gate-collector capacitance can be reduced and the reverse blocking voltage can be improved without increasing the on-voltage. In addition, the emitter electrode 7 is locally connected through a high resistance, and a p-type high impurity region 2-3 is further provided at the center in the long side direction of the p-type floating region 2-2. It is a feature. The other parts are the same as in FIG. With this structure, the p-type floating region 2-2 between the high impurity region 2-3 and the contact region 11 functions as a resistance region, and the formation of the high impurity region 2-3 is the emitter. Since it can be formed simultaneously with the high-concentration p ⁺ region 2-4 in contact with the electrode 7, the effect of the present invention can be obtained only by changing the pattern without adding a new process. In the first embodiment, the resistance value is adjusted by providing the high impurity concentration region 2-3 in the floating region 2-2. Therefore, as described in Patent Document 4, many contact regions are provided in the floating region. It is not necessary to adjust the resistance value, and the resistance value can be adjusted only by providing two contact regions in the floating region surrounded by the trench gate. The problem in the IGBT described in Patent Document 4 that the ratio of accumulation in the drift region is reduced and the on-voltage is increased is solved.

Actually, as shown in FIG. 1-1 (a), a contact region 11 with the emitter electrode is provided in the vicinity of the terminal end of the floating region surrounded by the trench gate 4, and a certain distance, for example, 20 μm is provided therefrom. A high impurity concentration region 2-3 is formed in the central portion of the floating region that is separated by a distance. In this case, the surface concentration of the p-type floating region is on the order of 10 ¹⁷ cm ⁻³ , and the surface concentration of the central p-type high impurity region is 10 ¹⁹ cm ⁻³ or more. Since the sheet resistance of the p-type floating region is about 400Ω / square (□), 400Ω / □ × 20 μm = 800 mΩ. Since the resistance including the respective resistances 41 between the contact region 11 and both ends of the high impurity concentration region 2-3 is 800 mΩ, the resistance 41 on one side is 400 mΩ. The on-voltage when the resistance value is 400 mΩ is about 1.9 V from the simulation relationship diagram of the on-voltage and resistance in the IGBT of Example 1 shown in FIG. On the other hand, FIG. 10 shows that the resistor 41 should be 400 mΩ or more in order to make the ON voltage 1.9 V or less. Further, from the simulation relationship diagram between the peak current reduction rate and the resistance shown in FIG. 9, it can be seen that when the resistance value is 400 mΩ or more, the peak current reduction rate is 62% or more. Therefore, it can be seen that there is an effect that an increase in di / dt is suppressed and a low ON voltage and a small mirror capacitance can be obtained.

  2A is a top view of FIG. 2A, FIG. 2B is a cross-sectional view taken along line AA of FIG. 2-1, and FIG. 2C is a cross-sectional view taken along line BB of FIG. The figure is shown. In the trench type insulated gate IGBT of FIGS. 2-1 and 2-2, the floating region portion 2-2 is locally connected to the emitter electrode 7 through the high resistance 41, and further, the p type floating region 2 is connected. -2 is provided with a p-type high impurity concentration region 2-3 at the center in the long-side direction, similar to the first embodiment, but the depth of the p-type high impurity concentration region 2-3 is The difference from the first embodiment is that the floating region 2-2 and the trench 4 are deeper than the depth. In the case of this structure, the concentration of the electric field is relaxed in the high impurity concentration region 2-3, which is preferable to the structure of Example 1 in this respect.

  In the trench-type insulated gate IGBT shown in FIG. 3, the floating region 2-2 is divided by a plurality of trenches, and the conductive polysilicon buried in each trench is connected to each other by the polysilicon 15 and further conductively connected to the emitter electrode. The second embodiment is different from the first embodiment in that the conductive polysilicon buried in the trench in the floating region is set to the same potential as the emitter electrode. FIG. 4 shows a modification of the trench type insulated gate IGBT having a different plane pattern shown in FIG.

  In the trench-type insulated gate IGBT shown in FIG. 5, the floating region 2-2 is divided by a plurality of trenches 4, and the conductive polysilicon 6 embedded in each trench 4 is in a floating state with respect to each other. This is different from the trench type insulated gate IGBT shown in FIGS. In the trench-type insulated gate IGBT shown in FIG. 6, the floating region 2-2 is divided by a plurality of trenches 4, and the conductive polysilicon 6 embedded in each trench 4 is insulated from each other by the interlayer insulating film 8 to be in a floating state. Has been. In the trench-type insulated gate IGBT shown in FIG. 7, the floating region 2-2 is divided by a plurality of trenches 4, and the conductive polysilicon 6 embedded in each trench 4 is connected to each other.

It is a top view of IGBT concerning the trench type insulated gate semiconductor device of this invention. (B) is AA sectional drawing of FIGS. 1-1, (c) is the BB sectional drawing. It is a top view of IGBT concerning the trench type insulated gate semiconductor device of this invention. (B) is AA sectional drawing of FIG. 2-1, (c) is the BB sectional drawing. (A) of IGBT concerning the trench type insulated gate semiconductor device of this invention is a top view, (b) is CC plane figure of top view (a). (A) of IGBT concerning the trench type insulated gate semiconductor device of this invention is a top view, (b) is DD sectional drawing of a top view (a). (A) of IGBT concerning the trench type insulated gate semiconductor device of this invention is a top view, (b) is EE sectional drawing of a top view (a). (A) of IGBT concerning the trench type insulated gate semiconductor device of this invention is a top view, (b) is FF sectional drawing of a top view (a). (A) of IGBT concerning the trench type insulated gate semiconductor device of this invention is a top view, (b) is GG sectional drawing of a top view (a). (A) of the IGBT concerning the conventional trench type insulated gate semiconductor device is a top view, (b) is HH sectional drawing of a top view (a). It is a related figure by simulation of the resistance value of IGBT of this invention, and the reduction rate of a peak current. FIG. 6 is a relationship diagram by simulation of the resistance value and the on-voltage of the IGBT of the present invention.

Explanation of symbols

1 drift layer 2 channel layer 2-1 channel region 2-2 floating region 2-3 p-type high impurity region 2-4 p ⁺ region 3 n ⁺ -type emitter region 4 trench 5 gate insulating film 6 conductive polysilicon gate electrode 7 Emitter electrode 8 Interlayer insulating film 9 Collector electrode 10 Collector layer 11 Contact region 12 Gate runner 13 Aluminum gate electrode 14 Resistance 15 Polysilicon.

Claims (3)

A first semiconductor layer composed of a semiconductor substrate of one conductivity type, a second semiconductor layer of another conductivity type formed on one main surface layer of the semiconductor substrate, and another formed on the other main surface layer of the semiconductor substrate a third semiconductor layer of the conductivity type, the second and the fourth semiconductor region of one conductivity type which is selectively formed in the surface layer of the semiconductor layer, the first semiconductor from the surface of the fourth semiconductor region through the second semiconductor layer A trench reaching the layer, a first electrode in common contact with both surfaces of the second semiconductor layer and the fourth semiconductor region sandwiched between the trenches on the surface of the second semiconductor layer, and an insulating film in the trench A polysilicon gate electrode provided on the surface of the second semiconductor layer, electrically conductive on the surface of the third semiconductor layer, and a fifth semiconductor region of another conductivity type in contact with the first electrode via an interlayer insulating film. In an insulated gate semiconductor device having a second electrode in contact , Said sixth region of the other conductivity type high concentration at the surface concentration than the impurity concentration is 10 ¹⁹ cm ^-3 or more fifth semiconductor region is formed on the surface layer of the fifth semiconductor region, and the sixth region at least 20μm distance is connected before Symbol conductive and the first electrode to form a contact region in the interlayer insulating film of the fifth semiconductor region surface to keep the while, the fifth between the sixth region and the contact region A trench type insulated gate semiconductor device comprising a structure having a sheet resistance function of a predetermined size by a semiconductor region . The trench type insulated gate semiconductor device according to claim 1, wherein the sixth region is formed deeper than the trench. The trench type insulated gate semiconductor device according to claim 1, wherein the fifth semiconductor region is divided into a plurality of regions by a trench.

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