JP5070668B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a semiconductor device constituting a power MOSFET or IGBT (insulated gate bipolar transistor) having a trench gate structure.
[0002]
[Prior art]
In recent years, trench gate structures having the advantage of a dramatic improvement in channel density have been put to practical use in power MOSFETs and IGBTs, thyristors and diodes used in power converters. In particular, in a bipolar device such as an IGBT, the effect of carrier accumulation is improved by adopting a trench gate structure, so that a loss can be reduced in a high breakdown voltage device with a small contribution of a channel resistance component.
[0003]
FIG. 5 is a cross-sectional view showing a configuration of a conventional non-punch-through IGBT having a trench gate structure. As shown in FIG. 5, in this IGBT, a channel layer 12 having a uniform thickness is formed on the surface of the FZ wafer 1 to be the drift layer 11. The emitter region 13 is selectively formed on the surface layer of the channel layer 12. The gate electrode 14 made of polysilicon is provided through a gate oxide film 15 in a trench reaching the drift layer 11 from the surface of the emitter region 13 through the channel layer 12. The emitter electrode 16 is formed in common contact with a part of the emitter region 13 and the channel layer 12 (a portion sandwiched between two adjacent emitter regions 13) via the interlayer insulating film 17. On the other hand, a collector layer 18 is formed on the back surface of the FZ wafer 1, and a collector electrode 19 is further formed.
[0004]
In the IGBT having the configuration shown in FIG. 5, the larger the protruding amount “a” of the trench from the channel layer 12, the larger the distance between two adjacent trenches, that is, the distance b between two trenches sandwiching two opposing emitter regions 13 and 13. The narrower the hole is, the more difficult it is for holes injected from the collector layer 18 to escape to the emitter electrode 16. Therefore, carriers are accumulated in the drift layer 11, and the voltage drop in the drift layer 11 is reduced.
[0005]
[Problems to be solved by the invention]
However, there is a process limit to the distance between adjacent trenches. Further, when the extension of the trench from the channel layer is increased, the electric field concentration at the bottom portion of the trench increases, so that the breakdown voltage between the collector and the emitter is lowered.
[0006]
The present invention has been made in view of the above problems, and can improve the carrier accumulation effect and reduce the voltage drop in the drift layer without reducing the collector-emitter breakdown voltage. An object of the present invention is to provide a semiconductor device.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor device according to the present invention is a semiconductor device having a trench gate structure in which a first region in contact with an emitter electrode is trenched in a plurality of regions of a channel layer partitioned by a trench. greatly overhang trench from shallow first region than while the second region not in contact with the emitter electrode characterized in that projecting a rather small trench formation from relatively deep second region And
[0008]
According to the present invention, since the extension of the trench from the channel layer is large in the first region of the channel layer, it is difficult for holes injected from the collector layer to escape to the emitter electrode, and the carrier accumulation effect is enhanced. In the second region of the channel layer, since the extension of the trench from the channel layer is small, electric field concentration at the trench bottom is suppressed.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Here, an example in which the present invention is applied to an IGBT having a trench gate structure will be described.
[0010]
Embodiment 1 FIG.
1 is a cross-sectional view showing a configuration of a non-punch-through IGBT having a trench gate structure according to a first embodiment of the present invention. As shown in FIG. 1, the IGBT includes a first channel layer that forms a P-type channel layer that is a second semiconductor region on the surface of an N-type FZ wafer 2 that becomes a drift layer 21 that is a first semiconductor region. Region 22a and second region 22b. The first region 22a has a smaller diffusion depth than the second region 22b. In order to form the regions 22a and 22b having different diffusion depths in the channel layer in this way, a mask having a corresponding pattern is used, for example, ion implantation energy is changed according to the respective diffusion depths, and ions are implanted. The region 22b can be made substantially the same depth as the trench. Thus, by deepening the region 22b, the electric field at the trench bottom is relaxed, and the breakdown voltage between the collector and the emitter can be increased. In addition to means for changing the ion implantation energy, the regions 22a and 22b may be formed by changing the diffusion temperature and time after the trench formation.
[0011]
The N-type emitter region 23 which is the third semiconductor region is selectively formed except for the central portion of the surface layer of the first region 22a of the channel layer. A trench is formed at the boundary between the first region 22a and the second region 22b of the channel layer so as to sandwich the emitter region 23 therebetween. This trench is deeper than the first region 22a of the channel layer and is substantially the same depth as the second region 22b. A gate oxide film 25, which is an insulating film, is formed on the inner surface of the trench, and a gate electrode 24, which is a first electrode, is provided inside the trench by filling it with gate polysilicon.
[0012]
On the gate electrode 24, the emitter region 23, and the first region 22a and the second region 22b of the channel layer, an emitter electrode 26 that is a second electrode is stacked via an interlayer insulating film 27. The emitter electrode 26 is in contact with a part of the emitter region 23 and a portion between the opposed emitter regions 23 and 23 in the first region 22a of the channel layer. A P-type collector layer 28 which is a fourth semiconductor region is formed on the back surface of the FZ wafer 2, and a collector electrode 29 which is a third electrode is further formed.
[0013]
According to the first embodiment described above, in the non-punch through type IGBT, since the protrusion of the trench from the channel layer is large in the first region 22a of the channel layer, the holes injected from the collector layer 28 become the emitter electrode 26. Since it becomes difficult to penetrate, the carrier accumulation effect is enhanced, and the voltage drop in the drift layer 21 can be reduced. In addition, since the extension of the trench from the channel layer is small in the second region 22b of the channel layer, electric field concentration at the trench bottom is suppressed, so that a reduction in breakdown voltage between the collector and the emitter can be avoided. In addition, since holes do not escape to the emitter electrode 26 in the second region 22b, the effect of storing carriers is not impaired even if the extension of the trench is small.
[0014]
Embodiment 2. FIG.
FIG. 2 is a cross-sectional view showing a configuration of a field stop IGBT having a trench gate structure according to the second embodiment of the present invention. For the field stop type IGBT, ISPSD'00, P.I. 355-358, (2000), reported by Laska et al. As shown in FIG. 2, the IGBT of the second embodiment is a fifth semiconductor region as a field stop layer between the drift layer 21 and the collector layer 28 of the non-punch through type IGBT having the configuration shown in FIG. An N-type buffer layer 20 is provided. Other configurations are basically the same as those in the first embodiment. Therefore, the same components as those of the first embodiment are denoted by the same reference numerals and description thereof is omitted.
[0015]
According to the second embodiment, in the field stop type IGBT, the same effect as in the first embodiment, that is, without increasing the breakdown voltage between the collector and the emitter, the carrier accumulation effect is enhanced and the voltage drop in the drift layer is reduced. The effect that it can be made is acquired.
[0016]
Embodiment 3 FIG.
FIG. 3 is a cross-sectional view showing a configuration of a non-punch through IGBT having a trench gate structure according to a third embodiment of the present invention. As shown in FIG. 3, the IGBT of the third embodiment is divided into one or more, or two trenches in the example shown in FIG. It becomes the composition. Other configurations are basically the same as those in the first embodiment. Therefore, the same components as those of the first embodiment are denoted by the same reference numerals and description thereof is omitted.
[0017]
According to the third embodiment, the same effect as in the first embodiment, that is, without increasing the collector-emitter breakdown voltage, the carrier accumulation effect can be enhanced and the voltage drop in the drift layer can be reduced. An effect is obtained.
[0018]
Embodiment 4 FIG.
FIG. 4 is a sectional view showing the structure of a field stop IGBT having a trench gate structure according to the fourth embodiment of the present invention. As shown in FIG. 4, the IGBT according to the fourth embodiment has one or more channel region second regions 22b in the IGBT having the configuration shown in FIG. The structure is finely divided into individual trenches. Other configurations are basically the same as those of the second embodiment. Therefore, the same components as those of the second embodiment are denoted by the same reference numerals and description thereof is omitted.
[0019]
According to the fourth embodiment, the same effect as in the second embodiment, that is, without increasing the collector-emitter breakdown voltage in the field stop IGBT, the carrier accumulation effect is enhanced and the voltage drop in the drift layer is reduced. The effect that it can be made is acquired.
[0020]
In the above, this invention is not restricted to Embodiment 1-4 mentioned above, A various change is possible. For example, in each of the above-described embodiments, the second region 22b of the channel layer is not in contact with the emitter electrode 26 by the interlayer insulating film 27, but there is a resistance between the second region 22b and the emitter electrode 26. In the present invention, such a configuration is also included in the configuration in which the second region 22b and the emitter electrode 26 are not in contact with each other. Further, in each of the above-described embodiments, the first conductivity type is the N type and the second conductivity type is the P type. In each of the above-described embodiments, the IGBT has been described as an example. However, the present invention can also be applied to a power MOSFET having a trench gate structure.
[0021]
【Effect of the invention】
According to the present invention, the first region in contact with the emitter electrode among the plurality of regions partitioned by the trench in the channel layer is shallower than the trench, so that the extension of the trench from the channel layer is increased, and the collector layer Holes injected from the hole are difficult to escape to the emitter electrode. Accordingly, the carrier accumulation effect is enhanced, and the voltage drop in the drift layer can be reduced. In addition, since the second region that does not contact the emitter electrode is deeper than the first region among the plurality of regions of the channel layer, the overhang of the trench is small in this region, so that the electric field concentration at the trench bottom is suppressed. be able to. Therefore, a decrease in breakdown voltage between the collector and the emitter can be avoided.
[Brief description of the drawings]
1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention;
FIG. 2 is a cross-sectional view showing a configuration of a semiconductor device according to a second embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a configuration of a semiconductor device according to a third embodiment of the present invention.
FIG. 4 is a cross-sectional view showing a configuration of a semiconductor device according to a fourth embodiment of the present invention.
FIG. 5 is a cross-sectional view showing a configuration of a conventional semiconductor device.
[Explanation of symbols]
20 Buffer layer (fifth semiconductor region)
21 Drift layer (first semiconductor region)
22a First region (second semiconductor region) in channel layer
22b Second region in the channel layer (second semiconductor region)
23 Emitter region (third semiconductor region)
24 Gate electrode (first electrode)
25 Gate oxide film (insulating film)
26 Emitter electrode (second electrode)
28 Collector layer (fourth semiconductor region)
29 Collector electrode (third electrode)

Claims (3)

A first semiconductor region of a first conductivity type;
A second semiconductor region of a second conductivity type selectively formed on a surface portion of the first semiconductor region;
A third semiconductor region of a first conductivity type selectively formed on a surface portion of the second semiconductor region;
A fourth semiconductor region of the second conductivity type formed on the back surface of the first semiconductor region;
A first electrode provided through an insulating film in a plurality of trenches that reach the first semiconductor region from the surface of the third semiconductor region through the second semiconductor region;
A second electrode in common contact with a part of the second semiconductor region and the third semiconductor region;
A third electrode in contact with the fourth semiconductor region;
Comprising
Of the plurality of regions of the second semiconductor region partitioned by the trench, the first region in contact with the second electrode is relatively shallow and the protrusion of the trench from the first region is large. On the other hand, the second region not in contact with the second electrode is relatively deep and the protrusion of the trench from the second region is small,
In the second semiconductor region, wherein at least three trenches provided between the adjacent first regions, each of the second region in all between those 該To wrench is provided A semiconductor device.   The semiconductor device according to claim 1, wherein a fifth semiconductor region of a first conductivity type is provided between the first semiconductor region and the fourth semiconductor region.   The semiconductor device according to claim 1, wherein a resistor is provided between the second region and the second electrode.

Images