JP2000277726A - High breakdown strength semiconductor element - Google Patents

High breakdown strength semiconductor element

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JP2000277726A
JP2000277726A JP11077198A JP7719899A JP2000277726A JP 2000277726 A JP2000277726 A JP 2000277726A JP 11077198 A JP11077198 A JP 11077198A JP 7719899 A JP7719899 A JP 7719899A JP 2000277726 A JP2000277726 A JP 2000277726A
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type semiconductor
conductivity type
semiconductor layer
layer
conductive
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JP3751463B2 (en
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Akihiro Hachiman
Satoshi Urano
彰博 八幡
聡 浦野
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Toshiba Corp
株式会社東芝
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

Abstract

PROBLEM TO BE SOLVED: To provide a terminal structure suitable for a vertical superjunction structure, and to realize a high breakdown strength superjunction. SOLUTION: Stripe-shaped p-type layers 1 and n-type layers 2 constituting a vertical superjunction structure are formed alternately, and the number is set odd-numbered. Also the integrated values of the carrier density in the layer thickness direction of the p-type layers except the two p-type layers 1 arranged at the outermost sides and the n-type layers 2 are set so as to be substantially the same, and the integrated value of the carrier density in the layer thickness direction of the two p-type layers 1 arranged at the outermost sides is set to be almost half that of the other p-type layers 1 and the n-type layers 2. Then the upper edge of the stripe-shaped p-type layers 1 and n-type layers 2 is brought into contact with a p-type layer 3 with high density, and this p-type layer 3 is surrounded by a p-type layer (reserve layer 4) of low concentration.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は高耐圧半導体素子に係わり、終端構造と縦型スーパージャンクションを持つ高耐圧半導体素子に関する。 The present invention relates to relates to a high-voltage semiconductor device, it relates to a high-voltage semiconductor device having a termination structure and a vertical superjunction.

【0002】 [0002]

【従来の技術】近年のパワーエレクトロニクス分野における電源機器の小型化、高性能化への要求を受けて、パワー半導体素子では、高耐圧・大電流化とともに、低損失化、高速化、高破壊耐量化に対する性能改善が注力されている。 BACKGROUND ART miniaturization of the power devices in recent years the field of power electronics, in response to a request to high performance, the power semiconductor element, with a high breakdown voltage, high current, low loss, high speed, high fracture resistance performance improvement for the capacity has been focused. その中で、ストライプ状のp型半導体層とn Among them, the stripe-shaped p-type semiconductor layer and the n
型半導体層が交互に繰り返して存在する、いわゆるスーパージャンクション構造が考案されている。 Type semiconductor layer is present alternately repeated, so-called super junction structure has been devised.

【0003】このスーパージャンクション構造は、ダイオードやMOSFET等のパワー半導体素子に用いられた場合、オン状態において非常にオン抵抗が低くなるとともに、オフ状態で容易に空乏化することから高耐圧特性を示すという利点を持つ。 [0003] The super junction structure, when used in the power semiconductor element such as a diode or MOSFET, with very on-resistance is low in the ON state, indicating a high withstand voltage characteristic since it easily depleted in the OFF state It has the advantage that.

【0004】例えば、特開平7−7154において示されるように、パワーMOSFETの内部領域にスーパージャンクション構造に相当する補助領域を形成することが述べている。 [0004] For example, as shown in JP-A-7-7154, and it said that to form an auxiliary region corresponding to the super junction structure on the interior region of the power MOSFET. しかしながら、かかる補助領域では逆電圧が印加された際にその電荷キャリアが空にされることが開示されているのみであり、実際にスーパージャンクション構造を有する素子を実用化するに際して重要な終端構造については具体的な開示はない。 However, the charge carriers when the reverse voltage is applied in such an auxiliary area is only disclosed to be emptied, actually the critical termination structure upon the practical use of devices having a super junction structure there is no specific disclosure.

【0005】 [0005]

【発明が解決しようとする課題】本発明者らは、スーパージャンクション構造を有する素子を実用化する場合に、スーパージャンクション構造の最外部、特に終端構造において、高耐圧化が不十分であり、これにより素子の破壊が起こることを見出した。 The present inventors have found 0005], when the practical use of devices having a superjunction structure, the outermost super junction structure, particularly in the termination structure, is insufficient high breakdown voltage, which It was found that the breakdown of the device occurs by.

【0006】本発明は、かかる実情に鑑みてなされたものであり、スーパージャンクション構造の高耐圧化を図り素子破壊を防止する終端構造を提供することを目的とするものである。 [0006] The present invention has been made in view of the above circumstances, it is an object to provide a termination structure for preventing the element breakdown achieving high breakdown voltage of the super junction structure.

【0007】 [0007]

【課題を解決するための手段】前述した課題を解決するために、本発明の第1は、第1導電型半導体領域と、この第1導電型半導体領域に接して形成された第1導電型半導体層と、前記第1導電型半導体領域及び前記第1導電型半導体層に接して形成された第2導電型半導体層と、前記第1導電型半導体層及び前記第2導電型半導体層に接して形成された第2導電型半導体領域とを備え、 Means for Solving the Problems In order to solve the aforementioned problems, a first aspect of the present invention includes a first conductivity type semiconductor region, a first conductivity type formed in contact with the first conductivity type semiconductor region a semiconductor layer, a second conductivity type semiconductor layer formed in contact with the first conductive type semiconductor region and the first conductivity type semiconductor layer, in contact with the first conductive type semiconductor layer and the second conductive semiconductor layer and a second conductivity type semiconductor region formed Te,
前記第1導電型半導体層及び前記第2導電型半導体層は交互に繰り返して配置されており、その最外部の第1導電型半導体層又は前記第2導電型半導体層の層厚み方向のキャリア濃度の積分値が、その内部に配置された前記第1導電型半導体層及び前記第2導電型半導体層の層厚み方向のキャリア濃度の積分値の概略半分であることを特徴とする高耐圧半導体素子を提供する。 The first conductive type semiconductor layer and the second conductive semiconductor layer are disposed alternately and repeatedly, the carrier concentration of the layer thickness direction of the first conductivity type of the outermost semiconductor layer or the second conductive semiconductor layer high voltage semiconductor device of the integrated value, characterized in that it is a schematic half the integral value of the layer thickness direction of the carrier concentration of the said inside located first conductivity type semiconductor layer and the second conductive semiconductor layer I will provide a.

【0008】また、本発明の第2は、第1導電型半導体領域と、第2導電型半導体領域と、これらの第1導電型半導体領域と第2導電型半導体領域との間に挟まれて形成され、交互に繰り返して配置された第1導電型半導体層及び第2導電型半導体層とを備え、この第1導電型半導体層及び第2導電型半導体層の繰り返し配置方向は、 [0008] The second present invention comprises a first conductivity type semiconductor region, a second conductivity type semiconductor region is sandwiched between these first conductivity type semiconductor region and the second conductivity type semiconductor region is formed, and a first conductivity type semiconductor layer and the second conductive type semiconductor layer disposed alternately and repeatedly, repeatedly arranged direction of the first conductive type semiconductor layer and the second conductive type semiconductor layer,
前記第1導電型半導体領域と前記第2導電型半導体領域とを結ぶ方向に対して概略垂直であるとともに、前記第1導電型半導体層はオン状態でドリフト電流を流すとともにオフ状態で空乏化し、前記第2導電型半導体層はオフ状態で空乏化し、かつ最外部の第1導電型半導体層又は前記第2導電型半導体層の層厚み方向のキャリア濃度の積分値が、その内部に配置された前記第1導電型半導体層及び前記第2導電型半導体層の層厚み方向のキャリア濃度の積分値の概略半分であることを特徴とする高耐圧半導体素子を提供する。 With schematic is perpendicular to the direction connecting the said first conductivity type semiconductor region and the second conductivity type semiconductor region, the first conductivity type semiconductor layer is depleted in the off-state with flow drift current in the on state, the second conductive semiconductor layer is depleted in the off state, and the integral value of the layer thickness direction of the carrier concentration of the first conductivity type semiconductor layer or the second conductive type semiconductor layer of the outermost were placed therein to provide a high voltage semiconductor device which is a schematic half the integral value of the layer thickness direction of the carrier concentration of said first conductivity type semiconductor layer and the second conductive semiconductor layer.

【0009】また、本発明の第3は、高濃度第1導電型半導体領域と、この高濃度第1導電型半導体領域に接して形成された第1導電型半導体層と、前記高濃度第1導電型半導体領域及び前記第1導電型半導体層に接して形成された第2導電型半導体層と、前記第1導電型半導体層及び前記第2導電型半導体層に接して形成された高濃度第2導電型半導体領域と、前記第1導電型半導体層及び前記第2導電型半導体層を取り囲んで形成された低濃度第1導電型半導体領域と、この低濃度第1導電型半導体領域及び前記高濃度第2導電型半導体領域に接して形成され、前記高濃度第2導電型半導体領域より低濃度の低濃度第2導電型半導体領域とを備え、前記第1導電型半導体層及び前記第2導電型半導体層は交互に繰り返して配置されており [0009] The third present invention, a high concentration first conductivity type semiconductor region, and the high concentration first conductivity type semiconductor layer formed in contact with the first conductivity type semiconductor region, the heavily doped first a second conductivity type semiconductor layer formed in contact with the conductive type semiconductor region and the first conductivity type semiconductor layer, a high concentration first formed in contact with the first conductive type semiconductor layer and the second conductive semiconductor layer and second conductivity type semiconductor region, a first conductivity type semiconductor layer and the low concentration first conductivity type semiconductor region of the second conductivity type semiconductor layer is surrounded by forming, the low concentration first conductivity type semiconductor region and the high It formed in contact with a concentration second conductivity type semiconductor region, the high concentration than the second conductivity type semiconductor region and a low density low density second conductivity type semiconductor region of the first conductivity type semiconductor layer and the second conductive type semiconductor layer is disposed alternately and repeatedly その最外部の第1導電型半導体層又は前記第2導電型半導体層の層厚み方向のキャリア濃度の積分値が、その内部に配置された前記第1導電型半導体層及び前記第2導電型半導体層の層厚み方向のキャリア濃度の積分値の概略半分であることを特徴とする高耐圧半導体素子を提供する。 Integrated value of the layer thickness direction of the carrier concentration of the first conductivity type of the outermost semiconductor layer or the second conductive type semiconductor layer, the first conductive type semiconductor layer and the second conductive type semiconductor disposed therein to provide a high voltage semiconductor device which is a schematic half the integral value of the layer thickness direction of the carrier concentration of the layer.

【0010】また、本発明の第4は、高濃度第1導電型半導体領域と、高濃度第2導電型半導体領域と、これらの高濃度第1導電型半導体領域と高濃度第2導電型半導体領域との間に挟まれて形成され、交互に繰り返して配置された第1導電型半導体層及び第2導電型半導体層と、これらの第1導電型半導体層及び第2導電型半導体層を取り囲んで形成された低濃度第1導電型半導体領域と、この低濃度第1導電型半導体領域及び前記高濃度第2導電型半導体領域に接して形成され、前記高濃度第2 Further, the fourth invention, a high concentration first conductivity type semiconductor region, a high concentration second conductivity type semiconductor region, these high-concentration first-conductivity-type semiconductor region and the high-concentration second conductivity type semiconductor is formed sandwiched between the region, surrounds the first conductivity type semiconductor layer and the second conductive type semiconductor layer disposed alternately and repeatedly, these first conductivity type semiconductor layer and the second conductive type semiconductor layer in a low concentration first conductivity type semiconductor region formed, formed in contact with the low concentration first conductivity type semiconductor region and said high concentration second conductivity type semiconductor region, the high concentration second
導電型半導体領域より低濃度の低濃度第2導電型半導体領域とを備え、前記第1導電型半導体層及び第2導電型半導体層の繰り返し配置方向は、前記高濃度第1導電型半導体領域と前記高濃度第2導電型半導体領域とを結ぶ方向に対して概略垂直であるとともに、前記第1導電型半導体層はオン状態でドリフト電流を流すとともにオフ状態で空乏化し、前記第2導電型半導体層はオフ状態で空乏化し、かつ最外部の第1導電型半導体層又は前記第2導電型半導体層の層厚み方向のキャリア濃度の積分値が、その内部に配置された前記第1導電型半導体層及び前記第2導電型半導体層の層厚み方向のキャリア濃度の積分値の概略半分であることを特徴とする高耐圧半導体素子を提供する。 A conductive-type semiconductor region and a low density low density second conductivity type semiconductor region, repeatedly arranged direction of the first conductive type semiconductor layer and the second conductive type semiconductor layer, and the high concentration first conductivity type semiconductor region with schematic it is perpendicular to the direction connecting the said high concentration second conductivity type semiconductor region, the first conductivity type semiconductor layer is depleted in the off-state with flow drift current in the on state, the second conductive semiconductor layer depleted in the off state, and the integral value of the layer thickness direction of the carrier concentration of the first conductivity type semiconductor layer or the second conductive type semiconductor layer of the outermost is the first conductivity type semiconductor disposed therein to provide a high voltage semiconductor device which is a schematic half of the layer and the integral value of the layer thickness direction of the carrier concentration of the second conductivity type semiconductor layer.

【0011】また、本発明の第5は、高濃度第1導電型半導体領域と、この高濃度第1導電型半導体領域に接して形成された第1導電型半導体層と、前記高濃度第1導電型半導体領域及び前記第1導電型半導体層に接して形成された第2導電型半導体層と、前記第1導電型半導体層及び前記第2導電型半導体層に接して形成された高濃度第2導電型半導体領域と、前記第1導電型半導体層及び前記第2導電型半導体層を取り囲んで形成された低濃度第1導電型半導体領域と、この低濃度第1導電型半導体領域に接して形成され、前記高濃度第2導電型半導体領域を取り囲むように当該領域から離間して設けられたリング状の第2導電型半導体領域層とを備え、前記第1 Further, the fifth aspect of the present invention, a high concentration first conductivity type semiconductor region, and the high concentration first conductivity type semiconductor layer formed in contact with the first conductivity type semiconductor region, the heavily doped first a second conductivity type semiconductor layer formed in contact with the conductive type semiconductor region and the first conductivity type semiconductor layer, a high concentration first formed in contact with the first conductive type semiconductor layer and the second conductive semiconductor layer and second conductivity type semiconductor region, a first conductivity type semiconductor layer and the low concentration first conductivity type semiconductor region formed surrounding the second conductive semiconductor layer, in contact with the low concentration first conductivity type semiconductor region is formed, and a the high-concentration second conductivity type spaced apart from the region second conductivity type annular provided so as to surround the semiconductor region semiconductor region layer, said first
導電型半導体層及び前記第2導電型半導体層は交互に繰り返して配置されており、その最外部の第1導電型半導体層又は前記第2導電型半導体層の層厚み方向のキャリア濃度の積分値が、その内部に配置された前記第1導電型半導体層及び前記第2導電型半導体層の層厚み方向のキャリア濃度の積分値の概略半分であることを特徴とする高耐圧半導体素子を提供する。 Conductivity type semiconductor layer and the second conductive semiconductor layer are disposed alternately and repeatedly, the integral value of the layer thickness direction of the carrier concentration of the first conductivity type of the outermost semiconductor layer or the second conductive semiconductor layer but to provide a high voltage semiconductor device which is a schematic half the integral value of the layer thickness direction of the carrier concentration of the said inside located first conductivity type semiconductor layer and the second conductive semiconductor layer .

【0012】さらにまた、本発明の第6は、高濃度第1 [0012] Further, the sixth invention, a high concentration first
導電型半導体領域と、高濃度第2導電型半導体領域と、 A conductive type semiconductor region, a high-concentration second conductivity type semiconductor region,
これらの高濃度第1導電型半導体電極層と高濃度第2導電型半導体電極層との間に挟まれて形成され、交互に繰り返して配置された第1導電型半導体層及び第2導電型半導体層と、これらの第1導電型半導体層及び第2導電型を取り囲んで形成された低濃度第1導電型半導体領域と、この低濃度第1導電型半導体領域に接して形成され、前記高濃度第2導電型半導体領域を取り囲むように当該領域から離間して設けられたリング状の第2導電型半導体領域層とを備え、前記第1導電型半導体層及び第2導電型半導体層の繰り返し配置方向は、前記高濃度第1導電型半導体領域と前記高濃度第2導電型半導体領域とを結ぶ方向に対して概略垂直であるとともに、前記第1導電型半導体層はオン状態でドリフト電流を流すとともにオフ状態で空乏 Sandwiched between these high-concentration first-conductivity-type semiconductor electrode layer and the high-concentration second conductivity type semiconductor electrode layer is formed, the first conductive type semiconductor layer and the second conductive type semiconductor disposed alternately and repeatedly a layer, and these first conductivity type semiconductor layer and a low concentration first conductivity type semiconductor region formed surrounding the second conductivity type, formed in contact with the low concentration first conductivity type semiconductor region, the high concentration and a second conductivity type spaced apart from the region second conductivity type annular provided so as to surround the semiconductor region semiconductor region layer, repeating arrangement of said first conductivity type semiconductor layer and the second conductive type semiconductor layer direction, along with schematic is perpendicular to the direction connecting the said high concentration first conductivity type semiconductor region and the high concentration second conductivity type semiconductor region, the first conductive semiconductor layer flow drift current in the on state depletion in with off state し、前記第2導電型半導体層はオフ状態で空乏化し、かつ最外部の第1導電型半導体層又は前記第2導電型半導体層の層厚み方向のキャリア濃度の積分値が、その内部に配置された前記第1導電型半導体層及び前記第2導電型半導体層の層厚み方向のキャリア濃度の積分値の概略半分であることを特徴とする高耐圧半導体素子を提供する。 And, the second conductive semiconductor layer is depleted in the off state, and the integral value of the layer thickness direction of the carrier concentration of the first conductivity type semiconductor layer or the second conductive type semiconductor layer of the outermost is disposed therein to provide a high breakdown voltage semiconductor device characterized by been a schematic half the integral value of the layer thickness direction of the carrier concentration of said first conductivity type semiconductor layer and the second conductive semiconductor layer.

【0013】上述した本発明の第3、4においては、前記第2導電型半導体領域はオフ状態で空乏化し、その空乏領域は前記第1導電型半導体層及び前記第2導電型半導体層において空乏化により生ずる空乏領域と接することが好ましい。 [0013] In the third and fourth of the present invention described above, the second conductivity type semiconductor region is depleted in the OFF state, the depletion region is depleted in the first conductive type semiconductor layer and the second conductive semiconductor layer it is preferably in contact with the depletion region caused by reduction.

【0014】また、上述した本発明の第5、6においては、前記リング状の第2導電型半導体領域層に接する低濃度第1導電型半導体領域はオフ状態で空乏化し、その空乏領域は前記第1導電型半導体層及び前記第2導電型半導体層において空乏化により生ずる空乏領域と接することが好ましい。 Further, in the fifth and sixth of the present invention described above, a low concentration first conductivity type semiconductor region in contact with the second conductivity type semiconductor region layer of said ring-shaped depleted in the off state, the depletion region is the it is preferably in contact with the depletion region caused by depletion in the first conductive type semiconductor layer and the second conductive semiconductor layer.

【0015】また、上述した各発明において、前記第1 Further, in each invention described above, the first
導電型半導体層及び前記第2導電型半導体層は、お互いに平行なストライプ状の層であることが好ましい。 Conductivity type semiconductor layer and the second conductive type semiconductor layer is preferably a layer of parallel stripes each other. さらに、前記第1導電型半導体層及び前記第2導電型半導体層は、奇数個存在することが好ましい。 Further, the first conductive type semiconductor layer and the second conductive type semiconductor layer is preferably an odd number exists. さらにまた、前記高耐圧半導体素子は縦型の構造を有するものであることが好ましい。 Furthermore, the high-breakdown voltage semiconductor element is preferably one having a vertical structure.

【0016】 [0016]

【発明の実施の形態】以下、本発明の実施形態について図面を参照しつつ詳細に説明する。 DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments will be described in detail with reference to the accompanying drawings of the present invention. (第1の実施形態)図1は、本発明の第1の実施形態に係る高耐圧半導体素子の構造を示す上面図である。 (First Embodiment) FIG. 1 is a top view showing the structure of a high breakdown voltage semiconductor device according to a first embodiment of the present invention. 図2 Figure 2
は、図1の点線AA´を通る断面における断面図である。 Is a cross-sectional view in section through the broken line AA' of Figure 1. この断面図では図1の素子構造の半分のみを示している。 In this sectional view shows only half of the device structure of Figure 1.

【0017】図1、図2に示される高耐圧半導体素子は縦型のダイオードに係るものである。 [0017] Figure 1, the high-voltage semiconductor device shown in FIG. 2 is a view according to a vertical diode. これらの図に示すように、本実施形態の縦型のダイオードは、低濃度のn As shown in these drawings, a vertical diode of the present embodiment, the low concentration of n
型層5の一方の面に高濃度のn型層10が形成され、また他方の面には高濃度のp型層3が選択的に形成されており、これらのn型層10とp型層3との間にはスーパージャンクション構造が設けられている。 High concentration n-type layer 10 of is formed on one surface of the mold layer 5, also on the other surface has a high concentration of p-type layer 3 is selectively formed, these n-type layer 10 and p-type super junction structure is provided between the layer 3. このスーパージャンクション構造は、ストライプ状のp型層1とn型層2が交互に繰り返して設けられており、その数は奇数個である。 The super junction structure, a stripe-shaped p-type layer 1 and the n-type layer 2 is provided alternately and repeatedly, the number is odd. 素子上面から見た場合、かかるストライプ状のp型層1とn型層2の存在領域は高濃度のp型層3の存在領域の中に含まれた形となっている。 When viewed from the top of elements, the existence region of such a stripe-shaped p-type layer 1 and the n-type layer 2 has a shape contained within the existing area of ​​the high-concentration p-type layer 3. 本来ならばストライプ状のp型層1とn型層2とは高濃度のp型層3 It would otherwise striped p-type layer 1 and the n-type layer 2 a high concentration and a p-type layer 3
の下に隠れていて見えない筈であるが、分かりやすくするためにここでは電極等を省略してスーパージャンクション構造を示した。 Should the invisible have hidden under, but here for clarity showing a super junction structure by omitting the electrodes and the like.

【0018】その最外部のp型層1の層厚み方向のキャリア濃度の積分値は、一番外側を除いた残りの内部に配置されたp型層1とn型層2の層厚み方向のキャリア濃度の積分値の概略半分となっている。 [0018] of the outermost integral value of the carrier concentration of the layer thickness direction of the p-type layer 1, the outermost remaining inside arranged p-type layer 1 and the n-type layer 2 of the layer thickness direction, excluding It has become a schematic half of the integral value of the carrier concentration. これらの一番外側を除いた残りのp型層1とn型層2の層厚み方向のキャリア濃度の積分値は一定となっている。 Integrated value of the remaining p-type layer 1 and the layer thickness direction of the carrier concentration of the n-type layer 2 except for these outermost is constant. ここでは一番外側のストライプ状の層をp型層1としたが、n型層2であっても上記キャリア濃度積分値の条件を満たせば効果は同様である。 This was the outermost stripe layer and p-type layer 1, but the effect satisfies the n-type layer 2 is a the carrier density integral value even if the conditions were the same.

【0019】例えば、一番外側のp型層1の濃度及び厚みを1×10 15 cm -3 、3.5μm、或いは5×10 14 [0019] For example, the outermost p-type layer 1 concentration and 1 × 10 15 cm -3 thickness, 3.5 [mu] m, or 5 × 10 14
cm -3 、7.0μm、一番外側を除いた残りの内部に配置されたp型層1とn型層2の濃度及び厚みを、それぞれ1×10 15 cm -3 、7.0μmとすることが可能であり、かかる条件の下で上記キャリア濃度積分値の条件を満足する。 cm -3, 7.0 .mu.m, most outside the remaining layer 1 and the n-type layer 2 p-type which is disposed within the concentration and thickness excluding each 1 × 10 15 cm -3, and 7.0 .mu.m it is possible to satisfy the condition of the carrier density integration value under such conditions. したがって、例えば逆電圧4000Vを印加する条件下では、OFF状態において上記スーパージャンクション構造はその最外周部分においても完全空乏化し高耐圧特性を示すようになる。 Thus, for example, under conditions of applying a reverse voltage 4000V, the super junction structure in the OFF state also exhibits a fully depleted high withstand voltage characteristics in the outermost peripheral portion thereof.

【0020】ストライプ状のp型層1とn型層2と接する高濃度のp型層3は、低濃度のp型層4(例えば、濃度は1×10 13 cm -3 。後述する実施形態も同様。)で囲まれており、この層がリサーフ層として電界を緩和する働きをする。 [0020] Embodiment high-concentration p-type layer 3 in contact with the stripe-shaped p-type layer 1 and the n-type layer 2, a low concentration of p-type layer 4 (e.g., concentration of 1 × 10 13 cm -3. Later are enclosed in the same manner.) also, this layer serves to relax the electric field as a RESURF layer. 例えば、p型層3の深さは6.0μm、 For example, the depth of the p-type layer 3 is 6.0 .mu.m,
濃度は2×10 17 cm -3であり、また、p型層4の深さは5.0μm、濃度は3×10 15 cm -3である。 Concentration was 2 × 10 17 cm -3, The depth of the p-type layer 4 is 5.0 .mu.m, the concentration is 3 × 10 15 cm -3.

【0021】かかる条件の下では、p型層4とn型ベース層5とのpn接合から伸びる空乏層は上記スーパージャンクション構造において形成される空乏層と完全に接続され、この終端部分における耐圧を十分に確保することが可能である。 [0021] Under such conditions, the depletion layer extending from the pn junction between the p-type layer 4 and the n-type base layer 5 is fully connected to the depletion layer formed in the superjunction structure, the breakdown voltage in the terminal portion it is possible to sufficiently secure. 例えば逆電圧4000Vを印加する条件下では、OFF状態において上記スーパージャンクション構造の終端部分は完全空乏化し高耐圧特性を示すようになる。 For example, in the conditions for applying a reverse voltage 4000V, terminal portion of the superjunction structure in the OFF state is as shown fully depleted high withstand voltage characteristics.

【0022】なお、図1、図2において、6は高濃度のn型ストッパー層であり、リサーフ層であるp型層4から伸びる空乏層が基板エッジ部分にまで到達することを防止して耐圧を確保するために設けられる。 [0022] Incidentally, FIG. 1, 2, 6 are high-concentration n-type stopper layer, to prevent the depletion layer extending from the p-type layer 4 is a RESURF layer reaches up to the substrate edge breakdown voltage It provided in order to ensure. また、7は絶縁膜、8はアノード電極、9はストッパー電極、11 Further, 7 denotes an insulating film, 8 anode electrode, 9 stopper electrode, 11
はカソード電極である。 It is a cathode electrode.

【0023】以上述べた構造による縦型のスーパージャンクション構造を有するダイオードによれば、OFF状態においてスーパージャンクション構造はその最外周部分においても完全空乏化し高耐圧特性を示すようになる。 According to a diode having a vertical superjunction structure according to [0023] above-mentioned structure, the superjunction structures in the OFF state also exhibits a fully depleted high withstand voltage characteristics in the outermost peripheral portion thereof. また、OFF状態においてスーパージャンクション構造の終端部分において完全空乏化を図り高耐圧特性を確保することが可能である。 Further, it is possible to ensure a high breakdown voltage characteristic achieving complete depletion at the end portion of the superjunction structure in the OFF state.

【0024】図3は、図1に示す本実施形態に係る縦形のダイオードの漏れ電流特性を示す特性図である。 FIG. 3 is a characteristic diagram showing a leakage current characteristic of the vertical diode of the present embodiment shown in FIG. 横軸は印加電圧、縦軸は漏れ電流を示している。 The horizontal axis is the applied voltage and the ordinate indicates the leakage current. 図3に示されるように本実施形態に係る縦形のダイオードは440 Vertical is the diode 440 according to this embodiment, as shown in FIG. 3
0V程度の耐圧を持っていることがわかる。 It can be seen that has a breakdown voltage of about 0V. また、かかるダイオードのオン抵抗は0.03Ωcm 2であり、非常に低いオン抵抗を示した。 The on-resistance of such diode is 0.03Omucm 2, showed very low on-resistance.

【0025】(第2の実施形態)図4は、本発明の第2 [0025] (Second Embodiment) FIG. 4 is a second embodiment of the present invention
の実施形態に係る高耐圧半導体素子の構造を示す上面図である。 Is a top view showing the structure of a high breakdown voltage semiconductor device according to the embodiment of. 図5は、図4の点線BB´を通る断面における断面図である。 Figure 5 is a cross-sectional view in section through the broken line BB' in FIG. この断面図では図4の素子構造の半分のみを示している。 In this sectional view shows only half of the device structure of FIG. なお、図1と同一部分には同一符号を付して示し詳細な説明は省略する。 The detailed description are denoted by the same reference numerals as in FIG. 1 will be omitted.

【0026】本実施形態の高耐圧半導体素子も縦型のダイオードに係るものである。 The high breakdown voltage semiconductor device of this embodiment also relates to a vertical diode. 図4、図5に示すように、 4, as shown in FIG. 5,
本実施形態の縦型のダイオードが第1の実施形態のダイオードと異なる点は、ストライプ状のp型層1とn型層2と接する高濃度のp型層3を囲む低濃度のp型層(リサーフ層)4の代わりに、複数の同心円状の高濃度のp That vertical diode of the present embodiment is different from the diode of the first embodiment, the low-concentration p-type layer surrounding the high-concentration p-type layer 3 in contact with the stripe-shaped p-type layer 1 and the n-type layer 2 instead of (RESURF layer) 4, a plurality of concentric high concentration p
型層(ガードリング層)12が設けられている点である。 In that type layer (guard ring layer) 12 is provided. かかるp型層(ガードリング層)12はp型層3の周囲を取り囲むように設けられており、このp型層12 Such p-type layer (guard ring layer) 12 is provided so as to surround the p-type layer 3, the p-type layer 12
がリサーフ層と同様に電界を緩和する働きをする。 There serves to relax the electric field like the RESURF layer. 例えば、p型層3の深さは6.0μm、濃度は2×10 17 For example, the depth of the p-type layer 3 is 6.0 .mu.m, the concentration is 2 × 10 17 c
-3であり、また、p型層12の深さは6.0μm、幅は10.0μm、濃度は5×10 18 cm -3 、p型層3からの距離は10.0μm、お互いの間隔は10.0〜4 a m -3, The depth of the p-type layer 12 is 6.0 .mu.m, width 10.0 [mu] m, the concentration is 5 × 10 18 cm -3, the distance from the p-type layer 3 is 10.0 [mu] m, each other the interval from 10.0 to 4
0.0μmである。 It is 0.0μm.

【0027】かかる条件の下では、上記スーパージャンクション構造において第1の実施形態と同様に完全空乏化が達成されるとともに、p型層12とn型ベース層5 [0027] Under such conditions, the first embodiment as well as completely depleted is achieved in the super junction structure, p-type layer 12 and the n-type base layer 5
とのpn接合から伸びる空乏層は上記スーパージャンクション構造の空乏層と完全に接続され、この終端部分における耐圧を十分に確保することが可能である。 Depletion layer extending from the pn junction between the fully connected and depletion of the super junction structure, it is possible to sufficiently ensure the breakdown voltage in the terminal portion. 例えば逆電圧4000Vを印加する条件下では、OFF状態において上記スーパージャンクション構造の終端部分は完全空乏化し図3と同様な高耐圧特性を示すことがわかった。 For example, in the conditions for applying a reverse voltage 4000V, terminal portion of the superjunction structure in the OFF state was found to exhibit a high withstand voltage characteristics similar to a fully depleted Figure 3. また、かかるダイオードのオン抵抗は0.03Ωc The on-resistance of such diode 0.03Ωc
2であり、非常に低いオン抵抗を示した。 m 2, and showed a very low on-resistance.

【0028】(第3の実施形態)図6は、本発明の第3 [0028] (Third Embodiment) FIG. 6, the third invention
の実施形態に係る高耐圧半導体素子の構造を示す断面斜視図である。 It is a cross-sectional perspective view showing a structure of a high breakdown voltage semiconductor device according to the embodiment of. 図1と同一部分には同一符号を付して示し詳細な説明は省略する。 DETAILED DESCRIPTION denoted by the same reference numerals in FIG. 1 and the same parts will be omitted.

【0029】図6に示すように、本実施形態の高耐圧半導体素子は縦型のプレーナ型MOS構造を有する素子(例えばMOSFET)である。 As shown in FIG. 6, the high-voltage semiconductor device of this embodiment is a device having a planar type MOS structure of a vertical (e.g., MOSFET). 低濃度のn型層(ベース層)5の一方の面には高濃度のn型ドレイン層15が形成され、また他方の面にはp型ベース層13が選択的に形成されており、これらのn型ドレイン層15とp型ベース層13との間には第1の実施形態と同様のスーパージャンクション構造(p型層1とn型層2)が設けられている。 On one surface of the 5 low-concentration n-type layer (base layer) heavily doped n-type drain layer 15 is formed, also on the other surface is p-type base layer 13 is selectively formed, they as in the first embodiment of the super junction structure (p-type layer 1 and the n-type layer 2) is provided between the n-type drain layer 15 and the p-type base layer 13 of.

【0030】p型ベース層13の表面には選択的にn型ソース層14が形成され、スーパージャンクション構造(p型層1とn型層2)、n型ソース層14、及びp型ベース層13の表面上には、ゲート絶縁膜(シリコン酸化膜等)16を介してゲート電極17が設けられている。 [0030] The surface of the p-type base layer 13 is selectively n-type source layer 14 is formed, the super junction structure (p-type layer 1 and the n-type layer 2), n-type source layer 14, and the p-type base layer on 13 surfaces of the gate electrode 17 is provided via a gate insulating film (silicon oxide film) 16. この実施形態の場合には、ゲート絶縁膜16及びゲート電極17はスーパージャンクション構造(p型層1 In this embodiment, the gate insulating film 16 and the gate electrode 17 is super junction structure (p-type layer 1
とn型層2)の部分まで延在している。 It extends to a portion of the n-type layer 2). これにより、効率よくスーパージャンクション構造に電子を注入することが可能である。 Thus, it is possible to efficiently inject electrons into the super junction structure.

【0031】本実施形態に係るMOS構造を有する素子も、OFF状態においてスーパージャンクション構造はその最外周部分においても完全空乏化し高耐圧特性を示すようになる。 The elements having a MOS structure according to the present embodiment also, the super junction structure in the OFF state also exhibits a fully depleted high withstand voltage characteristics in the outermost peripheral portion thereof. また、OFF状態において、p型層4とn型層5とのpn接合から伸びる空乏層は上記スーパージャンクション構造において形成される空乏層と完全に接続され、この終端部分における耐圧を十分に確保することが可能である。 Further, in the OFF state, the depletion layer extending from the pn junction between the p-type layer 4 and the n-type layer 5 is fully connected to the depletion layer formed in the super junction structure, a sufficient breakdown voltage in this end portion It is possible. 本実施形態では、終端構造としてリサーフ層(p型層4)を示したが、図4、図5に示したガードリング層(p型層12)を用いても高耐圧を得ることができた。 In this embodiment shows RESURF layer as a termination structure (p-type layer 4), FIG. 4, it was possible to obtain a high breakdown voltage using the guard ring layer (p-type layer 12) shown in FIG. 5 . また、終端構造がリサーフ層であっても、ガードリング層であっても、オン抵抗は非常に低かった。 Further, the termination structure even RESURF layer, even the guard ring layer, the ON resistance is very low.

【0032】(第4の実施形態)図7は、本発明の第4 [0032] (Fourth Embodiment) FIG. 7, the fourth of the present invention
の実施形態に係る高耐圧半導体素子の構造を示す断面斜視図である。 It is a cross-sectional perspective view showing a structure of a high breakdown voltage semiconductor device according to the embodiment of. 図6と同一部分には同一符号を付して示し詳細な説明は省略する。 DETAILED DESCRIPTION denoted by the same reference numerals in FIG. 6, the same parts will be omitted.

【0033】図7に示すように、本実施形態の高耐圧半導体素子は縦型のトレンチ型MOS構造を有する素子(例えばMOSFET)である。 As shown in FIG. 7, the high-voltage semiconductor device of this embodiment is a device having a trench MOS structure of a vertical (e.g., MOSFET). p型ベース層23が低濃度のn型層(ベース層)5の一方の面に選択的に形成されており、このp型ベース層23とn型ドレイン層1 p-type base layer 23 is selectively formed on one surface of the low concentration n-type layer (base layer) 5, the p-type base layer 23 and the n-type drain layer 1
5との間には第1の実施形態と同様のスーパージャンクション構造(p型層1とn型層2)が設けられている。 Between the 5 same super junction structure of the first embodiment (p-type layer 1 and the n-type layer 2) it is provided.

【0034】p型ベース層23の表面には選択的にn型ソース層24が形成され、これらのn型ソース層24及びp型ベース層23を貫通してトレンチ28が設けられている。 [0034] The surface of the p-type base layer 23 is formed selectively n-type source layer 24, these n-type source layer 24 and the p-type base layer 23 through the trench 28 is provided. このトレンチ28はスーパージャンクション構造(p型層1とn型層2)が設けられたn型層5に到達するように形成されている。 The trench 28 is formed so as to reach the n-type layer 5 a super junction structure (p-type layer 1 and the n-type layer 2) is provided. トレンチ28の内部にはゲート絶縁膜(シリコン酸化膜等)26を介してゲート電極27が設けられている。 Inside the trench 28 gate electrode 27 is provided via a gate insulating film (silicon oxide film) 26.

【0035】本実施形態に係るMOS構造を有する素子も、OFF状態においてスーパージャンクション構造はその最外周部分においても完全空乏化し高耐圧特性を示すようになる。 The elements having a MOS structure according to the present embodiment also, the super junction structure in the OFF state also exhibits a fully depleted high withstand voltage characteristics in the outermost peripheral portion thereof. また、OFF状態において、p型層4とn型層5とのpn接合から伸びる空乏層は上記スーパージャンクション構造において形成される空乏層と完全に接続され、この終端部分における耐圧を十分に確保することが可能である。 Further, in the OFF state, the depletion layer extending from the pn junction between the p-type layer 4 and the n-type layer 5 is fully connected to the depletion layer formed in the super junction structure, a sufficient breakdown voltage in this end portion It is possible. 本実施形態では、終端構造としてリサーフ層(p型層4)を示したが、図4、図5に示したガードリング層(p型層12)を用いても高耐圧を得ることができた。 In this embodiment shows RESURF layer as a termination structure (p-type layer 4), FIG. 4, it was possible to obtain a high breakdown voltage using the guard ring layer (p-type layer 12) shown in FIG. 5 . また、終端構造がリサーフ層であっても、ガードリング層であっても、オン抵抗は非常に低かった。 Further, the termination structure even RESURF layer, even the guard ring layer, the ON resistance is very low.

【0036】なお、本発明は上記実施形態に限定されることはない。 [0036] The present invention is not limited to the above embodiment. 例えば、縦型の高耐圧半導体素子に限らず、横型の高耐圧半導体素子等の様々な型の高耐圧半導体素子に対して本発明を適用することも可能である。 For example, not only the vertical high-voltage semiconductor device, it is also possible to apply the present invention to a high-voltage semiconductor device of the various types of high-voltage semiconductor device such as a lateral. また、スーパージャンクション構造におけるp型層1とn Further, p-type layer 1 and the n in the superjunction structure
型層2とを入れ換えて配置しても良く、この場合にもO It may be arranged interchanged and type layer 2, O in this case
FF状態においてスーパージャンクション構造はその最外周部分においても完全空乏化し高耐圧特性を示すようになる。 Superjunction structure in FF state also exhibits a fully depleted high withstand voltage characteristics in the outermost peripheral portion thereof. その他、本発明の趣旨を逸脱しない範囲で種々変形して実施することが可能である。 Further, the invention is capable of being modified in various ways without departing from the scope of the present invention.

【0037】 [0037]

【発明の効果】本発明により、スーパージャンクション構造を有する半導体素子の高耐圧化を実現することが可能である。 According to the present invention, it is possible to realize a high breakdown voltage semiconductor device having a super junction structure.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】 本発明の第1の実施形態に係るスーパージャンクション構造を有する縦型ダイオードの構造を示す上面図。 Top view showing the structure of a vertical type diode having a super junction structure according to a first embodiment of the present invention; FIG.

【図2】 図1の破線AA´に沿った面における断面図。 2 is a cross-sectional view in a plane along the broken line AA' of Figure 1.

【図3】 図1に示す縦型ダイオードの漏れ電流特性を示す特性図。 [Figure 3] characteristic diagram showing the leakage current characteristics of the vertical type diode shown in FIG.

【図4】 本発明の第2の実施形態に係るスーパージャンクション構造を有する縦型ダイオードの構造を示す上面図。 Top view showing the structure of a vertical type diode having a super junction structure according to a second embodiment of the present invention; FIG.

【図5】 図4の破線BB´に沿った面における断面図。 Figure 5 is a cross-sectional view in a plane along the broken line BB' in FIG.

【図6】 本発明の第3の実施形態に係るスーパージャンクション構造を有する縦型のプレーナ型MOS構造素子を示す断面斜視図。 FIG. 6 is a cross-sectional perspective view of a vertical planar MOS structure element having a super junction structure according to a third embodiment of the present invention.

【図7】 本発明の第4の実施形態に係るスーパージャンクション構造を有する縦型のトレンチ型MOS構造素子を示す断面斜視図。 FIG. 7 is a cross-sectional perspective view of a vertical trench-type MOS structure element having a super junction structure according to a fourth embodiment of the present invention.

【符号の説明】 DESCRIPTION OF SYMBOLS

1…ストライプ状のp型層 2…ストライプ状のn型層 3…高濃度のp型層 4…低濃度のp型層(リサーフ層) 5…低濃度のn型層 6…高濃度のn型ストッパー層 7…絶縁膜 8…アノード電極 9…ストッパー電極 10…高濃度のn型層 11…カソード電極 12…高濃度のp型層(ガードリング層) 13、23…p型ベース層 14、24…n型ソース層 15…n型ドレイン層 16、26…ゲート絶縁膜 17、27…ゲート電極 28…トレンチ 1 ... striped p-type layer 2 ... striped n-type layer 3 ... high-concentration p-type layer 4 ... low concentration p-type layer of the (RESURF layer) 5 ... low-concentration n-type layer 6 ... high-concentration n -type stopper layer 7 ... insulation film 8 ... anode electrode 9 ... stopper electrode 10 ... high-concentration n-type layer 11 ... cathode electrode 12 ... high-concentration p-type layer of the (guard ring layers) 13, 23 ... p-type base layer 14, 24 ... n-type source layer 15 ... n-type drain layer 16, 26 ... gate insulating film 17 and 27 ... gate electrode 28 ... trench

Claims (11)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 第1導電型半導体領域と、この第1導電型半導体領域に接して形成された第1導電型半導体層と、前記第1導電型半導体領域及び前記第1導電型半導体層に接して形成された第2導電型半導体層と、前記第1導電型半導体層及び前記第2導電型半導体層に接して形成された第2導電型半導体領域とを備え、前記第1導電型半導体層及び前記第2導電型半導体層は交互に繰り返して配置されており、その最外部の第1導電型半導体層又は前記第2導電型半導体層の層厚み方向のキャリア濃度の積分値が、その内部に配置された前記第1導電型半導体層及び前記第2導電型半導体層の層厚み方向のキャリア濃度の積分値の概略半分であることを特徴とする高耐圧半導体素子。 And 1. A first conductivity type semiconductor region, a first conductivity type semiconductor layer formed in contact with the first conductivity type semiconductor region, the first conductive type semiconductor region and the first conductivity type semiconductor layer contact with the second conductivity type semiconductor layer formed in said a second conductivity type semiconductor region formed in contact with the first conductive type semiconductor layer and the second conductive type semiconductor layer, the first conductive semiconductor layer and the second conductive semiconductor layer are disposed alternately and repeatedly, the integrated value of the layer thickness direction of the carrier concentration of the first conductivity type of the outermost semiconductor layer or the second conductive type semiconductor layer, the high-voltage semiconductor device which is a schematic half the integral value of the layer thickness direction of the carrier concentration inside the first conductive type semiconductor layer disposed on and the second conductive semiconductor layer.
  2. 【請求項2】 第1導電型半導体領域と、第2導電型半導体領域と、これらの第1導電型半導体領域と第2導電型半導体領域との間に挟まれて形成され、交互に繰り返して配置された第1導電型半導体層及び第2導電型半導体層とを備え、この第1導電型半導体層及び第2導電型半導体層の繰り返し配置方向は、前記第1導電型半導体領域と前記第2導電型半導体領域とを結ぶ方向に対して概略垂直であるとともに、前記第1導電型半導体層はオン状態でドリフト電流を流すとともにオフ状態で空乏化し、前記第2導電型半導体層はオフ状態で空乏化し、かつ最外部の第1導電型半導体層又は前記第2導電型半導体層の層厚み方向のキャリア濃度の積分値が、その内部に配置された前記第1導電型半導体層及び前記第2導電型半導体層の層厚み 2. A first conductivity type semiconductor region, a second conductivity type semiconductor region, which is formed sandwiched between these first conductivity type semiconductor region and the second conductivity type semiconductor region, alternately and repeatedly and a first conductivity type semiconductor layer and the second conductive type semiconductor layer arranged, repeatedly arranged direction of the first conductive type semiconductor layer and the second conductive type semiconductor layer, the said first conductivity type semiconductor region first with schematic is perpendicular to the direction connecting the second conductivity type semiconductor region, the first conductivity type semiconductor layer is depleted in the off-state with flow drift current in the on state, the second conductive semiconductor layer oFF state in depletion turned into, and the integral value of the layer thickness direction of the carrier concentration of the first conductivity type semiconductor layer or the second conductive type semiconductor layer of the outermost, but its interior is arranged a first conductive type semiconductor layer and the second layer thickness of the second conductivity type semiconductor layer 方向のキャリア濃度の積分値の概略半分であることを特徴とする高耐圧半導体素子。 High-voltage semiconductor device which is a schematic half the integral value of the direction of the carrier concentration.
  3. 【請求項3】 高濃度第1導電型半導体領域と、この高濃度第1導電型半導体領域に接して形成された第1導電型半導体層と、前記高濃度第1導電型半導体領域及び前記第1導電型半導体層に接して形成された第2導電型半導体層と、前記第1導電型半導体層及び前記第2導電型半導体層に接して形成された高濃度第2導電型半導体領域と、前記第1導電型半導体層及び前記第2導電型半導体層を取り囲んで形成された低濃度第1導電型半導体領域と、この低濃度第1導電型半導体領域及び前記高濃度第2導電型半導体領域に接して形成され、前記高濃度第2導電型半導体領域より低濃度の低濃度第2導電型半導体領域とを備え、前記第1導電型半導体層及び前記第2 3. A high-concentration first-conductivity-type semiconductor region, and the high concentration first conductivity type semiconductor layer formed in contact with the first conductivity type semiconductor region, the high concentration first conductivity type semiconductor region and the second a second conductivity type semiconductor layer formed in contact with the first conductivity type semiconductor layer, the first conductivity type semiconductor layer and the high-concentration second conductivity type semiconductor region formed in contact with the second conductive type semiconductor layer, a low concentration first conductivity type semiconductor region formed surrounding the first conductive semiconductor layer and the second conductive type semiconductor layer, the low concentration first conductivity type semiconductor region and said high concentration second conductivity type semiconductor region to be formed in contact, the high-concentration than that of the second conductivity type semiconductor region and a low density low density second conductivity type semiconductor region of the first conductivity type semiconductor layer and the second
    導電型半導体層は交互に繰り返して配置されており、その最外部の第1導電型半導体層又は前記第2導電型半導体層の層厚み方向のキャリア濃度の積分値が、その内部に配置された前記第1導電型半導体層及び前記第2導電型半導体層の層厚み方向のキャリア濃度の積分値の概略半分であることを特徴とする高耐圧半導体素子。 Conductivity type semiconductor layer are arranged alternately and repeatedly, the integral value of the layer thickness direction of the carrier concentration of the first conductivity type of the outermost semiconductor layer or the second conductive type semiconductor layer, disposed therein high-voltage semiconductor device which is a schematic half the integral value of the layer thickness direction of the carrier concentration of said first conductivity type semiconductor layer and the second conductive semiconductor layer.
  4. 【請求項4】 高濃度第1導電型半導体領域と、高濃度第2導電型半導体領域と、これらの高濃度第1導電型半導体領域と高濃度第2導電型半導体領域との間に挟まれて形成され、交互に繰り返して配置された第1導電型半導体層及び第2導電型半導体層と、これらの第1導電型半導体層及び第2導電型半導体層を取り囲んで形成された低濃度第1導電型半導体領域と、この低濃度第1導電型半導体領域及び前記高濃度第2導電型半導体領域に接して形成され、前記高濃度第2導電型半導体領域より低濃度の低濃度第2導電型半導体領域とを備え、前記第1 4. A high-concentration first-conductivity-type semiconductor region, a high-concentration second conductivity type semiconductor region, sandwiched between these high-concentration first-conductivity-type semiconductor region and the high-concentration second conductivity type semiconductor region formed Te, a first conductive type semiconductor layer and the second conductive type semiconductor layer disposed alternately and repeatedly, a low concentration first formed surrounding these first conductivity type semiconductor layer and the second conductive type semiconductor layer a first conductivity type semiconductor region, the low density is in contact with is formed on the first conductivity type semiconductor region and said high concentration second conductivity type semiconductor region, the heavily doped low concentration of the low concentration second conductivity than the second conductivity type semiconductor region and a type semiconductor region, said first
    導電型半導体層及び第2導電型半導体層の繰り返し配置方向は、前記高濃度第1導電型半導体領域と前記高濃度第2導電型半導体領域とを結ぶ方向に対して概略垂直であるとともに、前記第1導電型半導体層はオン状態でドリフト電流を流すとともにオフ状態で空乏化し、前記第2導電型半導体層はオフ状態で空乏化し、かつ最外部の第1導電型半導体層又は前記第2導電型半導体層の層厚み方向のキャリア濃度の積分値が、その内部に配置された前記第1導電型半導体層及び前記第2導電型半導体層の層厚み方向のキャリア濃度の積分値の概略半分であることを特徴とする高耐圧半導体素子。 Repeatedly arranged direction of the conductive type semiconductor layer and the second conductive type semiconductor layer, together with the schematic is perpendicular to the direction connecting the said high concentration first conductivity type semiconductor region and the high concentration second conductivity type semiconductor region, wherein the first conductive type semiconductor layer depleted in the off-state with flow drift current in the on state, the second conductive semiconductor layer is depleted in the off state, and the first conductive type semiconductor layer of the outermost or the second conductive integrated value of the layer thickness direction of the carrier concentration type semiconductor layer is a schematic half the integral value of the layer thickness direction of the carrier concentration of the said inside located first conductivity type semiconductor layer and the second conductive semiconductor layer high voltage semiconductor element characterized in that.
  5. 【請求項5】 高濃度第1導電型半導体領域と、この高濃度第1導電型半導体領域に接して形成された第1導電型半導体層と、前記高濃度第1導電型半導体領域及び前記第1導電型半導体層に接して形成された第2導電型半導体層と、前記第1導電型半導体層及び前記第2導電型半導体層に接して形成された高濃度第2導電型半導体領域と、前記第1導電型半導体層及び前記第2導電型半導体層を取り囲んで形成された低濃度第1導電型半導体領域と、この低濃度第1導電型半導体領域に接して形成され、前記高濃度第2導電型半導体領域を取り囲むように当該領域から離間して設けられたリング状の第2導電型半導体領域層とを備え、前記第1導電型半導体層及び前記第2導電型半導体層は交互に繰り返して配置されており、その最外部の第 5. A high-concentration first-conductivity-type semiconductor region, and the high concentration first conductivity type semiconductor layer formed in contact with the first conductivity type semiconductor region, the high concentration first conductivity type semiconductor region and the second a second conductivity type semiconductor layer formed in contact with the first conductivity type semiconductor layer, the first conductivity type semiconductor layer and the high-concentration second conductivity type semiconductor region formed in contact with the second conductive type semiconductor layer, a low concentration first conductivity type semiconductor region formed surrounding the first conductive semiconductor layer and the second conductive type semiconductor layer is formed in contact with the low concentration first conductivity type semiconductor region, said high concentration first and a second conductivity type spaced apart from the region second conductivity type annular provided so as to surround the semiconductor region semiconductor region layer, the first conductive type semiconductor layer and the second conductive semiconductor layer alternately Repeat are arranged, first of its outermost 1導電型半導体層又は前記第2導電型半導体層の層厚み方向のキャリア濃度の積分値が、その内部に配置された前記第1導電型半導体層及び前記第2導電型半導体層の層厚み方向のキャリア濃度の積分値の概略半分であることを特徴とする高耐圧半導体素子。 1 integrated value of the layer thickness direction of the carrier concentration of the conductive type semiconductor layer or the second conductive semiconductor layer, a layer thickness direction of the said inside located first conductivity type semiconductor layer and the second conductive semiconductor layer high voltage semiconductor device characterized by the schematic half the integral value of the carrier concentration.
  6. 【請求項6】 高濃度第1導電型半導体領域と、高濃度第2導電型半導体領域と、これらの高濃度第1導電型半導体電極層と高濃度第2導電型半導体電極層との間に挟まれて形成され、交互に繰り返して配置された第1導電型半導体層及び第2導電型半導体層と、これらの第1導電型半導体層及び第2導電型を取り囲んで形成された低濃度第1導電型半導体領域と、この低濃度第1導電型半導体領域に接して形成され、前記高濃度第2導電型半導体領域を取り囲むように当該領域から離間して設けられたリング状の第2導電型半導体領域層とを備え、前記第1導電型半導体層及び第2導電型半導体層の繰り返し配置方向は、前記高濃度第1導電型半導体領域と前記高濃度第2導電型半導体領域とを結ぶ方向に対して概略垂直であるとともに、前 6. A high-concentration first-conductivity-type semiconductor region, between the high concentration and the second conductive type semiconductor region, these high-concentration first-conductivity-type semiconductor electrode layer and the high-concentration second conductivity type semiconductor electrode layer is sandwiched by forming a first conductivity type semiconductor layer and the second conductive type semiconductor layer disposed alternately and repeatedly, a low concentration first formed surrounding these first conductivity type semiconductor layer and the second conductive type a first conductivity type semiconductor region, this is formed in contact with the low concentration first conductivity type semiconductor region, the high concentration second conductive ring-shaped with spaced apart from the region provided so as to surround the second conductivity type semiconductor region and a semiconductor region layer, repeatedly arranged direction of the first conductive type semiconductor layer and the second conductive type semiconductor layer, connecting said high concentration first conductivity type semiconductor region and said high concentration second conductivity type semiconductor region with schematic it is perpendicular to the direction, before 記第1導電型半導体層はオン状態でドリフト電流を流すとともにオフ状態で空乏化し、前記第2導電型半導体層はオフ状態で空乏化し、かつ最外部の第1導電型半導体層又は前記第2導電型半導体層の層厚み方向のキャリア濃度の積分値が、その内部に配置された前記第1導電型半導体層及び前記第2導電型半導体層の層厚み方向のキャリア濃度の積分値の概略半分であることを特徴とする高耐圧半導体素子。 Serial first conductive type semiconductor layer is depleted in the off-state with flow drift current in the on state, the second conductive semiconductor layer is depleted in the off state, and the first conductivity type semiconductor layer or the second outermost integrated value of the layer thickness direction of the carrier concentration of the conductive semiconductor layer is a schematic half the integral value of the layer thickness direction of the carrier concentration of the said inside located first conductivity type semiconductor layer and the second conductive semiconductor layer high voltage semiconductor device characterized by at.
  7. 【請求項7】 前記第1導電型半導体層及び前記第2導電型半導体層は、お互いに平行なストライプ状の層であることを特徴とする請求項1乃至6記載の高耐圧半導体素子。 Wherein said first conductivity type semiconductor layer and the second conductive semiconductor layer, a high-voltage semiconductor device according to claim 1 to 6, wherein the parallel stripe-like layers to each other.
  8. 【請求項8】 前記第1導電型半導体層及び前記第2導電型半導体層は、奇数個存在することを特徴とする請求項1乃至7記載の高耐圧半導体素子。 Wherein said first conductivity type semiconductor layer and the second conductive semiconductor layer, a high-voltage semiconductor device according to claim 1 to 7, wherein the odd number is present.
  9. 【請求項9】 前記低濃度第2導電型半導体領域はオフ状態で空乏化し、その空乏領域は前記第1導電型半導体層及び前記第2導電型半導体層において空乏化により生ずる空乏領域と接することを特徴とする請求項3、4、 Wherein said low concentration second conductivity type semiconductor region is depleted in the OFF state, in contact with the depletion region of the first conductivity type semiconductor layer and the depletion region caused by depletion in the second conductivity type semiconductor layer claim 3 and 4, characterized in,
    7、又は8記載の高耐圧半導体素子。 7, or 8 high-voltage semiconductor device according.
  10. 【請求項10】 前記リング状の第2導電型半導体領域層に接する低濃度第1導電型半導体領域はオフ状態で空乏化し、その空乏領域は前記第1導電型半導体層及び前記第2導電型半導体層において空乏化により生ずる空乏領域と接することを特徴とする請求項5乃至8記載の高耐圧半導体素子。 Wherein said ring-shaped low concentration first conductivity type semiconductor region in contact with the second conductivity type semiconductor region layer depleted in the off state, the depletion region of the first conductivity type semiconductor layer and the second conductivity type high voltage semiconductor device according to claim 5 to 8, wherein the contact with the depletion region caused by depletion of the semiconductor layer.
  11. 【請求項11】 前記高耐圧半導体素子は縦型の構造を有するものであることを特徴とする請求項1乃至9記載の高耐圧半導体素子。 Wherein said high-voltage semiconductor device is a high voltage semiconductor device according to claim 1 to 9, wherein the one having a vertical structure.
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