JP5238866B2 - Power semiconductor device - Google Patents

Description

  The present invention relates to a power semiconductor device, for example, used for a vertical power device such as a vertical diode or a vertical transistor.

  A vertical power device generally has electrodes on the upper and lower surfaces of a chip. In the off state, a negative voltage is applied to the upper electrode and a positive voltage is applied to the lower electrode. In a vertical diode that is an example of a vertical power device, the upper electrode is an anode electrode, and the lower electrode is a cathode electrode. In another example, a vertical MOSFET or a vertical IGBT (Integrated Gate Bipolar Transistor), the upper electrode is a source electrode or an emitter electrode, and the lower electrode is a drain electrode or a collector electrode.

  In the vertical power device, a vertical diode and a vertical transistor are provided in the element part, and a terminal part is provided on the outer periphery of the element part so that a voltage is not applied to the side surface of the chip. At the terminal portion, an electric field is generated not only in the vertical direction but also in the horizontal direction. Therefore, the termination length needs to be 2 to 4 times the thickness of the drift layer holding the breakdown voltage so that the breakdown voltage is not reduced by the lateral electric field. However, if the termination length is long, the effective area ratio in the chip decreases, and the on-resistance or on-voltage of the chip increases.

  As a structure for shortening the terminal length and increasing the effective area ratio, a structure in which a deep trench reaching the high concentration substrate from the semiconductor layer surface is formed (see, for example, Patent Document 1). In this structure, the element portion and the side surface of the chip are insulated and separated by a deep trench, thereby preventing a decrease in breakdown voltage at the termination portion, and by reducing the termination length to about the trench width, the effective area ratio is reduced. Can be improved.

  However, it takes a long etching time to form a deep trench, and the longer the trench width, the longer the time. Conversely, if the trench width is wide, the volume of the trench becomes large, and it becomes difficult to embed an insulating film uniformly in the trench. As a result, voids are generated in the insulating film, resulting in an increase in leakage current due to the deterioration of the insulating properties of the terminal portion.

JP 2006-41223 A

  An object of the present invention is to provide a power semiconductor device capable of realizing a low on-resistance and a high breakdown voltage with a relatively short termination length and a shallow trench.

  One embodiment of the present invention includes, for example, a first semiconductor layer of a first or second conductivity type, a second semiconductor layer of a first conductivity type formed on the first semiconductor layer, and the second semiconductor layer. A third semiconductor layer of the second conductivity type selectively formed on the surface of the semiconductor layer, and one or more trenches formed on the outer periphery of the third semiconductor layer on the surface of the second semiconductor layer An insulating film embedded in the trench, a first main electrode electrically connected to the first semiconductor layer, and a second main electrode electrically connected to the third semiconductor layer The depth of the bottom surface of the trench is deeper than the lower surface of the third semiconductor layer and shallower than the upper surface of the first semiconductor layer, and some or all of the trenches are The power semiconductor device is in contact with a side surface of the third semiconductor layer.

  According to the present invention, it is possible to provide a power semiconductor device capable of realizing a low on-resistance and a high breakdown voltage with a relatively short termination length and a shallow trench.

It is the top view and side sectional view which show typically the structure of the power semiconductor device of 1st Embodiment. It is the top view and side sectional view which show typically the structure of the modification of 1st Embodiment. It is a top view which shows typically the structure of the modification of 1st Embodiment. It is the top view and side sectional view which show typically the structure of the modification of 1st Embodiment. It is the top view and side sectional view which show typically the structure of the modification of 1st Embodiment. It is a side sectional view showing typically the composition of the modification of a 1st embodiment. It is a top view which shows typically the structure of the modification of 1st Embodiment. It is the top view and side sectional view which show typically the structure of the semiconductor device for electric power of 2nd Embodiment. It is the top view and side sectional view which show typically the structure of the modification of 2nd Embodiment. It is the top view and side sectional view which show typically the structure of the power semiconductor device of 3rd Embodiment. It is the top view and side sectional view which show typically the structure of the modification of 3rd Embodiment. It is the top view and side sectional view which show typically the structure of the power semiconductor device of 4th Embodiment. It is a top view which shows typically the structure of the semiconductor device for electric power of 5th Embodiment. It is a top view which shows typically the structure of the modification of 5th Embodiment. It is a top view which shows typically the structure of the modification of 5th Embodiment. It is a top view which shows typically the structure of the power semiconductor device of 6th Embodiment. It is a top view which shows typically the structure of the modification of 6th Embodiment.

  Embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the first conductivity type is n-type and the second conductivity type is p-type, but these may be reversed. Moreover, the same code | symbol is attached | subjected to the same part in drawing.

(First embodiment)
1A and 1B are a plan view and a side sectional view schematically showing the configuration of the power semiconductor device of the first embodiment. The side sectional view shows a section taken along the line AA ′ shown in the plan view.

  The power semiconductor device of FIG. 1 is a vertical diode, an n + semiconductor substrate 101 that is an example of a first semiconductor layer, an n− semiconductor layer 102 that is an example of a second semiconductor layer, and a third semiconductor. P anode layer 103, which is an example of a layer, guard ring layer 104, which is an example of a fourth semiconductor layer, trench 111, insulating film 121, cathode electrode 131, which is an example of a first main electrode, And an anode electrode 132 which is an example of the two main electrodes.

  The power semiconductor device of FIG. 1 further includes a field stop layer 141, a field stop electrode 142, and a field insulating film 143.

  In FIG. 1, an n− semiconductor layer 102 is formed on an n + semiconductor substrate 101, and a p anode layer 103 is selectively formed on the surface of the n− semiconductor layer 102. The cathode electrode 131 is electrically connected to the n + semiconductor substrate 101, and the anode electrode 132 is electrically connected to the p anode layer 103. In this embodiment, the n + layer 101 is used as a substrate and the n− layer 102 is formed on one side of the substrate by crystal growth. Conversely, the n− layer 102 is used as a substrate, and the n + layer 101 is formed by impurity diffusion. It may be formed on one side.

  The power semiconductor device in FIG. 1 has an element portion that is a region through which current flows in an on state, and a termination portion that is an outer peripheral region of the element portion. In FIG. 1, a region where the p anode layer 103 is provided is an element portion, and an outer peripheral region of the p anode layer 103 is a termination portion.

  At the termination portion, a field stop layer 141 and a field stop electrode 142 are formed so that the depletion layer does not extend to the chip side wall. A field insulating film 143 is formed between the field stop electrode 142 and the anode electrode 132.

  The trench 111 is formed on the outer periphery of the p anode layer 103 on the surface of the n − semiconductor layer 102. The trench 111 is formed in a spiral shape so as to surround the p anode layer 103 when viewed from above the n − semiconductor layer 102. An insulating film 121 is embedded in the trench 111. As shown in the side sectional view, the depth of the bottom surface of the trench 111 is deeper than the lower surface of the p anode layer 103 and shallower than the upper surface of the n + semiconductor substrate 101. Further, as shown in the plan view and the side sectional view, the trench 111 is in contact with the side surface of the p anode layer 103. In the present embodiment, the portion near the tip of the trench 111 is in contact with the side surface of the p anode layer 103 so as to surround the p anode layer 103.

  In FIG. 1, the trench 111 is formed in a spiral shape. Therefore, the n − semiconductor layer 102 has a region sandwiched between the trenches 111, specifically, a region sandwiched between portions constituting the trench 111. In this region, a plurality of guard ring layers 104 are selectively formed on the surface of the n − semiconductor layer 102. In this region, the n − semiconductor layers 102 and the guard ring layers 104 are alternately exposed on the surface. The guard ring layer 104 is a p-type semiconductor layer like the p anode layer 103.

In the present embodiment, by forming such a spiral trench 111, the termination length can be shortened while maintaining a high breakdown voltage. In Figure 1, the termination length is indicated by L _T. In the power semiconductor device of FIG. 1, when a high voltage is applied to the vertical diode in the off state, the depletion layer extends from the p anode layer 103 to the termination portion. In the termination portion, the depletion layer extends not only in the vertical direction of the n− semiconductor layer (drift layer) 102 but also in the lateral direction toward the chip sidewall.

  In the present embodiment, the region sandwiched between the trenches 111 is connected from the p anode layer 103 to the chip side wall by a spiral semiconductor layer (n− semiconductor layer 102 and guard ring layer 104). Therefore, in the power semiconductor device of FIG. 1, when a high voltage is applied in the off state, the depletion layer extends along the semiconductor layer, and the potential distribution becomes a spiral distribution. At this time, the potential difference between the guard ring layers 104 adjacent to each other via the trench 111 is held by the insulating film 121 in the trench 111. An electric field is also generated on the side wall of the inner trench 111 to hold the voltage. In the spiral semiconductor layer, the n − semiconductor layer 102 and the guard ring layer 104 are alternately and periodically arranged along the spiral.

In the conventional termination structure, the voltage is held only at the interface between the field insulating film and the semiconductor layer. On the other hand, in the termination structure of this embodiment, a voltage is held at the insulating film 121 in the trench 111 and the interface between the trench 111 and the semiconductor layer. Therefore, in this embodiment, the distance of the depletion layer that holds the voltage can be increased by the length of the trench 111. This is because the depletion layer that holds the voltage extends along the trench 111. Therefore, in the present embodiment, even with a shorter end length L _T, effective for termination length becomes longer the distance that can depletion layer extends, it is possible to obtain a high breakdown voltage. In this embodiment, by forming a plurality of guard ring layers 104 in a region sandwiched between the trenches 111, a plurality of p-type layers are formed in the region, and the pn perpendicular to the direction in which the spiral extends Many joint surfaces are periodically formed along the spiral. Thereby, in this embodiment, compared with the case where the guard ring layer 104 is not formed, electric field concentration in the direction along the trench 111 can be suppressed, and a high voltage can be realized.

  In this embodiment, since the effective termination length is long, the electric field generated at the termination portion is reduced. As a result, the leakage current at the terminal end is reduced. In the present embodiment, the generation of hot carriers and the movement of mobile ions are further suppressed by reducing the electric field generated at the terminal portion. As a result, it is possible to realize a power semiconductor device that hardly changes in characteristics and has high reliability.

  Further, as described above, in this embodiment, the region sandwiched between the trenches 111 is connected from the p anode layer 103 to the chip side wall by a spiral semiconductor layer (n− semiconductor layer 102 and guard ring layer 104). Yes.

  Therefore, in this embodiment, holes injected from the p anode layer 103 into the n − semiconductor layer 102 in the on state are quickly discharged to the p anode layer 103 through the mesa portion (spiral semiconductor layer) in the off state. The Thereby, in this embodiment, a high-speed recovery operation becomes possible. In the present embodiment, since the discharged carriers are not accumulated, the electric field distribution at the terminal portion does not change even in a dynamic state, and a high recovery tolerance can be obtained. Further, in the present embodiment, even if holes are generated at the terminal end due to avalanche breakdown, holes are not easily accumulated at the terminal end because they are quickly discharged to the p anode layer 103 through the mesa. Thereby, in this embodiment, a high avalanche tolerance can be obtained. Such an effect cannot be obtained when a concentric trench in contact with the entire side surface of the p anode layer is provided instead of providing a spiral trench in contact with a part of the side surface of the p anode layer.

  Further, in this embodiment, since the termination length can be shortened, the on-resistance of the chip can be lowered. Also, in this embodiment, even if the termination length is shortened, the effective termination length can be increased. Therefore, the termination length is set short despite the adoption of a shallow trench, and the effective area in the chip is set. The ratio can be increased. In the present embodiment, the depth of the bottom surface of the trench 111 is set deeper than the lower surface of the p anode layer 103 and shallower than the upper surface of the n + semiconductor substrate 101.

  Hereinafter, various modifications of the power semiconductor device of the present embodiment will be described with reference to FIGS. 2 to 7 are a plan view and a side sectional view schematically showing the configuration of these modified examples.

  In FIG. 1, the guard ring layer 104 is formed only inside the spiral trench 111. On the other hand, in this embodiment, as shown in FIG. 2, the guard ring layer 104 may be formed outside the spiral trench 111.

  In FIG. 3, the distance of the guard ring layer 104 along the trench 111 is indicated by a, and the length of the guard ring layer 104 along the trench 111 is indicated by b. In this embodiment, when the depletion layer extends along the trench 111, the interval a between the guard ring layers 104 is set so that the depletion layer can easily reach the adjacent guard ring layer 104 from one guard ring layer 104. It is desirable that the length is smaller than the length b of the ring layer 104. This is because the interval between the guard ring layers 104 can be narrowed without reducing the number of guard ring layers 104 by relatively reducing the value of a and relatively increasing the value of b. Further, since the breakdown electric field of the insulating film 121 is usually 10 times or more the critical electric field of silicon, it is desirable that ten or more guard ring layers 104 are formed during one round of the spiral.

  In addition, the voltage held by the insulating film 121 sandwiched between the guard ring layers 104 is equal to the voltage held by the sidewall of the trench 111. On the other hand, as described above, the breakdown electric field of the insulating film 121 is usually 10 times or more the critical electric field of silicon. Therefore, the width of the trench 111 is desirably 1/10 or more of the depth of the trench 111 so that dielectric breakdown does not occur in the insulating film 121.

  1 to 3, the guard ring layer 104 is arranged so that the guard ring layers 104 face each other with the trench 111 interposed therebetween. However, the above-described effect can also be obtained when other arrangements are adopted. Can be obtained. In the present embodiment, for example, as shown in FIG. 4, the guard ring layer 104 may be arranged in an offset shape. That is, each guard ring layer 104 may be disposed so as to face the n − semiconductor layer 102 with the trench 111 interposed therebetween.

  Further, the power semiconductor device of this embodiment may include a plurality of field plate electrodes 144 electrically connected to the guard ring layer 104 as shown in FIG. Thereby, in the power semiconductor device, the electric field distribution is hardly changed due to the charge in the field insulating film 143 and the charge on the chip surface, and high breakdown voltage and high reliability can be obtained. In FIG. 5, one field plate electrode 144 is provided on each guard ring layer 104.

  In FIG. 6, the depth of the trench 111 is indicated by d, the number of the trenches 111 is indicated by n, and the thickness of the n− semiconductor layer 102 is indicated by t. However, n represents the minimum number of trench sections existing on one side of the p anode layer 103 in an arbitrary side section crossing the p anode layer 103. In FIG. 6, three trench cross sections exist on the left side of the p anode layer 103, two trench cross sections exist on the right side, and n is 2.

  In the present embodiment, as the trench depth d increases, the voltage held on the sidewall of the trench 111 increases. Therefore, in this embodiment, it is possible to reduce the number of trenches n as the trench depth d increases. Since the voltage is held on the side wall of the trench 111 and outside the outermost trench 111, the number of locations for holding the voltage is the number of trenches n plus one.

  In this embodiment, since the voltage in the vertical direction of the n − semiconductor layer 102 is divided and held in the horizontal direction of the terminal portion, a high breakdown voltage is held by making the horizontal electric field smaller than the vertical electric field. be able to. Therefore, the trench depth d is desirably larger than the thickness t of the n− semiconductor layer 102 divided by the number (n + 1) of voltage holding portions. That is, it is desirable that a relationship of d> t / (n + 1) holds between d, t, and n.

  1 to 6, only one spiral trench 111 is formed in the power semiconductor device. On the other hand, in this embodiment, as shown in FIG. 7, two or more spiral trenches 111 may be formed in the power semiconductor device. FIG. 7 shows a total of four trenches 111. In FIG. 7, all the trenches 111 are in contact with the side surfaces of the p anode layer 103, but only some of the trenches 111 may be in contact with the side surfaces of the p anode layer 103. The above-described effects described with reference to FIG. 1 can also be obtained in the case of FIG.

  As described above, the power semiconductor device of this embodiment includes one or more spiral trenches 111, and the depth of the bottom surface of the trench 111 is deeper than the bottom surface of the p anode layer 103, and the n + semiconductor substrate 101 It is shallower than the upper surface, and part or all of the trench 111 is in contact with the side surface of the p anode layer 103. Thereby, in this embodiment, a low on-resistance and a high breakdown voltage can be realized with a relatively short termination length and a shallow trench 111.

  The power semiconductor devices of the second to sixth embodiments will be described below. These embodiments are modifications of the first embodiment, and these embodiments will be described with a focus on differences from the first embodiment.

(Second Embodiment)
FIG. 8 is a plan view and a side sectional view schematically showing the configuration of the power semiconductor device of the second embodiment.

  The power semiconductor device in FIG. 8 is a vertical power MOSFET, and includes an n + semiconductor substrate 101 that is an example of a first semiconductor layer, an n− semiconductor layer 102 that is an example of a second semiconductor layer, A p base layer 201 that is an example of a semiconductor layer, a p + contact layer 202, an n + source layer 203, a guard ring layer 104 that is an example of a fourth semiconductor layer, a trench 111, an insulating film 121, and a gate insulation The film 211 includes a gate electrode 221 that is a control electrode, a drain electrode 231 that is an example of a first main electrode, and a source electrode 232 that is an example of a second main electrode.

  The power semiconductor device of FIG. 8 further includes a field stop layer 141, a field stop electrode 142, and a field insulating film 143.

  In FIG. 8, an n− semiconductor layer 102 is formed on an n + semiconductor substrate 101, and a p base layer 201 is selectively formed on the surface of the n− semiconductor layer 102. Further, in FIG. 8, a p + contact layer 202 is selectively formed on the surface of the p base layer 201, and an n + source layer 203 is selectively formed on the surfaces of the p base layer 201 and the p + contact layer 202. The gate electrode 221 is formed on the n− semiconductor layer 102, the p base layer 201, and the n + source layer 203 with the gate insulating film 211 interposed therebetween. The drain electrode 231 is electrically connected to the n + semiconductor substrate 101, and the source electrode 232 is electrically connected to the p base layer 201 and the p + contact layer 202.

  In FIG. 8, the trench 111 is formed on the termination portion, that is, the outer periphery of the p base layer 201 on the surface of the n − semiconductor layer 102. The trench 111 is formed in a spiral shape. Therefore, the n − semiconductor layer 102 has a region sandwiched between the trenches 111. In this region, a plurality of guard ring layers 104 are selectively formed on the surface of the n − semiconductor layer 102. In the present embodiment, as in the first embodiment, by forming such a spiral trench 111, the termination length can be shortened while maintaining a high breakdown voltage.

  In the present embodiment, since the trench 111 is spiral, the region sandwiched between the trenches 111 is a spiral semiconductor layer (n− semiconductor layer 102 and guard ring layer 104) from the p base layer 201 to the chip sidewall. ). For this reason, even when a high voltage is applied to the vertical power MOSFET and an avalanche breakdown occurs, the holes at the terminal end are quickly discharged along the spiral semiconductor layer. Thereby, in this embodiment, a high avalanche resistance can be obtained. In the spiral semiconductor layer, the n − semiconductor layer 102 and the guard ring layer 104 are alternately and periodically arranged along the spiral. As a result, in the semiconductor layer, a large number of pn junction surfaces perpendicular to the direction in which the spiral extends are periodically formed along the spiral.

  This embodiment can be applied not only to the power semiconductor device of FIG. 8 but also to the power semiconductor device of FIG. FIG. 9 is a plan view and a side cross-sectional view schematically showing a configuration of a modification of the power semiconductor device of FIG.

  The power semiconductor device in FIG. 9 is a vertical IGBT, and includes a p + semiconductor substrate 301 as an example of a first semiconductor layer, an n− semiconductor layer 102 as an example of a second semiconductor layer, and a third semiconductor. P base layer 201, which is an example of a layer, p + contact layer 202, n + source layer 203, guard ring layer 104 which is an example of a fourth semiconductor layer, trench 111, insulating film 121, and gate insulating film 211, a gate electrode 221 that is a control electrode, a collector electrode 311 that is an example of a first main electrode, and an emitter electrode 312 that is an example of a second main electrode.

  The arrangement of the collector electrode 311 and the emitter electrode 312 is the same as that of the drain electrode 231 and the source electrode 232, respectively.

  As described above, the power semiconductor device according to this embodiment includes one or more spiral trenches 111, and the depth of the bottom surface of the trench 111 is deeper than the bottom surface of the p base layer 201. It is shallower than the upper surface, and part or all of the trench 111 is in contact with the side surface of the p base layer 201. Thereby, in this embodiment, a low on-resistance and a high breakdown voltage can be realized with a relatively short termination length and a shallow trench 111.

(Third embodiment)
FIG. 10 is a plan view and a side sectional view schematically showing the configuration of the power semiconductor device of the third embodiment. The power semiconductor device of FIG. 10 is a vertical diode, similar to the power semiconductor device of FIG.

  In the first embodiment, the guard ring layer 104 is formed in a region sandwiched between the trenches 111, whereas in the present embodiment, the RESURF layer 401 that is depleted by application of a high voltage to the sidewalls of the trench 111. Is formed. The RESURF layer 401 is a p-type semiconductor layer and is an example of a fifth semiconductor layer.

  When a high voltage is applied, the RESURF layer 401 is depleted and holds the voltage. Since the RESURF layer 401 of this embodiment holds a voltage in the same manner as the sidewall of the trench 111 of the first embodiment holds a voltage, according to this embodiment, the termination length is shortened while maintaining a high breakdown voltage. can do. Moreover, in this embodiment, since the trench 111 is spiral, high recovery tolerance and high avalanche tolerance can be obtained.

  In this embodiment, the potential distribution in the RESURF layer 401 can be flattened by optimizing the impurity concentration in the RESURF layer 401. Thereby, a flat electric field distribution can be obtained in the direction along the trench 111 as compared with the case where the guard ring layer 104 is formed. Thereby, in this embodiment, electric field concentration is suppressed and it becomes easy to obtain a high withstand voltage.

  The RESURF layer 401 can be formed by performing ion implantation from an oblique direction after forming the trench 111. In FIG. 10, the RESURF layer 401 is formed only on the side wall of the trench 111. On the other hand, in this embodiment, as shown in FIG. 11, the RESURF layer 401 may be formed on the side wall and the bottom of the trench 111. FIGS. 11A and 11B are a plan view and a side sectional view schematically showing a configuration of a modification of the power semiconductor device of FIG.

  In the present embodiment, as in the first embodiment, a low on-resistance and a high breakdown voltage can be realized with a relatively short termination length and a shallow trench 111. Note that the RESURF layer 401 has an advantage of being easier to form than the guard ring layer 104. On the other hand, the guard ring layer 104 has an advantage that it is less susceptible to variations in the manufacturing process than the RESURF layer 401.

(Fourth embodiment)
FIG. 12 is a plan view and a side sectional view schematically showing the configuration of the power semiconductor device of the fourth embodiment. The power semiconductor device of FIG. 12 is a vertical diode, similar to the power semiconductor device of FIG.

  In the first to third embodiments, the guard ring layer 104 and the RESURF layer 401 are provided in the power semiconductor device. In the present embodiment, a plurality of floating electrodes 501 are provided in the power semiconductor device. It has been. The floating electrode 501 is selectively formed in the trench 111, and the side surface and the bottom surface of the floating electrode 501 are covered with the insulating film 121. Therefore, the potential of the floating electrode 501 is in a floating state.

  In the present embodiment, by forming such a floating electrode 501, the depletion layer easily extends along the trench 111 when a high voltage is applied, as in the case of forming the guard ring layer 104. Thereby, in this embodiment, a high breakdown voltage can be obtained.

  In the present embodiment, as in the first embodiment, a low on-resistance and a high breakdown voltage can be realized with a relatively short termination length and a shallow trench 111.

(Fifth embodiment)
FIG. 13 is a plan view schematically showing the configuration of the power semiconductor device of the fifth embodiment. The power semiconductor device of FIG. 13 is a vertical diode, similar to the device of FIG.

  The power semiconductor device in FIG. 1 includes one trench 111 formed in a spiral shape, whereas the power semiconductor device in FIG. 13 includes a plurality of trenches 601 formed in a straight line shape. .

  In FIG. 13, these trenches 601 are formed on the outer periphery of the p anode layer 103 on the surface of the n − semiconductor layer 102. These trenches 601 are formed in a straight line so as to surround the p anode layer 103 when viewed from above the n − semiconductor layer 102. In the same manner as the insulating film 121 is embedded in the trench 111 of FIG. 1, an insulating film 611 is embedded in the trench 601 of FIG.

  Note that the depth of the bottom surface of the trench 601 is set to be deeper than the lower surface of the p anode layer 103 and shallower than the upper surface of the n + semiconductor substrate 101, similarly to the trench 111. Further, as shown in FIG. 13, a part of the trench 601 is in contact with the side surface of the p anode layer 103 as in the case of the trench 111. In the present embodiment, one end of these trenches is in contact with the side surface of the p anode layer 103. In FIG. 13, all of the trenches 601 may be in contact with the side surface of the p anode layer 103.

  In FIG. 13, each of the trenches 601 is formed to extend from the vicinity of the side surface of the p anode layer 103 toward the outer periphery, and the direction in which each of the trenches 601 extends is inclined with respect to the normal direction of the side surface. . For example, in FIG. 13, the trench indicated by T extends from the side surface indicated by S to the outer periphery, and the extending direction of the trench T is inclined neither parallel nor perpendicular to the normal line of the side surface S.

  As described above, the trench 601 is formed not obliquely from the p anode layer 103 toward the field stop layer 143 but obliquely. As a result, in this embodiment, the voltage is applied in the vertical direction of the p anode layer 103 and the field stop layer 143, whereas the depletion layer extends in an oblique direction along the trench 601. Thereby, in this embodiment, even when the termination length is short, the depletion layer distance becomes long and a high breakdown voltage can be obtained.

  In the present embodiment, since the depletion layer distance is long, the electric field generated at the terminal portion is reduced. As a result, the leakage current at the terminal end is reduced. In the present embodiment, the generation of hot carriers and the movement of mobile ions are further suppressed by reducing the electric field generated at the terminal portion. As a result, it is possible to realize a power semiconductor device that hardly changes in characteristics and has high reliability.

  In the present embodiment, the trench 601 is not in contact with the entire side surface of the p anode layer 103 but is in contact with only a part of the side surface of the p anode layer 103.

  Therefore, in this embodiment, holes injected from the p anode layer 103 to the n − semiconductor layer 102 in the on state are in the mesa portion (the n − semiconductor layer 102 and the guard ring layer sandwiched between the trenches 601 in the off state). 104) to the p anode layer 103 quickly. In the first embodiment or the like, the holes are the same as discharged through the spiral semiconductor layer. Thereby, in this embodiment, a high-speed recovery operation becomes possible. In the present embodiment, since the discharged carriers are not accumulated, the electric field distribution at the terminal portion does not change even in a dynamic state, and a high recovery tolerance can be obtained. Further, in the present embodiment, even if holes are generated at the terminal end due to avalanche breakdown, the holes are quickly discharged to the p anode layer 103 through the mesa portion, so that holes are not easily accumulated at the terminal end (also in the first embodiment). It is the same as the form). Thereby, in this embodiment, a high avalanche tolerance can be obtained. Such an effect cannot be obtained when a trench in contact with the entire side surface of the p anode layer is provided instead of providing a trench in contact with only a part of the side surface of the p anode layer.

  In addition, the trench structure of this embodiment has an advantage that holes can be easily removed as compared with the trench structures of the first to fourth embodiments.

  Hereinafter, various modifications of the power semiconductor device of the present embodiment will be described with reference to FIGS. 14 and 15. 14 and 15 are plan views schematically showing the configuration of these modified examples.

  In FIG. 13, the guard ring layer 104 is formed in a region sandwiched between the trenches 601, whereas in FIG. 14, the RESURF layer 401 that is depleted by application of a high voltage is formed on the sidewall of the trench 601. ing. In FIG. 14, since the depletion layer extends along the trench 601, the same effect as in the case of FIG. 13 is obtained. The RESURF layer 401 is formed on the entire four side surfaces of each trench 601. In FIG. 14, the RESURF layer 401 may be formed on the side wall and the bottom of each trench 601. In FIG. 14, the RESURF layer 401 may be formed on the entire terminal portion.

  In the present embodiment, the power semiconductor device may include a plurality of trenches 601 formed in a curved shape, as shown in FIG. In detail, the trench 601 in FIG. 15 is formed in a stepped shape.

  In FIG. 15, each of the trenches 601 is formed to extend from the vicinity of the side surface of the p anode layer 103 toward the outer periphery, and the direction in which each of the trenches 601 extends on the average is relative to the normal direction of this side surface. Tilted. For example, in FIG. 15, the trench indicated by τ extends from the side surface indicated by σ to the outer periphery, and the direction in which the trench τ extends on average is not parallel to or perpendicular to the normal line of the side surface τ. In FIG. 15, the direction in which the trench τ extends on the average is indicated by X.

  In addition, this embodiment is applicable not only to a vertical diode but also to a vertical power MOSFET and a vertical IGBT. The matters described in relation to FIGS. 1 to 12 are also applicable to this embodiment.

  As described above, the power semiconductor device of this embodiment includes a plurality of linear or curved trenches 601, and the depth of the bottom surface of the trench 601 is deeper than the lower surface of the p anode layer 103, and the n + semiconductor substrate 101. The trench 601 is partly or entirely in contact with the side surface of the p anode layer 103. Thereby, in this embodiment, a low on-resistance and a high breakdown voltage can be realized with a relatively short termination length and a shallow trench 601.

(Sixth embodiment)
FIG. 16 is a plan view schematically showing the configuration of the power semiconductor device of the sixth embodiment. The power semiconductor device of FIG. 16 is a vertical diode, similar to the device of FIG.

  The power semiconductor device in FIG. 1 includes one trench 111 formed in a spiral shape, whereas the power semiconductor device in FIG. 16 includes a plurality of trenches 701 formed in a broken line shape. .

  In FIG. 16, these trenches 701 are formed on the outer periphery of the p anode layer 103 on the surface of the n − semiconductor layer 102. These trenches 701 are formed in a broken line shape so as to surround the p anode layer 103 when viewed from above the n − semiconductor layer 102. In the same manner as the insulating film 121 is embedded in the trench 111 in FIG. 1, an insulating film 711 is embedded in the trench 701 in FIG.

  Note that the depth of the bottom surface of the trench 701 is set to be deeper than the lower surface of the p anode layer 103 and shallower than the upper surface of the n + semiconductor substrate 101, similarly to the trench 111. Also, as shown in FIG. 16, a part of the trench 701 is in contact with the side surface of the p anode layer 103, like the trench 111. In the present embodiment, the longitudinal side surfaces of these trenches are in contact with the side surfaces of the p anode layer 103.

  In FIG. 16, the trench 701 is formed in a broken line shape so as to surround the p anode layer 103. In the power semiconductor device of FIG. 16, when a high voltage is applied to the vertical diode, the depletion layer extends from the p anode layer 103 toward the field stop layer 141. In the present embodiment, when the depletion layer extends in the vertical direction of the p anode layer 103 and the field stop layer 143, the pattern of the trench 701 is set so that it always meets the insulating film 711. Thereby, in the present embodiment, the voltage is also retained in the insulating film 711.

  Further, in this embodiment, the trench 701 is formed in a broken line shape, so that a voltage is held in the vertical direction along the trench 701 without forming a storage layer in silicon that is in contact with the trench 701. As a result, in this embodiment, the surface distance of the terminal portion is increased. Thereby, this embodiment can implement | achieve a high proof pressure and high reliability by reducing an average electric field.

  Hereinafter, a modification of the power semiconductor device of the present embodiment will be described with reference to FIG. FIG. 17 is a plan view schematically showing the configuration of the modified example.

  In FIG. 16, the guard ring layer 104 is formed in a region sandwiched between the trenches 701, whereas in FIG. 17, the RESURF layer 401 that is depleted by application of a high voltage is formed on the sidewall of the trench 701. ing. In FIG. 17, since the depletion layer extends along the trench 701, the same effect as in FIG. 16 can be obtained. The RESURF layer 401 is formed on the entire four side surfaces of each trench 701. In FIG. 17, the RESURF layer 401 may be formed on the side wall and the bottom of each trench 701. In FIG. 17, the RESURF layer 401 may be formed on the entire terminal portion.

  In addition, this embodiment is applicable not only to a vertical diode but also to a vertical power MOSFET and a vertical IGBT. The matters described in relation to FIGS. 1 to 12 are also applicable to this embodiment.

  As described above, the power semiconductor device of this embodiment includes a plurality of broken-line trenches 701, and the depth of the bottom surface of the trench 701 is deeper than the lower surface of the p anode layer 103 and from the upper surface of the n + semiconductor substrate 101. The trench 701 is partly in contact with the side surface of the p anode layer 103. Thereby, in this embodiment, a low on-resistance and a high breakdown voltage can be realized with a relatively short termination length and a shallow trench 701.

  In the second embodiment, the gate electrode 221 has a striped gate pattern, but may have another gate pattern. Examples of such gate patterns include mesh, offset mesh, and honeycomb gate patterns.

  In the second embodiment, the gate electrode 221 has a planar gate structure, but may have another gate structure. An example of such a gate structure is a trench gate structure.

  In the first embodiment, it has been described that the width of the trench 111 is desirably 1/10 or more of the depth of the trench 111. This condition is not only applied to the power semiconductor device having the guard ring layer 104 but can also be applied to the power semiconductor device having the RESURF layer 401 and the floating electrode 501.

  As mentioned above, although the example of the specific aspect of this invention was demonstrated by 1st-6th embodiment, this invention is not limited to these embodiment.

101 n + semiconductor substrate 102 n-semiconductor layer 103 p anode layer 104 guard ring layer 111, 601, 701 trench 121, 611, 711 insulating film 131 cathode electrode 132 anode electrode 201 p base layer 202 p + contact layer 203 n + source layer 211 gate Insulating film 221 Gate electrode 231 Drain electrode 232 Source electrode 301 p + Semiconductor substrate 311 Collector electrode 312 Emitter electrode 401 RESURF layer 501 Floating electrode

Claims (3)

A first semiconductor layer of the first or second conductivity type;
A second semiconductor layer of a first conductivity type formed on the first semiconductor layer;
A third semiconductor layer of a second conductivity type selectively formed on the surface of the second semiconductor layer;
A plurality of trenches formed on the outer surface of the third semiconductor layer on the surface of the second semiconductor layer, and formed in a linear or curved shape when viewed from above the second semiconductor layer ;
An insulating film embedded in the trench;
A first main electrode electrically connected to the first semiconductor layer;
A second main electrode electrically connected to the third semiconductor layer,
The depth of the bottom surface of the trench is deeper than the lower surface of the third semiconductor layer and shallower than the upper surface of the first semiconductor layer,
A part or all of the trench is in contact with a side surface of the third semiconductor layer ;
Each of the plurality of trenches is formed so as to extend from the vicinity of the side surface of the third semiconductor layer toward the outer periphery, and a direction in which each of the plurality of trenches extends is inclined with respect to a normal direction of the side surface. and the power semiconductor device, characterized in that are. 2. The semiconductor device according to claim 1, further comprising a plurality of second conductivity type fourth semiconductor layers selectively formed on a surface of the second semiconductor layer in a region sandwiched between the trenches. Power semiconductor device. The power semiconductor device according to claim 1, further comprising a fifth semiconductor layer of a second conductivity type formed on a side wall of the trench and depleted by application of a predetermined voltage.

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